shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 static int radeon_do_cleanup_cp(struct drm_device * dev);
  40
  41 /* CP microcode (from ATI) */
  42 static const u32 R200_cp_microcode[][2] = {
  43         {0x21007000, 0000000000},
  44         {0x20007000, 0000000000},
  45         {0x000000ab, 0x00000004},
  46         {0x000000af, 0x00000004},
  47         {0x66544a49, 0000000000},
  48         {0x49494174, 0000000000},
  49         {0x54517d83, 0000000000},
  50         {0x498d8b64, 0000000000},
  51         {0x49494949, 0000000000},
  52         {0x49da493c, 0000000000},
  53         {0x49989898, 0000000000},
  54         {0xd34949d5, 0000000000},
  55         {0x9dc90e11, 0000000000},
  56         {0xce9b9b9b, 0000000000},
  57         {0x000f0000, 0x00000016},
  58         {0x352e232c, 0000000000},
  59         {0x00000013, 0x00000004},
  60         {0x000f0000, 0x00000016},
  61         {0x352e272c, 0000000000},
  62         {0x000f0001, 0x00000016},
  63         {0x3239362f, 0000000000},
  64         {0x000077ef, 0x00000002},
  65         {0x00061000, 0x00000002},
  66         {0x00000020, 0x0000001a},
  67         {0x00004000, 0x0000001e},
  68         {0x00061000, 0x00000002},
  69         {0x00000020, 0x0000001a},
  70         {0x00004000, 0x0000001e},
  71         {0x00061000, 0x00000002},
  72         {0x00000020, 0x0000001a},
  73         {0x00004000, 0x0000001e},
  74         {0x00000016, 0x00000004},
  75         {0x0003802a, 0x00000002},
  76         {0x040067e0, 0x00000002},
  77         {0x00000016, 0x00000004},
  78         {0x000077e0, 0x00000002},
  79         {0x00065000, 0x00000002},
  80         {0x000037e1, 0x00000002},
  81         {0x040067e1, 0x00000006},
  82         {0x000077e0, 0x00000002},
  83         {0x000077e1, 0x00000002},
  84         {0x000077e1, 0x00000006},
  85         {0xffffffff, 0000000000},
  86         {0x10000000, 0000000000},
  87         {0x0003802a, 0x00000002},
  88         {0x040067e0, 0x00000006},
  89         {0x00007675, 0x00000002},
  90         {0x00007676, 0x00000002},
  91         {0x00007677, 0x00000002},
  92         {0x00007678, 0x00000006},
  93         {0x0003802b, 0x00000002},
  94         {0x04002676, 0x00000002},
  95         {0x00007677, 0x00000002},
  96         {0x00007678, 0x00000006},
  97         {0x0000002e, 0x00000018},
  98         {0x0000002e, 0x00000018},
  99         {0000000000, 0x00000006},
 100         {0x0000002f, 0x00000018},
 101         {0x0000002f, 0x00000018},
 102         {0000000000, 0x00000006},
 103         {0x01605000, 0x00000002},
 104         {0x00065000, 0x00000002},
 105         {0x00098000, 0x00000002},
 106         {0x00061000, 0x00000002},
 107         {0x64c0603d, 0x00000004},
 108         {0x00080000, 0x00000016},
 109         {0000000000, 0000000000},
 110         {0x0400251d, 0x00000002},
 111         {0x00007580, 0x00000002},
 112         {0x00067581, 0x00000002},
 113         {0x04002580, 0x00000002},
 114         {0x00067581, 0x00000002},
 115         {0x00000046, 0x00000004},
 116         {0x00005000, 0000000000},
 117         {0x00061000, 0x00000002},
 118         {0x0000750e, 0x00000002},
 119         {0x00019000, 0x00000002},
 120         {0x00011055, 0x00000014},
 121         {0x00000055, 0x00000012},
 122         {0x0400250f, 0x00000002},
 123         {0x0000504a, 0x00000004},
 124         {0x00007565, 0x00000002},
 125         {0x00007566, 0x00000002},
 126         {0x00000051, 0x00000004},
 127         {0x01e655b4, 0x00000002},
 128         {0x4401b0dc, 0x00000002},
 129         {0x01c110dc, 0x00000002},
 130         {0x2666705d, 0x00000018},
 131         {0x040c2565, 0x00000002},
 132         {0x0000005d, 0x00000018},
 133         {0x04002564, 0x00000002},
 134         {0x00007566, 0x00000002},
 135         {0x00000054, 0x00000004},
 136         {0x00401060, 0x00000008},
 137         {0x00101000, 0x00000002},
 138         {0x000d80ff, 0x00000002},
 139         {0x00800063, 0x00000008},
 140         {0x000f9000, 0x00000002},
 141         {0x000e00ff, 0x00000002},
 142         {0000000000, 0x00000006},
 143         {0x00000080, 0x00000018},
 144         {0x00000054, 0x00000004},
 145         {0x00007576, 0x00000002},
 146         {0x00065000, 0x00000002},
 147         {0x00009000, 0x00000002},
 148         {0x00041000, 0x00000002},
 149         {0x0c00350e, 0x00000002},
 150         {0x00049000, 0x00000002},
 151         {0x00051000, 0x00000002},
 152         {0x01e785f8, 0x00000002},
 153         {0x00200000, 0x00000002},
 154         {0x00600073, 0x0000000c},
 155         {0x00007563, 0x00000002},
 156         {0x006075f0, 0x00000021},
 157         {0x20007068, 0x00000004},
 158         {0x00005068, 0x00000004},
 159         {0x00007576, 0x00000002},
 160         {0x00007577, 0x00000002},
 161         {0x0000750e, 0x00000002},
 162         {0x0000750f, 0x00000002},
 163         {0x00a05000, 0x00000002},
 164         {0x00600076, 0x0000000c},
 165         {0x006075f0, 0x00000021},
 166         {0x000075f8, 0x00000002},
 167         {0x00000076, 0x00000004},
 168         {0x000a750e, 0x00000002},
 169         {0x0020750f, 0x00000002},
 170         {0x00600079, 0x00000004},
 171         {0x00007570, 0x00000002},
 172         {0x00007571, 0x00000002},
 173         {0x00007572, 0x00000006},
 174         {0x00005000, 0x00000002},
 175         {0x00a05000, 0x00000002},
 176         {0x00007568, 0x00000002},
 177         {0x00061000, 0x00000002},
 178         {0x00000084, 0x0000000c},
 179         {0x00058000, 0x00000002},
 180         {0x0c607562, 0x00000002},
 181         {0x00000086, 0x00000004},
 182         {0x00600085, 0x00000004},
 183         {0x400070dd, 0000000000},
 184         {0x000380dd, 0x00000002},
 185         {0x00000093, 0x0000001c},
 186         {0x00065095, 0x00000018},
 187         {0x040025bb, 0x00000002},
 188         {0x00061096, 0x00000018},
 189         {0x040075bc, 0000000000},
 190         {0x000075bb, 0x00000002},
 191         {0x000075bc, 0000000000},
 192         {0x00090000, 0x00000006},
 193         {0x00090000, 0x00000002},
 194         {0x000d8002, 0x00000006},
 195         {0x00005000, 0x00000002},
 196         {0x00007821, 0x00000002},
 197         {0x00007800, 0000000000},
 198         {0x00007821, 0x00000002},
 199         {0x00007800, 0000000000},
 200         {0x01665000, 0x00000002},
 201         {0x000a0000, 0x00000002},
 202         {0x000671cc, 0x00000002},
 203         {0x0286f1cd, 0x00000002},
 204         {0x000000a3, 0x00000010},
 205         {0x21007000, 0000000000},
 206         {0x000000aa, 0x0000001c},
 207         {0x00065000, 0x00000002},
 208         {0x000a0000, 0x00000002},
 209         {0x00061000, 0x00000002},
 210         {0x000b0000, 0x00000002},
 211         {0x38067000, 0x00000002},
 212         {0x000a00a6, 0x00000004},
 213         {0x20007000, 0000000000},
 214         {0x01200000, 0x00000002},
 215         {0x20077000, 0x00000002},
 216         {0x01200000, 0x00000002},
 217         {0x20007000, 0000000000},
 218         {0x00061000, 0x00000002},
 219         {0x0120751b, 0x00000002},
 220         {0x8040750a, 0x00000002},
 221         {0x8040750b, 0x00000002},
 222         {0x00110000, 0x00000002},
 223         {0x000380dd, 0x00000002},
 224         {0x000000bd, 0x0000001c},
 225         {0x00061096, 0x00000018},
 226         {0x844075bd, 0x00000002},
 227         {0x00061095, 0x00000018},
 228         {0x840075bb, 0x00000002},
 229         {0x00061096, 0x00000018},
 230         {0x844075bc, 0x00000002},
 231         {0x000000c0, 0x00000004},
 232         {0x804075bd, 0x00000002},
 233         {0x800075bb, 0x00000002},
 234         {0x804075bc, 0x00000002},
 235         {0x00108000, 0x00000002},
 236         {0x01400000, 0x00000002},
 237         {0x006000c4, 0x0000000c},
 238         {0x20c07000, 0x00000020},
 239         {0x000000c6, 0x00000012},
 240         {0x00800000, 0x00000006},
 241         {0x0080751d, 0x00000006},
 242         {0x000025bb, 0x00000002},
 243         {0x000040c0, 0x00000004},
 244         {0x0000775c, 0x00000002},
 245         {0x00a05000, 0x00000002},
 246         {0x00661000, 0x00000002},
 247         {0x0460275d, 0x00000020},
 248         {0x00004000, 0000000000},
 249         {0x00007999, 0x00000002},
 250         {0x00a05000, 0x00000002},
 251         {0x00661000, 0x00000002},
 252         {0x0460299b, 0x00000020},
 253         {0x00004000, 0000000000},
 254         {0x01e00830, 0x00000002},
 255         {0x21007000, 0000000000},
 256         {0x00005000, 0x00000002},
 257         {0x00038042, 0x00000002},
 258         {0x040025e0, 0x00000002},
 259         {0x000075e1, 0000000000},
 260         {0x00000001, 0000000000},
 261         {0x000380d9, 0x00000002},
 262         {0x04007394, 0000000000},
 263         {0000000000, 0000000000},
 264         {0000000000, 0000000000},
 265         {0000000000, 0000000000},
 266         {0000000000, 0000000000},
 267         {0000000000, 0000000000},
 268         {0000000000, 0000000000},
 269         {0000000000, 0000000000},
 270         {0000000000, 0000000000},
 271         {0000000000, 0000000000},
 272         {0000000000, 0000000000},
 273         {0000000000, 0000000000},
 274         {0000000000, 0000000000},
 275         {0000000000, 0000000000},
 276         {0000000000, 0000000000},
 277         {0000000000, 0000000000},
 278         {0000000000, 0000000000},
 279         {0000000000, 0000000000},
 280         {0000000000, 0000000000},
 281         {0000000000, 0000000000},
 282         {0000000000, 0000000000},
 283         {0000000000, 0000000000},
 284         {0000000000, 0000000000},
 285         {0000000000, 0000000000},
 286         {0000000000, 0000000000},
 287         {0000000000, 0000000000},
 288         {0000000000, 0000000000},
 289         {0000000000, 0000000000},
 290         {0000000000, 0000000000},
 291         {0000000000, 0000000000},
 292         {0000000000, 0000000000},
 293         {0000000000, 0000000000},
 294         {0000000000, 0000000000},
 295         {0000000000, 0000000000},
 296         {0000000000, 0000000000},
 297         {0000000000, 0000000000},
 298         {0000000000, 0000000000},
 299 };
 300
 301 static const u32 radeon_cp_microcode[][2] = {
 302         {0x21007000, 0000000000},
 303         {0x20007000, 0000000000},
 304         {0x000000b4, 0x00000004},
 305         {0x000000b8, 0x00000004},
 306         {0x6f5b4d4c, 0000000000},
 307         {0x4c4c427f, 0000000000},
 308         {0x5b568a92, 0000000000},
 309         {0x4ca09c6d, 0000000000},
 310         {0xad4c4c4c, 0000000000},
 311         {0x4ce1af3d, 0000000000},
 312         {0xd8afafaf, 0000000000},
 313         {0xd64c4cdc, 0000000000},
 314         {0x4cd10d10, 0000000000},
 315         {0x000f0000, 0x00000016},
 316         {0x362f242d, 0000000000},
 317         {0x00000012, 0x00000004},
 318         {0x000f0000, 0x00000016},
 319         {0x362f282d, 0000000000},
 320         {0x000380e7, 0x00000002},
 321         {0x04002c97, 0x00000002},
 322         {0x000f0001, 0x00000016},
 323         {0x333a3730, 0000000000},
 324         {0x000077ef, 0x00000002},
 325         {0x00061000, 0x00000002},
 326         {0x00000021, 0x0000001a},
 327         {0x00004000, 0x0000001e},
 328         {0x00061000, 0x00000002},
 329         {0x00000021, 0x0000001a},
 330         {0x00004000, 0x0000001e},
 331         {0x00061000, 0x00000002},
 332         {0x00000021, 0x0000001a},
 333         {0x00004000, 0x0000001e},
 334         {0x00000017, 0x00000004},
 335         {0x0003802b, 0x00000002},
 336         {0x040067e0, 0x00000002},
 337         {0x00000017, 0x00000004},
 338         {0x000077e0, 0x00000002},
 339         {0x00065000, 0x00000002},
 340         {0x000037e1, 0x00000002},
 341         {0x040067e1, 0x00000006},
 342         {0x000077e0, 0x00000002},
 343         {0x000077e1, 0x00000002},
 344         {0x000077e1, 0x00000006},
 345         {0xffffffff, 0000000000},
 346         {0x10000000, 0000000000},
 347         {0x0003802b, 0x00000002},
 348         {0x040067e0, 0x00000006},
 349         {0x00007675, 0x00000002},
 350         {0x00007676, 0x00000002},
 351         {0x00007677, 0x00000002},
 352         {0x00007678, 0x00000006},
 353         {0x0003802c, 0x00000002},
 354         {0x04002676, 0x00000002},
 355         {0x00007677, 0x00000002},
 356         {0x00007678, 0x00000006},
 357         {0x0000002f, 0x00000018},
 358         {0x0000002f, 0x00000018},
 359         {0000000000, 0x00000006},
 360         {0x00000030, 0x00000018},
 361         {0x00000030, 0x00000018},
 362         {0000000000, 0x00000006},
 363         {0x01605000, 0x00000002},
 364         {0x00065000, 0x00000002},
 365         {0x00098000, 0x00000002},
 366         {0x00061000, 0x00000002},
 367         {0x64c0603e, 0x00000004},
 368         {0x000380e6, 0x00000002},
 369         {0x040025c5, 0x00000002},
 370         {0x00080000, 0x00000016},
 371         {0000000000, 0000000000},
 372         {0x0400251d, 0x00000002},
 373         {0x00007580, 0x00000002},
 374         {0x00067581, 0x00000002},
 375         {0x04002580, 0x00000002},
 376         {0x00067581, 0x00000002},
 377         {0x00000049, 0x00000004},
 378         {0x00005000, 0000000000},
 379         {0x000380e6, 0x00000002},
 380         {0x040025c5, 0x00000002},
 381         {0x00061000, 0x00000002},
 382         {0x0000750e, 0x00000002},
 383         {0x00019000, 0x00000002},
 384         {0x00011055, 0x00000014},
 385         {0x00000055, 0x00000012},
 386         {0x0400250f, 0x00000002},
 387         {0x0000504f, 0x00000004},
 388         {0x000380e6, 0x00000002},
 389         {0x040025c5, 0x00000002},
 390         {0x00007565, 0x00000002},
 391         {0x00007566, 0x00000002},
 392         {0x00000058, 0x00000004},
 393         {0x000380e6, 0x00000002},
 394         {0x040025c5, 0x00000002},
 395         {0x01e655b4, 0x00000002},
 396         {0x4401b0e4, 0x00000002},
 397         {0x01c110e4, 0x00000002},
 398         {0x26667066, 0x00000018},
 399         {0x040c2565, 0x00000002},
 400         {0x00000066, 0x00000018},
 401         {0x04002564, 0x00000002},
 402         {0x00007566, 0x00000002},
 403         {0x0000005d, 0x00000004},
 404         {0x00401069, 0x00000008},
 405         {0x00101000, 0x00000002},
 406         {0x000d80ff, 0x00000002},
 407         {0x0080006c, 0x00000008},
 408         {0x000f9000, 0x00000002},
 409         {0x000e00ff, 0x00000002},
 410         {0000000000, 0x00000006},
 411         {0x0000008f, 0x00000018},
 412         {0x0000005b, 0x00000004},
 413         {0x000380e6, 0x00000002},
 414         {0x040025c5, 0x00000002},
 415         {0x00007576, 0x00000002},
 416         {0x00065000, 0x00000002},
 417         {0x00009000, 0x00000002},
 418         {0x00041000, 0x00000002},
 419         {0x0c00350e, 0x00000002},
 420         {0x00049000, 0x00000002},
 421         {0x00051000, 0x00000002},
 422         {0x01e785f8, 0x00000002},
 423         {0x00200000, 0x00000002},
 424         {0x0060007e, 0x0000000c},
 425         {0x00007563, 0x00000002},
 426         {0x006075f0, 0x00000021},
 427         {0x20007073, 0x00000004},
 428         {0x00005073, 0x00000004},
 429         {0x000380e6, 0x00000002},
 430         {0x040025c5, 0x00000002},
 431         {0x00007576, 0x00000002},
 432         {0x00007577, 0x00000002},
 433         {0x0000750e, 0x00000002},
 434         {0x0000750f, 0x00000002},
 435         {0x00a05000, 0x00000002},
 436         {0x00600083, 0x0000000c},
 437         {0x006075f0, 0x00000021},
 438         {0x000075f8, 0x00000002},
 439         {0x00000083, 0x00000004},
 440         {0x000a750e, 0x00000002},
 441         {0x000380e6, 0x00000002},
 442         {0x040025c5, 0x00000002},
 443         {0x0020750f, 0x00000002},
 444         {0x00600086, 0x00000004},
 445         {0x00007570, 0x00000002},
 446         {0x00007571, 0x00000002},
 447         {0x00007572, 0x00000006},
 448         {0x000380e6, 0x00000002},
 449         {0x040025c5, 0x00000002},
 450         {0x00005000, 0x00000002},
 451         {0x00a05000, 0x00000002},
 452         {0x00007568, 0x00000002},
 453         {0x00061000, 0x00000002},
 454         {0x00000095, 0x0000000c},
 455         {0x00058000, 0x00000002},
 456         {0x0c607562, 0x00000002},
 457         {0x00000097, 0x00000004},
 458         {0x000380e6, 0x00000002},
 459         {0x040025c5, 0x00000002},
 460         {0x00600096, 0x00000004},
 461         {0x400070e5, 0000000000},
 462         {0x000380e6, 0x00000002},
 463         {0x040025c5, 0x00000002},
 464         {0x000380e5, 0x00000002},
 465         {0x000000a8, 0x0000001c},
 466         {0x000650aa, 0x00000018},
 467         {0x040025bb, 0x00000002},
 468         {0x000610ab, 0x00000018},
 469         {0x040075bc, 0000000000},
 470         {0x000075bb, 0x00000002},
 471         {0x000075bc, 0000000000},
 472         {0x00090000, 0x00000006},
 473         {0x00090000, 0x00000002},
 474         {0x000d8002, 0x00000006},
 475         {0x00007832, 0x00000002},
 476         {0x00005000, 0x00000002},
 477         {0x000380e7, 0x00000002},
 478         {0x04002c97, 0x00000002},
 479         {0x00007820, 0x00000002},
 480         {0x00007821, 0x00000002},
 481         {0x00007800, 0000000000},
 482         {0x01200000, 0x00000002},
 483         {0x20077000, 0x00000002},
 484         {0x01200000, 0x00000002},
 485         {0x20007000, 0x00000002},
 486         {0x00061000, 0x00000002},
 487         {0x0120751b, 0x00000002},
 488         {0x8040750a, 0x00000002},
 489         {0x8040750b, 0x00000002},
 490         {0x00110000, 0x00000002},
 491         {0x000380e5, 0x00000002},
 492         {0x000000c6, 0x0000001c},
 493         {0x000610ab, 0x00000018},
 494         {0x844075bd, 0x00000002},
 495         {0x000610aa, 0x00000018},
 496         {0x840075bb, 0x00000002},
 497         {0x000610ab, 0x00000018},
 498         {0x844075bc, 0x00000002},
 499         {0x000000c9, 0x00000004},
 500         {0x804075bd, 0x00000002},
 501         {0x800075bb, 0x00000002},
 502         {0x804075bc, 0x00000002},
 503         {0x00108000, 0x00000002},
 504         {0x01400000, 0x00000002},
 505         {0x006000cd, 0x0000000c},
 506         {0x20c07000, 0x00000020},
 507         {0x000000cf, 0x00000012},
 508         {0x00800000, 0x00000006},
 509         {0x0080751d, 0x00000006},
 510         {0000000000, 0000000000},
 511         {0x0000775c, 0x00000002},
 512         {0x00a05000, 0x00000002},
 513         {0x00661000, 0x00000002},
 514         {0x0460275d, 0x00000020},
 515         {0x00004000, 0000000000},
 516         {0x01e00830, 0x00000002},
 517         {0x21007000, 0000000000},
 518         {0x6464614d, 0000000000},
 519         {0x69687420, 0000000000},
 520         {0x00000073, 0000000000},
 521         {0000000000, 0000000000},
 522         {0x00005000, 0x00000002},
 523         {0x000380d0, 0x00000002},
 524         {0x040025e0, 0x00000002},
 525         {0x000075e1, 0000000000},
 526         {0x00000001, 0000000000},
 527         {0x000380e0, 0x00000002},
 528         {0x04002394, 0x00000002},
 529         {0x00005000, 0000000000},
 530         {0000000000, 0000000000},
 531         {0000000000, 0000000000},
 532         {0x00000008, 0000000000},
 533         {0x00000004, 0000000000},
 534         {0000000000, 0000000000},
 535         {0000000000, 0000000000},
 536         {0000000000, 0000000000},
 537         {0000000000, 0000000000},
 538         {0000000000, 0000000000},
 539         {0000000000, 0000000000},
 540         {0000000000, 0000000000},
 541         {0000000000, 0000000000},
 542         {0000000000, 0000000000},
 543         {0000000000, 0000000000},
 544         {0000000000, 0000000000},
 545         {0000000000, 0000000000},
 546         {0000000000, 0000000000},
 547         {0000000000, 0000000000},
 548         {0000000000, 0000000000},
 549         {0000000000, 0000000000},
 550         {0000000000, 0000000000},
 551         {0000000000, 0000000000},
 552         {0000000000, 0000000000},
 553         {0000000000, 0000000000},
 554         {0000000000, 0000000000},
 555         {0000000000, 0000000000},
 556         {0000000000, 0000000000},
 557         {0000000000, 0000000000},
 558 };
 559
 560 static const u32 R300_cp_microcode[][2] = {
 561         { 0x4200e000, 0000000000 },
 562         { 0x4000e000, 0000000000 },
 563         { 0x000000af, 0x00000008 },
 564         { 0x000000b3, 0x00000008 },
 565         { 0x6c5a504f, 0000000000 },
 566         { 0x4f4f497a, 0000000000 },
 567         { 0x5a578288, 0000000000 },
 568         { 0x4f91906a, 0000000000 },
 569         { 0x4f4f4f4f, 0000000000 },
 570         { 0x4fe24f44, 0000000000 },
 571         { 0x4f9c9c9c, 0000000000 },
 572         { 0xdc4f4fde, 0000000000 },
 573         { 0xa1cd4f4f, 0000000000 },
 574         { 0xd29d9d9d, 0000000000 },
 575         { 0x4f0f9fd7, 0000000000 },
 576         { 0x000ca000, 0x00000004 },
 577         { 0x000d0012, 0x00000038 },
 578         { 0x0000e8b4, 0x00000004 },
 579         { 0x000d0014, 0x00000038 },
 580         { 0x0000e8b6, 0x00000004 },
 581         { 0x000d0016, 0x00000038 },
 582         { 0x0000e854, 0x00000004 },
 583         { 0x000d0018, 0x00000038 },
 584         { 0x0000e855, 0x00000004 },
 585         { 0x000d001a, 0x00000038 },
 586         { 0x0000e856, 0x00000004 },
 587         { 0x000d001c, 0x00000038 },
 588         { 0x0000e857, 0x00000004 },
 589         { 0x000d001e, 0x00000038 },
 590         { 0x0000e824, 0x00000004 },
 591         { 0x000d0020, 0x00000038 },
 592         { 0x0000e825, 0x00000004 },
 593         { 0x000d0022, 0x00000038 },
 594         { 0x0000e830, 0x00000004 },
 595         { 0x000d0024, 0x00000038 },
 596         { 0x0000f0c0, 0x00000004 },
 597         { 0x000d0026, 0x00000038 },
 598         { 0x0000f0c1, 0x00000004 },
 599         { 0x000d0028, 0x00000038 },
 600         { 0x0000f041, 0x00000004 },
 601         { 0x000d002a, 0x00000038 },
 602         { 0x0000f184, 0x00000004 },
 603         { 0x000d002c, 0x00000038 },
 604         { 0x0000f185, 0x00000004 },
 605         { 0x000d002e, 0x00000038 },
 606         { 0x0000f186, 0x00000004 },
 607         { 0x000d0030, 0x00000038 },
 608         { 0x0000f187, 0x00000004 },
 609         { 0x000d0032, 0x00000038 },
 610         { 0x0000f180, 0x00000004 },
 611         { 0x000d0034, 0x00000038 },
 612         { 0x0000f393, 0x00000004 },
 613         { 0x000d0036, 0x00000038 },
 614         { 0x0000f38a, 0x00000004 },
 615         { 0x000d0038, 0x00000038 },
 616         { 0x0000f38e, 0x00000004 },
 617         { 0x0000e821, 0x00000004 },
 618         { 0x0140a000, 0x00000004 },
 619         { 0x00000043, 0x00000018 },
 620         { 0x00cce800, 0x00000004 },
 621         { 0x001b0001, 0x00000004 },
 622         { 0x08004800, 0x00000004 },
 623         { 0x001b0001, 0x00000004 },
 624         { 0x08004800, 0x00000004 },
 625         { 0x001b0001, 0x00000004 },
 626         { 0x08004800, 0x00000004 },
 627         { 0x0000003a, 0x00000008 },
 628         { 0x0000a000, 0000000000 },
 629         { 0x02c0a000, 0x00000004 },
 630         { 0x000ca000, 0x00000004 },
 631         { 0x00130000, 0x00000004 },
 632         { 0x000c2000, 0x00000004 },
 633         { 0xc980c045, 0x00000008 },
 634         { 0x2000451d, 0x00000004 },
 635         { 0x0000e580, 0x00000004 },
 636         { 0x000ce581, 0x00000004 },
 637         { 0x08004580, 0x00000004 },
 638         { 0x000ce581, 0x00000004 },
 639         { 0x0000004c, 0x00000008 },
 640         { 0x0000a000, 0000000000 },
 641         { 0x000c2000, 0x00000004 },
 642         { 0x0000e50e, 0x00000004 },
 643         { 0x00032000, 0x00000004 },
 644         { 0x00022056, 0x00000028 },
 645         { 0x00000056, 0x00000024 },
 646         { 0x0800450f, 0x00000004 },
 647         { 0x0000a050, 0x00000008 },
 648         { 0x0000e565, 0x00000004 },
 649         { 0x0000e566, 0x00000004 },
 650         { 0x00000057, 0x00000008 },
 651         { 0x03cca5b4, 0x00000004 },
 652         { 0x05432000, 0x00000004 },
 653         { 0x00022000, 0x00000004 },
 654         { 0x4ccce063, 0x00000030 },
 655         { 0x08274565, 0x00000004 },
 656         { 0x00000063, 0x00000030 },
 657         { 0x08004564, 0x00000004 },
 658         { 0x0000e566, 0x00000004 },
 659         { 0x0000005a, 0x00000008 },
 660         { 0x00802066, 0x00000010 },
 661         { 0x00202000, 0x00000004 },
 662         { 0x001b00ff, 0x00000004 },
 663         { 0x01000069, 0x00000010 },
 664         { 0x001f2000, 0x00000004 },
 665         { 0x001c00ff, 0x00000004 },
 666         { 0000000000, 0x0000000c },
 667         { 0x00000085, 0x00000030 },
 668         { 0x0000005a, 0x00000008 },
 669         { 0x0000e576, 0x00000004 },
 670         { 0x000ca000, 0x00000004 },
 671         { 0x00012000, 0x00000004 },
 672         { 0x00082000, 0x00000004 },
 673         { 0x1800650e, 0x00000004 },
 674         { 0x00092000, 0x00000004 },
 675         { 0x000a2000, 0x00000004 },
 676         { 0x000f0000, 0x00000004 },
 677         { 0x00400000, 0x00000004 },
 678         { 0x00000079, 0x00000018 },
 679         { 0x0000e563, 0x00000004 },
 680         { 0x00c0e5f9, 0x000000c2 },
 681         { 0x0000006e, 0x00000008 },
 682         { 0x0000a06e, 0x00000008 },
 683         { 0x0000e576, 0x00000004 },
 684         { 0x0000e577, 0x00000004 },
 685         { 0x0000e50e, 0x00000004 },
 686         { 0x0000e50f, 0x00000004 },
 687         { 0x0140a000, 0x00000004 },
 688         { 0x0000007c, 0x00000018 },
 689         { 0x00c0e5f9, 0x000000c2 },
 690         { 0x0000007c, 0x00000008 },
 691         { 0x0014e50e, 0x00000004 },
 692         { 0x0040e50f, 0x00000004 },
 693         { 0x00c0007f, 0x00000008 },
 694         { 0x0000e570, 0x00000004 },
 695         { 0x0000e571, 0x00000004 },
 696         { 0x0000e572, 0x0000000c },
 697         { 0x0000a000, 0x00000004 },
 698         { 0x0140a000, 0x00000004 },
 699         { 0x0000e568, 0x00000004 },
 700         { 0x000c2000, 0x00000004 },
 701         { 0x00000089, 0x00000018 },
 702         { 0x000b0000, 0x00000004 },
 703         { 0x18c0e562, 0x00000004 },
 704         { 0x0000008b, 0x00000008 },
 705         { 0x00c0008a, 0x00000008 },
 706         { 0x000700e4, 0x00000004 },
 707         { 0x00000097, 0x00000038 },
 708         { 0x000ca099, 0x00000030 },
 709         { 0x080045bb, 0x00000004 },
 710         { 0x000c209a, 0x00000030 },
 711         { 0x0800e5bc, 0000000000 },
 712         { 0x0000e5bb, 0x00000004 },
 713         { 0x0000e5bc, 0000000000 },
 714         { 0x00120000, 0x0000000c },
 715         { 0x00120000, 0x00000004 },
 716         { 0x001b0002, 0x0000000c },
 717         { 0x0000a000, 0x00000004 },
 718         { 0x0000e821, 0x00000004 },
 719         { 0x0000e800, 0000000000 },
 720         { 0x0000e821, 0x00000004 },
 721         { 0x0000e82e, 0000000000 },
 722         { 0x02cca000, 0x00000004 },
 723         { 0x00140000, 0x00000004 },
 724         { 0x000ce1cc, 0x00000004 },
 725         { 0x050de1cd, 0x00000004 },
 726         { 0x000000a7, 0x00000020 },
 727         { 0x4200e000, 0000000000 },
 728         { 0x000000ae, 0x00000038 },
 729         { 0x000ca000, 0x00000004 },
 730         { 0x00140000, 0x00000004 },
 731         { 0x000c2000, 0x00000004 },
 732         { 0x00160000, 0x00000004 },
 733         { 0x700ce000, 0x00000004 },
 734         { 0x001400aa, 0x00000008 },
 735         { 0x4000e000, 0000000000 },
 736         { 0x02400000, 0x00000004 },
 737         { 0x400ee000, 0x00000004 },
 738         { 0x02400000, 0x00000004 },
 739         { 0x4000e000, 0000000000 },
 740         { 0x000c2000, 0x00000004 },
 741         { 0x0240e51b, 0x00000004 },
 742         { 0x0080e50a, 0x00000005 },
 743         { 0x0080e50b, 0x00000005 },
 744         { 0x00220000, 0x00000004 },
 745         { 0x000700e4, 0x00000004 },
 746         { 0x000000c1, 0x00000038 },
 747         { 0x000c209a, 0x00000030 },
 748         { 0x0880e5bd, 0x00000005 },
 749         { 0x000c2099, 0x00000030 },
 750         { 0x0800e5bb, 0x00000005 },
 751         { 0x000c209a, 0x00000030 },
 752         { 0x0880e5bc, 0x00000005 },
 753         { 0x000000c4, 0x00000008 },
 754         { 0x0080e5bd, 0x00000005 },
 755         { 0x0000e5bb, 0x00000005 },
 756         { 0x0080e5bc, 0x00000005 },
 757         { 0x00210000, 0x00000004 },
 758         { 0x02800000, 0x00000004 },
 759         { 0x00c000c8, 0x00000018 },
 760         { 0x4180e000, 0x00000040 },
 761         { 0x000000ca, 0x00000024 },
 762         { 0x01000000, 0x0000000c },
 763         { 0x0100e51d, 0x0000000c },
 764         { 0x000045bb, 0x00000004 },
 765         { 0x000080c4, 0x00000008 },
 766         { 0x0000f3ce, 0x00000004 },
 767         { 0x0140a000, 0x00000004 },
 768         { 0x00cc2000, 0x00000004 },
 769         { 0x08c053cf, 0x00000040 },
 770         { 0x00008000, 0000000000 },
 771         { 0x0000f3d2, 0x00000004 },
 772         { 0x0140a000, 0x00000004 },
 773         { 0x00cc2000, 0x00000004 },
 774         { 0x08c053d3, 0x00000040 },
 775         { 0x00008000, 0000000000 },
 776         { 0x0000f39d, 0x00000004 },
 777         { 0x0140a000, 0x00000004 },
 778         { 0x00cc2000, 0x00000004 },
 779         { 0x08c0539e, 0x00000040 },
 780         { 0x00008000, 0000000000 },
 781         { 0x03c00830, 0x00000004 },
 782         { 0x4200e000, 0000000000 },
 783         { 0x0000a000, 0x00000004 },
 784         { 0x200045e0, 0x00000004 },
 785         { 0x0000e5e1, 0000000000 },
 786         { 0x00000001, 0000000000 },
 787         { 0x000700e1, 0x00000004 },
 788         { 0x0800e394, 0000000000 },
 789         { 0000000000, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817 };
 818
 819 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 820 {
 821         u32 ret;
 822         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 823         ret = RADEON_READ(R520_MC_IND_DATA);
 824         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 825         return ret;
 826 }
 827
 828 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 829 {
 830         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 831         return RADEON_READ(RS690_MC_DATA);
 832 }
 833
 834 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 835 {
 836
 837         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 838                 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 839         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 840                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 841         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 842                 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 843         else
 844                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 845 }
 846
 847 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 848 {
 849         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 850                 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 851         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 852                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 853         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 854                 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 855         else
 856                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 857 }
 858
 859 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 860 {
 861         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 862                 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 863         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 864                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 865         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 866                 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 867         else
 868                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 869 }
 870
 871 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 872 {
 873         drm_radeon_private_t *dev_priv = dev->dev_private;
 874
 875         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 876         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 877 }
 878
 879 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 880 {
 881         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 882         return RADEON_READ(RADEON_PCIE_DATA);
 883 }
 884
 885 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 886 {
 887         u32 ret;
 888         RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
 889         ret = RADEON_READ(RADEON_IGPGART_DATA);
 890         RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
 891         return ret;
 892 }
 893
 894 #if RADEON_FIFO_DEBUG
 895 static void radeon_status(drm_radeon_private_t * dev_priv)
 896 {
 897         printk("%s:\n", __FUNCTION__);
 898         printk("RBBM_STATUS = 0x%08x\n",
 899                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 900         printk("CP_RB_RTPR = 0x%08x\n",
 901                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 902         printk("CP_RB_WTPR = 0x%08x\n",
 903                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 904         printk("AIC_CNTL = 0x%08x\n",
 905                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 906         printk("AIC_STAT = 0x%08x\n",
 907                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 908         printk("AIC_PT_BASE = 0x%08x\n",
 909                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 910         printk("TLB_ADDR = 0x%08x\n",
 911                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 912         printk("TLB_DATA = 0x%08x\n",
 913                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 914 }
 915 #endif
 916
 917 /* ================================================================
 918  * Engine, FIFO control
 919  */
 920
 921 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 922 {
 923         u32 tmp;
 924         int i;
 925
 926         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 927
 928         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 929         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 930         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 931
 932         for (i = 0; i < dev_priv->usec_timeout; i++) {
 933                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 934                       & RADEON_RB3D_DC_BUSY)) {
 935                         return 0;
 936                 }
 937                 DRM_UDELAY(1);
 938         }
 939
 940 #if RADEON_FIFO_DEBUG
 941         DRM_ERROR("failed!\n");
 942         radeon_status(dev_priv);
 943 #endif
 944         return -EBUSY;
 945 }
 946
 947 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 948 {
 949         int i;
 950
 951         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 952
 953         for (i = 0; i < dev_priv->usec_timeout; i++) {
 954                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 955                              & RADEON_RBBM_FIFOCNT_MASK);
 956                 if (slots >= entries)
 957                         return 0;
 958                 DRM_UDELAY(1);
 959         }
 960
 961 #if RADEON_FIFO_DEBUG
 962         DRM_ERROR("failed!\n");
 963         radeon_status(dev_priv);
 964 #endif
 965         return -EBUSY;
 966 }
 967
 968 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 969 {
 970         int i, ret;
 971
 972         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 973
 974         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 975         if (ret)
 976                 return ret;
 977
 978         for (i = 0; i < dev_priv->usec_timeout; i++) {
 979                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 980                       & RADEON_RBBM_ACTIVE)) {
 981                         radeon_do_pixcache_flush(dev_priv);
 982                         return 0;
 983                 }
 984                 DRM_UDELAY(1);
 985         }
 986
 987 #if RADEON_FIFO_DEBUG
 988         DRM_ERROR("failed!\n");
 989         radeon_status(dev_priv);
 990 #endif
 991         return -EBUSY;
 992 }
 993
 994 /* ================================================================
 995  * CP control, initialization
 996  */
 997
 998 /* Load the microcode for the CP */
 999 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1000 {
1001         int i;
1002         DRM_DEBUG("\n");
1003
1004         radeon_do_wait_for_idle(dev_priv);
1005
1006         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1007
1008         if (dev_priv->microcode_version == UCODE_R200) {
1009                 DRM_INFO("Loading R200 Microcode\n");
1010                 for (i = 0; i < 256; i++) {
1011                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1012                                      R200_cp_microcode[i][1]);
1013                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1014                                      R200_cp_microcode[i][0]);
1015                 }
1016         } else if (dev_priv->microcode_version == UCODE_R300) {
1017                 DRM_INFO("Loading R300 Microcode\n");
1018                 for (i = 0; i < 256; i++) {
1019                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1020                                      R300_cp_microcode[i][1]);
1021                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1022                                      R300_cp_microcode[i][0]);
1023                 }
1024         } else {
1025                 for (i = 0; i < 256; i++) {
1026                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1027                                      radeon_cp_microcode[i][1]);
1028                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1029                                      radeon_cp_microcode[i][0]);
1030                 }
1031         }
1032 }
1033
1034 /* Flush any pending commands to the CP.  This should only be used just
1035  * prior to a wait for idle, as it informs the engine that the command
1036  * stream is ending.
1037  */
1038 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1039 {
1040         DRM_DEBUG("\n");
1041 #if 0
1042         u32 tmp;
1043
1044         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1045         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1046 #endif
1047 }
1048
1049 /* Wait for the CP to go idle.
1050  */
1051 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1052 {
1053         RING_LOCALS;
1054         DRM_DEBUG("\n");
1055
1056         BEGIN_RING(6);
1057
1058         RADEON_PURGE_CACHE();
1059         RADEON_PURGE_ZCACHE();
1060         RADEON_WAIT_UNTIL_IDLE();
1061
1062         ADVANCE_RING();
1063         COMMIT_RING();
1064
1065         return radeon_do_wait_for_idle(dev_priv);
1066 }
1067
1068 /* Start the Command Processor.
1069  */
1070 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1071 {
1072         RING_LOCALS;
1073         DRM_DEBUG("\n");
1074
1075         radeon_do_wait_for_idle(dev_priv);
1076
1077         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1078
1079         dev_priv->cp_running = 1;
1080
1081         BEGIN_RING(6);
1082
1083         RADEON_PURGE_CACHE();
1084         RADEON_PURGE_ZCACHE();
1085         RADEON_WAIT_UNTIL_IDLE();
1086
1087         ADVANCE_RING();
1088         COMMIT_RING();
1089 }
1090
1091 /* Reset the Command Processor.  This will not flush any pending
1092  * commands, so you must wait for the CP command stream to complete
1093  * before calling this routine.
1094  */
1095 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1096 {
1097         u32 cur_read_ptr;
1098         DRM_DEBUG("\n");
1099
1100         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1101         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1102         SET_RING_HEAD(dev_priv, cur_read_ptr);
1103         dev_priv->ring.tail = cur_read_ptr;
1104 }
1105
1106 /* Stop the Command Processor.  This will not flush any pending
1107  * commands, so you must flush the command stream and wait for the CP
1108  * to go idle before calling this routine.
1109  */
1110 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1111 {
1112         DRM_DEBUG("\n");
1113
1114         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1115
1116         dev_priv->cp_running = 0;
1117 }
1118
1119 /* Reset the engine.  This will stop the CP if it is running.
1120  */
1121 static int radeon_do_engine_reset(struct drm_device * dev)
1122 {
1123         drm_radeon_private_t *dev_priv = dev->dev_private;
1124         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1125         DRM_DEBUG("\n");
1126
1127         radeon_do_pixcache_flush(dev_priv);
1128
1129         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1130                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1131                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1132
1133                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1134                                                     RADEON_FORCEON_MCLKA |
1135                                                     RADEON_FORCEON_MCLKB |
1136                                                     RADEON_FORCEON_YCLKA |
1137                                                     RADEON_FORCEON_YCLKB |
1138                                                     RADEON_FORCEON_MC |
1139                                                     RADEON_FORCEON_AIC));
1140
1141                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142
1143                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1144                                                       RADEON_SOFT_RESET_CP |
1145                                                       RADEON_SOFT_RESET_HI |
1146                                                       RADEON_SOFT_RESET_SE |
1147                                                       RADEON_SOFT_RESET_RE |
1148                                                       RADEON_SOFT_RESET_PP |
1149                                                       RADEON_SOFT_RESET_E2 |
1150                                                       RADEON_SOFT_RESET_RB));
1151                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1153                                                       ~(RADEON_SOFT_RESET_CP |
1154                                                         RADEON_SOFT_RESET_HI |
1155                                                         RADEON_SOFT_RESET_SE |
1156                                                         RADEON_SOFT_RESET_RE |
1157                                                         RADEON_SOFT_RESET_PP |
1158                                                         RADEON_SOFT_RESET_E2 |
1159                                                         RADEON_SOFT_RESET_RB)));
1160                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1161
1162                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1163                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1164                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1165         }
1166
1167         /* Reset the CP ring */
1168         radeon_do_cp_reset(dev_priv);
1169
1170         /* The CP is no longer running after an engine reset */
1171         dev_priv->cp_running = 0;
1172
1173         /* Reset any pending vertex, indirect buffers */
1174         radeon_freelist_reset(dev);
1175
1176         return 0;
1177 }
1178
1179 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1180                                        drm_radeon_private_t * dev_priv)
1181 {
1182         u32 ring_start, cur_read_ptr;
1183         u32 tmp;
1184
1185         /* Initialize the memory controller. With new memory map, the fb location
1186          * is not changed, it should have been properly initialized already. Part
1187          * of the problem is that the code below is bogus, assuming the GART is
1188          * always appended to the fb which is not necessarily the case
1189          */
1190         if (!dev_priv->new_memmap)
1191                 radeon_write_fb_location(dev_priv,
1192                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1193                              | (dev_priv->fb_location >> 16));
1194
1195 #if __OS_HAS_AGP
1196         if (dev_priv->flags & RADEON_IS_AGP) {
1197                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1198                 radeon_write_agp_location(dev_priv,
1199                              (((dev_priv->gart_vm_start - 1 +
1200                                 dev_priv->gart_size) & 0xffff0000) |
1201                               (dev_priv->gart_vm_start >> 16)));
1202
1203                 ring_start = (dev_priv->cp_ring->offset
1204                               - dev->agp->base
1205                               + dev_priv->gart_vm_start);
1206         } else
1207 #endif
1208                 ring_start = (dev_priv->cp_ring->offset
1209                               - (unsigned long)dev->sg->virtual
1210                               + dev_priv->gart_vm_start);
1211
1212         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1213
1214         /* Set the write pointer delay */
1215         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1216
1217         /* Initialize the ring buffer's read and write pointers */
1218         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1219         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1220         SET_RING_HEAD(dev_priv, cur_read_ptr);
1221         dev_priv->ring.tail = cur_read_ptr;
1222
1223 #if __OS_HAS_AGP
1224         if (dev_priv->flags & RADEON_IS_AGP) {
1225                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1226                              dev_priv->ring_rptr->offset
1227                              - dev->agp->base + dev_priv->gart_vm_start);
1228         } else
1229 #endif
1230         {
1231                 struct drm_sg_mem *entry = dev->sg;
1232                 unsigned long tmp_ofs, page_ofs;
1233
1234                 tmp_ofs = dev_priv->ring_rptr->offset -
1235                                 (unsigned long)dev->sg->virtual;
1236                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1237
1238                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1239                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1240                           (unsigned long)entry->busaddr[page_ofs],
1241                           entry->handle + tmp_ofs);
1242         }
1243
1244         /* Set ring buffer size */
1245 #ifdef __BIG_ENDIAN
1246         RADEON_WRITE(RADEON_CP_RB_CNTL,
1247                      RADEON_BUF_SWAP_32BIT |
1248                      (dev_priv->ring.fetch_size_l2ow << 18) |
1249                      (dev_priv->ring.rptr_update_l2qw << 8) |
1250                      dev_priv->ring.size_l2qw);
1251 #else
1252         RADEON_WRITE(RADEON_CP_RB_CNTL,
1253                      (dev_priv->ring.fetch_size_l2ow << 18) |
1254                      (dev_priv->ring.rptr_update_l2qw << 8) |
1255                      dev_priv->ring.size_l2qw);
1256 #endif
1257
1258         /* Start with assuming that writeback doesn't work */
1259         dev_priv->writeback_works = 0;
1260
1261         /* Initialize the scratch register pointer.  This will cause
1262          * the scratch register values to be written out to memory
1263          * whenever they are updated.
1264          *
1265          * We simply put this behind the ring read pointer, this works
1266          * with PCI GART as well as (whatever kind of) AGP GART
1267          */
1268         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1269                      + RADEON_SCRATCH_REG_OFFSET);
1270
1271         dev_priv->scratch = ((__volatile__ u32 *)
1272                              dev_priv->ring_rptr->handle +
1273                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1274
1275         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1276
1277         /* Turn on bus mastering */
1278         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1279         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1280
1281         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1282         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1283
1284         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1285         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1286                      dev_priv->sarea_priv->last_dispatch);
1287
1288         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1289         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1290
1291         radeon_do_wait_for_idle(dev_priv);
1292
1293         /* Sync everything up */
1294         RADEON_WRITE(RADEON_ISYNC_CNTL,
1295                      (RADEON_ISYNC_ANY2D_IDLE3D |
1296                       RADEON_ISYNC_ANY3D_IDLE2D |
1297                       RADEON_ISYNC_WAIT_IDLEGUI |
1298                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1299
1300 }
1301
1302 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1303 {
1304         u32 tmp;
1305
1306         /* Writeback doesn't seem to work everywhere, test it here and possibly
1307          * enable it if it appears to work
1308          */
1309         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1310         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1311
1312         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1313                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1314                     0xdeadbeef)
1315                         break;
1316                 DRM_UDELAY(1);
1317         }
1318
1319         if (tmp < dev_priv->usec_timeout) {
1320                 dev_priv->writeback_works = 1;
1321                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1322         } else {
1323                 dev_priv->writeback_works = 0;
1324                 DRM_INFO("writeback test failed\n");
1325         }
1326         if (radeon_no_wb == 1) {
1327                 dev_priv->writeback_works = 0;
1328                 DRM_INFO("writeback forced off\n");
1329         }
1330
1331         if (!dev_priv->writeback_works) {
1332                 /* Disable writeback to avoid unnecessary bus master transfers */
1333                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1334                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1335         }
1336 }
1337
1338 /* Enable or disable IGP GART on the chip */
1339 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1340 {
1341         u32 temp, tmp;
1342
1343         tmp = RADEON_READ(RADEON_AIC_CNTL);
1344         DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
1345         if (on) {
1346                 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1347                          dev_priv->gart_vm_start,
1348                          (long)dev_priv->gart_info.bus_addr,
1349                          dev_priv->gart_size);
1350
1351                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1352                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1353                 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1354                 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1355                                      dev_priv->gart_info.bus_addr);
1356
1357                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1358                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1359
1360                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1361                 dev_priv->gart_size = 32*1024*1024;
1362                 radeon_write_agp_location(dev_priv,
1363                              (((dev_priv->gart_vm_start - 1 +
1364                                dev_priv->gart_size) & 0xffff0000) |
1365                              (dev_priv->gart_vm_start >> 16)));
1366
1367                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1368                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1369
1370                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1371                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1372                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1373                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1374        }
1375 }
1376
1377 /* Enable or disable RS690 GART on the chip */
1378 static void radeon_set_rs690gart(drm_radeon_private_t * dev_priv, int on)
1379 {
1380         u32 temp;
1381
1382         if (on) {
1383                 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
1384                          dev_priv->gart_vm_start,
1385                          (long)dev_priv->gart_info.bus_addr,
1386                          dev_priv->gart_size);
1387
1388                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
1389                 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
1390
1391                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1392                   RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1393
1394                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
1395                 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
1396
1397                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
1398                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
1399                 RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp);
1400
1401                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
1402                 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
1403
1404                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
1405                                 (unsigned int)dev_priv->gart_vm_start);
1406
1407                 dev_priv->gart_size = 32*1024*1024;
1408                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1409                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
1410
1411                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
1412
1413                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
1414                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1415                       RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1416
1417                 do
1418                 {
1419                     temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1420                     if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1421                             RS690_MC_GART_CLEAR_DONE)
1422                         break;
1423                     DRM_UDELAY(1);
1424                 } while(1);
1425
1426                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1427                                     RS690_MC_GART_CC_CLEAR);
1428                 do
1429                 {
1430                     temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1431                     if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1432                             RS690_MC_GART_CLEAR_DONE)
1433                         break;
1434                     DRM_UDELAY(1);
1435                 } while(1);
1436
1437                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1438                                     RS690_MC_GART_CC_NO_CHANGE);
1439     }
1440     else
1441     {
1442         RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
1443     }
1444 }
1445
1446 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1447 {
1448         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1449         if (on) {
1450
1451                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1452                           dev_priv->gart_vm_start,
1453                           (long)dev_priv->gart_info.bus_addr,
1454                           dev_priv->gart_size);
1455                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1456                                   dev_priv->gart_vm_start);
1457                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1458                                   dev_priv->gart_info.bus_addr);
1459                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1460                                   dev_priv->gart_vm_start);
1461                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1462                                   dev_priv->gart_vm_start +
1463                                   dev_priv->gart_size - 1);
1464
1465                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1466
1467                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1468                                   RADEON_PCIE_TX_GART_EN);
1469         } else {
1470                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1471                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1472         }
1473 }
1474
1475 /* Enable or disable PCI GART on the chip */
1476 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1477 {
1478         u32 tmp;
1479
1480         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
1481         {
1482                 radeon_set_rs690gart(dev_priv, on);
1483                 return;
1484         }
1485
1486         if (dev_priv->flags & RADEON_IS_IGPGART) {
1487                 radeon_set_igpgart(dev_priv, on);
1488                 return;
1489         }
1490
1491         if (dev_priv->flags & RADEON_IS_PCIE) {
1492                 radeon_set_pciegart(dev_priv, on);
1493                 return;
1494         }
1495
1496         tmp = RADEON_READ(RADEON_AIC_CNTL);
1497
1498         if (on) {
1499                 RADEON_WRITE(RADEON_AIC_CNTL,
1500                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1501
1502                 /* set PCI GART page-table base address
1503                  */
1504                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1505
1506                 /* set address range for PCI address translate
1507                  */
1508                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1509                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1510                              + dev_priv->gart_size - 1);
1511
1512                 /* Turn off AGP aperture -- is this required for PCI GART?
1513                  */
1514                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1515                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1516         } else {
1517                 RADEON_WRITE(RADEON_AIC_CNTL,
1518                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1519         }
1520 }
1521
1522 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1523 {
1524         drm_radeon_private_t *dev_priv = dev->dev_private;
1525
1526         DRM_DEBUG("\n");
1527
1528         /* if we require new memory map but we don't have it fail */
1529         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1530                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1531                 radeon_do_cleanup_cp(dev);
1532                 return -EINVAL;
1533         }
1534
1535         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1536         {
1537                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1538                 dev_priv->flags &= ~RADEON_IS_AGP;
1539         }
1540         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1541                  && !init->is_pci)
1542         {
1543                 DRM_DEBUG("Restoring AGP flag\n");
1544                 dev_priv->flags |= RADEON_IS_AGP;
1545         }
1546
1547         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1548                 DRM_ERROR("PCI GART memory not allocated!\n");
1549                 radeon_do_cleanup_cp(dev);
1550                 return -EINVAL;
1551         }
1552
1553         dev_priv->usec_timeout = init->usec_timeout;
1554         if (dev_priv->usec_timeout < 1 ||
1555             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1556                 DRM_DEBUG("TIMEOUT problem!\n");
1557                 radeon_do_cleanup_cp(dev);
1558                 return -EINVAL;
1559         }
1560
1561         /* Enable vblank on CRTC1 for older X servers
1562          */
1563         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1564
1565         switch(init->func) {
1566         case RADEON_INIT_R200_CP:
1567                 dev_priv->microcode_version = UCODE_R200;
1568                 break;
1569         case RADEON_INIT_R300_CP:
1570                 dev_priv->microcode_version = UCODE_R300;
1571                 break;
1572         default:
1573                 dev_priv->microcode_version = UCODE_R100;
1574         }
1575
1576         dev_priv->do_boxes = 0;
1577         dev_priv->cp_mode = init->cp_mode;
1578
1579         /* We don't support anything other than bus-mastering ring mode,
1580          * but the ring can be in either AGP or PCI space for the ring
1581          * read pointer.
1582          */
1583         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1584             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1585                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1586                 radeon_do_cleanup_cp(dev);
1587                 return -EINVAL;
1588         }
1589
1590         switch (init->fb_bpp) {
1591         case 16:
1592                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1593                 break;
1594         case 32:
1595         default:
1596                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1597                 break;
1598         }
1599         dev_priv->front_offset = init->front_offset;
1600         dev_priv->front_pitch = init->front_pitch;
1601         dev_priv->back_offset = init->back_offset;
1602         dev_priv->back_pitch = init->back_pitch;
1603
1604         switch (init->depth_bpp) {
1605         case 16:
1606                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1607                 break;
1608         case 32:
1609         default:
1610                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1611                 break;
1612         }
1613         dev_priv->depth_offset = init->depth_offset;
1614         dev_priv->depth_pitch = init->depth_pitch;
1615
1616         /* Hardware state for depth clears.  Remove this if/when we no
1617          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1618          * all values to prevent unwanted 3D state from slipping through
1619          * and screwing with the clear operation.
1620          */
1621         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1622                                            (dev_priv->color_fmt << 10) |
1623                                            (dev_priv->microcode_version ==
1624                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1625
1626         dev_priv->depth_clear.rb3d_zstencilcntl =
1627             (dev_priv->depth_fmt |
1628              RADEON_Z_TEST_ALWAYS |
1629              RADEON_STENCIL_TEST_ALWAYS |
1630              RADEON_STENCIL_S_FAIL_REPLACE |
1631              RADEON_STENCIL_ZPASS_REPLACE |
1632              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1633
1634         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1635                                          RADEON_BFACE_SOLID |
1636                                          RADEON_FFACE_SOLID |
1637                                          RADEON_FLAT_SHADE_VTX_LAST |
1638                                          RADEON_DIFFUSE_SHADE_FLAT |
1639                                          RADEON_ALPHA_SHADE_FLAT |
1640                                          RADEON_SPECULAR_SHADE_FLAT |
1641                                          RADEON_FOG_SHADE_FLAT |
1642                                          RADEON_VTX_PIX_CENTER_OGL |
1643                                          RADEON_ROUND_MODE_TRUNC |
1644                                          RADEON_ROUND_PREC_8TH_PIX);
1645
1646
1647         dev_priv->ring_offset = init->ring_offset;
1648         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1649         dev_priv->buffers_offset = init->buffers_offset;
1650         dev_priv->gart_textures_offset = init->gart_textures_offset;
1651
1652         dev_priv->sarea = drm_getsarea(dev);
1653         if (!dev_priv->sarea) {
1654                 DRM_ERROR("could not find sarea!\n");
1655                 radeon_do_cleanup_cp(dev);
1656                 return -EINVAL;
1657         }
1658
1659         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1660         if (!dev_priv->cp_ring) {
1661                 DRM_ERROR("could not find cp ring region!\n");
1662                 radeon_do_cleanup_cp(dev);
1663                 return -EINVAL;
1664         }
1665         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1666         if (!dev_priv->ring_rptr) {
1667                 DRM_ERROR("could not find ring read pointer!\n");
1668                 radeon_do_cleanup_cp(dev);
1669                 return -EINVAL;
1670         }
1671         dev->agp_buffer_token = init->buffers_offset;
1672         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1673         if (!dev->agp_buffer_map) {
1674                 DRM_ERROR("could not find dma buffer region!\n");
1675                 radeon_do_cleanup_cp(dev);
1676                 return -EINVAL;
1677         }
1678
1679         if (init->gart_textures_offset) {
1680                 dev_priv->gart_textures =
1681                     drm_core_findmap(dev, init->gart_textures_offset);
1682                 if (!dev_priv->gart_textures) {
1683                         DRM_ERROR("could not find GART texture region!\n");
1684                         radeon_do_cleanup_cp(dev);
1685                         return -EINVAL;
1686                 }
1687         }
1688
1689         dev_priv->sarea_priv =
1690             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1691                                     init->sarea_priv_offset);
1692
1693 #if __OS_HAS_AGP
1694         if (dev_priv->flags & RADEON_IS_AGP) {
1695                 drm_core_ioremap(dev_priv->cp_ring, dev);
1696                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1697                 drm_core_ioremap(dev->agp_buffer_map, dev);
1698                 if (!dev_priv->cp_ring->handle ||
1699                     !dev_priv->ring_rptr->handle ||
1700                     !dev->agp_buffer_map->handle) {
1701                         DRM_ERROR("could not find ioremap agp regions!\n");
1702                         radeon_do_cleanup_cp(dev);
1703                         return -EINVAL;
1704                 }
1705         } else
1706 #endif
1707         {
1708                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1709                 dev_priv->ring_rptr->handle =
1710                     (void *)dev_priv->ring_rptr->offset;
1711                 dev->agp_buffer_map->handle =
1712                     (void *)dev->agp_buffer_map->offset;
1713
1714                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1715                           dev_priv->cp_ring->handle);
1716                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1717                           dev_priv->ring_rptr->handle);
1718                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1719                           dev->agp_buffer_map->handle);
1720         }
1721
1722         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1723         dev_priv->fb_size =
1724                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1725                 - dev_priv->fb_location;
1726
1727         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1728                                         ((dev_priv->front_offset
1729                                           + dev_priv->fb_location) >> 10));
1730
1731         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1732                                        ((dev_priv->back_offset
1733                                          + dev_priv->fb_location) >> 10));
1734
1735         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1736                                         ((dev_priv->depth_offset
1737                                           + dev_priv->fb_location) >> 10));
1738
1739         dev_priv->gart_size = init->gart_size;
1740
1741         /* New let's set the memory map ... */
1742         if (dev_priv->new_memmap) {
1743                 u32 base = 0;
1744
1745                 DRM_INFO("Setting GART location based on new memory map\n");
1746
1747                 /* If using AGP, try to locate the AGP aperture at the same
1748                  * location in the card and on the bus, though we have to
1749                  * align it down.
1750                  */
1751 #if __OS_HAS_AGP
1752                 if (dev_priv->flags & RADEON_IS_AGP) {
1753                         base = dev->agp->base;
1754                         /* Check if valid */
1755                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1756                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1757                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1758                                          dev->agp->base);
1759                                 base = 0;
1760                         }
1761                 }
1762 #endif
1763                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1764                 if (base == 0) {
1765                         base = dev_priv->fb_location + dev_priv->fb_size;
1766                         if (base < dev_priv->fb_location ||
1767                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1768                                 base = dev_priv->fb_location
1769                                         - dev_priv->gart_size;
1770                 }
1771                 dev_priv->gart_vm_start = base & 0xffc00000u;
1772                 if (dev_priv->gart_vm_start != base)
1773                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1774                                  base, dev_priv->gart_vm_start);
1775         } else {
1776                 DRM_INFO("Setting GART location based on old memory map\n");
1777                 dev_priv->gart_vm_start = dev_priv->fb_location +
1778                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1779         }
1780
1781 #if __OS_HAS_AGP
1782         if (dev_priv->flags & RADEON_IS_AGP)
1783                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1784                                                  - dev->agp->base
1785                                                  + dev_priv->gart_vm_start);
1786         else
1787 #endif
1788                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1789                                         - (unsigned long)dev->sg->virtual
1790                                         + dev_priv->gart_vm_start);
1791
1792         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1793         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1794         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1795                   dev_priv->gart_buffers_offset);
1796
1797         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1798         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1799                               + init->ring_size / sizeof(u32));
1800         dev_priv->ring.size = init->ring_size;
1801         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1802
1803         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1804         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1805
1806         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1807         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1808
1809         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1810
1811         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1812
1813 #if __OS_HAS_AGP
1814         if (dev_priv->flags & RADEON_IS_AGP) {
1815                 /* Turn off PCI GART */
1816                 radeon_set_pcigart(dev_priv, 0);
1817         } else
1818 #endif
1819         {
1820                 /* if we have an offset set from userspace */
1821                 if (dev_priv->pcigart_offset_set) {
1822                         dev_priv->gart_info.bus_addr =
1823                             dev_priv->pcigart_offset + dev_priv->fb_location;
1824                         dev_priv->gart_info.mapping.offset =
1825                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1826                         dev_priv->gart_info.mapping.size =
1827                             dev_priv->gart_info.table_size;
1828
1829                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1830                         dev_priv->gart_info.addr =
1831                             dev_priv->gart_info.mapping.handle;
1832
1833                         if (dev_priv->flags & RADEON_IS_PCIE)
1834                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1835                         else
1836                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1837                         dev_priv->gart_info.gart_table_location =
1838                             DRM_ATI_GART_FB;
1839
1840                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1841                                   dev_priv->gart_info.addr,
1842                                   dev_priv->pcigart_offset);
1843                 } else {
1844                         if (dev_priv->flags & RADEON_IS_IGPGART)
1845                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1846                         else
1847                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1848                         dev_priv->gart_info.gart_table_location =
1849                             DRM_ATI_GART_MAIN;
1850                         dev_priv->gart_info.addr = NULL;
1851                         dev_priv->gart_info.bus_addr = 0;
1852                         if (dev_priv->flags & RADEON_IS_PCIE) {
1853                                 DRM_ERROR
1854                                     ("Cannot use PCI Express without GART in FB memory\n");
1855                                 radeon_do_cleanup_cp(dev);
1856                                 return -EINVAL;
1857                         }
1858                 }
1859
1860                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1861                         DRM_ERROR("failed to init PCI GART!\n");
1862                         radeon_do_cleanup_cp(dev);
1863                         return -ENOMEM;
1864                 }
1865
1866                 /* Turn on PCI GART */
1867                 radeon_set_pcigart(dev_priv, 1);
1868         }
1869
1870         radeon_cp_load_microcode(dev_priv);
1871         radeon_cp_init_ring_buffer(dev, dev_priv);
1872
1873         dev_priv->last_buf = 0;
1874
1875         radeon_do_engine_reset(dev);
1876         radeon_test_writeback(dev_priv);
1877
1878         return 0;
1879 }
1880
1881 static int radeon_do_cleanup_cp(struct drm_device * dev)
1882 {
1883         drm_radeon_private_t *dev_priv = dev->dev_private;
1884         DRM_DEBUG("\n");
1885
1886         /* Make sure interrupts are disabled here because the uninstall ioctl
1887          * may not have been called from userspace and after dev_private
1888          * is freed, it's too late.
1889          */
1890         if (dev->irq_enabled)
1891                 drm_irq_uninstall(dev);
1892
1893 #if __OS_HAS_AGP
1894         if (dev_priv->flags & RADEON_IS_AGP) {
1895                 if (dev_priv->cp_ring != NULL) {
1896                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1897                         dev_priv->cp_ring = NULL;
1898                 }
1899                 if (dev_priv->ring_rptr != NULL) {
1900                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1901                         dev_priv->ring_rptr = NULL;
1902                 }
1903                 if (dev->agp_buffer_map != NULL) {
1904                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1905                         dev->agp_buffer_map = NULL;
1906                 }
1907         } else
1908 #endif
1909         {
1910
1911                 if (dev_priv->gart_info.bus_addr) {
1912                         /* Turn off PCI GART */
1913                         radeon_set_pcigart(dev_priv, 0);
1914                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1915                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1916                 }
1917
1918                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1919                 {
1920                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1921                         dev_priv->gart_info.addr = 0;
1922                 }
1923         }
1924         /* only clear to the start of flags */
1925         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1926
1927         return 0;
1928 }
1929
1930 /* This code will reinit the Radeon CP hardware after a resume from disc.
1931  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1932  * here we make sure that all Radeon hardware initialisation is re-done without
1933  * affecting running applications.
1934  *
1935  * Charl P. Botha <http://cpbotha.net>
1936  */
1937 static int radeon_do_resume_cp(struct drm_device * dev)
1938 {
1939         drm_radeon_private_t *dev_priv = dev->dev_private;
1940
1941         if (!dev_priv) {
1942                 DRM_ERROR("Called with no initialization\n");
1943                 return -EINVAL;
1944         }
1945
1946         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1947
1948 #if __OS_HAS_AGP
1949         if (dev_priv->flags & RADEON_IS_AGP) {
1950                 /* Turn off PCI GART */
1951                 radeon_set_pcigart(dev_priv, 0);
1952         } else
1953 #endif
1954         {
1955                 /* Turn on PCI GART */
1956                 radeon_set_pcigart(dev_priv, 1);
1957         }
1958
1959         radeon_cp_load_microcode(dev_priv);
1960         radeon_cp_init_ring_buffer(dev, dev_priv);
1961
1962         radeon_do_engine_reset(dev);
1963
1964         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1965
1966         return 0;
1967 }
1968
1969 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1970 {
1971         drm_radeon_init_t *init = data;
1972
1973         LOCK_TEST_WITH_RETURN(dev, file_priv);
1974
1975         if (init->func == RADEON_INIT_R300_CP)
1976                 r300_init_reg_flags(dev);
1977
1978         switch (init->func) {
1979         case RADEON_INIT_CP:
1980         case RADEON_INIT_R200_CP:
1981         case RADEON_INIT_R300_CP:
1982                 return radeon_do_init_cp(dev, init);
1983         case RADEON_CLEANUP_CP:
1984                 return radeon_do_cleanup_cp(dev);
1985         }
1986
1987         return -EINVAL;
1988 }
1989
1990 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1991 {
1992         drm_radeon_private_t *dev_priv = dev->dev_private;
1993         DRM_DEBUG("\n");
1994
1995         LOCK_TEST_WITH_RETURN(dev, file_priv);
1996
1997         if (dev_priv->cp_running) {
1998                 DRM_DEBUG("while CP running\n");
1999                 return 0;
2000         }
2001         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
2002                 DRM_DEBUG("called with bogus CP mode (%d)\n",
2003                           dev_priv->cp_mode);
2004                 return 0;
2005         }
2006
2007         radeon_do_cp_start(dev_priv);
2008
2009         return 0;
2010 }
2011
2012 /* Stop the CP.  The engine must have been idled before calling this
2013  * routine.
2014  */
2015 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
2016 {
2017         drm_radeon_private_t *dev_priv = dev->dev_private;
2018         drm_radeon_cp_stop_t *stop = data;
2019         int ret;
2020         DRM_DEBUG("\n");
2021
2022         LOCK_TEST_WITH_RETURN(dev, file_priv);
2023
2024         if (!dev_priv->cp_running)
2025                 return 0;
2026
2027         /* Flush any pending CP commands.  This ensures any outstanding
2028          * commands are exectuted by the engine before we turn it off.
2029          */
2030         if (stop->flush) {
2031                 radeon_do_cp_flush(dev_priv);
2032         }
2033
2034         /* If we fail to make the engine go idle, we return an error
2035          * code so that the DRM ioctl wrapper can try again.
2036          */
2037         if (stop->idle) {
2038                 ret = radeon_do_cp_idle(dev_priv);
2039                 if (ret)
2040                         return ret;
2041         }
2042
2043         /* Finally, we can turn off the CP.  If the engine isn't idle,
2044          * we will get some dropped triangles as they won't be fully
2045          * rendered before the CP is shut down.
2046          */
2047         radeon_do_cp_stop(dev_priv);
2048
2049         /* Reset the engine */
2050         radeon_do_engine_reset(dev);
2051
2052         return 0;
2053 }
2054
2055 void radeon_do_release(struct drm_device * dev)
2056 {
2057         drm_radeon_private_t *dev_priv = dev->dev_private;
2058         int i, ret;
2059
2060         if (dev_priv) {
2061                 if (dev_priv->cp_running) {
2062                         /* Stop the cp */
2063                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
2064                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
2065 #ifdef __linux__
2066                                 schedule();
2067 #else
2068 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
2069                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
2070                                        1);
2071 #else
2072                                 tsleep(&ret, PZERO, "rdnrel", 1);
2073 #endif
2074 #endif
2075                         }
2076                         radeon_do_cp_stop(dev_priv);
2077                         radeon_do_engine_reset(dev);
2078                 }
2079
2080                 /* Disable *all* interrupts */
2081                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
2082                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
2083
2084                 if (dev_priv->mmio) {   /* remove all surfaces */
2085                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2086                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
2087                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
2088                                              16 * i, 0);
2089                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
2090                                              16 * i, 0);
2091                         }
2092                 }
2093
2094                 /* Free memory heap structures */
2095                 radeon_mem_takedown(&(dev_priv->gart_heap));
2096                 radeon_mem_takedown(&(dev_priv->fb_heap));
2097
2098                 /* deallocate kernel resources */
2099                 radeon_do_cleanup_cp(dev);
2100         }
2101 }
2102
2103 /* Just reset the CP ring.  Called as part of an X Server engine reset.
2104  */
2105 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2106 {
2107         drm_radeon_private_t *dev_priv = dev->dev_private;
2108         DRM_DEBUG("\n");
2109
2110         LOCK_TEST_WITH_RETURN(dev, file_priv);
2111
2112         if (!dev_priv) {
2113                 DRM_DEBUG("called before init done\n");
2114                 return -EINVAL;
2115         }
2116
2117         radeon_do_cp_reset(dev_priv);
2118
2119         /* The CP is no longer running after an engine reset */
2120         dev_priv->cp_running = 0;
2121
2122         return 0;
2123 }
2124
2125 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
2126 {
2127         drm_radeon_private_t *dev_priv = dev->dev_private;
2128         DRM_DEBUG("\n");
2129
2130         LOCK_TEST_WITH_RETURN(dev, file_priv);
2131
2132         return radeon_do_cp_idle(dev_priv);
2133 }
2134
2135 /* Added by Charl P. Botha to call radeon_do_resume_cp().
2136  */
2137 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
2138 {
2139
2140         return radeon_do_resume_cp(dev);
2141 }
2142
2143 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2144 {
2145         DRM_DEBUG("\n");
2146
2147         LOCK_TEST_WITH_RETURN(dev, file_priv);
2148
2149         return radeon_do_engine_reset(dev);
2150 }
2151
2152 /* ================================================================
2153  * Fullscreen mode
2154  */
2155
2156 /* KW: Deprecated to say the least:
2157  */
2158 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
2159 {
2160         return 0;
2161 }
2162
2163 /* ================================================================
2164  * Freelist management
2165  */
2166
2167 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2168  *   bufs until freelist code is used.  Note this hides a problem with
2169  *   the scratch register * (used to keep track of last buffer
2170  *   completed) being written to before * the last buffer has actually
2171  *   completed rendering.
2172  *
2173  * KW:  It's also a good way to find free buffers quickly.
2174  *
2175  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2176  * sleep.  However, bugs in older versions of radeon_accel.c mean that
2177  * we essentially have to do this, else old clients will break.
2178  *
2179  * However, it does leave open a potential deadlock where all the
2180  * buffers are held by other clients, which can't release them because
2181  * they can't get the lock.
2182  */
2183
2184 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2185 {
2186         struct drm_device_dma *dma = dev->dma;
2187         drm_radeon_private_t *dev_priv = dev->dev_private;
2188         drm_radeon_buf_priv_t *buf_priv;
2189         struct drm_buf *buf;
2190         int i, t;
2191         int start;
2192
2193         if (++dev_priv->last_buf >= dma->buf_count)
2194                 dev_priv->last_buf = 0;
2195
2196         start = dev_priv->last_buf;
2197
2198         for (t = 0; t < dev_priv->usec_timeout; t++) {
2199                 u32 done_age = GET_SCRATCH(1);
2200                 DRM_DEBUG("done_age = %d\n", done_age);
2201                 for (i = start; i < dma->buf_count; i++) {
2202                         buf = dma->buflist[i];
2203                         buf_priv = buf->dev_private;
2204                         if (buf->file_priv == NULL || (buf->pending &&
2205                                                        buf_priv->age <=
2206                                                        done_age)) {
2207                                 dev_priv->stats.requested_bufs++;
2208                                 buf->pending = 0;
2209                                 return buf;
2210                         }
2211                         start = 0;
2212                 }
2213
2214                 if (t) {
2215                         DRM_UDELAY(1);
2216                         dev_priv->stats.freelist_loops++;
2217                 }
2218         }
2219
2220         DRM_DEBUG("returning NULL!\n");
2221         return NULL;
2222 }
2223
2224 #if 0
2225 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2226 {
2227         struct drm_device_dma *dma = dev->dma;
2228         drm_radeon_private_t *dev_priv = dev->dev_private;
2229         drm_radeon_buf_priv_t *buf_priv;
2230         struct drm_buf *buf;
2231         int i, t;
2232         int start;
2233         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2234
2235         if (++dev_priv->last_buf >= dma->buf_count)
2236                 dev_priv->last_buf = 0;
2237
2238         start = dev_priv->last_buf;
2239         dev_priv->stats.freelist_loops++;
2240
2241         for (t = 0; t < 2; t++) {
2242                 for (i = start; i < dma->buf_count; i++) {
2243                         buf = dma->buflist[i];
2244                         buf_priv = buf->dev_private;
2245                         if (buf->file_priv == 0 || (buf->pending &&
2246                                                     buf_priv->age <=
2247                                                     done_age)) {
2248                                 dev_priv->stats.requested_bufs++;
2249                                 buf->pending = 0;
2250                                 return buf;
2251                         }
2252                 }
2253                 start = 0;
2254         }
2255
2256         return NULL;
2257 }
2258 #endif
2259
2260 void radeon_freelist_reset(struct drm_device * dev)
2261 {
2262         struct drm_device_dma *dma = dev->dma;
2263         drm_radeon_private_t *dev_priv = dev->dev_private;
2264         int i;
2265
2266         dev_priv->last_buf = 0;
2267         for (i = 0; i < dma->buf_count; i++) {
2268                 struct drm_buf *buf = dma->buflist[i];
2269                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2270                 buf_priv->age = 0;
2271         }
2272 }
2273
2274 /* ================================================================
2275  * CP command submission
2276  */
2277
2278 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2279 {
2280         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2281         int i;
2282         u32 last_head = GET_RING_HEAD(dev_priv);
2283
2284         for (i = 0; i < dev_priv->usec_timeout; i++) {
2285                 u32 head = GET_RING_HEAD(dev_priv);
2286
2287                 ring->space = (head - ring->tail) * sizeof(u32);
2288                 if (ring->space <= 0)
2289                         ring->space += ring->size;
2290                 if (ring->space > n)
2291                         return 0;
2292
2293                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2294
2295                 if (head != last_head)
2296                         i = 0;
2297                 last_head = head;
2298
2299                 DRM_UDELAY(1);
2300         }
2301
2302         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2303 #if RADEON_FIFO_DEBUG
2304         radeon_status(dev_priv);
2305         DRM_ERROR("failed!\n");
2306 #endif
2307         return -EBUSY;
2308 }
2309
2310 static int radeon_cp_get_buffers(struct drm_device *dev,
2311                                  struct drm_file *file_priv,
2312                                  struct drm_dma * d)
2313 {
2314         int i;
2315         struct drm_buf *buf;
2316
2317         for (i = d->granted_count; i < d->request_count; i++) {
2318                 buf = radeon_freelist_get(dev);
2319                 if (!buf)
2320                         return -EBUSY;  /* NOTE: broken client */
2321
2322                 buf->file_priv = file_priv;
2323
2324                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2325                                      sizeof(buf->idx)))
2326                         return -EFAULT;
2327                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2328                                      sizeof(buf->total)))
2329                         return -EFAULT;
2330
2331                 d->granted_count++;
2332         }
2333         return 0;
2334 }
2335
2336 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2337 {
2338         struct drm_device_dma *dma = dev->dma;
2339         int ret = 0;
2340         struct drm_dma *d = data;
2341
2342         LOCK_TEST_WITH_RETURN(dev, file_priv);
2343
2344         /* Please don't send us buffers.
2345          */
2346         if (d->send_count != 0) {
2347                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2348                           DRM_CURRENTPID, d->send_count);
2349                 return -EINVAL;
2350         }
2351
2352         /* We'll send you buffers.
2353          */
2354         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2355                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2356                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2357                 return -EINVAL;
2358         }
2359
2360         d->granted_count = 0;
2361
2362         if (d->request_count) {
2363                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2364         }
2365
2366         return ret;
2367 }
2368
2369 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2370 {
2371         drm_radeon_private_t *dev_priv;
2372         int ret = 0;
2373
2374         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2375         if (dev_priv == NULL)
2376                 return -ENOMEM;
2377
2378         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2379         dev->dev_private = (void *)dev_priv;
2380         dev_priv->flags = flags;
2381
2382         switch (flags & RADEON_FAMILY_MASK) {
2383         case CHIP_R100:
2384         case CHIP_RV200:
2385         case CHIP_R200:
2386         case CHIP_R300:
2387         case CHIP_R350:
2388         case CHIP_R420:
2389         case CHIP_RV410:
2390         case CHIP_RV515:
2391         case CHIP_R520:
2392         case CHIP_RV570:
2393         case CHIP_R580:
2394                 dev_priv->flags |= RADEON_HAS_HIERZ;
2395                 break;
2396         default:
2397                 /* all other chips have no hierarchical z buffer */
2398                 break;
2399         }
2400
2401         if (drm_device_is_agp(dev))
2402                 dev_priv->flags |= RADEON_IS_AGP;
2403         else if (drm_device_is_pcie(dev))
2404                 dev_priv->flags |= RADEON_IS_PCIE;
2405         else
2406                 dev_priv->flags |= RADEON_IS_PCI;
2407
2408         DRM_DEBUG("%s card detected\n",
2409                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2410         return ret;
2411 }
2412
2413 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2414  * have to find them.
2415  */
2416 int radeon_driver_firstopen(struct drm_device *dev)
2417 {
2418         int ret;
2419         drm_local_map_t *map;
2420         drm_radeon_private_t *dev_priv = dev->dev_private;
2421
2422         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2423
2424         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2425                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2426                          _DRM_READ_ONLY, &dev_priv->mmio);
2427         if (ret != 0)
2428                 return ret;
2429
2430         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2431         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2432                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2433                          _DRM_WRITE_COMBINING, &map);
2434         if (ret != 0)
2435                 return ret;
2436
2437         return 0;
2438 }
2439
2440 int radeon_driver_unload(struct drm_device *dev)
2441 {
2442         drm_radeon_private_t *dev_priv = dev->dev_private;
2443
2444         DRM_DEBUG("\n");
2445         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2446
2447         dev->dev_private = NULL;
2448         return 0;
2449 }