shared-core/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37
  38 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
  39                                               u32 mask)
  40 {
  41         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
  42         if (irqs)
  43                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
  44         return irqs;
  45 }
  46
  47 /* Interrupts - Used for device synchronization and flushing in the
  48  * following circumstances:
  49  *
  50  * - Exclusive FB access with hw idle:
  51  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
  52  *
  53  * - Frame throttling, NV_fence:
  54  *    - Drop marker irq's into command stream ahead of time.
  55  *    - Wait on irq's with lock *not held*
  56  *    - Check each for termination condition
  57  *
  58  * - Internally in cp_getbuffer, etc:
  59  *    - as above, but wait with lock held???
  60  *
  61  * NOTE: These functions are misleadingly named -- the irq's aren't
  62  * tied to dma at all, this is just a hangover from dri prehistory.
  63  */
  64
  65 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
  66 {
  67         drm_device_t *dev = (drm_device_t *) arg;
  68         drm_radeon_private_t *dev_priv =
  69             (drm_radeon_private_t *) dev->dev_private;
  70         u32 stat;
  71
  72         /* Only consider the bits we're interested in - others could be used
  73          * outside the DRM
  74          */
  75         stat = radeon_acknowledge_irqs(dev_priv, dev_priv->irq_enable_reg);
  76         if (!stat)
  77                 return IRQ_NONE;
  78
  79         /* SW interrupt */
  80         if (stat & RADEON_SW_INT_TEST) {
  81                 DRM_WAKEUP(&dev_priv->swi_queue);
  82         }
  83
  84         /* VBLANK interrupt */
  85         if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
  86                 int vblank_crtc = dev_priv->vblank_crtc;
  87
  88                 if ((vblank_crtc &
  89                      (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
  90                     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
  91                         if (stat & RADEON_CRTC_VBLANK_STAT)
  92                                 atomic_inc(&dev->vbl_received);
  93                         if (stat & RADEON_CRTC2_VBLANK_STAT)
  94                                 atomic_inc(&dev->vbl_received2);
  95                 } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
  96                            (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
  97                            ((stat & RADEON_CRTC2_VBLANK_STAT) &&
  98                             (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
  99                         atomic_inc(&dev->vbl_received);
 100
 101                 DRM_WAKEUP(&dev->vbl_queue);
 102                 drm_vbl_send_signals(dev);
 103         }
 104
 105         return IRQ_HANDLED;
 106 }
 107
 108 static int radeon_emit_irq(drm_device_t * dev)
 109 {
 110         drm_radeon_private_t *dev_priv = dev->dev_private;
 111         unsigned int ret;
 112         RING_LOCALS;
 113
 114         atomic_inc(&dev_priv->swi_emitted);
 115         ret = atomic_read(&dev_priv->swi_emitted);
 116
 117         BEGIN_RING(4);
 118         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 119         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 120         ADVANCE_RING();
 121         COMMIT_RING();
 122
 123         return ret;
 124 }
 125
 126 static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
 127 {
 128         drm_radeon_private_t *dev_priv =
 129             (drm_radeon_private_t *) dev->dev_private;
 130         int ret = 0;
 131
 132         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 133                 return 0;
 134
 135         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 136
 137         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 138                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 139
 140         return ret;
 141 }
 142
 143 int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
 144                                  int crtc)
 145 {
 146         drm_radeon_private_t *dev_priv =
 147             (drm_radeon_private_t *) dev->dev_private;
 148         unsigned int cur_vblank;
 149         int ret = 0;
 150         int ack = 0;
 151         atomic_t *counter;
 152         if (!dev_priv) {
 153                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 154                 return DRM_ERR(EINVAL);
 155         }
 156
 157         if (crtc == DRM_RADEON_VBLANK_CRTC1) {
 158                 counter = &dev->vbl_received;
 159                 ack |= RADEON_CRTC_VBLANK_STAT;
 160         } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
 161                 counter = &dev->vbl_received2;
 162                 ack |= RADEON_CRTC2_VBLANK_STAT;
 163         } else
 164                 return DRM_ERR(EINVAL);
 165
 166         radeon_acknowledge_irqs(dev_priv, ack);
 167
 168         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 169
 170         /* Assume that the user has missed the current sequence number
 171          * by about a day rather than she wants to wait for years
 172          * using vertical blanks...
 173          */
 174         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 175                     (((cur_vblank = atomic_read(counter))
 176                       - *sequence) <= (1 << 23)));
 177
 178         *sequence = cur_vblank;
 179
 180         return ret;
 181 }
 182
 183 int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
 184 {
 185         return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
 186 }
 187
 188 int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
 189 {
 190         return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
 191 }
 192
 193 /* Needs the lock as it touches the ring.
 194  */
 195 int radeon_irq_emit(DRM_IOCTL_ARGS)
 196 {
 197         DRM_DEVICE;
 198         drm_radeon_private_t *dev_priv = dev->dev_private;
 199         drm_radeon_irq_emit_t emit;
 200         int result;
 201
 202         LOCK_TEST_WITH_RETURN(dev, filp);
 203
 204         if (!dev_priv) {
 205                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 206                 return DRM_ERR(EINVAL);
 207         }
 208
 209         DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data,
 210                                  sizeof(emit));
 211
 212         result = radeon_emit_irq(dev);
 213
 214         if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
 215                 DRM_ERROR("copy_to_user\n");
 216                 return DRM_ERR(EFAULT);
 217         }
 218
 219         return 0;
 220 }
 221
 222 /* Doesn't need the hardware lock.
 223  */
 224 int radeon_irq_wait(DRM_IOCTL_ARGS)
 225 {
 226         DRM_DEVICE;
 227         drm_radeon_private_t *dev_priv = dev->dev_private;
 228         drm_radeon_irq_wait_t irqwait;
 229
 230         if (!dev_priv) {
 231                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 232                 return DRM_ERR(EINVAL);
 233         }
 234
 235         DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data,
 236                                  sizeof(irqwait));
 237
 238         return radeon_wait_irq(dev, irqwait.irq_seq);
 239 }
 240
 241 static void radeon_enable_interrupt(drm_device_t *dev)
 242 {
 243         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 244
 245         dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
 246         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
 247                 dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
 248
 249         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
 250                 dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
 251
 252         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
 253         dev_priv->irq_enabled = 1;
 254 }
 255
 256 /* drm_dma.h hooks
 257 */
 258 void radeon_driver_irq_preinstall(drm_device_t * dev)
 259 {
 260         drm_radeon_private_t *dev_priv =
 261             (drm_radeon_private_t *) dev->dev_private;
 262
 263         /* Disable *all* interrupts */
 264         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 265
 266         /* Clear bits if they're already high */
 267         radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
 268                                            RADEON_CRTC_VBLANK_STAT));
 269 }
 270
 271 void radeon_driver_irq_postinstall(drm_device_t * dev)
 272 {
 273         drm_radeon_private_t *dev_priv =
 274             (drm_radeon_private_t *) dev->dev_private;
 275
 276         atomic_set(&dev_priv->swi_emitted, 0);
 277         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 278
 279         radeon_enable_interrupt(dev);
 280 }
 281
 282 void radeon_driver_irq_uninstall(drm_device_t * dev)
 283 {
 284         drm_radeon_private_t *dev_priv =
 285             (drm_radeon_private_t *) dev->dev_private;
 286         if (!dev_priv)
 287                 return;
 288
 289         dev_priv->irq_enabled = 0;
 290
 291         /* Disable *all* interrupts */
 292         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 293 }
 294
 295
 296 int radeon_vblank_crtc_get(drm_device_t *dev)
 297 {
 298         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 299         u32 flag;
 300         u32 value;
 301
 302         flag = RADEON_READ(RADEON_GEN_INT_CNTL);
 303         value = 0;
 304
 305         if (flag & RADEON_CRTC_VBLANK_MASK)
 306                 value |= DRM_RADEON_VBLANK_CRTC1;
 307
 308         if (flag & RADEON_CRTC2_VBLANK_MASK)
 309                 value |= DRM_RADEON_VBLANK_CRTC2;
 310         return value;
 311 }
 312
 313 int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
 314 {
 315         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 316         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 317                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 318                 return DRM_ERR(EINVAL);
 319         }
 320         dev_priv->vblank_crtc = (unsigned int)value;
 321         radeon_enable_interrupt(dev);
 322         return 0;
 323 }