1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel Dänzer <michel@daenzer.net>
36 #include "radeon_drm.h"
37 #include "radeon_drv.h"
39 /* Interrupts - Used for device synchronization and flushing in the
40 * following circumstances:
42 * - Exclusive FB access with hw idle:
43 * - Wait for GUI Idle (?) interrupt, then do normal flush.
45 * - Frame throttling, NV_fence:
46 * - Drop marker irq's into command stream ahead of time.
47 * - Wait on irq's with lock *not held*
48 * - Check each for termination condition
50 * - Internally in cp_getbuffer, etc:
51 * - as above, but wait with lock held???
53 * NOTE: These functions are misleadingly named -- the irq's aren't
54 * tied to dma at all, this is just a hangover from dri prehistory.
57 void DRM(dma_service)( DRM_IRQ_ARGS )
59 drm_device_t *dev = (drm_device_t *) arg;
60 drm_radeon_private_t *dev_priv =
61 (drm_radeon_private_t *)dev->dev_private;
64 stat = RADEON_READ(RADEON_GEN_INT_STATUS);
69 if (stat & RADEON_SW_INT_TEST) {
70 DRM_WAKEUP( &dev_priv->swi_queue );
73 /* VBLANK interrupt */
74 if (stat & RADEON_CRTC_VBLANK_STAT) {
75 atomic_inc(&dev->vbl_received);
76 DRM_WAKEUP(&dev->vbl_queue);
77 DRM(vbl_send_signals)( dev );
80 /* Acknowledge all the bits in GEN_INT_STATUS -- seem to get
81 * more than we asked for...
83 RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
86 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
88 u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS );
90 RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
93 int radeon_emit_irq(drm_device_t *dev)
95 drm_radeon_private_t *dev_priv = dev->dev_private;
99 atomic_inc(&dev_priv->swi_emitted);
100 ret = atomic_read(&dev_priv->swi_emitted);
103 OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
104 OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
112 int radeon_wait_irq(drm_device_t *dev, int swi_nr)
114 drm_radeon_private_t *dev_priv =
115 (drm_radeon_private_t *)dev->dev_private;
118 if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
121 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
123 /* This is a hack to work around mysterious freezes on certain
126 radeon_acknowledge_irqs( dev_priv );
128 DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
129 RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
134 int radeon_emit_and_wait_irq(drm_device_t *dev)
136 return radeon_wait_irq( dev, radeon_emit_irq(dev) );
140 int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
142 drm_radeon_private_t *dev_priv =
143 (drm_radeon_private_t *)dev->dev_private;
144 unsigned int cur_vblank;
148 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
149 return DRM_ERR(EINVAL);
152 radeon_acknowledge_irqs( dev_priv );
154 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
156 /* Assume that the user has missed the current sequence number
157 * by about a day rather than she wants to wait for years
158 * using vertical blanks...
160 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
161 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
162 - *sequence ) <= (1<<23) ) );
164 *sequence = cur_vblank;
170 /* Needs the lock as it touches the ring.
172 int radeon_irq_emit( DRM_IOCTL_ARGS )
175 drm_radeon_private_t *dev_priv = dev->dev_private;
176 drm_radeon_irq_emit_t emit;
179 LOCK_TEST_WITH_RETURN( dev );
182 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
183 return DRM_ERR(EINVAL);
186 DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t *)data,
189 result = radeon_emit_irq( dev );
191 if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
192 DRM_ERROR( "copy_to_user\n" );
193 return DRM_ERR(EFAULT);
200 /* Doesn't need the hardware lock.
202 int radeon_irq_wait( DRM_IOCTL_ARGS )
205 drm_radeon_private_t *dev_priv = dev->dev_private;
206 drm_radeon_irq_wait_t irqwait;
209 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
210 return DRM_ERR(EINVAL);
213 DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t *)data,
216 return radeon_wait_irq( dev, irqwait.irq_seq );
222 void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
223 drm_radeon_private_t *dev_priv =
224 (drm_radeon_private_t *)dev->dev_private;
226 /* Disable *all* interrupts */
227 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
229 /* Clear bits if they're already high */
230 radeon_acknowledge_irqs( dev_priv );
233 void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
234 drm_radeon_private_t *dev_priv =
235 (drm_radeon_private_t *)dev->dev_private;
237 atomic_set(&dev_priv->swi_emitted, 0);
238 DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
240 /* Turn on SW and VBL ints */
241 RADEON_WRITE( RADEON_GEN_INT_CNTL,
242 RADEON_CRTC_VBLANK_MASK |
243 RADEON_SW_INT_ENABLE );
246 void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
247 drm_radeon_private_t *dev_priv =
248 (drm_radeon_private_t *)dev->dev_private;
250 /* Disable *all* interrupts */
251 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );