1 /* radeon_state.c -- State support for Radeon -*- linux-c -*- */
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
32 #include "drm_sarea.h"
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
36 /* ================================================================
37 * Helper functions for client state checking and fixup
40 static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
42 drm_file_t * filp_priv,
46 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
47 struct drm_radeon_driver_file_fields *radeon_priv;
49 /* Hrm ... the story of the offset ... So this function converts
50 * the various ideas of what userland clients might have for an
51 * offset in the card address space into an offset into the card
52 * address space :) So with a sane client, it should just keep
53 * the value intact and just do some boundary checking. However,
54 * not all clients are sane. Some older clients pass us 0 based
55 * offsets relative to the start of the framebuffer and some may
56 * assume the AGP aperture it appended to the framebuffer, so we
57 * try to detect those cases and fix them up.
59 * Note: It might be a good idea here to make sure the offset lands
60 * in some "allowed" area to protect things like the PCIE GART...
63 /* First, the best case, the offset already lands in either the
64 * framebuffer or the GART mapped space
66 if (radeon_check_offset(dev_priv, off))
69 /* Ok, that didn't happen... now check if we have a zero based
70 * offset that fits in the framebuffer + gart space, apply the
71 * magic offset we get from SETPARAM or calculated from fb_location
73 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
74 radeon_priv = filp_priv->driver_priv;
75 off += radeon_priv->radeon_fb_delta;
78 /* Finally, assume we aimed at a GART offset if beyond the fb */
80 off = off - fb_end - 1 + dev_priv->gart_vm_start;
82 /* Now recheck and fail if out of bounds */
83 if (radeon_check_offset(dev_priv, off)) {
84 DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
88 return DRM_ERR(EINVAL);
91 static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
93 drm_file_t * filp_priv,
98 case RADEON_EMIT_PP_MISC:
99 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
100 &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
101 DRM_ERROR("Invalid depth buffer offset\n");
102 return DRM_ERR(EINVAL);
106 case RADEON_EMIT_PP_CNTL:
107 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
108 &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
109 DRM_ERROR("Invalid colour buffer offset\n");
110 return DRM_ERR(EINVAL);
114 case R200_EMIT_PP_TXOFFSET_0:
115 case R200_EMIT_PP_TXOFFSET_1:
116 case R200_EMIT_PP_TXOFFSET_2:
117 case R200_EMIT_PP_TXOFFSET_3:
118 case R200_EMIT_PP_TXOFFSET_4:
119 case R200_EMIT_PP_TXOFFSET_5:
120 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
122 DRM_ERROR("Invalid R200 texture offset\n");
123 return DRM_ERR(EINVAL);
127 case RADEON_EMIT_PP_TXFILTER_0:
128 case RADEON_EMIT_PP_TXFILTER_1:
129 case RADEON_EMIT_PP_TXFILTER_2:
130 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
131 &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
132 DRM_ERROR("Invalid R100 texture offset\n");
133 return DRM_ERR(EINVAL);
137 case R200_EMIT_PP_CUBIC_OFFSETS_0:
138 case R200_EMIT_PP_CUBIC_OFFSETS_1:
139 case R200_EMIT_PP_CUBIC_OFFSETS_2:
140 case R200_EMIT_PP_CUBIC_OFFSETS_3:
141 case R200_EMIT_PP_CUBIC_OFFSETS_4:
142 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
144 for (i = 0; i < 5; i++) {
145 if (radeon_check_and_fixup_offset(dev_priv,
149 ("Invalid R200 cubic texture offset\n");
150 return DRM_ERR(EINVAL);
156 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
157 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
158 case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
160 for (i = 0; i < 5; i++) {
161 if (radeon_check_and_fixup_offset(dev_priv,
165 ("Invalid R100 cubic texture offset\n");
166 return DRM_ERR(EINVAL);
172 case R200_EMIT_VAP_CTL: {
175 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
180 case RADEON_EMIT_RB3D_COLORPITCH:
181 case RADEON_EMIT_RE_LINE_PATTERN:
182 case RADEON_EMIT_SE_LINE_WIDTH:
183 case RADEON_EMIT_PP_LUM_MATRIX:
184 case RADEON_EMIT_PP_ROT_MATRIX_0:
185 case RADEON_EMIT_RB3D_STENCILREFMASK:
186 case RADEON_EMIT_SE_VPORT_XSCALE:
187 case RADEON_EMIT_SE_CNTL:
188 case RADEON_EMIT_SE_CNTL_STATUS:
189 case RADEON_EMIT_RE_MISC:
190 case RADEON_EMIT_PP_BORDER_COLOR_0:
191 case RADEON_EMIT_PP_BORDER_COLOR_1:
192 case RADEON_EMIT_PP_BORDER_COLOR_2:
193 case RADEON_EMIT_SE_ZBIAS_FACTOR:
194 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
195 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
196 case R200_EMIT_PP_TXCBLEND_0:
197 case R200_EMIT_PP_TXCBLEND_1:
198 case R200_EMIT_PP_TXCBLEND_2:
199 case R200_EMIT_PP_TXCBLEND_3:
200 case R200_EMIT_PP_TXCBLEND_4:
201 case R200_EMIT_PP_TXCBLEND_5:
202 case R200_EMIT_PP_TXCBLEND_6:
203 case R200_EMIT_PP_TXCBLEND_7:
204 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
205 case R200_EMIT_TFACTOR_0:
206 case R200_EMIT_VTX_FMT_0:
207 case R200_EMIT_MATRIX_SELECT_0:
208 case R200_EMIT_TEX_PROC_CTL_2:
209 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
210 case R200_EMIT_PP_TXFILTER_0:
211 case R200_EMIT_PP_TXFILTER_1:
212 case R200_EMIT_PP_TXFILTER_2:
213 case R200_EMIT_PP_TXFILTER_3:
214 case R200_EMIT_PP_TXFILTER_4:
215 case R200_EMIT_PP_TXFILTER_5:
216 case R200_EMIT_VTE_CNTL:
217 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
218 case R200_EMIT_PP_TAM_DEBUG3:
219 case R200_EMIT_PP_CNTL_X:
220 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
221 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
222 case R200_EMIT_RE_SCISSOR_TL_0:
223 case R200_EMIT_RE_SCISSOR_TL_1:
224 case R200_EMIT_RE_SCISSOR_TL_2:
225 case R200_EMIT_SE_VAP_CNTL_STATUS:
226 case R200_EMIT_SE_VTX_STATE_CNTL:
227 case R200_EMIT_RE_POINTSIZE:
228 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
229 case R200_EMIT_PP_CUBIC_FACES_0:
230 case R200_EMIT_PP_CUBIC_FACES_1:
231 case R200_EMIT_PP_CUBIC_FACES_2:
232 case R200_EMIT_PP_CUBIC_FACES_3:
233 case R200_EMIT_PP_CUBIC_FACES_4:
234 case R200_EMIT_PP_CUBIC_FACES_5:
235 case RADEON_EMIT_PP_TEX_SIZE_0:
236 case RADEON_EMIT_PP_TEX_SIZE_1:
237 case RADEON_EMIT_PP_TEX_SIZE_2:
238 case R200_EMIT_RB3D_BLENDCOLOR:
239 case R200_EMIT_TCL_POINT_SPRITE_CNTL:
240 case RADEON_EMIT_PP_CUBIC_FACES_0:
241 case RADEON_EMIT_PP_CUBIC_FACES_1:
242 case RADEON_EMIT_PP_CUBIC_FACES_2:
243 case R200_EMIT_PP_TRI_PERF_CNTL:
244 case R200_EMIT_PP_AFS_0:
245 case R200_EMIT_PP_AFS_1:
246 case R200_EMIT_ATF_TFACTOR:
247 case R200_EMIT_PP_TXCTLALL_0:
248 case R200_EMIT_PP_TXCTLALL_1:
249 case R200_EMIT_PP_TXCTLALL_2:
250 case R200_EMIT_PP_TXCTLALL_3:
251 case R200_EMIT_PP_TXCTLALL_4:
252 case R200_EMIT_PP_TXCTLALL_5:
253 case R200_EMIT_VAP_PVS_CNTL:
254 /* These packets don't contain memory offsets */
258 DRM_ERROR("Unknown state packet ID %d\n", id);
259 return DRM_ERR(EINVAL);
265 static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
267 drm_file_t *filp_priv,
268 drm_radeon_kcmd_buffer_t *
272 u32 *cmd = (u32 *) cmdbuf->buf;
276 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
278 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
279 DRM_ERROR("Not a type 3 packet\n");
280 return DRM_ERR(EINVAL);
283 if (4 * *cmdsz > cmdbuf->bufsz) {
284 DRM_ERROR("Packet size larger than size of data provided\n");
285 return DRM_ERR(EINVAL);
288 switch(cmd[0] & 0xff00) {
289 /* XXX Are there old drivers needing other packets? */
291 case RADEON_3D_DRAW_IMMD:
292 case RADEON_3D_DRAW_VBUF:
293 case RADEON_3D_DRAW_INDX:
294 case RADEON_WAIT_FOR_IDLE:
296 case RADEON_3D_CLEAR_ZMASK:
297 /* case RADEON_CP_NEXT_CHAR:
298 case RADEON_CP_PLY_NEXTSCAN:
299 case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
300 /* these packets are safe */
303 case RADEON_CP_3D_DRAW_IMMD_2:
304 case RADEON_CP_3D_DRAW_VBUF_2:
305 case RADEON_CP_3D_DRAW_INDX_2:
306 case RADEON_3D_CLEAR_HIZ:
307 /* safe but r200 only */
308 if (dev_priv->microcode_version != UCODE_R200) {
309 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
310 return DRM_ERR(EINVAL);
314 case RADEON_3D_LOAD_VBPNTR:
315 count = (cmd[0] >> 16) & 0x3fff;
317 if (count > 18) { /* 12 arrays max */
318 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
320 return DRM_ERR(EINVAL);
323 /* carefully check packet contents */
324 narrays = cmd[1] & ~0xc000;
327 while ((k < narrays) && (i < (count + 2))) {
328 i++; /* skip attribute field */
329 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) {
331 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
333 return DRM_ERR(EINVAL);
339 /* have one more to process, they come in pairs */
340 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) {
342 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
344 return DRM_ERR(EINVAL);
349 /* do the counts match what we expect ? */
350 if ((k != narrays) || (i != (count + 2))) {
352 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
353 k, i, narrays, count + 1);
354 return DRM_ERR(EINVAL);
358 case RADEON_3D_RNDR_GEN_INDX_PRIM:
359 if (dev_priv->microcode_version != UCODE_R100) {
360 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
361 return DRM_ERR(EINVAL);
363 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) {
364 DRM_ERROR("Invalid rndr_gen_indx offset\n");
365 return DRM_ERR(EINVAL);
369 case RADEON_CP_INDX_BUFFER:
370 if (dev_priv->microcode_version != UCODE_R200) {
371 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
372 return DRM_ERR(EINVAL);
374 if ((cmd[1] & 0x8000ffff) != 0x80000810) {
375 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
376 return DRM_ERR(EINVAL);
378 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) {
379 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
380 return DRM_ERR(EINVAL);
384 case RADEON_CNTL_HOSTDATA_BLT:
385 case RADEON_CNTL_PAINT_MULTI:
386 case RADEON_CNTL_BITBLT_MULTI:
387 /* MSB of opcode: next DWORD GUI_CNTL */
388 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
389 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
390 offset = cmd[2] << 10;
391 if (radeon_check_and_fixup_offset
392 (dev_priv, filp_priv, &offset)) {
393 DRM_ERROR("Invalid first packet offset\n");
394 return DRM_ERR(EINVAL);
396 cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
399 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
400 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
401 offset = cmd[3] << 10;
402 if (radeon_check_and_fixup_offset
403 (dev_priv, filp_priv, &offset)) {
404 DRM_ERROR("Invalid second packet offset\n");
405 return DRM_ERR(EINVAL);
407 cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
412 DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00);
413 return DRM_ERR(EINVAL);
419 /* ================================================================
420 * CP hardware state programming functions
423 static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
424 drm_clip_rect_t * box)
428 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
429 box->x1, box->y1, box->x2, box->y2);
432 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
433 OUT_RING((box->y1 << 16) | box->x1);
434 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
435 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
441 static int radeon_emit_state(drm_radeon_private_t * dev_priv,
442 drm_file_t * filp_priv,
443 drm_radeon_context_regs_t * ctx,
444 drm_radeon_texture_regs_t * tex,
448 DRM_DEBUG("dirty=0x%08x\n", dirty);
450 if (dirty & RADEON_UPLOAD_CONTEXT) {
451 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
452 &ctx->rb3d_depthoffset)) {
453 DRM_ERROR("Invalid depth buffer offset\n");
454 return DRM_ERR(EINVAL);
457 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
458 &ctx->rb3d_coloroffset)) {
459 DRM_ERROR("Invalid depth buffer offset\n");
460 return DRM_ERR(EINVAL);
464 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
465 OUT_RING(ctx->pp_misc);
466 OUT_RING(ctx->pp_fog_color);
467 OUT_RING(ctx->re_solid_color);
468 OUT_RING(ctx->rb3d_blendcntl);
469 OUT_RING(ctx->rb3d_depthoffset);
470 OUT_RING(ctx->rb3d_depthpitch);
471 OUT_RING(ctx->rb3d_zstencilcntl);
472 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
473 OUT_RING(ctx->pp_cntl);
474 OUT_RING(ctx->rb3d_cntl);
475 OUT_RING(ctx->rb3d_coloroffset);
476 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
477 OUT_RING(ctx->rb3d_colorpitch);
481 if (dirty & RADEON_UPLOAD_VERTFMT) {
483 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
484 OUT_RING(ctx->se_coord_fmt);
488 if (dirty & RADEON_UPLOAD_LINE) {
490 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
491 OUT_RING(ctx->re_line_pattern);
492 OUT_RING(ctx->re_line_state);
493 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
494 OUT_RING(ctx->se_line_width);
498 if (dirty & RADEON_UPLOAD_BUMPMAP) {
500 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
501 OUT_RING(ctx->pp_lum_matrix);
502 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
503 OUT_RING(ctx->pp_rot_matrix_0);
504 OUT_RING(ctx->pp_rot_matrix_1);
508 if (dirty & RADEON_UPLOAD_MASKS) {
510 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
511 OUT_RING(ctx->rb3d_stencilrefmask);
512 OUT_RING(ctx->rb3d_ropcntl);
513 OUT_RING(ctx->rb3d_planemask);
517 if (dirty & RADEON_UPLOAD_VIEWPORT) {
519 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
520 OUT_RING(ctx->se_vport_xscale);
521 OUT_RING(ctx->se_vport_xoffset);
522 OUT_RING(ctx->se_vport_yscale);
523 OUT_RING(ctx->se_vport_yoffset);
524 OUT_RING(ctx->se_vport_zscale);
525 OUT_RING(ctx->se_vport_zoffset);
529 if (dirty & RADEON_UPLOAD_SETUP) {
531 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
532 OUT_RING(ctx->se_cntl);
533 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
534 OUT_RING(ctx->se_cntl_status);
538 if (dirty & RADEON_UPLOAD_MISC) {
540 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
541 OUT_RING(ctx->re_misc);
545 if (dirty & RADEON_UPLOAD_TEX0) {
546 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
547 &tex[0].pp_txoffset)) {
548 DRM_ERROR("Invalid texture offset for unit 0\n");
549 return DRM_ERR(EINVAL);
553 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
554 OUT_RING(tex[0].pp_txfilter);
555 OUT_RING(tex[0].pp_txformat);
556 OUT_RING(tex[0].pp_txoffset);
557 OUT_RING(tex[0].pp_txcblend);
558 OUT_RING(tex[0].pp_txablend);
559 OUT_RING(tex[0].pp_tfactor);
560 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
561 OUT_RING(tex[0].pp_border_color);
565 if (dirty & RADEON_UPLOAD_TEX1) {
566 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
567 &tex[1].pp_txoffset)) {
568 DRM_ERROR("Invalid texture offset for unit 1\n");
569 return DRM_ERR(EINVAL);
573 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
574 OUT_RING(tex[1].pp_txfilter);
575 OUT_RING(tex[1].pp_txformat);
576 OUT_RING(tex[1].pp_txoffset);
577 OUT_RING(tex[1].pp_txcblend);
578 OUT_RING(tex[1].pp_txablend);
579 OUT_RING(tex[1].pp_tfactor);
580 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
581 OUT_RING(tex[1].pp_border_color);
585 if (dirty & RADEON_UPLOAD_TEX2) {
586 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
587 &tex[2].pp_txoffset)) {
588 DRM_ERROR("Invalid texture offset for unit 2\n");
589 return DRM_ERR(EINVAL);
593 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
594 OUT_RING(tex[2].pp_txfilter);
595 OUT_RING(tex[2].pp_txformat);
596 OUT_RING(tex[2].pp_txoffset);
597 OUT_RING(tex[2].pp_txcblend);
598 OUT_RING(tex[2].pp_txablend);
599 OUT_RING(tex[2].pp_tfactor);
600 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
601 OUT_RING(tex[2].pp_border_color);
610 static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
611 drm_file_t * filp_priv,
612 drm_radeon_state_t * state)
616 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
618 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
619 OUT_RING(state->context2.se_zbias_factor);
620 OUT_RING(state->context2.se_zbias_constant);
624 return radeon_emit_state(dev_priv, filp_priv, &state->context,
625 state->tex, state->dirty);
628 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
629 * 1.3 cmdbuffers allow all previous state to be updated as well as
630 * the tcl scalar and vector areas.
636 } packet[RADEON_MAX_STATE_PACKETS] = {
637 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
638 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
639 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
640 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
641 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
642 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
643 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
644 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
645 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
646 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
647 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
648 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
649 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
650 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
651 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
652 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
653 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
654 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
655 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
656 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
657 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
658 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
659 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
660 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
661 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
662 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
663 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
664 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
665 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
666 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
667 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
668 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
669 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
670 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
671 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
672 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
673 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
674 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
675 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
676 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
677 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
678 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
679 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
680 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
681 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
682 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
683 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
684 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
685 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
686 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
687 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
688 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
689 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
690 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
691 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
692 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
693 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
694 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
695 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
696 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
697 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
698 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
699 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
700 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
701 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
702 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
703 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
704 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
705 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
706 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
707 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
708 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
709 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
710 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
711 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
712 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
713 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
714 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
715 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
716 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
717 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
718 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
719 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
720 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
721 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
722 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
723 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
724 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
725 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
726 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
727 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
728 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
729 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
730 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
731 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
732 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
733 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
734 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
737 /* ================================================================
738 * Performance monitoring functions
741 static void radeon_clear_box(drm_radeon_private_t * dev_priv,
742 int x, int y, int w, int h, int r, int g, int b)
747 x += dev_priv->sarea_priv->boxes[0].x1;
748 y += dev_priv->sarea_priv->boxes[0].y1;
750 switch (dev_priv->color_fmt) {
751 case RADEON_COLOR_FORMAT_RGB565:
752 color = (((r & 0xf8) << 8) |
753 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
755 case RADEON_COLOR_FORMAT_ARGB8888:
757 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
762 RADEON_WAIT_UNTIL_3D_IDLE();
763 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
764 OUT_RING(0xffffffff);
769 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
770 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
771 RADEON_GMC_BRUSH_SOLID_COLOR |
772 (dev_priv->color_fmt << 8) |
773 RADEON_GMC_SRC_DATATYPE_COLOR |
774 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
776 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
777 OUT_RING(dev_priv->front_pitch_offset);
779 OUT_RING(dev_priv->back_pitch_offset);
784 OUT_RING((x << 16) | y);
785 OUT_RING((w << 16) | h);
790 static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
792 /* Collapse various things into a wait flag -- trying to
793 * guess if userspase slept -- better just to have them tell us.
795 if (dev_priv->stats.last_frame_reads > 1 ||
796 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
797 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
800 if (dev_priv->stats.freelist_loops) {
801 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
804 /* Purple box for page flipping
806 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
807 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
809 /* Red box if we have to wait for idle at any point
811 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
812 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
814 /* Blue box: lost context?
817 /* Yellow box for texture swaps
819 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
820 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
822 /* Green box if hardware never idles (as far as we can tell)
824 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
825 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
827 /* Draw bars indicating number of buffers allocated
828 * (not a great measure, easily confused)
830 if (dev_priv->stats.requested_bufs) {
831 if (dev_priv->stats.requested_bufs > 100)
832 dev_priv->stats.requested_bufs = 100;
834 radeon_clear_box(dev_priv, 4, 16,
835 dev_priv->stats.requested_bufs, 4,
839 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
843 /* ================================================================
844 * CP command dispatch functions
847 static void radeon_cp_dispatch_clear(drm_device_t * dev,
848 drm_radeon_clear_t * clear,
849 drm_radeon_clear_rect_t * depth_boxes)
851 drm_radeon_private_t *dev_priv = dev->dev_private;
852 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
853 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
854 int nbox = sarea_priv->nbox;
855 drm_clip_rect_t *pbox = sarea_priv->boxes;
856 unsigned int flags = clear->flags;
857 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
860 DRM_DEBUG("flags = 0x%x\n", flags);
862 dev_priv->stats.clears++;
864 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
865 unsigned int tmp = flags;
867 flags &= ~(RADEON_FRONT | RADEON_BACK);
868 if (tmp & RADEON_FRONT)
869 flags |= RADEON_BACK;
870 if (tmp & RADEON_BACK)
871 flags |= RADEON_FRONT;
874 if (flags & (RADEON_FRONT | RADEON_BACK)) {
878 /* Ensure the 3D stream is idle before doing a
879 * 2D fill to clear the front or back buffer.
881 RADEON_WAIT_UNTIL_3D_IDLE();
883 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
884 OUT_RING(clear->color_mask);
888 /* Make sure we restore the 3D state next time.
890 dev_priv->sarea_priv->ctx_owner = 0;
892 for (i = 0; i < nbox; i++) {
895 int w = pbox[i].x2 - x;
896 int h = pbox[i].y2 - y;
898 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
901 if (flags & RADEON_FRONT) {
905 (RADEON_CNTL_PAINT_MULTI, 4));
906 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
907 RADEON_GMC_BRUSH_SOLID_COLOR |
910 RADEON_GMC_SRC_DATATYPE_COLOR |
912 RADEON_GMC_CLR_CMP_CNTL_DIS);
914 OUT_RING(dev_priv->front_pitch_offset);
915 OUT_RING(clear->clear_color);
917 OUT_RING((x << 16) | y);
918 OUT_RING((w << 16) | h);
923 if (flags & RADEON_BACK) {
927 (RADEON_CNTL_PAINT_MULTI, 4));
928 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
929 RADEON_GMC_BRUSH_SOLID_COLOR |
932 RADEON_GMC_SRC_DATATYPE_COLOR |
934 RADEON_GMC_CLR_CMP_CNTL_DIS);
936 OUT_RING(dev_priv->back_pitch_offset);
937 OUT_RING(clear->clear_color);
939 OUT_RING((x << 16) | y);
940 OUT_RING((w << 16) | h);
948 /* no docs available, based on reverse engeneering by Stephane Marchesin */
949 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
950 && (flags & RADEON_CLEAR_FASTZ)) {
953 int depthpixperline =
954 dev_priv->depth_fmt ==
955 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
961 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
962 ((clear->depth_mask & 0xff) << 24);
964 /* Make sure we restore the 3D state next time.
965 * we haven't touched any "normal" state - still need this?
967 dev_priv->sarea_priv->ctx_owner = 0;
969 if ((dev_priv->flags & RADEON_HAS_HIERZ)
970 && (flags & RADEON_USE_HIERZ)) {
971 /* FIXME : reverse engineer that for Rx00 cards */
972 /* FIXME : the mask supposedly contains low-res z values. So can't set
973 just to the max (0xff? or actually 0x3fff?), need to take z clear
974 value into account? */
975 /* pattern seems to work for r100, though get slight
976 rendering errors with glxgears. If hierz is not enabled for r100,
977 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
978 other ones are ignored, and the same clear mask can be used. That's
979 very different behaviour than R200 which needs different clear mask
980 and different number of tiles to clear if hierz is enabled or not !?!
982 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
984 /* clear mask : chooses the clearing pattern.
985 rv250: could be used to clear only parts of macrotiles
986 (but that would get really complicated...)?
987 bit 0 and 1 (either or both of them ?!?!) are used to
988 not clear tile (or maybe one of the bits indicates if the tile is
989 compressed or not), bit 2 and 3 to not clear tile 1,...,.
990 Pattern is as follows:
991 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
992 bits -------------------------------------------------
993 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
994 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
995 covers 256 pixels ?!?
1001 RADEON_WAIT_UNTIL_2D_IDLE();
1002 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1003 tempRB3D_DEPTHCLEARVALUE);
1004 /* what offset is this exactly ? */
1005 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
1006 /* need ctlstat, otherwise get some strange black flickering */
1007 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1008 RADEON_RB3D_ZC_FLUSH_ALL);
1011 for (i = 0; i < nbox; i++) {
1012 int tileoffset, nrtilesx, nrtilesy, j;
1013 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
1014 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1015 && !(dev_priv->microcode_version == UCODE_R200)) {
1016 /* FIXME : figure this out for r200 (when hierz is enabled). Or
1017 maybe r200 actually doesn't need to put the low-res z value into
1018 the tile cache like r100, but just needs to clear the hi-level z-buffer?
1019 Works for R100, both with hierz and without.
1020 R100 seems to operate on 2x1 8x8 tiles, but...
1021 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
1022 problematic with resolutions which are not 64 pix aligned? */
1024 ((pbox[i].y1 >> 3) * depthpixperline +
1027 ((pbox[i].x2 & ~63) -
1028 (pbox[i].x1 & ~63)) >> 4;
1030 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1031 for (j = 0; j <= nrtilesy; j++) {
1034 (RADEON_3D_CLEAR_ZMASK, 2));
1036 OUT_RING(tileoffset * 8);
1037 /* the number of tiles to clear */
1038 OUT_RING(nrtilesx + 4);
1039 /* clear mask : chooses the clearing pattern. */
1040 OUT_RING(clearmask);
1042 tileoffset += depthpixperline >> 6;
1044 } else if (dev_priv->microcode_version == UCODE_R200) {
1045 /* works for rv250. */
1046 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
1048 ((pbox[i].y1 >> 3) * depthpixperline +
1051 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
1053 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1054 for (j = 0; j <= nrtilesy; j++) {
1057 (RADEON_3D_CLEAR_ZMASK, 2));
1059 /* judging by the first tile offset needed, could possibly
1060 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1061 macro tiles, though would still need clear mask for
1062 right/bottom if truely 4x4 granularity is desired ? */
1063 OUT_RING(tileoffset * 16);
1064 /* the number of tiles to clear */
1065 OUT_RING(nrtilesx + 1);
1066 /* clear mask : chooses the clearing pattern. */
1067 OUT_RING(clearmask);
1069 tileoffset += depthpixperline >> 5;
1071 } else { /* rv 100 */
1072 /* rv100 might not need 64 pix alignment, who knows */
1073 /* offsets are, hmm, weird */
1075 ((pbox[i].y1 >> 4) * depthpixperline +
1078 ((pbox[i].x2 & ~63) -
1079 (pbox[i].x1 & ~63)) >> 4;
1081 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
1082 for (j = 0; j <= nrtilesy; j++) {
1085 (RADEON_3D_CLEAR_ZMASK, 2));
1086 OUT_RING(tileoffset * 128);
1087 /* the number of tiles to clear */
1088 OUT_RING(nrtilesx + 4);
1089 /* clear mask : chooses the clearing pattern. */
1090 OUT_RING(clearmask);
1092 tileoffset += depthpixperline >> 6;
1097 /* TODO don't always clear all hi-level z tiles */
1098 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1099 && (dev_priv->microcode_version == UCODE_R200)
1100 && (flags & RADEON_USE_HIERZ))
1101 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
1102 /* FIXME : the mask supposedly contains low-res z values. So can't set
1103 just to the max (0xff? or actually 0x3fff?), need to take z clear
1104 value into account? */
1107 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1108 OUT_RING(0x0); /* First tile */
1110 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
1115 /* We have to clear the depth and/or stencil buffers by
1116 * rendering a quad into just those buffers. Thus, we have to
1117 * make sure the 3D engine is configured correctly.
1119 else if ((dev_priv->microcode_version == UCODE_R200) &&
1120 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1125 int tempRB3D_ZSTENCILCNTL;
1126 int tempRB3D_STENCILREFMASK;
1127 int tempRB3D_PLANEMASK;
1129 int tempSE_VTE_CNTL;
1130 int tempSE_VTX_FMT_0;
1131 int tempSE_VTX_FMT_1;
1132 int tempSE_VAP_CNTL;
1133 int tempRE_AUX_SCISSOR_CNTL;
1138 tempRB3D_CNTL = depth_clear->rb3d_cntl;
1140 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1141 tempRB3D_STENCILREFMASK = 0x0;
1143 tempSE_CNTL = depth_clear->se_cntl;
1147 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
1149 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
1151 tempRB3D_PLANEMASK = 0x0;
1153 tempRE_AUX_SCISSOR_CNTL = 0x0;
1156 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
1158 /* Vertex format (X, Y, Z, W) */
1160 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
1161 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
1162 tempSE_VTX_FMT_1 = 0x0;
1165 * Depth buffer specific enables
1167 if (flags & RADEON_DEPTH) {
1168 /* Enable depth buffer */
1169 tempRB3D_CNTL |= RADEON_Z_ENABLE;
1171 /* Disable depth buffer */
1172 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1176 * Stencil buffer specific enables
1178 if (flags & RADEON_STENCIL) {
1179 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1180 tempRB3D_STENCILREFMASK = clear->depth_mask;
1182 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1183 tempRB3D_STENCILREFMASK = 0x00000000;
1186 if (flags & RADEON_USE_COMP_ZBUF) {
1187 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1188 RADEON_Z_DECOMPRESSION_ENABLE;
1190 if (flags & RADEON_USE_HIERZ) {
1191 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1195 RADEON_WAIT_UNTIL_2D_IDLE();
1197 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1198 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1199 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1200 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1201 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1202 tempRB3D_STENCILREFMASK);
1203 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1204 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1205 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1206 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1207 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1208 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1209 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1212 /* Make sure we restore the 3D state next time.
1214 dev_priv->sarea_priv->ctx_owner = 0;
1216 for (i = 0; i < nbox; i++) {
1218 /* Funny that this should be required --
1221 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1224 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1225 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1226 RADEON_PRIM_WALK_RING |
1227 (3 << RADEON_NUM_VERTICES_SHIFT)));
1228 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1229 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1230 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1231 OUT_RING(0x3f800000);
1232 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1233 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1234 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1235 OUT_RING(0x3f800000);
1236 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1237 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1238 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1239 OUT_RING(0x3f800000);
1242 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1244 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1246 rb3d_cntl = depth_clear->rb3d_cntl;
1248 if (flags & RADEON_DEPTH) {
1249 rb3d_cntl |= RADEON_Z_ENABLE;
1251 rb3d_cntl &= ~RADEON_Z_ENABLE;
1254 if (flags & RADEON_STENCIL) {
1255 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1256 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1258 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1259 rb3d_stencilrefmask = 0x00000000;
1262 if (flags & RADEON_USE_COMP_ZBUF) {
1263 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1264 RADEON_Z_DECOMPRESSION_ENABLE;
1266 if (flags & RADEON_USE_HIERZ) {
1267 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1271 RADEON_WAIT_UNTIL_2D_IDLE();
1273 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1274 OUT_RING(0x00000000);
1275 OUT_RING(rb3d_cntl);
1277 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1278 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1279 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1280 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1283 /* Make sure we restore the 3D state next time.
1285 dev_priv->sarea_priv->ctx_owner = 0;
1287 for (i = 0; i < nbox; i++) {
1289 /* Funny that this should be required --
1292 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1296 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1297 OUT_RING(RADEON_VTX_Z_PRESENT |
1298 RADEON_VTX_PKCOLOR_PRESENT);
1299 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1300 RADEON_PRIM_WALK_RING |
1301 RADEON_MAOS_ENABLE |
1302 RADEON_VTX_FMT_RADEON_MODE |
1303 (3 << RADEON_NUM_VERTICES_SHIFT)));
1305 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1306 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1307 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1310 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1311 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1312 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1315 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1316 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1317 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1324 /* Increment the clear counter. The client-side 3D driver must
1325 * wait on this value before performing the clear ioctl. We
1326 * need this because the card's so damned fast...
1328 dev_priv->sarea_priv->last_clear++;
1332 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1333 RADEON_WAIT_UNTIL_IDLE();
1338 static void radeon_cp_dispatch_swap(drm_device_t * dev)
1340 drm_radeon_private_t *dev_priv = dev->dev_private;
1341 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1342 int nbox = sarea_priv->nbox;
1343 drm_clip_rect_t *pbox = sarea_priv->boxes;
1348 /* Do some trivial performance monitoring...
1350 if (dev_priv->do_boxes)
1351 radeon_cp_performance_boxes(dev_priv);
1353 /* Wait for the 3D stream to idle before dispatching the bitblt.
1354 * This will prevent data corruption between the two streams.
1358 RADEON_WAIT_UNTIL_3D_IDLE();
1362 for (i = 0; i < nbox; i++) {
1365 int w = pbox[i].x2 - x;
1366 int h = pbox[i].y2 - y;
1368 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
1372 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
1373 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1374 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1375 RADEON_GMC_BRUSH_NONE |
1376 (dev_priv->color_fmt << 8) |
1377 RADEON_GMC_SRC_DATATYPE_COLOR |
1379 RADEON_DP_SRC_SOURCE_MEMORY |
1380 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1382 /* Make this work even if front & back are flipped:
1384 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
1385 if (dev_priv->current_page == 0) {
1386 OUT_RING(dev_priv->back_pitch_offset);
1387 OUT_RING(dev_priv->front_pitch_offset);
1389 OUT_RING(dev_priv->front_pitch_offset);
1390 OUT_RING(dev_priv->back_pitch_offset);
1393 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
1394 OUT_RING((x << 16) | y);
1395 OUT_RING((x << 16) | y);
1396 OUT_RING((w << 16) | h);
1401 /* Increment the frame counter. The client-side 3D driver must
1402 * throttle the framerate by waiting for this value before
1403 * performing the swapbuffer ioctl.
1405 dev_priv->sarea_priv->last_frame++;
1409 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1410 RADEON_WAIT_UNTIL_2D_IDLE();
1415 static void radeon_cp_dispatch_flip(drm_device_t * dev)
1417 drm_radeon_private_t *dev_priv = dev->dev_private;
1418 drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
1419 int offset = (dev_priv->current_page == 1)
1420 ? dev_priv->front_offset : dev_priv->back_offset;
1422 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1424 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1426 /* Do some trivial performance monitoring...
1428 if (dev_priv->do_boxes) {
1429 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1430 radeon_cp_performance_boxes(dev_priv);
1433 /* Update the frame offsets for both CRTCs
1437 RADEON_WAIT_UNTIL_3D_IDLE();
1438 OUT_RING_REG(RADEON_CRTC_OFFSET,
1439 ((sarea->frame.y * dev_priv->front_pitch +
1440 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1442 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1447 /* Increment the frame counter. The client-side 3D driver must
1448 * throttle the framerate by waiting for this value before
1449 * performing the swapbuffer ioctl.
1451 dev_priv->sarea_priv->last_frame++;
1452 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1453 1 - dev_priv->current_page;
1457 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1462 static int bad_prim_vertex_nr(int primitive, int nr)
1464 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1465 case RADEON_PRIM_TYPE_NONE:
1466 case RADEON_PRIM_TYPE_POINT:
1468 case RADEON_PRIM_TYPE_LINE:
1469 return (nr & 1) || nr == 0;
1470 case RADEON_PRIM_TYPE_LINE_STRIP:
1472 case RADEON_PRIM_TYPE_TRI_LIST:
1473 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1474 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1475 case RADEON_PRIM_TYPE_RECT_LIST:
1476 return nr % 3 || nr == 0;
1477 case RADEON_PRIM_TYPE_TRI_FAN:
1478 case RADEON_PRIM_TYPE_TRI_STRIP:
1487 unsigned int finish;
1489 unsigned int numverts;
1490 unsigned int offset;
1491 unsigned int vc_format;
1492 } drm_radeon_tcl_prim_t;
1494 static void radeon_cp_dispatch_vertex(drm_device_t * dev,
1496 drm_radeon_tcl_prim_t * prim)
1498 drm_radeon_private_t *dev_priv = dev->dev_private;
1499 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1500 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1501 int numverts = (int)prim->numverts;
1502 int nbox = sarea_priv->nbox;
1506 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1508 prim->vc_format, prim->start, prim->finish, prim->numverts);
1510 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1511 DRM_ERROR("bad prim %x numverts %d\n",
1512 prim->prim, prim->numverts);
1517 /* Emit the next cliprect */
1519 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1522 /* Emit the vertex buffer rendering commands */
1525 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1528 OUT_RING(prim->vc_format);
1529 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1530 RADEON_COLOR_ORDER_RGBA |
1531 RADEON_VTX_FMT_RADEON_MODE |
1532 (numverts << RADEON_NUM_VERTICES_SHIFT));
1540 static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
1542 drm_radeon_private_t *dev_priv = dev->dev_private;
1543 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1546 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1548 /* Emit the vertex buffer age */
1550 RADEON_DISPATCH_AGE(buf_priv->age);
1557 static void radeon_cp_dispatch_indirect(drm_device_t * dev,
1558 drm_buf_t * buf, int start, int end)
1560 drm_radeon_private_t *dev_priv = dev->dev_private;
1562 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1565 int offset = (dev_priv->gart_buffers_offset
1566 + buf->offset + start);
1567 int dwords = (end - start + 3) / sizeof(u32);
1569 /* Indirect buffer data must be an even number of
1570 * dwords, so if we've been given an odd number we must
1571 * pad the data with a Type-2 CP packet.
1575 ((char *)dev->agp_buffer_map->handle
1576 + buf->offset + start);
1577 data[dwords++] = RADEON_CP_PACKET2;
1580 /* Fire off the indirect buffer */
1583 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1591 static void radeon_cp_dispatch_indices(drm_device_t * dev,
1592 drm_buf_t * elt_buf,
1593 drm_radeon_tcl_prim_t * prim)
1595 drm_radeon_private_t *dev_priv = dev->dev_private;
1596 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1597 int offset = dev_priv->gart_buffers_offset + prim->offset;
1601 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1602 int count = (prim->finish - start) / sizeof(u16);
1603 int nbox = sarea_priv->nbox;
1605 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1608 prim->start, prim->finish, prim->offset, prim->numverts);
1610 if (bad_prim_vertex_nr(prim->prim, count)) {
1611 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1615 if (start >= prim->finish || (prim->start & 0x7)) {
1616 DRM_ERROR("buffer prim %d\n", prim->prim);
1620 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1622 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1623 elt_buf->offset + prim->start);
1625 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1627 data[2] = prim->numverts;
1628 data[3] = prim->vc_format;
1629 data[4] = (prim->prim |
1630 RADEON_PRIM_WALK_IND |
1631 RADEON_COLOR_ORDER_RGBA |
1632 RADEON_VTX_FMT_RADEON_MODE |
1633 (count << RADEON_NUM_VERTICES_SHIFT));
1637 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1639 radeon_cp_dispatch_indirect(dev, elt_buf,
1640 prim->start, prim->finish);
1647 #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1649 static int radeon_cp_dispatch_texture(DRMFILE filp,
1651 drm_radeon_texture_t * tex,
1652 drm_radeon_tex_image_t * image)
1654 drm_radeon_private_t *dev_priv = dev->dev_private;
1655 drm_file_t *filp_priv;
1659 const u8 __user *data;
1660 int size, dwords, tex_width, blit_width, spitch;
1663 u32 texpitch, microtile;
1667 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
1669 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1670 DRM_ERROR("Invalid destination offset\n");
1671 return DRM_ERR(EINVAL);
1674 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1676 /* Flush the pixel cache. This ensures no pixel data gets mixed
1677 * up with the texture data from the host data blit, otherwise
1678 * part of the texture image may be corrupted.
1681 RADEON_FLUSH_CACHE();
1682 RADEON_WAIT_UNTIL_IDLE();
1685 /* The compiler won't optimize away a division by a variable,
1686 * even if the only legal values are powers of two. Thus, we'll
1687 * use a shift instead.
1689 switch (tex->format) {
1690 case RADEON_TXFORMAT_ARGB8888:
1691 case RADEON_TXFORMAT_RGBA8888:
1692 format = RADEON_COLOR_FORMAT_ARGB8888;
1693 tex_width = tex->width * 4;
1694 blit_width = image->width * 4;
1696 case RADEON_TXFORMAT_AI88:
1697 case RADEON_TXFORMAT_ARGB1555:
1698 case RADEON_TXFORMAT_RGB565:
1699 case RADEON_TXFORMAT_ARGB4444:
1700 case RADEON_TXFORMAT_VYUY422:
1701 case RADEON_TXFORMAT_YVYU422:
1702 format = RADEON_COLOR_FORMAT_RGB565;
1703 tex_width = tex->width * 2;
1704 blit_width = image->width * 2;
1706 case RADEON_TXFORMAT_I8:
1707 case RADEON_TXFORMAT_RGB332:
1708 format = RADEON_COLOR_FORMAT_CI8;
1709 tex_width = tex->width * 1;
1710 blit_width = image->width * 1;
1713 DRM_ERROR("invalid texture format %d\n", tex->format);
1714 return DRM_ERR(EINVAL);
1716 spitch = blit_width >> 6;
1717 if (spitch == 0 && image->height > 1)
1718 return DRM_ERR(EINVAL);
1720 texpitch = tex->pitch;
1721 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1723 if (tex_width < 64) {
1724 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1725 /* we got tiled coordinates, untile them */
1731 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1734 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1735 tex->offset >> 10, tex->pitch, tex->format,
1736 image->x, image->y, image->width, image->height);
1738 /* Make a copy of some parameters in case we have to
1739 * update them for a multi-pass texture blit.
1741 height = image->height;
1742 data = (const u8 __user *)image->data;
1744 size = height * blit_width;
1746 if (size > RADEON_MAX_TEXTURE_SIZE) {
1747 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1748 size = height * blit_width;
1749 } else if (size < 4 && size > 0) {
1751 } else if (size == 0) {
1755 buf = radeon_freelist_get(dev);
1757 radeon_do_cp_idle(dev_priv);
1758 buf = radeon_freelist_get(dev);
1761 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1762 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
1763 return DRM_ERR(EFAULT);
1764 return DRM_ERR(EAGAIN);
1767 /* Dispatch the indirect buffer.
1770 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1773 #define RADEON_COPY_MT(_buf, _data, _width) \
1775 if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
1776 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1777 return DRM_ERR(EFAULT); \
1782 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1783 however, we cannot use blitter directly for texture width < 64 bytes,
1784 since minimum tex pitch is 64 bytes and we need this to match
1785 the texture width, otherwise the blitter will tile it wrong.
1786 Thus, tiling manually in this case. Additionally, need to special
1787 case tex height = 1, since our actual image will have height 2
1788 and we need to ensure we don't read beyond the texture size
1790 if (tex->height == 1) {
1791 if (tex_width >= 64 || tex_width <= 16) {
1792 RADEON_COPY_MT(buffer, data,
1793 (int)(tex_width * sizeof(u32)));
1794 } else if (tex_width == 32) {
1795 RADEON_COPY_MT(buffer, data, 16);
1796 RADEON_COPY_MT(buffer + 8,
1799 } else if (tex_width >= 64 || tex_width == 16) {
1800 RADEON_COPY_MT(buffer, data,
1801 (int)(dwords * sizeof(u32)));
1802 } else if (tex_width < 16) {
1803 for (i = 0; i < tex->height; i++) {
1804 RADEON_COPY_MT(buffer, data, tex_width);
1808 } else if (tex_width == 32) {
1809 /* TODO: make sure this works when not fitting in one buffer
1810 (i.e. 32bytes x 2048...) */
1811 for (i = 0; i < tex->height; i += 2) {
1812 RADEON_COPY_MT(buffer, data, 16);
1814 RADEON_COPY_MT(buffer + 8, data, 16);
1816 RADEON_COPY_MT(buffer + 4, data, 16);
1818 RADEON_COPY_MT(buffer + 12, data, 16);
1824 if (tex_width >= 32) {
1825 /* Texture image width is larger than the minimum, so we
1826 * can upload it directly.
1828 RADEON_COPY_MT(buffer, data,
1829 (int)(dwords * sizeof(u32)));
1831 /* Texture image width is less than the minimum, so we
1832 * need to pad out each image scanline to the minimum
1835 for (i = 0; i < tex->height; i++) {
1836 RADEON_COPY_MT(buffer, data, tex_width);
1843 #undef RADEON_COPY_MT
1846 offset = dev_priv->gart_buffers_offset + buf->offset;
1848 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1849 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1850 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1851 RADEON_GMC_BRUSH_NONE |
1853 RADEON_GMC_SRC_DATATYPE_COLOR |
1855 RADEON_DP_SRC_SOURCE_MEMORY |
1856 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1857 OUT_RING((spitch << 22) | (offset >> 10));
1858 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1860 OUT_RING((image->x << 16) | image->y);
1861 OUT_RING((image->width << 16) | height);
1862 RADEON_WAIT_UNTIL_2D_IDLE();
1865 radeon_cp_discard_buffer(dev, buf);
1867 /* Update the input parameters for next time */
1869 image->height -= height;
1870 image->data = (const u8 __user *)image->data + size;
1871 } while (image->height > 0);
1873 /* Flush the pixel cache after the blit completes. This ensures
1874 * the texture data is written out to memory before rendering
1878 RADEON_FLUSH_CACHE();
1879 RADEON_WAIT_UNTIL_2D_IDLE();
1884 static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1886 drm_radeon_private_t *dev_priv = dev->dev_private;
1893 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1894 OUT_RING(0x00000000);
1896 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1897 for (i = 0; i < 32; i++) {
1898 OUT_RING(stipple[i]);
1904 static void radeon_apply_surface_regs(int surf_index,
1905 drm_radeon_private_t *dev_priv)
1907 if (!dev_priv->mmio)
1910 radeon_do_cp_idle(dev_priv);
1912 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1913 dev_priv->surfaces[surf_index].flags);
1914 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1915 dev_priv->surfaces[surf_index].lower);
1916 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1917 dev_priv->surfaces[surf_index].upper);
1920 /* Allocates a virtual surface
1921 * doesn't always allocate a real surface, will stretch an existing
1922 * surface when possible.
1924 * Note that refcount can be at most 2, since during a free refcount=3
1925 * might mean we have to allocate a new surface which might not always
1927 * For example : we allocate three contigous surfaces ABC. If B is
1928 * freed, we suddenly need two surfaces to store A and C, which might
1929 * not always be available.
1931 static int alloc_surface(drm_radeon_surface_alloc_t *new,
1932 drm_radeon_private_t *dev_priv, DRMFILE filp)
1934 struct radeon_virt_surface *s;
1936 int virt_surface_index;
1937 uint32_t new_upper, new_lower;
1939 new_lower = new->address;
1940 new_upper = new_lower + new->size - 1;
1943 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1944 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
1945 RADEON_SURF_ADDRESS_FIXED_MASK)
1946 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1949 /* make sure there is no overlap with existing surfaces */
1950 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1951 if ((dev_priv->surfaces[i].refcount != 0) &&
1952 (((new_lower >= dev_priv->surfaces[i].lower) &&
1953 (new_lower < dev_priv->surfaces[i].upper)) ||
1954 ((new_lower < dev_priv->surfaces[i].lower) &&
1955 (new_upper > dev_priv->surfaces[i].lower)))) {
1960 /* find a virtual surface */
1961 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1962 if (dev_priv->virt_surfaces[i].filp == 0)
1964 if (i == 2 * RADEON_MAX_SURFACES) {
1967 virt_surface_index = i;
1969 /* try to reuse an existing surface */
1970 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1972 if ((dev_priv->surfaces[i].refcount == 1) &&
1973 (new->flags == dev_priv->surfaces[i].flags) &&
1974 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1975 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1976 s->surface_index = i;
1977 s->lower = new_lower;
1978 s->upper = new_upper;
1979 s->flags = new->flags;
1981 dev_priv->surfaces[i].refcount++;
1982 dev_priv->surfaces[i].lower = s->lower;
1983 radeon_apply_surface_regs(s->surface_index, dev_priv);
1984 return virt_surface_index;
1988 if ((dev_priv->surfaces[i].refcount == 1) &&
1989 (new->flags == dev_priv->surfaces[i].flags) &&
1990 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1991 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1992 s->surface_index = i;
1993 s->lower = new_lower;
1994 s->upper = new_upper;
1995 s->flags = new->flags;
1997 dev_priv->surfaces[i].refcount++;
1998 dev_priv->surfaces[i].upper = s->upper;
1999 radeon_apply_surface_regs(s->surface_index, dev_priv);
2000 return virt_surface_index;
2004 /* okay, we need a new one */
2005 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2006 if (dev_priv->surfaces[i].refcount == 0) {
2007 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2008 s->surface_index = i;
2009 s->lower = new_lower;
2010 s->upper = new_upper;
2011 s->flags = new->flags;
2013 dev_priv->surfaces[i].refcount = 1;
2014 dev_priv->surfaces[i].lower = s->lower;
2015 dev_priv->surfaces[i].upper = s->upper;
2016 dev_priv->surfaces[i].flags = s->flags;
2017 radeon_apply_surface_regs(s->surface_index, dev_priv);
2018 return virt_surface_index;
2022 /* we didn't find anything */
2026 static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
2029 struct radeon_virt_surface *s;
2031 /* find the virtual surface */
2032 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2033 s = &(dev_priv->virt_surfaces[i]);
2035 if ((lower == s->lower) && (filp == s->filp)) {
2036 if (dev_priv->surfaces[s->surface_index].
2038 dev_priv->surfaces[s->surface_index].
2041 if (dev_priv->surfaces[s->surface_index].
2043 dev_priv->surfaces[s->surface_index].
2046 dev_priv->surfaces[s->surface_index].refcount--;
2047 if (dev_priv->surfaces[s->surface_index].
2049 dev_priv->surfaces[s->surface_index].
2052 radeon_apply_surface_regs(s->surface_index,
2061 static void radeon_surfaces_release(DRMFILE filp,
2062 drm_radeon_private_t * dev_priv)
2065 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2066 if (dev_priv->virt_surfaces[i].filp == filp)
2067 free_surface(filp, dev_priv,
2068 dev_priv->virt_surfaces[i].lower);
2072 /* ================================================================
2075 static int radeon_surface_alloc(DRM_IOCTL_ARGS)
2078 drm_radeon_private_t *dev_priv = dev->dev_private;
2079 drm_radeon_surface_alloc_t alloc;
2082 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2083 return DRM_ERR(EINVAL);
2086 DRM_COPY_FROM_USER_IOCTL(alloc,
2087 (drm_radeon_surface_alloc_t __user *) data,
2090 if (alloc_surface(&alloc, dev_priv, filp) == -1)
2091 return DRM_ERR(EINVAL);
2096 static int radeon_surface_free(DRM_IOCTL_ARGS)
2099 drm_radeon_private_t *dev_priv = dev->dev_private;
2100 drm_radeon_surface_free_t memfree;
2103 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2104 return DRM_ERR(EINVAL);
2107 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data,
2110 if (free_surface(filp, dev_priv, memfree.address))
2111 return DRM_ERR(EINVAL);
2116 static int radeon_cp_clear(DRM_IOCTL_ARGS)
2119 drm_radeon_private_t *dev_priv = dev->dev_private;
2120 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2121 drm_radeon_clear_t clear;
2122 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2125 LOCK_TEST_WITH_RETURN(dev, filp);
2127 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
2130 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2132 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2133 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2135 if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
2136 sarea_priv->nbox * sizeof(depth_boxes[0])))
2137 return DRM_ERR(EFAULT);
2139 radeon_cp_dispatch_clear(dev, &clear, depth_boxes);
2145 /* Not sure why this isn't set all the time:
2147 static int radeon_do_init_pageflip(drm_device_t * dev)
2149 drm_radeon_private_t *dev_priv = dev->dev_private;
2155 RADEON_WAIT_UNTIL_3D_IDLE();
2156 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2157 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2158 RADEON_CRTC_OFFSET_FLIP_CNTL);
2159 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2160 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2161 RADEON_CRTC_OFFSET_FLIP_CNTL);
2164 dev_priv->page_flipping = 1;
2165 dev_priv->current_page = 0;
2166 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
2171 /* Called whenever a client dies, from drm_release.
2172 * NOTE: Lock isn't necessarily held when this is called!
2174 static int radeon_do_cleanup_pageflip(drm_device_t * dev)
2176 drm_radeon_private_t *dev_priv = dev->dev_private;
2179 if (dev_priv->current_page != 0)
2180 radeon_cp_dispatch_flip(dev);
2182 dev_priv->page_flipping = 0;
2186 /* Swapping and flipping are different operations, need different ioctls.
2187 * They can & should be intermixed to support multiple 3d windows.
2189 static int radeon_cp_flip(DRM_IOCTL_ARGS)
2192 drm_radeon_private_t *dev_priv = dev->dev_private;
2195 LOCK_TEST_WITH_RETURN(dev, filp);
2197 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2199 if (!dev_priv->page_flipping)
2200 radeon_do_init_pageflip(dev);
2202 radeon_cp_dispatch_flip(dev);
2208 static int radeon_cp_swap(DRM_IOCTL_ARGS)
2211 drm_radeon_private_t *dev_priv = dev->dev_private;
2212 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2215 LOCK_TEST_WITH_RETURN(dev, filp);
2217 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2219 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2220 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2222 radeon_cp_dispatch_swap(dev);
2223 dev_priv->sarea_priv->ctx_owner = 0;
2229 static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2232 drm_radeon_private_t *dev_priv = dev->dev_private;
2233 drm_file_t *filp_priv;
2234 drm_radeon_sarea_t *sarea_priv;
2235 drm_device_dma_t *dma = dev->dma;
2237 drm_radeon_vertex_t vertex;
2238 drm_radeon_tcl_prim_t prim;
2240 LOCK_TEST_WITH_RETURN(dev, filp);
2243 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2244 return DRM_ERR(EINVAL);
2247 sarea_priv = dev_priv->sarea_priv;
2249 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2251 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2254 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2255 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2257 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2258 DRM_ERROR("buffer index %d (of %d max)\n",
2259 vertex.idx, dma->buf_count - 1);
2260 return DRM_ERR(EINVAL);
2262 if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2263 DRM_ERROR("buffer prim %d\n", vertex.prim);
2264 return DRM_ERR(EINVAL);
2267 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2268 VB_AGE_TEST_WITH_RETURN(dev_priv);
2270 buf = dma->buflist[vertex.idx];
2272 if (buf->filp != filp) {
2273 DRM_ERROR("process %d using buffer owned by %p\n",
2274 DRM_CURRENTPID, buf->filp);
2275 return DRM_ERR(EINVAL);
2278 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2279 return DRM_ERR(EINVAL);
2282 /* Build up a prim_t record:
2285 buf->used = vertex.count; /* not used? */
2287 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2288 if (radeon_emit_state(dev_priv, filp_priv,
2289 &sarea_priv->context_state,
2290 sarea_priv->tex_state,
2291 sarea_priv->dirty)) {
2292 DRM_ERROR("radeon_emit_state failed\n");
2293 return DRM_ERR(EINVAL);
2296 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2297 RADEON_UPLOAD_TEX1IMAGES |
2298 RADEON_UPLOAD_TEX2IMAGES |
2299 RADEON_REQUIRE_QUIESCENCE);
2303 prim.finish = vertex.count; /* unused */
2304 prim.prim = vertex.prim;
2305 prim.numverts = vertex.count;
2306 prim.vc_format = dev_priv->sarea_priv->vc_format;
2308 radeon_cp_dispatch_vertex(dev, buf, &prim);
2311 if (vertex.discard) {
2312 radeon_cp_discard_buffer(dev, buf);
2319 static int radeon_cp_indices(DRM_IOCTL_ARGS)
2322 drm_radeon_private_t *dev_priv = dev->dev_private;
2323 drm_file_t *filp_priv;
2324 drm_radeon_sarea_t *sarea_priv;
2325 drm_device_dma_t *dma = dev->dma;
2327 drm_radeon_indices_t elts;
2328 drm_radeon_tcl_prim_t prim;
2331 LOCK_TEST_WITH_RETURN(dev, filp);
2334 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2335 return DRM_ERR(EINVAL);
2337 sarea_priv = dev_priv->sarea_priv;
2339 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2341 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2344 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2345 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);
2347 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
2348 DRM_ERROR("buffer index %d (of %d max)\n",
2349 elts.idx, dma->buf_count - 1);
2350 return DRM_ERR(EINVAL);
2352 if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2353 DRM_ERROR("buffer prim %d\n", elts.prim);
2354 return DRM_ERR(EINVAL);
2357 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2358 VB_AGE_TEST_WITH_RETURN(dev_priv);
2360 buf = dma->buflist[elts.idx];
2362 if (buf->filp != filp) {
2363 DRM_ERROR("process %d using buffer owned by %p\n",
2364 DRM_CURRENTPID, buf->filp);
2365 return DRM_ERR(EINVAL);
2368 DRM_ERROR("sending pending buffer %d\n", elts.idx);
2369 return DRM_ERR(EINVAL);
2372 count = (elts.end - elts.start) / sizeof(u16);
2373 elts.start -= RADEON_INDEX_PRIM_OFFSET;
2375 if (elts.start & 0x7) {
2376 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
2377 return DRM_ERR(EINVAL);
2379 if (elts.start < buf->used) {
2380 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
2381 return DRM_ERR(EINVAL);
2384 buf->used = elts.end;
2386 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2387 if (radeon_emit_state(dev_priv, filp_priv,
2388 &sarea_priv->context_state,
2389 sarea_priv->tex_state,
2390 sarea_priv->dirty)) {
2391 DRM_ERROR("radeon_emit_state failed\n");
2392 return DRM_ERR(EINVAL);
2395 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2396 RADEON_UPLOAD_TEX1IMAGES |
2397 RADEON_UPLOAD_TEX2IMAGES |
2398 RADEON_REQUIRE_QUIESCENCE);
2401 /* Build up a prim_t record:
2403 prim.start = elts.start;
2404 prim.finish = elts.end;
2405 prim.prim = elts.prim;
2406 prim.offset = 0; /* offset from start of dma buffers */
2407 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2408 prim.vc_format = dev_priv->sarea_priv->vc_format;
2410 radeon_cp_dispatch_indices(dev, buf, &prim);
2412 radeon_cp_discard_buffer(dev, buf);
2419 static int radeon_cp_texture(DRM_IOCTL_ARGS)
2422 drm_radeon_private_t *dev_priv = dev->dev_private;
2423 drm_radeon_texture_t tex;
2424 drm_radeon_tex_image_t image;
2427 LOCK_TEST_WITH_RETURN(dev, filp);
2429 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
2432 if (tex.image == NULL) {
2433 DRM_ERROR("null texture image!\n");
2434 return DRM_ERR(EINVAL);
2437 if (DRM_COPY_FROM_USER(&image,
2438 (drm_radeon_tex_image_t __user *) tex.image,
2440 return DRM_ERR(EFAULT);
2442 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2443 VB_AGE_TEST_WITH_RETURN(dev_priv);
2445 ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image);
2451 static int radeon_cp_stipple(DRM_IOCTL_ARGS)
2454 drm_radeon_private_t *dev_priv = dev->dev_private;
2455 drm_radeon_stipple_t stipple;
2458 LOCK_TEST_WITH_RETURN(dev, filp);
2460 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
2463 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
2464 return DRM_ERR(EFAULT);
2466 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2468 radeon_cp_dispatch_stipple(dev, mask);
2474 static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2477 drm_radeon_private_t *dev_priv = dev->dev_private;
2478 drm_device_dma_t *dma = dev->dma;
2480 drm_radeon_indirect_t indirect;
2483 LOCK_TEST_WITH_RETURN(dev, filp);
2486 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2487 return DRM_ERR(EINVAL);
2490 DRM_COPY_FROM_USER_IOCTL(indirect,
2491 (drm_radeon_indirect_t __user *) data,
2494 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
2495 indirect.idx, indirect.start, indirect.end, indirect.discard);
2497 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
2498 DRM_ERROR("buffer index %d (of %d max)\n",
2499 indirect.idx, dma->buf_count - 1);
2500 return DRM_ERR(EINVAL);
2503 buf = dma->buflist[indirect.idx];
2505 if (buf->filp != filp) {
2506 DRM_ERROR("process %d using buffer owned by %p\n",
2507 DRM_CURRENTPID, buf->filp);
2508 return DRM_ERR(EINVAL);
2511 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
2512 return DRM_ERR(EINVAL);
2515 if (indirect.start < buf->used) {
2516 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2517 indirect.start, buf->used);
2518 return DRM_ERR(EINVAL);
2521 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2522 VB_AGE_TEST_WITH_RETURN(dev_priv);
2524 buf->used = indirect.end;
2526 /* Wait for the 3D stream to idle before the indirect buffer
2527 * containing 2D acceleration commands is processed.
2531 RADEON_WAIT_UNTIL_3D_IDLE();
2535 /* Dispatch the indirect buffer full of commands from the
2536 * X server. This is insecure and is thus only available to
2537 * privileged clients.
2539 radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end);
2540 if (indirect.discard) {
2541 radeon_cp_discard_buffer(dev, buf);
2548 static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2551 drm_radeon_private_t *dev_priv = dev->dev_private;
2552 drm_file_t *filp_priv;
2553 drm_radeon_sarea_t *sarea_priv;
2554 drm_device_dma_t *dma = dev->dma;
2556 drm_radeon_vertex2_t vertex;
2558 unsigned char laststate;
2560 LOCK_TEST_WITH_RETURN(dev, filp);
2563 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2564 return DRM_ERR(EINVAL);
2567 sarea_priv = dev_priv->sarea_priv;
2569 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2571 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2574 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2575 DRM_CURRENTPID, vertex.idx, vertex.discard);
2577 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2578 DRM_ERROR("buffer index %d (of %d max)\n",
2579 vertex.idx, dma->buf_count - 1);
2580 return DRM_ERR(EINVAL);
2583 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2584 VB_AGE_TEST_WITH_RETURN(dev_priv);
2586 buf = dma->buflist[vertex.idx];
2588 if (buf->filp != filp) {
2589 DRM_ERROR("process %d using buffer owned by %p\n",
2590 DRM_CURRENTPID, buf->filp);
2591 return DRM_ERR(EINVAL);
2595 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2596 return DRM_ERR(EINVAL);
2599 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2600 return DRM_ERR(EINVAL);
2602 for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) {
2603 drm_radeon_prim_t prim;
2604 drm_radeon_tcl_prim_t tclprim;
2606 if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim)))
2607 return DRM_ERR(EFAULT);
2609 if (prim.stateidx != laststate) {
2610 drm_radeon_state_t state;
2612 if (DRM_COPY_FROM_USER(&state,
2613 &vertex.state[prim.stateidx],
2615 return DRM_ERR(EFAULT);
2617 if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
2618 DRM_ERROR("radeon_emit_state2 failed\n");
2619 return DRM_ERR(EINVAL);
2622 laststate = prim.stateidx;
2625 tclprim.start = prim.start;
2626 tclprim.finish = prim.finish;
2627 tclprim.prim = prim.prim;
2628 tclprim.vc_format = prim.vc_format;
2630 if (prim.prim & RADEON_PRIM_WALK_IND) {
2631 tclprim.offset = prim.numverts * 64;
2632 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2634 radeon_cp_dispatch_indices(dev, buf, &tclprim);
2636 tclprim.numverts = prim.numverts;
2637 tclprim.offset = 0; /* not used */
2639 radeon_cp_dispatch_vertex(dev, buf, &tclprim);
2642 if (sarea_priv->nbox == 1)
2643 sarea_priv->nbox = 0;
2646 if (vertex.discard) {
2647 radeon_cp_discard_buffer(dev, buf);
2654 static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2655 drm_file_t * filp_priv,
2656 drm_radeon_cmd_header_t header,
2657 drm_radeon_kcmd_buffer_t *cmdbuf)
2659 int id = (int)header.packet.packet_id;
2661 int *data = (int *)cmdbuf->buf;
2664 if (id >= RADEON_MAX_STATE_PACKETS)
2665 return DRM_ERR(EINVAL);
2667 sz = packet[id].len;
2668 reg = packet[id].start;
2670 if (sz * sizeof(int) > cmdbuf->bufsz) {
2671 DRM_ERROR("Packet size provided larger than data provided\n");
2672 return DRM_ERR(EINVAL);
2675 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
2676 DRM_ERROR("Packet verification failed\n");
2677 return DRM_ERR(EINVAL);
2681 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2682 OUT_RING_TABLE(data, sz);
2685 cmdbuf->buf += sz * sizeof(int);
2686 cmdbuf->bufsz -= sz * sizeof(int);
2690 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2691 drm_radeon_cmd_header_t header,
2692 drm_radeon_kcmd_buffer_t *cmdbuf)
2694 int sz = header.scalars.count;
2695 int start = header.scalars.offset;
2696 int stride = header.scalars.stride;
2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2701 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2702 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2703 OUT_RING_TABLE(cmdbuf->buf, sz);
2705 cmdbuf->buf += sz * sizeof(int);
2706 cmdbuf->bufsz -= sz * sizeof(int);
2712 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2713 drm_radeon_cmd_header_t header,
2714 drm_radeon_kcmd_buffer_t *cmdbuf)
2716 int sz = header.scalars.count;
2717 int start = ((unsigned int)header.scalars.offset) + 0x100;
2718 int stride = header.scalars.stride;
2722 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2723 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2724 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2725 OUT_RING_TABLE(cmdbuf->buf, sz);
2727 cmdbuf->buf += sz * sizeof(int);
2728 cmdbuf->bufsz -= sz * sizeof(int);
2732 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2733 drm_radeon_cmd_header_t header,
2734 drm_radeon_kcmd_buffer_t *cmdbuf)
2736 int sz = header.vectors.count;
2737 int start = header.vectors.offset;
2738 int stride = header.vectors.stride;
2742 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2744 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2745 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2746 OUT_RING_TABLE(cmdbuf->buf, sz);
2749 cmdbuf->buf += sz * sizeof(int);
2750 cmdbuf->bufsz -= sz * sizeof(int);
2754 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2755 drm_radeon_cmd_header_t header,
2756 drm_radeon_kcmd_buffer_t *cmdbuf)
2758 int sz = header.veclinear.count * 4;
2759 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2764 if (sz * 4 > cmdbuf->bufsz)
2765 return DRM_ERR(EINVAL);
2768 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2769 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2770 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2771 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2772 OUT_RING_TABLE(cmdbuf->buf, sz);
2775 cmdbuf->buf += sz * sizeof(int);
2776 cmdbuf->bufsz -= sz * sizeof(int);
2780 static int radeon_emit_packet3(drm_device_t * dev,
2781 drm_file_t * filp_priv,
2782 drm_radeon_kcmd_buffer_t *cmdbuf)
2784 drm_radeon_private_t *dev_priv = dev->dev_private;
2791 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2793 DRM_ERROR("Packet verification failed\n");
2798 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2801 cmdbuf->buf += cmdsz * 4;
2802 cmdbuf->bufsz -= cmdsz * 4;
2806 static int radeon_emit_packet3_cliprect(drm_device_t *dev,
2807 drm_file_t *filp_priv,
2808 drm_radeon_kcmd_buffer_t *cmdbuf,
2811 drm_radeon_private_t *dev_priv = dev->dev_private;
2812 drm_clip_rect_t box;
2815 drm_clip_rect_t __user *boxes = cmdbuf->boxes;
2821 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2823 DRM_ERROR("Packet verification failed\n");
2831 if (i < cmdbuf->nbox) {
2832 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
2833 return DRM_ERR(EFAULT);
2834 /* FIXME The second and subsequent times round
2835 * this loop, send a WAIT_UNTIL_3D_IDLE before
2836 * calling emit_clip_rect(). This fixes a
2837 * lockup on fast machines when sending
2838 * several cliprects with a cmdbuf, as when
2839 * waving a 2D window over a 3D
2840 * window. Something in the commands from user
2841 * space seems to hang the card when they're
2842 * sent several times in a row. That would be
2843 * the correct place to fix it but this works
2844 * around it until I can figure that out - Tim
2848 RADEON_WAIT_UNTIL_3D_IDLE();
2851 radeon_emit_clip_rect(dev_priv, &box);
2855 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2858 } while (++i < cmdbuf->nbox);
2859 if (cmdbuf->nbox == 1)
2863 cmdbuf->buf += cmdsz * 4;
2864 cmdbuf->bufsz -= cmdsz * 4;
2868 static int radeon_emit_wait(drm_device_t * dev, int flags)
2870 drm_radeon_private_t *dev_priv = dev->dev_private;
2873 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2875 case RADEON_WAIT_2D:
2877 RADEON_WAIT_UNTIL_2D_IDLE();
2880 case RADEON_WAIT_3D:
2882 RADEON_WAIT_UNTIL_3D_IDLE();
2885 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2887 RADEON_WAIT_UNTIL_IDLE();
2891 return DRM_ERR(EINVAL);
2897 static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2900 drm_radeon_private_t *dev_priv = dev->dev_private;
2901 drm_file_t *filp_priv;
2902 drm_device_dma_t *dma = dev->dma;
2903 drm_buf_t *buf = NULL;
2905 drm_radeon_kcmd_buffer_t cmdbuf;
2906 drm_radeon_cmd_header_t header;
2907 int orig_nbox, orig_bufsz;
2910 LOCK_TEST_WITH_RETURN(dev, filp);
2913 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2914 return DRM_ERR(EINVAL);
2917 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2919 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2920 (drm_radeon_kcmd_buffer_t __user *) data,
2923 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2924 VB_AGE_TEST_WITH_RETURN(dev_priv);
2926 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2927 return DRM_ERR(EINVAL);
2930 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2931 * races between checking values and using those values in other code,
2932 * and simply to avoid a lot of function calls to copy in data.
2934 orig_bufsz = cmdbuf.bufsz;
2935 if (orig_bufsz != 0) {
2936 kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER);
2938 return DRM_ERR(ENOMEM);
2939 if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf,
2941 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2942 return DRM_ERR(EFAULT);
2947 orig_nbox = cmdbuf.nbox;
2949 if (dev_priv->microcode_version == UCODE_R300) {
2951 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2953 if (orig_bufsz != 0)
2954 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2959 /* microcode_version != r300 */
2960 while (cmdbuf.bufsz >= sizeof(header)) {
2962 header.i = *(int *)cmdbuf.buf;
2963 cmdbuf.buf += sizeof(header);
2964 cmdbuf.bufsz -= sizeof(header);
2966 switch (header.header.cmd_type) {
2967 case RADEON_CMD_PACKET:
2968 DRM_DEBUG("RADEON_CMD_PACKET\n");
2969 if (radeon_emit_packets
2970 (dev_priv, filp_priv, header, &cmdbuf)) {
2971 DRM_ERROR("radeon_emit_packets failed\n");
2976 case RADEON_CMD_SCALARS:
2977 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2978 if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
2979 DRM_ERROR("radeon_emit_scalars failed\n");
2984 case RADEON_CMD_VECTORS:
2985 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2986 if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
2987 DRM_ERROR("radeon_emit_vectors failed\n");
2992 case RADEON_CMD_DMA_DISCARD:
2993 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2994 idx = header.dma.buf_idx;
2995 if (idx < 0 || idx >= dma->buf_count) {
2996 DRM_ERROR("buffer index %d (of %d max)\n",
2997 idx, dma->buf_count - 1);
3001 buf = dma->buflist[idx];
3002 if (buf->filp != filp || buf->pending) {
3003 DRM_ERROR("bad buffer %p %p %d\n",
3004 buf->filp, filp, buf->pending);
3008 radeon_cp_discard_buffer(dev, buf);
3011 case RADEON_CMD_PACKET3:
3012 DRM_DEBUG("RADEON_CMD_PACKET3\n");
3013 if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) {
3014 DRM_ERROR("radeon_emit_packet3 failed\n");
3019 case RADEON_CMD_PACKET3_CLIP:
3020 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
3021 if (radeon_emit_packet3_cliprect
3022 (dev, filp_priv, &cmdbuf, orig_nbox)) {
3023 DRM_ERROR("radeon_emit_packet3_clip failed\n");
3028 case RADEON_CMD_SCALARS2:
3029 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
3030 if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
3031 DRM_ERROR("radeon_emit_scalars2 failed\n");
3036 case RADEON_CMD_WAIT:
3037 DRM_DEBUG("RADEON_CMD_WAIT\n");
3038 if (radeon_emit_wait(dev, header.wait.flags)) {
3039 DRM_ERROR("radeon_emit_wait failed\n");
3043 case RADEON_CMD_VECLINEAR:
3044 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
3045 if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) {
3046 DRM_ERROR("radeon_emit_veclinear failed\n");
3052 DRM_ERROR("bad cmd_type %d at %p\n",
3053 header.header.cmd_type,
3054 cmdbuf.buf - sizeof(header));
3059 if (orig_bufsz != 0)
3060 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
3062 DRM_DEBUG("DONE\n");
3067 if (orig_bufsz != 0)
3068 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
3069 return DRM_ERR(EINVAL);
3072 static int radeon_cp_getparam(DRM_IOCTL_ARGS)
3075 drm_radeon_private_t *dev_priv = dev->dev_private;
3076 drm_radeon_getparam_t param;
3080 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
3081 return DRM_ERR(EINVAL);
3084 DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
3087 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
3089 switch (param.param) {
3090 case RADEON_PARAM_GART_BUFFER_OFFSET:
3091 value = dev_priv->gart_buffers_offset;
3093 case RADEON_PARAM_LAST_FRAME:
3094 dev_priv->stats.last_frame_reads++;
3095 value = GET_SCRATCH(0);
3097 case RADEON_PARAM_LAST_DISPATCH:
3098 value = GET_SCRATCH(1);
3100 case RADEON_PARAM_LAST_CLEAR:
3101 dev_priv->stats.last_clear_reads++;
3102 value = GET_SCRATCH(2);
3104 case RADEON_PARAM_IRQ_NR:
3107 case RADEON_PARAM_GART_BASE:
3108 value = dev_priv->gart_vm_start;
3110 case RADEON_PARAM_REGISTER_HANDLE:
3111 value = dev_priv->mmio->offset;
3113 case RADEON_PARAM_STATUS_HANDLE:
3114 value = dev_priv->ring_rptr_offset;
3118 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
3119 * pointer which can't fit into an int-sized variable. According to
3120 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
3121 * not supporting it shouldn't be a problem. If the same functionality
3122 * is needed on 64-bit platforms, a new ioctl() would have to be added,
3123 * so backwards-compatibility for the embedded platforms can be
3124 * maintained. --davidm 4-Feb-2004.
3126 case RADEON_PARAM_SAREA_HANDLE:
3127 /* The lock is the first dword in the sarea. */
3128 value = (long)dev->lock.hw_lock;
3131 case RADEON_PARAM_GART_TEX_HANDLE:
3132 value = dev_priv->gart_textures_offset;
3134 case RADEON_PARAM_SCRATCH_OFFSET:
3135 if (!dev_priv->writeback_works)
3136 return DRM_ERR(EINVAL);
3137 value = RADEON_SCRATCH_REG_OFFSET;
3140 case RADEON_PARAM_CARD_TYPE:
3141 if (dev_priv->flags & RADEON_IS_PCIE)
3142 value = RADEON_CARD_PCIE;
3143 else if (dev_priv->flags & RADEON_IS_AGP)
3144 value = RADEON_CARD_AGP;
3146 value = RADEON_CARD_PCI;
3149 DRM_DEBUG( "Invalid parameter %d\n", param.param );
3150 return DRM_ERR(EINVAL);
3153 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
3154 DRM_ERROR("copy_to_user\n");
3155 return DRM_ERR(EFAULT);
3161 static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3164 drm_radeon_private_t *dev_priv = dev->dev_private;
3165 drm_file_t *filp_priv;
3166 drm_radeon_setparam_t sp;
3167 struct drm_radeon_driver_file_fields *radeon_priv;
3170 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
3171 return DRM_ERR(EINVAL);
3174 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
3176 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
3180 case RADEON_SETPARAM_FB_LOCATION:
3181 radeon_priv = filp_priv->driver_priv;
3182 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3184 case RADEON_SETPARAM_SWITCH_TILING:
3185 if (sp.value == 0) {
3186 DRM_DEBUG("color tiling disabled\n");
3187 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3188 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3189 dev_priv->sarea_priv->tiling_enabled = 0;
3190 } else if (sp.value == 1) {
3191 DRM_DEBUG("color tiling enabled\n");
3192 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3193 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3194 dev_priv->sarea_priv->tiling_enabled = 1;
3197 case RADEON_SETPARAM_PCIGART_LOCATION:
3198 dev_priv->pcigart_offset = sp.value;
3200 case RADEON_SETPARAM_NEW_MEMMAP:
3201 dev_priv->new_memmap = sp.value;
3204 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3205 return DRM_ERR(EINVAL);
3211 /* When a client dies:
3212 * - Check for and clean up flipped page state
3213 * - Free any alloced GART memory.
3214 * - Free any alloced radeon surfaces.
3216 * DRM infrastructure takes care of reclaiming dma buffers.
3218 void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp)
3220 if (dev->dev_private) {
3221 drm_radeon_private_t *dev_priv = dev->dev_private;
3222 if (dev_priv->page_flipping) {
3223 radeon_do_cleanup_pageflip(dev);
3225 radeon_mem_release(filp, dev_priv->gart_heap);
3226 radeon_mem_release(filp, dev_priv->fb_heap);
3227 radeon_surfaces_release(filp, dev_priv);
3231 void radeon_driver_lastclose(drm_device_t * dev)
3233 radeon_do_release(dev);
3236 int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv)
3238 drm_radeon_private_t *dev_priv = dev->dev_private;
3239 struct drm_radeon_driver_file_fields *radeon_priv;
3243 (struct drm_radeon_driver_file_fields *)
3244 drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
3249 filp_priv->driver_priv = radeon_priv;
3252 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3254 radeon_priv->radeon_fb_delta = 0;
3258 void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp_priv)
3260 struct drm_radeon_driver_file_fields *radeon_priv =
3261 filp_priv->driver_priv;
3263 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
3266 drm_ioctl_desc_t radeon_ioctls[] = {
3267 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3268 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3269 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3270 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3271 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, DRM_AUTH},
3272 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, DRM_AUTH},
3273 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, DRM_AUTH},
3274 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, DRM_AUTH},
3275 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, DRM_AUTH},
3276 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, DRM_AUTH},
3277 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, DRM_AUTH},
3278 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, DRM_AUTH},
3279 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, DRM_AUTH},
3280 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, DRM_AUTH},
3281 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3282 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, DRM_AUTH},
3283 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, DRM_AUTH},
3284 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, DRM_AUTH},
3285 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, DRM_AUTH},
3286 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, DRM_AUTH},
3287 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, DRM_AUTH},
3288 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
3289 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, DRM_AUTH},
3290 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, DRM_AUTH},
3291 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, DRM_AUTH},
3292 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, DRM_AUTH},
3293 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, DRM_AUTH}
3296 int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);