shared-core/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include "drmP.h"
  38 #include "drm.h"
  39 #include "via_drm.h"
  40 #include "via_drv.h"
  41 #include "via_3d_reg.h"
  42
  43 #define SetReg2DAGP(nReg, nData) {                              \
  44         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  45         *((uint32_t *)(vb) + 1) = (nData);                      \
  46         vb = ((uint32_t *)vb) + 2;                              \
  47         dev_priv->dma_low +=8;                                  \
  48 }
  49
  50 #define via_flush_write_combine() DRM_MEMORYBARRIER()
  51
  52 #define VIA_OUT_RING_QW(w1,w2)                  \
  53         *vb++ = (w1);                           \
  54         *vb++ = (w2);                           \
  55         dev_priv->dma_low += 8;
  56
  57 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
  58 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
  59 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
  60 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
  61 static int via_wait_idle(drm_via_private_t *dev_priv);
  62 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
  63
  64
  65 /*
  66  * Free space in command buffer.
  67  */
  68
  69 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
  70 {
  71         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  72         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  73
  74         return ((hw_addr <= dev_priv->dma_low) ?
  75                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  76                 (hw_addr - dev_priv->dma_low));
  77 }
  78
  79 /*
  80  * How much does the command regulator lag behind?
  81  */
  82
  83 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
  84 {
  85         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  86         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  87
  88         return ((hw_addr <= dev_priv->dma_low) ?
  89                 (dev_priv->dma_low - hw_addr) :
  90                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
  91 }
  92
  93 /*
  94  * Check that the given size fits in the buffer, otherwise wait.
  95  */
  96
  97 static inline int
  98 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
  99 {
 100         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 101         uint32_t cur_addr, hw_addr, next_addr;
 102         volatile uint32_t *hw_addr_ptr;
 103         uint32_t count;
 104         hw_addr_ptr = dev_priv->hw_addr_ptr;
 105         cur_addr = dev_priv->dma_low;
 106         next_addr = cur_addr + size + 512 * 1024;
 107         count = 1000000;
 108         do {
 109                 hw_addr = *hw_addr_ptr - agp_base;
 110                 if (count-- == 0) {
 111                         DRM_ERROR
 112                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 113                              hw_addr, cur_addr, next_addr);
 114                         return -1;
 115                 }
 116         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 117         return 0;
 118 }
 119
 120
 121 /*
 122  * Checks whether buffer head has reach the end. Rewind the ring buffer
 123  * when necessary.
 124  *
 125  * Returns virtual pointer to ring buffer.
 126  */
 127
 128 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 129                                       unsigned int size)
 130 {
 131         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 132             dev_priv->dma_high) {
 133                 via_cmdbuf_rewind(dev_priv);
 134         }
 135         if (via_cmdbuf_wait(dev_priv, size) != 0) {
 136                 return NULL;
 137         }
 138
 139         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 140 }
 141
 142 int via_dma_cleanup(struct drm_device * dev)
 143 {
 144         if (dev->dev_private) {
 145                 drm_via_private_t *dev_priv =
 146                         (drm_via_private_t *) dev->dev_private;
 147
 148                 if (dev_priv->ring.virtual_start) {
 149                         via_cmdbuf_reset(dev_priv);
 150
 151                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 152                         dev_priv->ring.virtual_start = NULL;
 153                 }
 154
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int via_initialize(struct drm_device * dev,
 161                           drm_via_private_t * dev_priv,
 162                           drm_via_dma_init_t * init)
 163 {
 164         if (!dev_priv || !dev_priv->mmio) {
 165                 DRM_ERROR("via_dma_init called before via_map_init\n");
 166                 return -EFAULT;
 167         }
 168
 169         if (dev_priv->ring.virtual_start != NULL) {
 170                 DRM_ERROR("called again without calling cleanup\n");
 171                 return -EFAULT;
 172         }
 173
 174         if (!dev->agp || !dev->agp->base) {
 175                 DRM_ERROR("called with no agp memory available\n");
 176                 return -EFAULT;
 177         }
 178
 179         if (dev_priv->chipset == VIA_DX9_0) {
 180                 DRM_ERROR("AGP DMA is not supported on this chip\n");
 181                 return -EINVAL;
 182         }
 183
 184         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 185         dev_priv->ring.map.size = init->size;
 186         dev_priv->ring.map.type = 0;
 187         dev_priv->ring.map.flags = 0;
 188         dev_priv->ring.map.mtrr = 0;
 189
 190         drm_core_ioremap(&dev_priv->ring.map, dev);
 191
 192         if (dev_priv->ring.map.handle == NULL) {
 193                 via_dma_cleanup(dev);
 194                 DRM_ERROR("can not ioremap virtual address for"
 195                           " ring buffer\n");
 196                 return -ENOMEM;
 197         }
 198
 199         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 200
 201         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 202         dev_priv->dma_low = 0;
 203         dev_priv->dma_high = init->size;
 204         dev_priv->dma_wrap = init->size;
 205         dev_priv->dma_offset = init->offset;
 206         dev_priv->last_pause_ptr = NULL;
 207         dev_priv->hw_addr_ptr =
 208                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
 209                 init->reg_pause_addr);
 210
 211         via_cmdbuf_start(dev_priv);
 212
 213         return 0;
 214 }
 215
 216 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
 217 {
 218         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 219         drm_via_dma_init_t *init = data;
 220         int retcode = 0;
 221
 222         switch (init->func) {
 223         case VIA_INIT_DMA:
 224                 if (!DRM_SUSER(DRM_CURPROC))
 225                         retcode = -EPERM;
 226                 else
 227                         retcode = via_initialize(dev, dev_priv, init);
 228                 break;
 229         case VIA_CLEANUP_DMA:
 230                 if (!DRM_SUSER(DRM_CURPROC))
 231                         retcode = -EPERM;
 232                 else
 233                         retcode = via_dma_cleanup(dev);
 234                 break;
 235         case VIA_DMA_INITIALIZED:
 236                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 237                         0 : -EFAULT;
 238                 break;
 239         default:
 240                 retcode = -EINVAL;
 241                 break;
 242         }
 243
 244         return retcode;
 245 }
 246
 247
 248
 249 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
 250 {
 251         drm_via_private_t *dev_priv;
 252         uint32_t *vb;
 253         int ret;
 254
 255         dev_priv = (drm_via_private_t *) dev->dev_private;
 256
 257         if (dev_priv->ring.virtual_start == NULL) {
 258                 DRM_ERROR("called without initializing AGP ring buffer.\n");
 259                 return -EFAULT;
 260         }
 261
 262         if (cmd->size > VIA_PCI_BUF_SIZE) {
 263                 return -ENOMEM;
 264         }
 265
 266         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 267                 return -EFAULT;
 268
 269         /*
 270          * Running this function on AGP memory is dead slow. Therefore
 271          * we run it on a temporary cacheable system memory buffer and
 272          * copy it to AGP memory when ready.
 273          */
 274
 275         if ((ret =
 276              via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
 277                                        cmd->size, dev, 1))) {
 278                 return ret;
 279         }
 280
 281         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 282         if (vb == NULL) {
 283                 return -EAGAIN;
 284         }
 285
 286         memcpy(vb, dev_priv->pci_buf, cmd->size);
 287
 288         dev_priv->dma_low += cmd->size;
 289
 290         /*
 291          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 292          * pad to greater size.
 293          */
 294
 295         if (cmd->size < 0x100)
 296                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
 297         via_cmdbuf_pause(dev_priv);
 298
 299         return 0;
 300 }
 301
 302 int via_driver_dma_quiescent(struct drm_device * dev)
 303 {
 304         drm_via_private_t *dev_priv = dev->dev_private;
 305
 306         if (!via_wait_idle(dev_priv)) {
 307                 return -EBUSY;
 308         }
 309         return 0;
 310 }
 311
 312 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 313 {
 314
 315         LOCK_TEST_WITH_RETURN(dev, file_priv);
 316
 317         return via_driver_dma_quiescent(dev);
 318 }
 319
 320 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
 321 {
 322         drm_via_cmdbuffer_t *cmdbuf = data;
 323         int ret;
 324
 325         LOCK_TEST_WITH_RETURN(dev, file_priv);
 326
 327         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
 328
 329         ret = via_dispatch_cmdbuffer(dev, cmdbuf);
 330         if (ret) {
 331                 return ret;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
 338                                       drm_via_cmdbuffer_t * cmd)
 339 {
 340         drm_via_private_t *dev_priv = dev->dev_private;
 341         int ret;
 342
 343         if (cmd->size > VIA_PCI_BUF_SIZE) {
 344                 return -ENOMEM;
 345         }
 346         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 347                 return -EFAULT;
 348
 349         if ((ret =
 350              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 351                                        cmd->size, dev, 0))) {
 352                 return ret;
 353         }
 354
 355         ret =
 356             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 357                                      cmd->size);
 358         return ret;
 359 }
 360
 361 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
 362 {
 363         drm_via_cmdbuffer_t *cmdbuf = data;
 364         int ret;
 365
 366         LOCK_TEST_WITH_RETURN(dev, file_priv);
 367
 368         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
 369
 370         ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
 371         if (ret) {
 372                 return ret;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 379                                          uint32_t * vb, int qw_count)
 380 {
 381         for (; qw_count > 0; --qw_count) {
 382                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 383         }
 384         return vb;
 385 }
 386
 387 /*
 388  * This function is used internally by ring buffer mangement code.
 389  *
 390  * Returns virtual pointer to ring buffer.
 391  */
 392 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 393 {
 394         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 395 }
 396
 397 /*
 398  * Hooks a segment of data into the tail of the ring-buffer by
 399  * modifying the pause address stored in the buffer itself. If
 400  * the regulator has already paused, restart it.
 401  */
 402 static int via_hook_segment(drm_via_private_t * dev_priv,
 403                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 404                             int no_pci_fire)
 405 {
 406         int paused, count;
 407         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 408         uint32_t reader,ptr;
 409
 410         paused = 0;
 411         via_flush_write_combine();
 412         (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
 413         *paused_at = pause_addr_lo;
 414         via_flush_write_combine();
 415         (void) *paused_at;
 416         reader = *(dev_priv->hw_addr_ptr);
 417         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 418                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 419         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 420
 421         if ((ptr - reader) <= dev_priv->dma_diff ) {
 422                 count = 10000000;
 423                 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
 424         }
 425
 426         if (paused && !no_pci_fire) {
 427                 reader = *(dev_priv->hw_addr_ptr);
 428                 if ((ptr - reader) == dev_priv->dma_diff) {
 429
 430                         /*
 431                          * There is a concern that these writes may stall the PCI bus
 432                          * if the GPU is not idle. However, idling the GPU first
 433                          * doesn't make a difference.
 434                          */
 435
 436                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 437                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 438                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 439                         VIA_READ(VIA_REG_TRANSPACE);
 440                 }
 441         }
 442
 443         return paused;
 444 }
 445
 446
 447
 448 static int via_wait_idle(drm_via_private_t *dev_priv)
 449 {
 450         int count = 10000000;
 451
 452         while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
 453
 454         while (count-- && (VIA_READ(VIA_REG_STATUS) &
 455                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 456                             VIA_3D_ENG_BUSY))) ;
 457         return count;
 458 }
 459
 460 static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,
 461                                uint32_t addr, uint32_t *cmd_addr_hi,
 462                                uint32_t *cmd_addr_lo, int skip_wait)
 463 {
 464         uint32_t agp_base;
 465         uint32_t cmd_addr, addr_lo, addr_hi;
 466         uint32_t *vb;
 467         uint32_t qw_pad_count;
 468
 469         if (!skip_wait)
 470                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
 471
 472         vb = via_get_dma(dev_priv);
 473         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 474                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 475
 476         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 477         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 478                 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 479
 480         cmd_addr = (addr) ? addr :
 481                 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 482         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 483                    (cmd_addr & HC_HAGPBpL_MASK));
 484         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 485
 486         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 487         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 488         return vb;
 489 }
 490
 491 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 492 {
 493         uint32_t pause_addr_lo, pause_addr_hi;
 494         uint32_t start_addr, start_addr_lo;
 495         uint32_t end_addr, end_addr_lo;
 496         uint32_t command;
 497         uint32_t agp_base;
 498         uint32_t ptr;
 499         uint32_t reader;
 500         int count;
 501
 502         dev_priv->dma_low = 0;
 503
 504         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 505         start_addr = agp_base;
 506         end_addr = agp_base + dev_priv->dma_high;
 507
 508         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 509         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 510         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 511                    ((end_addr & 0xff000000) >> 16));
 512
 513         dev_priv->last_pause_ptr =
 514                 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 515                               &pause_addr_hi, & pause_addr_lo, 1) - 1;
 516
 517         via_flush_write_combine();
 518         (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
 519
 520         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 521         VIA_WRITE(VIA_REG_TRANSPACE, command);
 522         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
 523         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
 524
 525         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 526         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 527         DRM_WRITEMEMORYBARRIER();
 528         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 529         VIA_READ(VIA_REG_TRANSPACE);
 530
 531         dev_priv->dma_diff = 0;
 532
 533         count = 10000000;
 534         while (!(VIA_READ(0x41c) & 0x80000000) && count--);
 535
 536         reader = *(dev_priv->hw_addr_ptr);
 537         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
 538             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 539
 540         /*
 541          * This is the difference between where we tell the
 542          * command reader to pause and where it actually pauses.
 543          * This differs between hw implementation so we need to
 544          * detect it.
 545          */
 546
 547         dev_priv->dma_diff = ptr - reader;
 548 }
 549
 550 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
 551 {
 552         uint32_t *vb;
 553
 554         via_cmdbuf_wait(dev_priv, qwords + 2);
 555         vb = via_get_dma(dev_priv);
 556         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
 557         via_align_buffer(dev_priv, vb, qwords);
 558 }
 559
 560 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 561 {
 562         uint32_t *vb = via_get_dma(dev_priv);
 563         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 564         SetReg2DAGP(0x10, 0 | (0 << 16));
 565         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 566 }
 567
 568 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 569 {
 570         uint32_t agp_base;
 571         uint32_t pause_addr_lo, pause_addr_hi;
 572         uint32_t jump_addr_lo, jump_addr_hi;
 573         volatile uint32_t *last_pause_ptr;
 574
 575         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 576         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 577                       &jump_addr_lo, 0);
 578
 579         dev_priv->dma_wrap = dev_priv->dma_low;
 580
 581
 582         /*
 583          * Wrap command buffer to the beginning.
 584          */
 585
 586         dev_priv->dma_low = 0;
 587         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
 588                 DRM_ERROR("via_cmdbuf_jump failed\n");
 589         }
 590
 591         via_dummy_bitblt(dev_priv);
 592         via_dummy_bitblt(dev_priv);
 593         last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 594                                        &pause_addr_lo, 0) -1;
 595         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 596                       &pause_addr_lo, 0);
 597         *last_pause_ptr = pause_addr_lo;
 598
 599         via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
 600 }
 601
 602 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
 603 {
 604         via_cmdbuf_jump(dev_priv);
 605 }
 606
 607 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 608 {
 609         uint32_t pause_addr_lo, pause_addr_hi;
 610
 611         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 612         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 613 }
 614
 615
 616 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
 617 {
 618         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 619 }
 620
 621 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 622 {
 623         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 624         via_wait_idle(dev_priv);
 625 }
 626
 627 /*
 628  * User interface to the space and lag functions.
 629  */
 630
 631 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
 632 {
 633         drm_via_cmdbuf_size_t *d_siz = data;
 634         int ret = 0;
 635         uint32_t tmp_size, count;
 636         drm_via_private_t *dev_priv;
 637
 638         DRM_DEBUG("\n");
 639         LOCK_TEST_WITH_RETURN(dev, file_priv);
 640
 641         dev_priv = (drm_via_private_t *) dev->dev_private;
 642
 643         if (dev_priv->ring.virtual_start == NULL) {
 644                 DRM_ERROR("called without initializing AGP ring buffer.\n");
 645                 return -EFAULT;
 646         }
 647
 648         count = 1000000;
 649         tmp_size = d_siz->size;
 650         switch (d_siz->func) {
 651         case VIA_CMDBUF_SPACE:
 652                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
 653                        && count--) {
 654                         if (!d_siz->wait) {
 655                                 break;
 656                         }
 657                 }
 658                 if (!count) {
 659                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 660                         ret = -EAGAIN;
 661                 }
 662                 break;
 663         case VIA_CMDBUF_LAG:
 664                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
 665                        && count--) {
 666                         if (!d_siz->wait) {
 667                                 break;
 668                         }
 669                 }
 670                 if (!count) {
 671                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 672                         ret = -EAGAIN;
 673                 }
 674                 break;
 675         default:
 676                 ret = -EFAULT;
 677         }
 678         d_siz->size = tmp_size;
 679
 680         return ret;
 681 }
 682
 683 #ifndef VIA_HAVE_DMABLIT
 684 int
 685 via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
 686         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 687         return -EINVAL;
 688 }
 689 int
 690 via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
 691         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 692         return -EINVAL;
 693 }
 694 #endif
 695
 696 struct drm_ioctl_desc via_ioctls[] = {
 697         DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
 698         DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),
 699         DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
 700         DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
 701         DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
 702         DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
 703         DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),
 704         DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
 705         DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
 706         DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
 707         DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
 708         DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
 709         DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
 710         DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
 711 };
 712
 713 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);