2 # Emulate a standalone simulator. Construct a sid configuration file
5 eval 'exec perl -S $0 ${1+"$@"}'
6 if $running_under_some_shell;
7 $running_under_some_shell = 0;
15 "arm" => "hw-cpu-arm7t",
16 "thumb" => "hw-cpu-arm7t",
17 "x86" => "hw-cpu-x86",
18 # INSERT NEW ENTRIES HERE
19 "m32r" => "hw-cpu-m32r/d",
20 "mep" => "hw-cpu-mep",
22 "sh5" => "hw-cpu-sh5",
23 "xstormy16" => "hw-cpu-xstormy16",
26 %cpu_defaultendian = (
35 "arm" => "sw-gloss-arm/angel",
36 "thumb" => "sw-gloss-arm/angel",
37 "x86" => "sw-gloss-generic/libgloss",
38 # INSERT NEW ENTRIES HERE
39 "m32r" => "sw-gloss-m32r/libgloss",
40 "mep" => "sw-gloss-generic/libgloss",
41 "mt" => "sw-gloss-generic/libgloss",
42 "sh5" => "sw-gloss-generic/libgloss",
43 "xstormy16" => "sw-gloss-generic/libgloss",
47 "arm" => "0x00000000,0x00800000",
48 "thumb" => "0x00000000,0x00800000",
49 "x86" => "0x00000,0x500000",
50 # INSERT NEW ENTRIES HERE
51 "m32r" => "0x00000000,0x00800000",
52 "mep" => "0x00000000,0x00200000:0x00300000,0x10000",
53 "mt" => "0x00000000,0x00800000",
54 "sh5" => "0x00000000,0x00800000", # check this
55 "xstormy16" => "0x00000000,0x00800000",
60 # ----------------------------------------------------------------------------
61 # Consume argument list
70 $opt_trace_semantics=0;
71 $opt_trace_disassemble=0;
74 $opt_trace_core_visual=0;
75 $opt_enable_warnings=0;
76 @opt_memory_region = ();
81 $opt_board="gloss-stdio";
103 # by default the loader data mapper connects to the cpu-mapper access-port
104 $load_mapper_data = "cpu-mapper access-port";
106 # (see perldoc Getopt::Long)
108 "help!" => ["help", "Print this help message."],
109 "version!" => ["version", "Print wrapper / sid versions."],
110 "cpu=s" => ["cpu=CPU (REQUIRED)", "Select target processor.", "none"],
111 "verbose|v!" => ["verbose|v", "Turn on various run-time verbosity settings.", "no"],
112 "save-temps!" => ["save-temps", "Keep generated sid configuration file.", "no"],
113 "trace-extract!" => ["trace-extract", "Turn on CPU insn decode tracing.", "no"],
114 "trace-semantics!" => ["trace-semantics", "Turn on CPU insn execute tracing.", "no"],
115 "trace-disassemble!" => ["trace-disassemble", "Turn on CPU insn execute disassembly.", "no"],
116 "trace-counter!" => ["trace-counter", "Turn on CPU insn counter.", "no"],
117 "trace-core!" => ["trace-core", "Turn on bus access tracing.", "no"],
118 # "trace-core-visual!" => ["trace-core-visual", "Turn on visual bus access tracing.", "no"],
119 "enable-warnings!" => ["enable-warnings", "Enable CPU execution warnings.", "no"],
120 "memory-region=s@" => ["memory-region=BASE,SIZE", "Add RAM region from BASE to BASE+SIZE-1.", "no",
122 " bus=MAPPER Attach memory to bus MAPPER",
123 " read-only Make memory read-only",
124 " alias=BASE2 Add an alias at BASE2",
125 " file=FILENAME Load/save memory image from file",
126 " mmap Memory map given file",
127 " latency=R:W Set read, write latencies [0:0]",
128 " latency=RW Set both latencies [0]"],
129 "gdb=i" => ["gdb=PORT", "Add a gdb/debugger interface on TCP port.", "",
130 "Equivalent to --gdbport cpu=PORT. [none]"],
131 "gdbport=i%" => ["gdbport PROCESSOR=PORT", "Add a gdb/debugger interface on TCP port", "",
132 "for the given processor. May be specified",
133 "more than once to debug multiple CPUs. [none]"],
134 "tksched!" => ["tksched", "Add a simple visual scheduler controller.", "no"],
135 "tksm!" => ["tksm", "Add an experimental Tk system monitor.", "no"],
136 "board=s" => ["board=BOARD", "Model given board or system.", "gloss"],
137 "engine=s" => ["engine=scache|pbb", "Set given cgen CPU engine.", "pbb"],
138 "EB!" => ["-EB | -EL", "Set powerup CPU mode to big/little endian.", "auto"],
140 "persistent!" => ["persistent", "Rerun top-level loop indefinitely.", "no"],
141 "no-run!" => ["no-run", "Make config file (--save-temps) and exit.", "no"],
142 "insn-count=i" => ["insn-count=N", "Block of uninterrupted ticks for insns", "10000"],
143 "gprof!" => ["gprof", "GPROF-profile, collect every insn-count ticks", "no"],
146 "wrap=s@" => ["wrap=COMPONENT", "Turn on SID API tracing for named component", "none"],
147 "load=s%" => ["load PROCESSOR=NAME", "Specify an executable to be loaded into", "",
148 "a specific processor. May be specified more",
149 "than once to load multiple processors. [cpu=exec]"],
150 "icache=s" => ["icache=TYPE", "Add an instruction cache.", "none"],
151 "dcache=s" => ["dcache=TYPE", "Add a data cache.", "none",
152 "refer to any existing \"hw-cache-TYPE\" component type",
153 "e.g., direct/64kb/32, 4way/256kb/64/lru"],
156 @options = keys (%options);
159 print STDERR "\nUsage: $0 --cpu=CPU [option ..] [--] [exec args ..]\n";
160 print STDERR "Options:\n";
162 foreach $usage_msgs (sort (values %options))
164 my $num_entries = scalar (@{$usage_msgs});
165 next if ($num_entries < 2);
167 my $option = @{$usage_msgs}[0];
168 my $synopsis = @{$usage_msgs}[1];
169 my $default = @{$usage_msgs}[2];
171 # Special handling for single dash options (eg. -EL).
174 printf STDERR " %-26s ", $option;
176 printf STDERR " --%-24s ", $option;
179 # If a default value has been given, display it within [ ].
182 my $width = 48 - length ($default);
183 printf STDERR "%-${width}s%s\n", $synopsis, "[" . $default . "]";
187 printf STDERR "%s\n", $synopsis;
190 # Print any supplementary lines of help.
191 for ($i = 3; $i < $num_entries; $i++)
193 printf STDERR "%28s%s\n", " ", @{$usage_msgs}[$i];
202 $memspecs = $gloss_memspecs{$opt_cpu};
203 @regions = split (/:/, $memspecs);
204 foreach $region (@regions)
206 push @opt_memory_region, $region;
209 $gloss_component_type = $gloss_comptype{$opt_cpu} || die "Unknown cpu $opt_cpu for gloss component type\n";
210 $first_section .= "# gloss\n" .
211 &sidconf_new("$gloss_component_type", "gloss") . "\n";
213 $second_section .= "# gloss
215 connect-pin init-sequence output-2 -> gloss reset
216 connect-pin cpu trap <-> gloss trap
217 connect-pin cpu trap-code -> gloss trap-code
218 set gloss verbose? $opt_verbose
219 connect-bus gloss target-memory $bus_upstream
221 if ($opt_cpu eq "x86")
223 $second_section .= "set gloss syscall-numbering-scheme cygmon\n";
226 if ($#exec_args >= 0) {
227 $second_section .= "# args
228 set gloss command-line \"$exec @exec_args\"
237 $first_section .= "# gloss <-> tty\n" .
238 &sidconf_new("hw-visual-tty", "tty") . "\n";
239 $third_section .= "# gloss <-> tty
240 relate tty \"$gloss_component_type gloss\" gloss
244 # check if gdb option is not specified
247 # gloss-stdio only allowed if gdb not specified
248 if ($board =~ /stdio/)
250 $first_section .= "# gloss <-> stdio\n" .
251 &sidconf_new("sid-io-stdio", "stdio") . "\n";
252 $second_section .= "# gloss <-> stdio
253 set host-sched 0-regular? 1
254 set host-sched 0-time 150 # apprx. human perception limit
255 connect-pin host-sched 0-event -> stdio poll
256 connect-pin gloss debug-tx -> stdio stdout
257 connect-pin gloss debug-rx <- stdio stdin
260 $second_section .= "# gloss w/o gdb
261 connect-pin gloss process-signal -> main stop!
262 connect-pin gloss process-signal -> yield-net input
265 # gloss gdb connections handled later in gdb section
268 my @ARGV_COPY = @ARGV;
271 &GetOptions(@options);
273 # handle version/help
275 print STDERR "$version\n";
276 system ("$sid", "-v");
279 if ($opt_help || $opt_cpu eq "") {
283 # handle leftover options
284 $exec = $#ARGV >= 0 ? (shift @ARGV) : "";
286 foreach $arg (@ARGV) {
287 # The double quotemeta() call is intended to allow arguments containing
288 # weird characters to go through both the cfgroot parser AND the run-time
289 # target libgloss parser.
290 push @exec_args, quotemeta(quotemeta($arg));
293 #if (!$exec && !$opt_gdb)
295 # warn "Executable name not supplied";
298 # --load cpu=<name> overrides $exec
299 if ($opt_load{"cpu"})
301 if ($exec && $exec ne $opt_load{"cpu"})
303 warn "--load cpu=" . $opt_load{"cpu"} . " overrides $exec\n";
305 $exec = $opt_load{"cpu"};
309 $opt_load{"cpu"} = "$exec";
312 # --gdbport cpu=port overrides --gdb
313 if ($opt_gdbport{"cpu"})
315 if ($opt_gdb && $opt_gdb ne $opt_gdbport{"cpu"})
317 warn "--gdbport cpu=" . $opt_gdbport{"cpu"} . " overrides --gdb=$opt_gdb\n";
319 $opt_gdb = $opt_gdbport{"cpu"};
323 $opt_gdbport{"cpu"} = $opt_gdb;
328 die "Cannot read executable `$exec'" if (! -r $exec && ! $opt_no_run);
331 # infer --save-temps from --no-run
332 if ($opt_no_run && (! $opt_save_temps))
337 # infer --persistent from --gdb=xxxx
343 # complete component library list
345 "audio" => "audio_component_library",
346 "cache" => "cache_component_library",
347 "cgencpu" => "cgen_component_library",
348 "consoles" => "console_component_library",
349 "gdb" => "gdb_component_library",
350 "gloss" => "gloss_component_library",
351 "glue" => "glue_component_library",
352 "ide" => "ide_component_library",
353 "interrupt" => "interrupt_component_library",
354 "hd44780u" => "hd44780u_component_library",
355 "loader" => "loader_component_library",
356 "mapper" => "mapper_component_library",
357 "memory" => "mem_component_library",
358 "mmu" => "mmu_component_library",
359 "parport" => "parport_component_library",
360 "prof" => "prof_component_library",
361 "rtc" => "rtc_component_library",
362 "sched" => "sched_component_library",
363 "tclapi" => "tcl_bridge_library",
364 "timers" => "timer_component_library",
365 "uart" => "uart_component_library",
366 "x86" => "x86_component_library"
370 # ----------------------------------------------------------------------------
371 # Configuration file construction
373 # Don't bother compute accurate values if config file is temporary
375 if ($opt_norun || $opt_save_temps) {
376 $whoami=qx{whoami}; chop ($whoami);
377 $hostname=qx{hostname}; chop ($hostname);
378 $date=qx{date}; chop ($date);
379 $uname=qx{uname}; chop ($uname);
386 $zeroth_section = "# sid configuration file
387 # created by $version
388 # run by $whoami @ $hostname ($uname) at $date
389 # args: @ARGV_COPY\n";
391 if ($opt_verbose) { $zeroth_section .= "set main verbose? true\n"; }
393 $cpu_component_type = $cpu_comptype{$opt_cpu} || die "Unknown cpu $opt_cpu for cpu component type\n";
394 $first_section = "# first section\n" .
395 &sidconf_new("$cpu_component_type", "cpu") . "\n" .
396 &sidconf_new("hw-mapper-basic", "cpu-mapper") . "\n" .
397 &sidconf_new("hw-glue-sequence-8", "init-sequence") . "\n" .
398 &sidconf_new("hw-glue-sequence-1", "hw-reset-net") . "\n" .
399 &sidconf_new("hw-glue-sequence-8", "deinit-sequence") . "\n" .
400 &sidconf_new("hw-glue-sequence-1", "yield-net") . "\n" .
401 &sidconf_new("hw-glue-sequence-2", "cache-flush-net") . "\n" .
402 &sidconf_new("sid-sched-host-accurate", "host-sched") . "\n" .
403 &sidconf_new("sid-sched-sim", "target-sched") . "\n" .
406 if ($opt_cpu eq "mt")
408 $first_section .= "# add io bus probe\n" .
409 &sidconf_new("hw-glue-probe-bus", "io-bus-probe") . "\n";
412 if ($opt_trace_core || $opt_trace_core_visual)
414 $first_section .= "# core tracing\n" .
415 &sidconf_new("hw-glue-probe-bus", "bus-probe") . "\n";
416 $bus_upstream = "bus-probe upstream";
420 $bus_upstream = "cpu-mapper access-port";
425 $cpu_insn_count = $opt_insn_count;
429 $cpu_insn_count = 10000;
434 $first_section .= "# gprof\n" .
435 &sidconf_new("sw-profile-gprof", "gprof") . "\n";
438 $enable_z_packet = "false";
439 $second_section = "# second section
441 set cpu step-insn-count $cpu_insn_count\n" .
442 ($opt_trace_semantics ? "set cpu trace-semantics? $opt_trace_semantics\n" : "") .
443 ($opt_trace_disassemble ? "set cpu trace-disassemble? $opt_trace_disassemble\n" : "") .
444 ($opt_trace_counter ? "set cpu trace-counter? $opt_trace_counter\n" : "") .
445 ($opt_trace_extract ? "set cpu trace-extract? $opt_trace_extract\n" : "") .
446 ($opt_enable_warnings ? "set cpu enable-warnings? $opt_enable_warnings\n" : "") .
447 "set host-sched num-clients 10 # large enough?
448 set target-sched num-clients 10 # large enough?
450 connect-pin main perform-activity -> host-sched advance
451 connect-pin main perform-activity -> target-sched advance
452 connect-pin main starting -> init-sequence input
453 connect-pin main stopping -> deinit-sequence input
454 connect-pin init-sequence output-0 -> hw-reset-net input
455 connect-pin hw-reset-net output-0 -> cpu reset!
456 set target-sched 0-name \"CPU stepping\"
457 connect-pin target-sched 0-event -> cpu step!
458 connect-pin target-sched 0-control <- cpu step-cycles
459 connect-pin target-sched time-query <- cpu time-query
460 connect-pin target-sched time-high -> cpu time-high
461 connect-pin target-sched time-low -> cpu time-low
462 connect-pin yield-net output-0 -> cpu yield
463 connect-pin yield-net output-0 -> host-sched yield
467 $first_section .= &sidconf_new("hw-cache-$opt_icache", "icache") . "\n";
468 $second_section .= "connect-bus cpu insn-memory icache upstream
469 connect-bus icache downstream $bus_upstream
470 set icache report-heading \"icache profile report\"
471 connect-pin init-sequence output-1 -> icache invalidate-all
472 connect-pin deinit-sequence output-6 -> icache report!
473 connect-pin cache-flush-net output-0 -> icache flush-all
474 connect-pin cache-flush-net output-1 -> icache invalidate-all\n";
475 # $bus_upstream = "icache upstream";
477 $second_section .= "connect-bus cpu insn-memory $bus_upstream\n";
481 $first_section .= &sidconf_new("hw-cache-$opt_dcache", "dcache") . "\n";
482 $second_section .= "connect-bus cpu data-memory dcache upstream
483 connect-bus dcache downstream $bus_upstream
484 set dcache report-heading \"dcache profile report\"
485 connect-pin init-sequence output-1 -> dcache invalidate-all
486 connect-pin deinit-sequence output-6 -> dcache report!
487 connect-pin cache-flush-net output-0 -> dcache flush-all
488 connect-pin cache-flush-net output-1 -> dcache invalidate-all\n";
489 $bus_upstream = "dcache upstream";
491 $second_section .= "connect-bus cpu data-memory $bus_upstream\n";
494 if ($opt_cpu eq "x86")
496 $second_section .= "set cpu memory-mode cygmon\n";
499 if ($opt_cpu eq "mt")
501 # Uncomment the next three lines to enable io bus tracing.
502 #$second_section .= "# Connect bus tracer to io bus accessor\n" .
503 #"connect-bus cpu io-memory io-bus-probe upstream\n" .
504 #"set io-bus-probe trace? 1\n";
509 $second_section .= "# gprof connections
510 connect-pin deinit-sequence output-7 -> gprof store
511 connect-pin cpu sample-gprof -> gprof sample
512 connect-pin cpu gprof-pc -> gprof pc
513 connect-pin cpu gprof-pc-hi -> gprof pc-hi
514 connect-pin cpu cg-caller -> gprof cg-caller
515 connect-pin cpu cg-callee -> gprof cg-callee
516 relate gprof target-component cpu
518 if ($opt_cpu eq "mep") {
519 $second_section .= "set gprof bucket-size 2\n";
522 $second_section .= "set gprof bucket-size 4\n";
526 if ($opt_trace_core || $opt_trace_core_visual)
528 $second_section .= "# core tracing
529 connect-bus bus-probe downstream cpu-mapper access-port
535 $second_section .= "set bus-probe trace? 1\n";
541 # ----------------------------------------------------------------------------
542 # Board-dependent logic
545 if ($opt_board =~ /pid7t/)
548 # XXX: what about SRAM, SSRAM memory regions???
550 if ($opt_board =~ /cygmon/)
552 die "board pid7t-cygmon only supported in little-endian mode (-EL)\n" unless ($opt_EL);
553 unshift @opt_memory_region, ( "0x04000000,0x00100000,file=armpid-cygmon.img,read-only" );
555 elsif ($opt_board =~ /eCosstub/)
557 die "board pid7t-eCos only supported in little-endian mode (-EL)\n" unless ($opt_EL);
558 unshift @opt_memory_region, ( "0x04000000,0x00100000,file=armpid-eCos.img,read-only" );
560 if ($opt_board =~ /redboot/)
562 die "board pid7t-redboot only supported in little-endian mode (-EL)\n" unless ($opt_EL);
563 unshift @opt_memory_region, ( "0x04000000,0x00100000,file=armpid-redboot.img,read-only" );
567 unshift @opt_memory_region, ( "0x04000000,0x00100000" ); # default 1MB ROM - writeable
570 unshift @opt_memory_region, ( "0x00000000,0x01000000" ); # default 16MB RAM
572 $first_section .= "# pid7t components\n" .
573 &sidconf_new("hw-remap/pause-arm/ref", "remapper") . "\n" .
574 &sidconf_new("hw-timer-arm/ref-sched", "timer1") . "\n" .
575 &sidconf_new("hw-timer-arm/ref-sched", "timer2") . "\n" .
576 &sidconf_new("hw-interrupt-arm/ref", "intctrl") . "\n" .
577 &sidconf_new("hw-uart-ns16550", "uart1") . "\n" .
578 &sidconf_new("hw-uart-ns16550", "uart2") . "\n" .
579 &sidconf_new("hw-parport-ps/2", "parport") . "\n" .
582 $second_section .= "# pid7t control connections
583 connect-pin target-sched 2-control <- timer1 divided-clock-control
584 connect-pin target-sched 2-event -> timer1 divided-clock-event
585 set target-sched 2-scale 1/4 # artificial speed-up
586 connect-pin timer1 interrupt -> intctrl interrupt-source-4
587 connect-pin target-sched 3-control <- timer2 divided-clock-control
588 connect-pin target-sched 3-event -> timer2 divided-clock-event
589 set target-sched 3-scale 1/4 # artificial speed-up
590 connect-pin timer2 interrupt -> intctrl interrupt-source-5
591 connect-pin intctrl interrupt -> cpu nirq
592 connect-pin intctrl fast-interrupt -> cpu nfiq
593 connect-pin hw-reset-net output-0 -> uart1 Reset
594 connect-pin hw-reset-net output-0 -> uart2 Reset
595 connect-pin hw-reset-net output-0 -> intctrl reset
596 connect-pin hw-reset-net output-0 -> timer1 reset
597 connect-pin hw-reset-net output-0 -> timer2 reset
598 connect-pin uart1 INTR -> intctrl interrupt-source-8
599 connect-pin uart2 INTR -> intctrl interrupt-source-9
600 connect-pin parport INTP -> intctrl interrupt-source-10
602 connect-bus cpu-mapper intctrl:[0xA000000,0xA000013] intctrl irq-registers
603 connect-bus cpu-mapper intctrl:[0xA000100,0xA00010F] intctrl fiq-registers
604 connect-bus cpu-mapper timer1:[0xA800000,0xA80000F] timer1 registers
605 connect-bus cpu-mapper timer2:[0xA800020,0xA80002F] timer2 registers
606 connect-bus cpu-mapper remapper:[0xB000000,0xB000037] remapper registers
607 connect-bus cpu-mapper uart1:[0xD800000,0xD80001F,4,1] uart1 Bus
608 connect-bus cpu-mapper uart2:[0xD800020,0xD80003F,4,1] uart2 Bus
609 connect-bus cpu-mapper parport:[0xD800040,0xD80005F,4,1] parport Bus
610 # set uart unframed mode
611 set uart1 sio-framing? 0
612 set uart2 sio-framing? 0
613 # remapper configuration
614 # NB: remapping polarity is opposite to document
615 set remapper num-relocations 1
616 set remapper 0-start 0x0
617 set remapper 0-end 0xFFFF
618 set remapper 0-reloc-to 0x04000000
621 # reconnect bus masters to pass through remapper
622 $third_section .= "# remapper reconnection
623 connect-bus remapper all $bus_upstream
624 disconnect-bus cpu insn-memory $bus_upstream
625 connect-bus cpu insn-memory remapper access-port
626 disconnect-bus cpu data-memory $bus_upstream
627 connect-bus cpu data-memory remapper access-port
630 # create uart <-> real world connections
631 if ($opt_board =~ /normalmap/)
633 $third_section .= "# disable remapper
634 set remapper remapping? no
638 # pull in this configuration.
639 configure_uart1_uart2();
641 elsif ($opt_board =~ /^cma110/)
644 # PS/2 kbd/ms, PCI, flash, gloss
646 unshift @opt_memory_region, ( "0x00000000,0x00800000" ); # default 8MB RAM
647 if ($opt_board =~ /:cma222/)
650 $first_section .= "# cma110/cma222 specific parts\n" .
651 &sidconf_new("hw-timer-arm/ref-sched", "timer") . "\n" .
652 &sidconf_new("hw-interrupt-cogent/cma222", "intctrl") . "\n" .
655 $second_section .= "# cma222 control connections
656 connect-pin target-sched 2-control <- timer divided-clock-control
657 connect-pin target-sched 2-event -> timer divided-clock-event
658 connect-pin timer interrupt -> intctrl interrupt-source-4
659 connect-pin intctrl interrupt -> cpu nirq
660 # connect the on-cpu board devices
661 connect-bus cpu-mapper intctrl:[0xF600000,0xF600037] intctrl irq-registers
662 connect-bus cpu-mapper timer:[0xF700020,0xF70003F] timer registers
667 die "Unknown board `$opt_board'\n";
670 $first_section .= "# cma110 common parts\n" .
671 &sidconf_new("hw-uart-ns16550", "uart1") . "\n" .
672 &sidconf_new("hw-uart-ns16550", "uart2") . "\n" .
673 &sidconf_new("hw-parport-ps/2", "parport") . "\n" .
674 &sidconf_new("hw-rtc-ds1642", "rtc") . "\n" .
675 &sidconf_new("hw-lcd-hd44780u-a02", "lcd") . "\n" .
676 &sidconf_new("hw-visual-lcd", "display") . "\n" .
679 $second_section .= "# cma110 control connections
680 connect-pin hw-reset-net output-0 -> uart1 Reset
681 connect-pin hw-reset-net output-0 -> uart2 Reset
682 connect-pin hw-reset-net output-0 -> timer reset
683 connect-pin uart1 INTR -> intctrl interrupt-source-2
684 connect-pin uart2 INTR -> intctrl interrupt-source-1
685 connect-pin parport INTP -> intctrl interrupt-source-4
686 # configure the clock
687 set host-sched num-clients 10
688 set host-sched 0-regular? 1
689 set host-sched 0-time 1000 # 1 sec
690 connect-pin host-sched 0-event -> rtc clock
691 connect-pin rtc clock-control -> host-sched 1-control
692 connect-pin rtc clock-event <- host-sched 1-event
694 #set display width 40 # 8 chars X 5 pixels per char
695 # note that hw-lcd-hd44780u may not support width of 80; this board
697 set display width 80 # 16 chars X 5 pixels per char
698 set display height 16 # two lines of 8 pixels
699 connect-pin host-sched 9-event -> lcd refresh-sync-event
700 connect-pin host-sched 9-control <- lcd refresh-sync-control
701 connect-pin lcd row-col -> display row-col
702 connect-pin lcd FR -> display FR
705 #connect-bus PCI pcibus:[0x4000000,0x5FEFFFF] pcibus config-space
706 #connect-bus ??? ??????:[0x5FF0000,0x5FFFFFF] v360epc registers
707 # ARM EPROM/FLASH memory
708 connect-bus cpu-mapper rtc:[0xE800000,0xE803FFF] rtc read-write-port
709 connect-bus cpu-mapper uart1:[0xE900000,0xE90001F,4,1] uart1 Bus
710 connect-bus cpu-mapper uart2:[0xE900020,0xE90003F,4,1] uart2 Bus
711 connect-bus cpu-mapper parport:[0xE900080,0xE90009F,4,1] parport Bus
713 connect-bus cpu-mapper lcd:[0xE900100,0xE90010F,4,1] lcd bus
715 #connect-bus PCI pcibus:[0xF200000,0xF2FFFFF] pcibus control-registers
716 # set uart unframed mode
717 set uart1 sio-framing? 0
718 set uart2 sio-framing? 0
721 # pull in this configuration.
722 configure_uart1_uart2();
725 elsif ($opt_cpu eq "mep" && ($opt_board ne "gloss-stdio"))
727 # Fallback defaults for incomplete configurations
728 $mepcfg_index = -1; # flag to detect match
730 $mepcfg_core_rev = 1;
731 $mepcfg_imem_size = 0;
732 $mepcfg_dmem_size = 0;
733 $mepcfg_icache_size = 0;
734 $mepcfg_icache_way = 1;
735 $mepcfg_icache_line_size = 32;
736 $mepcfg_dcache_size = 0;
737 $mepcfg_dcache_way = 1;
738 $mepcfg_dcache_line_size = 32;
740 $mepcfg_intc_channel_bitw = 32;
743 $mepcfg_cop_vliw_bitw = 0;
747 $mepcfg_opt_clip = 0;
759 $mepcfg_imem_size = 16;
760 $mepcfg_dmem_size = 32;
761 $mepcfg_icache_size = 16;
762 $mepcfg_icache_way = 1;
763 $mepcfg_icache_line_size = 32;
764 $mepcfg_dcache_size = 16;
765 $mepcfg_dcache_way = 1;
766 $mepcfg_dcache_line_size = 32;
767 $mepcfg_intc_channel_bitw = 16;
769 $mepcfg_cop_vliw_bitw = 64;
779 $mepcfg_endian = "big";
786 # Eww, ugly hack to change "hw-cpu-mep" in $first_section to
787 # "hw-cpu-mep-extNNN" for NNN=$mepcfg_index
788 $first_section =~ s|new hw-cpu-mep|new hw-cpu-mep-ext$mepcfg_index|;
791 if ($mepcfg_endian eq "big") { $opt_EB = 1; }
792 elsif ($mepcfg_endian eq "little") { $opt_EL = 1; }
794 $csr17 = (($mepcfg_core_id << 16) | (1 << 8) | $mepcfg_core_rev);
795 $second_section .= "set cpu csr17 $csr17\n";
797 $second_section .= "set cpu abs-option? " . ($mepcfg_opt_abs) . "\n";
798 $second_section .= "set cpu ave-option? " . ($mepcfg_opt_ave) . "\n";
799 $second_section .= "set cpu bit-option? " . ($mepcfg_opt_bit) . "\n";
800 $second_section .= "set cpu clip-option? " . ($mepcfg_opt_clip) . "\n";
801 $second_section .= "set cpu cp-option? " . ($mepcfg_opt_cp) . "\n";
802 $second_section .= "set cpu div-option? " . ($mepcfg_opt_div) . "\n";
803 $second_section .= "set cpu ldz-option? " . ($mepcfg_opt_ldz) . "\n";
804 $second_section .= "set cpu minmax-option? " . ($mepcfg_opt_min) . "\n";
805 $second_section .= "set cpu mul-option? " . ($mepcfg_opt_mul) . "\n";
806 $second_section .= "set cpu sat-option? " . ($mepcfg_opt_sat) . "\n";
808 $second_section .= "set cpu debug-option? " . ($mepcfg_dsu) . "\n";
809 $second_section .= "set cpu dsp-option? " . ($mepcfg_dsp) . "\n";
810 $second_section .= "set cpu uci-option? " . ($mepcfg_uci) . "\n";
812 $second_section .= "set cpu vliw32-option? " . ($mepcfg_cop_vliw_bits == 32 ? 1 : 0) . "\n";
813 $second_section .= "set cpu vliw64-option? " . ($mepcfg_cop_vliw_bits == 64 ? 1 : 0) . "\n";
815 # dmem/imem calculations; see mep RCFG definition and memory layout chapter
816 $mep_imem_base = ($mepcfg_imem_size == 0 ? 0 : 0x00200000);
817 $mep_imem_size = 1024 * $mepcfg_imem_size;
818 $mep_dmem_base = (($mepcfg_dmem_size == 0) ? 0 :
819 ($mepcfg_imem_size == 0) ? 0x00200000 :
820 ($mepcfg_dmem_size > 16) ? 0x00208000 :
821 ($mepcfg_imem_size >= 12) ? 0x00204000 :
822 ($mepcfg_dmem_size <= 8) ? 0x00202000 :
823 ($mepcfg_dmem_size <= 16) ? 0x00204000 :
824 0xdeadbeef); # can't happen
826 $mep_dmem_bank0_base = $mep_dmem_base;
827 $mep_dmem_bank1_base = $mep_dmem_base + 1024 * ($mepcfg_dmem_size == 6 ? 4 :
828 $mepcfg_dmem_size == 12 ? 8 :
829 $mepcfg_dmem_size == 24 ? 16 :
830 $mepcfg_dmem_size / 2);
831 $mep_dmem_bank0_size = 1024 * $mepcfg_dmem_size / 2;
832 $mep_dmem_bank1_size = 1024 * $mepcfg_dmem_size / 2;
834 # These are complex bitfields:
835 # LCFG: local memory configuration
836 $csr27 = (0x01000100 | # fixed bits
837 ($mepcfg_imem_size << 16) | # IRSZ
838 ($mepcfg_dmem_size << 0) | # DRSZ
839 (($mep_dmem_base >> 12) & 0xf)); # DRBA
840 $second_section .= "set cpu csr27 $csr27\n";
842 # CCFG: cache memory configuration
843 $csr28 = (0x00000000 | # no fixed bits
844 ($mepcfg_icache_size << 16) | # ICSZ
845 ($mepcfg_dcache_size << 0)); # DCSZ
846 $second_section .= "set cpu csr28 $csr28\n";
849 $zeroth_section .= "load libmepfamily.la mepfamily_component_library\n";
850 $first_section .= "# control space
851 new hw-mapper-basic cpu-control-space
852 set cpu-control-space latency 1
853 new hw-mapper-basic cpu-local-space
855 ($mepcfg_dsu ? "new hw-debug-mep cpu-dsu\n" : "") .
856 ($mepcfg_dmac ? "new hw-dma-mep cpu-dmac\n" : "") .
857 ($mepcfg_intc ? "new hw-interrupt-mep-${mepcfg_intc_channel_bitw} cpu-intc\n" : "");
859 $second_section .= "# configuration / connection of control space peripherals
860 connect-bus cpu control-space cpu-control-space access-port
862 ($mepcfg_dsu ? "connect-bus cpu-control-space dsu[4*0x800-0x802] cpu-dsu status-regs
863 connect-bus cpu-control-space dsu[4*0x900-0x902] cpu-dsu insn-regs
864 connect-bus cpu-control-space dsu[4*0xA00-0xA05] cpu-dsu data-regs\n" : "") .
865 ($mepcfg_dmac ? "connect-bus cpu-control-space dmac[4*0x1000-0x1009] cpu-dmac control-regs-low
866 connect-bus cpu-control-space dmac[4*0x1FFF-0x1FFF] cpu-dmac control-regs-high\n" : "") .
867 ($mepcfg_intc ? "connect-bus cpu-control-space intc[4*0x0-0x7] cpu-intc registers\n" : "");
870 ($mepcfg_dmac ? "# mep dmac connection
871 connect-bus cpu-dmac local-memory cpu-local-space access-port
872 connect-bus cpu-dmac main-memory cpu-mapper access-port
873 set target-sched 2-name \"DMA controller burst events\"
874 connect-pin target-sched 2-event -> cpu-dmac burst-event
875 connect-pin target-sched 2-control <- cpu-dmac burst-control
877 ($mepcfg_intc ? "# mep intc connection
878 connect-pin cpu-intc interrupt -> cpu interrupt
881 # mep instruction fetch buffer: 8 bytes
882 $first_section .= "# instruction fetch buffer
883 new hw-cache-buffer-8 cpu-insn-buffer
884 set cpu-insn-buffer write-through? true
885 connect-pin cache-flush-net output-0 -> cpu-insn-buffer flush-all
886 connect-pin init-sequence output-1 -> cpu-insn-buffer invalidate-all
889 # "default" memory layout
890 push @opt_memory_region, "0x00000000,0x200,latency=5"; # vec
891 push @opt_memory_region, "0x00010000,0x60000,latency=5"; # romdata.m
892 push @opt_memory_region, "0x00080000,0x80000,latency=5"; # code.m
893 push @opt_memory_region, "0x00100000,0x80000,latency=5"; # data.m
894 # push @opt_memory_region, "0x00300000,0x10000"; # icache data testing area
895 # push @opt_memory_region, "0x00310000,0x10000"; # icache tag testing area
896 # push @opt_memory_region, "0x00320000,0x10000"; # dcache data testing area
897 # push @opt_memory_region, "0x00330000,0x10000"; # dcache tag testing area
898 push @opt_memory_region, "0x01000000,0x8000,latency=5"; # romdata.s
899 push @opt_memory_region, "0x01008000,0x8000,latency=5"; # data.s
900 push @opt_memory_region, "0x02000000,0x100000,latency=5"; # data.l
901 push @opt_memory_region, "0x02200000,0x100000,latency=5"; # romdata.l
902 push @opt_memory_region, "0x02300000,0x100000,latency=5"; # code.l
903 push @opt_memory_region, "0x03000000,0x100000,latency=5"; # stack
904 push @opt_memory_region, "0x04000000,0x100000,latency=5"; # heap
906 $third_section .= "connect-bus cpu-mapper local:[0x00200000,0x00210000] cpu-local-space access-port\n";
908 push @opt_memory_region, ($mep_imem_base - 0x00200000) . "," . $mep_imem_size . ",bus=cpu-local-space,latency=2" if $mep_imem_size;
909 push @opt_memory_region, ($mep_dmem_bank0_base - 0x00200000) . "," . $mep_dmem_bank0_size . ",bus=cpu-local-space,latency=2" if $mep_dmem_bank0_size;
910 push @opt_memory_region, ($mep_dmem_bank1_base - 0x00200000) . "," . $mep_dmem_bank1_size . ",bus=cpu-local-space,latency=2" if $mep_dmem_bank1_size;
912 if ($mepcfg_icache_size)
915 ($mepcfg_icache_way == 1 ? "direct" : ($mepcfg_icache_way . "way")) . "/" .
916 $mepcfg_icache_size . "kb" . "/" .
917 $mepcfg_icache_line_size .
918 ($mepcfg_icache_way == 1 ? "" : "/random");
920 configure_mep_cached_bus("insn", $cachetype, $mepcfg_dsu);
921 $third_section .= "# icache tag test area
922 new hw-glue-probe-bus cpu-insn-cache-tagtest
923 new hw-memory-ram/rom-basic cpu-insn-cache-tag
924 set cpu-insn-cache-tag size 0x10000
925 connect-bus cpu-mapper [0x00310000-0x0031FFFF] cpu-insn-cache-tagtest upstream
926 connect-bus cpu-insn-cache-tagtest downstream cpu-insn-cache-tag read-write-port
927 connect-pin cpu-insn-cache-tagtest address -> cpu-insn-cache invalidate-all
933 disconnect-bus cpu insn-memory cpu-mapper access-port
934 connect-bus cpu insn-memory cpu-insn-buffer upstream
935 connect-bus cpu-insn-buffer downstream cpu-mapper access-port
936 connect-pin init-sequence output-0 -> cpu-insn-buffer invalidate-all\n";
938 if ($mepcfg_dcache_size)
941 ($mepcfg_dcache_way == 1 ? "direct" : ($mepcfg_dcache_way . "way")) . "/" .
942 $mepcfg_dcache_size . "kb" . "/" .
943 $mepcfg_dcache_line_size .
944 ($mepcfg_dcache_way == 1 ? "" : "/random");
945 configure_mep_cached_bus("data", $cachetype, $mepcfg_dsu);
946 $bus_upstream = "cpu-data-cachefilter access-port";
947 $third_section .= "# dcache tag test area
948 new hw-glue-probe-bus cpu-data-cache-tagtest
949 new hw-memory-ram/rom-basic cpu-data-cache-tag
950 set cpu-data-cache-tag size 0x10000
951 connect-bus cpu-mapper [0x00330000-0x0033FFFF] cpu-data-cache-tagtest upstream
952 connect-bus cpu-data-cache-tagtest downstream cpu-data-cache-tag read-write-port
953 connect-pin cpu-data-cache-tagtest address -> cpu-data-cache invalidate-all
958 $bus_upstream = "cpu-mapper access-port";
961 if ($opt_board =~ /gloss/)
963 # prevent configure_gloss from adding in the overlapping defaults
964 $gloss_memspecs{$opt_cpu}="";
965 configure_gloss ($opt_board);
968 elsif ($opt_board =~ /gloss/)
970 configure_gloss($opt_board);
974 die "Unknown board `$opt_board'\n";
979 # ------------------------------------------------------------------------
982 if ($opt_EB && $opt_EL) { die "Both -EB and -EL specified\n"; }
983 if (!$opt_EB && !$opt_EL && $opt_gdb != 0)
985 if ($cpu_defaultendian{$opt_cpu} eq "-EB") { $opt_EB = 1; }
986 elsif ($cpu_defaultendian{$opt_cpu} eq "-EL") { $opt_EL = 1; }
987 else { warn "Should specify endianness"; &usage; }
989 elsif (!$opt_EB && !$opt_EL && !$exec)
991 warn "Should specify executable"; &usage;
993 if ($opt_EB) { $third_section .= "set cpu endian big\n"; }
994 if ($opt_EL) { $third_section .= "set cpu endian little\n"; }
997 # ----------------------------------------------------------------------------
1000 # this is used by both the arm710t and cogent cma110 boards.
1001 sub configure_uart1_uart2
1003 # create uart <-> real world connections
1004 if ($opt_board =~ /uart1:stdio/)
1006 $first_section .= "# stdio1\n" .
1007 &sidconf_new("sid-io-stdio", "stdio1") . "\n";
1008 $second_section .= "# stdio1 polling
1009 set host-sched 0-regular? 1
1010 set host-sched 0-time 50
1011 connect-pin host-sched 0-event -> stdio1 poll
1013 $third_section .= "# stdio1 connection
1014 connect-pin uart1 Sout -> stdio1 stdout
1015 connect-pin uart1 Sin <- stdio1 stdin
1019 if ($opt_board =~ /uart2:stdio/)
1021 $first_section .= "# stdio2\n" .
1022 &sidconf_new("sid-io-stdio", "stdio2") . "\n";
1023 $second_section .= "# stdio2 polling
1024 set host-sched 0-regular? 1
1025 set host-sched 0-time 50
1026 connect-pin host-sched 0-event -> stdio2 poll
1028 $third_section .= "# stdio2 connection
1029 connect-pin uart2 Sout -> stdio2 stdout
1030 connect-pin uart2 Sin <- stdio2 stdout
1034 if ($opt_board =~ /uart1:tty/)
1038 $first_section .= "# tty1\n" .
1039 &sidconf_new("hw-visual-tty", "tty1") . "\n";
1040 $third_section .= "# tty1 auto-connection
1041 relate tty1 \"hw-uart-ns16550 uart1\" uart1
1045 if ($opt_board =~ /uart2:tty/)
1049 $first_section .= "# tty2\n" .
1050 &sidconf_new("hw-visual-tty", "tty2") . "\n";
1051 $third_section .= "# tty2 auto-connection
1052 relate tty2 \"hw-uart-ns16550 uart2\" uart2
1056 if ($opt_board =~ /uart1:([0-9]+)/)
1060 $first_section .= "# uart1 socket\n" .
1061 &sidconf_new("sid-io-socket-server", "uart1-console") . "\n";
1063 $second_section .= "# uart1 socketio config
1064 connect-pin host-sched 3-event -> uart1-console poll-event
1065 connect-pin host-sched 3-control <- uart1-console poll-control
1066 set uart1-console verbose? $opt_verbose
1067 set uart1-console sockaddr-local 0.0.0.0:$port
1068 connect-pin init-sequence output-2 -> uart1-console init
1069 connect-pin deinit-sequence output-6 -> uart1-console fini
1070 # make big receive fifo
1071 set uart1 in-fifo-length 4096
1074 $third_section .= "# uart1 <-> socket
1075 connect-pin uart1 Sout -> uart1-console tx
1076 connect-pin uart1 Sin <- uart1-console rx
1080 if ($opt_board =~ /uart2:([0-9]+)/)
1084 $first_section .= "# uart2 socket\n" .
1085 &sidconf_new("sid-io-socket-server", "uart2-console") . "\n";
1087 $second_section .= "# uart2 socketio config
1088 connect-pin host-sched 4-event -> uart2-console poll-event
1089 connect-pin host-sched 4-control <- uart2-console poll-control
1090 set uart2-console verbose? $opt_verbose
1091 set uart2-console sockaddr-local 0.0.0.0:$port
1092 connect-pin init-sequence output-2 -> uart2-console init
1093 connect-pin deinit-sequence output-6 -> uart2-console fini
1094 # make big receive fifo
1095 set uart2 in-fifo-length 4096
1098 $third_section .= "# uart2 <-> socket
1099 connect-pin uart2 Sout -> uart2-console tx
1100 connect-pin uart2 Sin <- uart2-console rx
1104 if ($opt_board =~ /uart1:gdb/ && $opt_gdb != 0)
1106 $third_section .= "# uart1 <-> cpu-gdb also
1107 connect-pin uart1 Sout -> cpu-gdb target-tx
1111 if ($opt_board =~ /uart2:gdb/ && $opt_gdb != 0)
1113 $third_section .= "# uart2 <-> cpu-gdb also
1114 connect-pin uart2 Sout -> cpu-gdb target-tx
1120 sub configure_harvard_bus
1124 $first_section .= "# $cpu harvard bus mappers\n" .
1125 &sidconf_new("hw-mapper-basic", "data-mapper") . "\n" .
1126 &sidconf_new("hw-mapper-basic", "insn-mapper") . "\n";
1128 $second_section .= "# $cpu harvard bus specific.
1129 disconnect-bus cpu insn-memory $bus_upstream
1130 connect-bus cpu insn-memory insn-mapper access-port
1131 disconnect-bus cpu data-memory $bus_upstream
1133 if ($opt_trace_core || $opt_trace_core_visual)
1135 $second_section .= "# $cpu harvard bus data probe.
1136 connect-bus cpu data-memory bus-probe upstream
1137 disconnect-bus bus-probe downstream cpu-mapper access-port
1138 connect-bus bus-probe downstream data-mapper access-port
1143 $second_section .= "# $cpu harvard bus data mapping.
1144 connect-bus cpu data-memory data-mapper access-port
1148 if ($opt_board =~ /gloss/)
1150 $second_section .= "# $cpu harvard bus specific gloss .
1151 disconnect-bus gloss target-memory $bus_upstream
1152 connect-bus gloss target-memory data-mapper access-port
1158 sub configure_mep_cached_bus
1160 my $addrspace = $_[0];
1161 my $cachetype = $_[1];
1164 $first_section .= "# $addrspace caching
1165 new hw-mapper-transparent cpu-${addrspace}-cachefilter
1166 new hw-cache-$cachetype cpu-${addrspace}-cache
1167 set cpu-${addrspace}-cache hit-latency 1
1168 set cpu-${addrspace}-cache miss-latency 1
1169 connect-pin cpu ${addrspace}-cache-enable -> cpu-${addrspace}-cachefilter bank
1170 connect-pin cache-flush-net output-0 -> cpu-${addrspace}-cache flush-all
1171 connect-pin cache-flush-net output-1 -> cpu-${addrspace}-cache invalidate-all
1173 $second_section .= "# $addrspace cache filtering
1174 disconnect-bus cpu ${addrspace}-memory $bus_upstream
1177 if ($addrspace eq "insn") {
1178 $second_section .= "connect-bus cpu insn-memory cpu-insn-buffer upstream\n";
1179 $cpubus = "cpu-insn-buffer downstream";
1181 $cpubus = "cpu data-memory";
1185 $second_section .= "connect-bus $cpubus cpu-dsu ${addrspace}-upstream
1186 connect-bus cpu-dsu ${addrspace}-downstream cpu-${addrspace}-cachefilter access-port
1189 $second_section .= "connect-bus $cpubus cpu-${addrspace}-cachefilter access-port\n";
1193 "connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00000000-0x007FFFFF]{0,1}:uncacheable cpu-mapper access-port
1194 connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00800000-0x7FFFFFFF]{1}:cached cpu-${addrspace}-cache upstream
1195 connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00800000-0x7FFFFFFF]{0}:uncached cpu-mapper access-port
1196 connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x80000000-0xBFFFFFFF]{0,1}:uncacheable cpu-mapper access-port
1197 connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0xC0000000-0xFFFFFFFF]{1}:cached cpu-${addrspace}-cache upstream
1198 connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0xC0000000-0xFFFFFFFF]{0}:uncached cpu-mapper access-port
1199 connect-bus cpu-${addrspace}-cache downstream cpu-mapper access-port
1200 # $addrspace cache setup
1201 set cpu-${addrspace}-cache report-heading \"${addrspace} profile report\"
1202 connect-pin init-sequence output-1 -> cpu-${addrspace}-cache invalidate-all\n" .
1203 ($opt_trace_counter ? "connect-pin deinit-sequence output-6 -> cpu-${addrspace}-cache report!\n" : "");
1206 if ($opt_cpu eq "arm")
1208 $enable_z_packet = "true";
1211 if ($opt_cpu eq "mt")
1213 $enable_z_packet = "true";
1216 if ($opt_cpu eq "sh5")
1218 $enable_z_packet = "true";
1221 if ($opt_cpu eq "xstormy16")
1223 $enable_z_packet = "true";
1226 if ($opt_cpu eq "mep")
1228 $enable_z_packet = "true";
1232 if ($opt_engine eq "pbb")
1234 # FIXME: the x86 component should support this setting
1235 if ($opt_cpu ne "x86")
1237 $second_section .= "set cpu engine-type pbb\n";
1240 elsif ($opt_engine eq "scache")
1242 $second_section .= "set cpu engine-type scache\n";
1246 die "Invalid engine type $opt_engine\n";
1251 # Generate a gdb component for each processor requested.
1253 foreach $processor (keys %opt_gdbport)
1255 $first_section .= "# $processor gdb\n" .
1256 &sidconf_new("sw-debug-gdb", "${processor}-gdb") . "\n" .
1257 &sidconf_new("sid-io-socket-server", "${processor}-gdb-socket") . "\n";
1258 $second_section .= "# ${processor}-gdb
1259 relate ${processor}-gdb cpu $processor
1260 relate ${processor}-gdb cfgroot main
1261 relate ${processor}-gdb target-schedulers target-sched
1262 relate ${processor}-gdb host-schedulers host-sched
1263 connect-pin ${processor}-gdb process-signal -> main stop!
1264 connect-pin init-sequence output-3 -> ${processor}-gdb init
1265 connect-pin deinit-sequence output-5 -> ${processor}-gdb deinit
1266 connect-pin ${processor}-gdb yield -> yield-net input
1267 connect-pin ${processor}-gdb flush-icache -> cache-flush-net input
1268 connect-pin cache-flush-net output-1 -> $processor flush-icache
1269 connect-pin ${processor}-gdb restart -> hw-reset-net input
1270 set ${processor}-gdb exit-on-detach? 1\n" .
1271 ($opt_verbose ? "set ${processor}-gdb trace-gdbsid? $opt_verbose\n" : "") .
1272 ($opt_verbose ? "set ${processor}-gdb trace-gdbserv? $opt_verbose\n" : "") .
1273 "# ${processor}-gdb-socket
1274 connect-pin init-sequence output-2 -> ${processor}-gdb-socket init
1275 connect-pin deinit-sequence output-6 -> ${processor}-gdb-socket fini
1276 connect-pin ${processor}-gdb-socket rx -> ${processor}-gdb remote-rx
1277 connect-pin ${processor}-gdb-socket tx <- ${processor}-gdb remote-tx
1278 connect-pin host-sched 6-event -> ${processor}-gdb-socket poll-event
1279 connect-pin host-sched 6-control <- ${processor}-gdb-socket poll-control
1280 set ${processor}-gdb-socket sockaddr-local 0.0.0.0:$opt_gdbport{$processor}\n" .
1281 ($opt_verbose ? "set ${processor}-gdb-socket verbose? $opt_verbose\n" : "");
1282 if ($processor ne "cpu")
1288 # Update the enable thresholds of the shedulers to account for GDB components
1289 # attached to processors other than the cpu.
1290 if ($non_cpu_gdbs != 0)
1292 $opt_persistent = 1;
1293 $sched_threshold = $non_cpu_gdbs + 1;
1295 # We want the target scheduler to come up enabled, so update the enabled?
1296 # attribute to match the threshold. The GDB components will take care of
1297 # disabling it when necessary.
1298 set target-sched enable-threshold $sched_threshold
1299 set target-sched enabled? $sched_threshold
1303 # Additional settings for main cpu gdb.
1306 if ($opt_board =~ /gloss/)
1308 $second_section .= "# gdb w/ gloss
1309 connect-pin gloss trap-chain <-> cpu-gdb trap
1310 connect-pin gloss trap-code-chain -> cpu-gdb trap-code
1311 connect-pin gloss process-signal -> cpu-gdb gloss-process-signal
1312 connect-pin gloss debug-tx -> cpu-gdb target-tx
1313 relate cpu-gdb gloss gloss
1314 set cpu-gdb enable-Z-packet? $enable_z_packet
1315 set cpu-gdb operating-mode? false
1320 $second_section .= "# gdb w/o gloss
1321 connect-pin cpu trap <-> cpu-gdb trap
1322 connect-pin cpu trap-code -> cpu-gdb trap-code
1327 # Generate a loader for each processor
1328 foreach $processor (keys %opt_load)
1330 $first_section .= "# ${processor} loader\n" .
1331 &sidconf_new("sw-load-elf", "${processor}-loader") . "\n";
1332 $second_section .= "# ${processor} loader
1333 set ${processor}-loader file \"$opt_load{$processor}\" \n" .
1334 ($opt_verbose ? "set ${processor}-loader verbose? $opt_verbose\n" : "");
1336 # Have the loader write data via $load_mapper_data for the "cpu" processor
1337 if ($processor eq "cpu")
1340 "connect-bus ${processor}-loader load-accessor-data $load_mapper_data\n";
1345 "connect-bus ${processor}-loader load-accessor-data ${processor}-mapper access-port # don't trace loading\n";
1349 "connect-bus ${processor}-loader load-accessor-insn ${processor}-mapper access-port # don't trace loading
1350 connect-pin init-sequence output-1 -> ${processor}-loader load!
1351 connect-pin ${processor}-loader start-pc-set -> ${processor} start-pc-set!
1352 connect-pin ${processor}-loader endian-set -> ${processor} endian-set!
1353 connect-pin ${processor}-loader error -> main stop!
1357 # --trace-core-visual
1359 if ($opt_trace_core_visual != 0)
1363 $first_section .= "# visual bus access viewer\n" .
1364 &sidconf_new("hw-visual-probe-bus", "visual-bus-probe") . "\n";
1365 $second_section .= "# visual bus access viewer
1366 set visual-bus-probe addr2line-cmd \"arm-elf-addr2line -C -f -e $exec\"
1367 relate visual-bus-probe cpu cpu
1368 connect-pin bus-probe address -> visual-bus-probe address
1369 connect-pin bus-probe data-high -> visual-bus-probe data-high
1370 connect-pin bus-probe data-low -> visual-bus-probe data-low
1371 connect-pin bus-probe status -> visual-bus-probe status
1372 connect-pin bus-probe type -> visual-bus-probe type
1381 $first_section .= "# tk system monitor\n" .
1382 &sidconf_new("sid-control-tksm", "tksm") . "\n";
1384 $second_section .= "# tk system monitor
1385 relate main component-catalog-informees tksm
1387 set host-sched 1-regular? 1
1388 set host-sched 1-time 1000
1389 connect-pin host-sched 1-event -> tksm refresh
1393 if ($opt_tksm && $opt_gdb)
1395 $third_section .= "# triggerpoint signal
1396 connect-pin tksm triggerpoint-hit -> cpu-gdb stop-target
1401 # ----------------------------------------------------------------------------
1405 while ($#opt_memory_region >= 0)
1407 $spec = shift @opt_memory_region;
1416 # [,relate=COMPONENT/RELATION] (deprecated)
1417 @spec = split /,/, $spec;
1419 # print STDERR "spec=$spec\n";
1420 die "Cannot parse memory region specification `$spec'.\n" if ($#spec < 1);
1422 $base = shift @spec;
1423 $base = oct($base) if ($base =~ /^0/);
1424 $size = shift @spec;
1425 $size = oct($size) if ($size =~ /^0/);
1427 die "Illegal memory region size `$size'\n" if ($size <= 0);
1429 $last = $base + $size - 1;
1430 $membus = "read-write-port"; # default read-write
1431 $memfile = ""; # default no file
1432 $memmapper = "cpu-mapper";
1433 $mmap = 0; # default no mmap
1434 $latr = 0; $latw = 0; # default no latencies
1439 $first_section .= "# memory region $mems ($spec)\n" .
1440 &sidconf_new("hw-memory-ram/rom-basic", "mem$mems") . "\n";
1441 $third_section .= "# memory region $mems ($spec) configuration\n" .
1442 "set mem$mems size $size\n";
1444 # consume other options
1448 if ($opt eq "read-only") { $membus = "read-only-port"; }
1449 elsif ($opt eq "mmap") { $mmap = 1; }
1450 elsif ($opt =~ /bus=(.+)/) { $memmapper = $1; }
1451 elsif ($opt =~ /file=(.+)/) { $memfile = $1; }
1452 elsif ($opt =~ /alias=(.+)/) { push @aliases, $1 }
1453 elsif ($opt =~ /relate=(.+)/) { push @relates, $1 }
1454 elsif ($opt =~ /latency=(\d+):(\d+)/) { $latr = $1; $latw = $2 }
1455 elsif ($opt =~ /latency=(\d+)/) { $latr = $1; $latw = $1 }
1456 else { die "Cannot parse memory region option `$opt'.\n"; }
1459 # process memory maps
1460 $third_section .= "connect-bus $memmapper mem$mems:[$base,$last] mem$mems $membus\n";
1462 foreach $alias (@aliases)
1464 $alias = oct($alias) if ($alias =~ /^0/);
1465 $aliasend = $alias + $size - 1;
1466 $third_section .= "connect-bus $memmapper mem$mems:[$alias,$aliasend] mem$mems $membus\n";
1469 foreach $relate (@relates) {
1470 $relate =~ /(.*)\/(.*)/;
1471 $third_section .= "relate $1 $2 mem$mems\n";
1474 # process file backing store
1477 $third_section .= "set mem$mems image-file \"$memfile\"\n";
1480 $third_section .= "connect-pin init-sequence output-1 -> mem$mems image-mmap\n";
1482 $third_section .= "connect-pin init-sequence output-1 -> mem$mems image-load\n";
1485 # save only if memory was writeable and not memory-mapped
1486 if ($membus eq "read-write-port" && !$mmap) {
1487 $third_section .= "connect-pin deinit-sequence output-6 -> mem$mems image-store\n";
1492 if ($latr != 0) { $third_section .= "set mem$mems read-latency $latr\n" }
1493 if ($latw != 0) { $third_section .= "set mem$mems write-latency $latw\n" }
1497 # ----------------------------------------------------------------------------
1498 # Really miscellanous stuff.
1503 $addr = $opt_sidrtc;
1504 $addr = oct($addr) if ($addr =~ /^0/);
1505 $addrend = $addr + 7;
1507 $first_section .= "# special rtc\n" .
1508 &sidconf_new("hw-rtc-sid", "sidrtc") . "\n";
1510 $third_section .= "# special rtc mapping
1511 connect-bus cpu-mapper sidrtc:[$addr,$addrend] sidrtc registers
1516 # sidcodec: 20 bytes
1519 $addr = $opt_sidcodec;
1520 $addr = oct($addr) if ($addr =~ /^0/);
1521 $addrend = $addr + 19;
1523 $first_section .= "# special codec & host audio\n" .
1524 &sidconf_new("hw-audio-sid", "sidcodec") . "\n" .
1525 &sidconf_new("sid-io-audio", "sidaudio") . "\n" .
1528 $third_section .= "# special codec mapping
1529 connect-bus cpu-mapper sidcodec:[$addr,$addrend] sidcodec registers
1530 # codec <-> host audio connections
1531 connect-pin sidcodec tx-sample -> sidaudio tx-sample
1532 connect-pin sidcodec rx-sample <- sidaudio rx-sample
1533 connect-pin sidcodec tx-mode -> sidaudio tx-mode
1534 connect-pin sidcodec tx-pending <- sidaudio tx-pending
1535 connect-pin sidcodec rx-mode -> sidaudio rx-mode
1536 connect-pin sidcodec rx-pending <- sidaudio rx-pending
1537 connect-pin sidcodec config-set -> sidaudio config-set
1538 # host audio polling
1539 set host-sched 7-regular? 1
1540 set host-sched 7-time 100
1541 connect-pin host-sched 7-event -> sidaudio poll
1546 if ($opt_tksched != 0)
1550 $first_section .= "# tk visual scheduler controller\n" .
1551 &sidconf_new("sid-visual-sched", "tksched") . "\n";
1553 $second_section .= "# tk system monitor
1554 relate tksched scheduler target-sched
1561 $first_section .= "# tcl/tk adaptive event polling" . "\n" .
1562 &sidconf_new("bridge-tcl", "tcl-event-consumer") . "\n";
1563 $third_section .= "# tcl/tk adaptive event polling
1564 connect-pin host-sched 2-event -> tcl-event-consumer !event
1565 connect-pin host-sched 2-control <- tcl-event-consumer !event-control
1566 connect-pin init-sequence output-7 -> tcl-event-consumer !event
1572 foreach $lib (sort keys %component_libs)
1574 $symbol = $component_libs{$lib};
1575 $lib_la = "lib" . $lib . ".la";
1577 # minor optimization: don't include large tcl dll unless needed
1578 next if ($any_tcl == 0 && $lib eq "tclapi");
1580 $zeroth_section .= "load $lib_la $symbol\n";
1584 # ----------------------------------------------------------------------------
1585 if ($opt_persistent) { $zeroth_section .= "set main persistent? true\n"; }
1588 $tmpdir = $ENV{'TMPDIR'} ? $ENV{'TMPDIR'} : "/tmp";
1589 $basename = $exec ne "" ? `basename $exec` : "sid";
1591 $tfile = $opt_save_temps ? "$basename.conf" : "$tmpdir/$basename-$$.conf";
1592 open CONFIG, ">$tfile" || die ("Cannot write to $tfile\n");
1593 print CONFIG $zeroth_section;
1594 print CONFIG $first_section;
1595 print CONFIG $second_section;
1596 print CONFIG $third_section;
1599 # ----------------------------------------------------------------------------
1602 if ($opt_save_temps)
1604 print "Configuration file saved to `$tfile'.\n";
1613 # ----------------------------------------------------------------------------
1614 # (Generate and) run a simulator
1617 push @args, ($tfile);
1619 # spawn sid child process
1623 # Process the exit code.
1624 if (($exit_value & 0xff00) == 0xff00) # catch old perls' fork rc bugs
1626 print "\nCannot run `@args': $!\n";
1629 if (! $opt_save_temps)
1634 exit ($exit_value >> 8);
1637 # ----------------------------------------------------------------------------
1641 my ($comptype,$compname) = @_;
1643 for ($i=0; $i<scalar(@opt_wrap); $i++) {
1644 if ($opt_wrap[$i] eq $compname) {
1649 # print $wrap_this == 0 ? "not" : "";
1650 # print " wrapping $compname $comptype\n";
1653 return "new sid-api-trace ${compname}
1654 new ${comptype} ${compname}-traced
1655 relate ${compname} victim ${compname}-traced";
1659 return "new ${comptype} ${compname}";