sid/bsp/pregen/arm-pidBE.conf

   1 # sid configuration file
   2 # created by Id: configrun-sid.in,v 1.99 2001/10/29 17:44:36 fche Exp
   3 # run by fche @ tooth (Linux) at Mon Oct 29 13:01:38 EST 2001
   4 # args: --cpu=arm --no-run --gdb=5000 --board=pid7t-uart1:gdb -EB
   5 load libaudio.la audio_component_library
   6 load libcache.la cache_component_library
   7 load libcgencpu.la cgen_component_library
   8 load libconsoles.la console_component_library
   9 load libgdb.la gdb_component_library
  10 load libgloss.la gloss_component_library
  11 load libglue.la glue_component_library
  12 load libhd44780u.la hd44780u_component_library
  13 load libide.la ide_component_library
  14 load libinterrupt.la interrupt_component_library
  15 load libloader.la loader_component_library
  16 load libmapper.la mapper_component_library
  17 load libmemory.la mem_component_library
  18 load libmmu.la mmu_component_library
  19 load libparport.la parport_component_library
  20 load libprof.la prof_component_library
  21 load librtc.la rtc_component_library
  22 load libsched.la sched_component_library
  23 load libtimers.la timer_component_library
  24 load libuart.la uart_component_library
  25 load libx86.la x86_component_library
  26 set main persistent? true
  27 # first section
  28 new hw-cpu-arm7t cpu
  29 new hw-mapper-basic cpu-mapper
  30 new hw-glue-sequence-8 init-sequence
  31 new hw-glue-sequence-1 hw-reset-net
  32 new hw-glue-sequence-8 deinit-sequence
  33 new hw-glue-sequence-1 yield-net
  34 new hw-glue-sequence-2 cache-flush-net
  35 new sid-sched-host-accurate host-sched
  36 new sid-sched-sim target-sched
  37 # pid7t components
  38 new hw-remap/pause-arm/ref remapper
  39 new hw-timer-arm/ref-sched timer1
  40 new hw-timer-arm/ref-sched timer2
  41 new hw-interrupt-arm/ref intctrl
  42 new hw-uart-ns16550 uart1
  43 new hw-uart-ns16550 uart2
  44 new hw-parport-ps/2 parport
  45 # cpu gdb
  46 new sw-debug-gdb cpu-gdb
  47 new sid-io-socket-server cpu-gdb-socket
  48 # memory region 1 (0x00000000,0x01000000)
  49 new hw-memory-ram/rom-basic mem1
  50 # memory region 2 (0x04000000,0x00100000)
  51 new hw-memory-ram/rom-basic mem2
  52 # second section
  53 # settings
  54 set cpu step-insn-count 10000
  55 set host-sched num-clients 10 # large enough?
  56 set target-sched num-clients 10 # large enough?
  57 # pin connections
  58 connect-pin main perform-activity -> host-sched advance
  59 connect-pin main perform-activity -> target-sched advance
  60 connect-pin main starting -> init-sequence input
  61 connect-pin main stopping -> deinit-sequence input
  62 connect-pin init-sequence output-0 -> hw-reset-net input
  63 connect-pin hw-reset-net output-0 -> cpu reset!
  64 connect-pin target-sched 0-event -> cpu step!
  65 connect-pin target-sched 0-control <- cpu step-cycles
  66 connect-pin yield-net output-0 -> cpu yield
  67 connect-pin yield-net output-0 -> host-sched yield
  68 connect-bus cpu insn-memory cpu-mapper access-port
  69 connect-bus cpu data-memory cpu-mapper access-port
  70 # pid7t control connections
  71 connect-pin target-sched 2-control <- timer1 divided-clock-control
  72 connect-pin target-sched 2-event -> timer1 divided-clock-event
  73 set target-sched 2-scale 1/4  # artificial speed-up
  74 connect-pin timer1 interrupt -> intctrl interrupt-source-4
  75 connect-pin target-sched 3-control <- timer2 divided-clock-control
  76 connect-pin target-sched 3-event -> timer2 divided-clock-event
  77 set target-sched 3-scale 1/4  # artificial speed-up
  78 connect-pin timer2 interrupt -> intctrl interrupt-source-5
  79 connect-pin intctrl interrupt -> cpu nirq
  80 connect-pin intctrl fast-interrupt -> cpu nfiq
  81 connect-pin hw-reset-net output-0 -> uart1 Reset
  82 connect-pin hw-reset-net output-0 -> uart2 Reset
  83 connect-pin hw-reset-net output-0 -> intctrl reset
  84 connect-pin hw-reset-net output-0 -> timer1 reset
  85 connect-pin hw-reset-net output-0 -> timer2 reset
  86 connect-pin uart1 INTR -> intctrl interrupt-source-8
  87 connect-pin uart2 INTR -> intctrl interrupt-source-9
  88 connect-pin parport INTP -> intctrl interrupt-source-10
  89 # pid7t memory map
  90 connect-bus cpu-mapper intctrl:[0xA000000,0xA000013] intctrl irq-registers
  91 connect-bus cpu-mapper intctrl:[0xA000100,0xA00010F] intctrl fiq-registers
  92 connect-bus cpu-mapper timer1:[0xA800000,0xA80000F] timer1 registers
  93 connect-bus cpu-mapper timer2:[0xA800020,0xA80002F] timer2 registers
  94 connect-bus cpu-mapper remapper:[0xB000000,0xB000037] remapper registers
  95 connect-bus cpu-mapper uart1:[0xD800000,0xD80001F,4,1] uart1 Bus
  96 connect-bus cpu-mapper uart2:[0xD800020,0xD80003F,4,1] uart2 Bus
  97 connect-bus cpu-mapper parport:[0xD800040,0xD80005F,4,1] parport Bus
  98 # set uart unframed mode
  99 set uart1 sio-framing? 0
 100 set uart2 sio-framing? 0
 101 # remapper configuration
 102 # NB: remapping polarity is opposite to document
 103 set remapper num-relocations 1
 104 set remapper 0-start 0x0
 105 set remapper 0-end 0xFFFF
 106 set remapper 0-reloc-to 0x04000000
 107 set cpu engine-type pbb
 108 # cpu-gdb
 109 relate cpu-gdb cpu cpu
 110 relate cpu-gdb cfgroot main
 111 relate cpu-gdb target-schedulers target-sched
 112 relate cpu-gdb host-schedulers host-sched
 113 connect-pin cpu-gdb process-signal -> main stop!
 114 connect-pin init-sequence output-3 -> cpu-gdb init
 115 connect-pin deinit-sequence output-5 -> cpu-gdb deinit
 116 connect-pin cpu-gdb yield -> yield-net input
 117 connect-pin cpu-gdb flush-icache -> cache-flush-net input
 118 connect-pin cache-flush-net output-1 -> cpu flush-icache
 119 connect-pin cpu-gdb restart -> hw-reset-net input
 120 set cpu-gdb exit-on-detach? 1
 121 # cpu-gdb-socket
 122 connect-pin init-sequence output-2 -> cpu-gdb-socket init
 123 connect-pin deinit-sequence output-6 -> cpu-gdb-socket fini
 124 connect-pin cpu-gdb-socket rx -> cpu-gdb remote-rx
 125 connect-pin cpu-gdb-socket tx <- cpu-gdb remote-tx
 126 connect-pin host-sched 6-event -> cpu-gdb-socket poll-event
 127 connect-pin host-sched 6-control <- cpu-gdb-socket poll-control
 128 set cpu-gdb-socket sockaddr-local 0.0.0.0:5000
 129 # gdb w/o gloss
 130 connect-pin cpu trap <-> cpu-gdb trap
 131 connect-pin cpu trap-code -> cpu-gdb trap-code
 132 set cpu endian big
 133 # remapper reconnection
 134 connect-bus remapper all cpu-mapper access-port
 135 disconnect-bus cpu insn-memory cpu-mapper access-port
 136 connect-bus cpu insn-memory remapper access-port
 137 disconnect-bus cpu data-memory cpu-mapper access-port
 138 connect-bus cpu data-memory remapper access-port
 139 # uart1 <-> cpu-gdb also
 140 connect-pin uart1 Sout -> cpu-gdb target-tx
 141 # memory region 1 (0x00000000,0x01000000) configuration
 142 set mem1 size 16777216
 143 connect-bus cpu-mapper mem1:[0,16777215] mem1 read-write-port
 144 # memory region 2 (0x04000000,0x00100000) configuration
 145 set mem2 size 1048576
 146 connect-bus cpu-mapper mem2:[67108864,68157439] mem2 read-write-port