1 // x86-memory-modes.cc - set up protected mode. -*- C++ -*-
3 // Copyright (C) 2001 Red Hat.
5 // Copyright (C) 2001 MandrakeSoft S.A.
9 // 75002 Paris - France
10 // http://www.linux-mandrake.com/
11 // http://www.mandrakesoft.com/
13 // This library is free software; you can redistribute it and/or
14 // modify it under the terms of the GNU Lesser General Public
15 // License as published by the Free Software Foundation; either
16 // version 2 of the License, or (at your option) any later version.
18 // This library is distributed in the hope that it will be useful,
19 // but WITHOUT ANY WARRANTY; without even the implied warranty of
20 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 // Lesser General Public License for more details.
23 // You should have received a copy of the GNU Lesser General Public
24 // License along with this library; if not, write to the Free Software
25 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 void x86_cpu::enter_protected_mode()
31 if (memory_mode == "default")
33 // This mode sets all segment bases to 0x0, and sets all
35 // create a global descriptor table in memory:
37 for(int i = 0; i < 16; i += 4)
38 write_data_memory_4(0x0, i, 0x0);
41 write_data_memory_4(0x0, 0x0010, 0xffff0000);
42 write_data_memory_4(0x0, 0x0014, 0x009b4f00);
45 write_data_memory_4(0x0, 0x0018, 0xffff0000);
46 write_data_memory_4(0x0, 0x001c, 0x00934f00);
48 // CS (Code Segment) selector and descriptor in bochs representation:
49 bx_cpu.sregs[BX_SEG_REG_CS].selector.value = 0x0010;
51 bx_cpu.sregs[BX_SEG_REG_CS].selector.index = 0x0002;
52 bx_cpu.sregs[BX_SEG_REG_CS].selector.ti = 0;
53 bx_cpu.sregs[BX_SEG_REG_CS].selector.rpl = 0;
55 bx_cpu.sregs[BX_SEG_REG_CS].cache.valid = 1;
56 bx_cpu.sregs[BX_SEG_REG_CS].cache.p = 1;
57 bx_cpu.sregs[BX_SEG_REG_CS].cache.dpl = 0;
58 bx_cpu.sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
59 bx_cpu.sregs[BX_SEG_REG_CS].cache.type = 3; /* read/write access */
61 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; /* data/stack segment */
62 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* normal expand up */
63 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
64 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
65 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.base = 0x00000000;
66 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xfffff;
67 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xfffff;
70 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.g = 0; /* byte granular */
71 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; /* 32bit default size */
72 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
75 // DS (Data Segment) selector and descriptor in bochs representation:
76 bx_cpu.sregs[BX_SEG_REG_DS].selector.value = 0x0018;
78 bx_cpu.sregs[BX_SEG_REG_DS].selector.index = 0x0003;
79 bx_cpu.sregs[BX_SEG_REG_DS].selector.ti = 0;
80 bx_cpu.sregs[BX_SEG_REG_DS].selector.rpl = 0;
82 bx_cpu.sregs[BX_SEG_REG_DS].cache.valid = 1;
83 bx_cpu.sregs[BX_SEG_REG_DS].cache.p = 1;
84 bx_cpu.sregs[BX_SEG_REG_DS].cache.dpl = 0;
85 bx_cpu.sregs[BX_SEG_REG_DS].cache.segment = 1; /* data/code segment */
86 bx_cpu.sregs[BX_SEG_REG_DS].cache.type = 3; /* read/write access */
88 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.executable = 0; /* data/stack segment */
89 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = 0; /* normal expand up */
90 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.r_w = 1; /* writeable */
91 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.a = 1; /* accessed */
92 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000;
93 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xfffff; // 2000
94 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xfffff;
97 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.g = 0; /* byte granular */
98 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.d_b = 1; /* 32bit default size */
99 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
102 /* ES (Extra Segment) and descriptor cache */
103 bx_cpu.sregs[BX_SEG_REG_ES].selector.value = 0x0018;
104 #if BX_CPU_LEVEL >= 2
105 bx_cpu.sregs[BX_SEG_REG_ES].selector.index = 0x0003;
106 bx_cpu.sregs[BX_SEG_REG_ES].selector.ti = 0;
107 bx_cpu.sregs[BX_SEG_REG_ES].selector.rpl = 0;
109 bx_cpu.sregs[BX_SEG_REG_ES].cache.valid = 1;
110 bx_cpu.sregs[BX_SEG_REG_ES].cache.p = 1;
111 bx_cpu.sregs[BX_SEG_REG_ES].cache.dpl = 0;
112 bx_cpu.sregs[BX_SEG_REG_ES].cache.segment = 1; /* data/code segment */
113 bx_cpu.sregs[BX_SEG_REG_ES].cache.type = 3; /* read/write access */
115 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.executable = 0; /* data/stack segment */
116 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = 0; /* normal expand up */
117 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.r_w = 1; /* writeable */
118 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.a = 1; /* accessed */
119 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.base = 0x00000000;
120 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.limit = 0xfffff;
121 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled = 0xfffff;
123 #if BX_CPU_LEVEL >= 3
124 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.g = 0; /* byte granular */
125 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.d_b = 1; /* 32bit default size */
126 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
129 /* FS and descriptor cache */
130 #if BX_CPU_LEVEL >= 3
131 bx_cpu.sregs[BX_SEG_REG_FS].selector.value = 0x0018;
132 bx_cpu.sregs[BX_SEG_REG_FS].selector.index = 0x0003;
133 bx_cpu.sregs[BX_SEG_REG_FS].selector.ti = 0;
134 bx_cpu.sregs[BX_SEG_REG_FS].selector.rpl = 0;
136 bx_cpu.sregs[BX_SEG_REG_FS].cache.valid = 1;
137 bx_cpu.sregs[BX_SEG_REG_FS].cache.p = 1;
138 bx_cpu.sregs[BX_SEG_REG_FS].cache.dpl = 0;
139 bx_cpu.sregs[BX_SEG_REG_FS].cache.segment = 1; /* data/code segment */
140 bx_cpu.sregs[BX_SEG_REG_FS].cache.type = 3; /* read/write access */
142 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.executable = 0; /* data/stack segment */
143 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.c_ed = 0; /* normal expand up */
144 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.r_w = 1; /* writeable */
145 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.a = 1; /* accessed */
146 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.base = 0x00000000;
147 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.limit = 0xfffff;
148 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled = 0xfffff;
149 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.g = 0; /* byte granular */
150 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.d_b = 1; /* 32bit default size */
151 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
155 /* GS and descriptor cache */
156 #if BX_CPU_LEVEL >= 3
157 bx_cpu.sregs[BX_SEG_REG_GS].selector.value = 0x0018;
158 bx_cpu.sregs[BX_SEG_REG_GS].selector.index = 0x0003;
159 bx_cpu.sregs[BX_SEG_REG_GS].selector.ti = 0;
160 bx_cpu.sregs[BX_SEG_REG_GS].selector.rpl = 0;
162 bx_cpu.sregs[BX_SEG_REG_GS].cache.valid = 1;
163 bx_cpu.sregs[BX_SEG_REG_GS].cache.p = 1;
164 bx_cpu.sregs[BX_SEG_REG_GS].cache.dpl = 0;
165 bx_cpu.sregs[BX_SEG_REG_GS].cache.segment = 1; /* data/code segment */
166 bx_cpu.sregs[BX_SEG_REG_GS].cache.type = 3; /* read/write access */
168 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.executable = 0; /* data/stack segment */
169 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.c_ed = 0; /* normal expand up */
170 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.r_w = 1; /* writeable */
171 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.a = 1; /* accessed */
172 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.base = 0x00000000;
173 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.limit = 0xfffff;
174 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled = 0xfffff;
175 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.g = 0; /* byte granular */
176 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.d_b = 1; /* 32bit default size */
177 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.avl = 0;
180 /* SS (Stack Segment) and descriptor cache */
181 bx_cpu.sregs[BX_SEG_REG_SS].selector.value = 0x0018;
182 #if BX_CPU_LEVEL >= 2
183 bx_cpu.sregs[BX_SEG_REG_SS].selector.index = 0x0003;
184 bx_cpu.sregs[BX_SEG_REG_SS].selector.ti = 0;
185 bx_cpu.sregs[BX_SEG_REG_SS].selector.rpl = 0;
187 bx_cpu.sregs[BX_SEG_REG_SS].cache.valid = 1;
188 bx_cpu.sregs[BX_SEG_REG_SS].cache.p = 1;
189 bx_cpu.sregs[BX_SEG_REG_SS].cache.dpl = 0;
190 bx_cpu.sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
191 bx_cpu.sregs[BX_SEG_REG_SS].cache.type = 3; /* read/write access */
193 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; /* data/stack segment */
194 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; /* normal expand up */
195 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; /* writeable */
196 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; /* accessed */
197 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.base = 0x00000000;
198 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xfffff;
199 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xfffff;
201 #if BX_CPU_LEVEL >= 3
202 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.g = 0; /* byte granular */
203 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; /* 32bit default size */
204 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
207 /* GDTR (Global Descriptor Table Register) */
208 #if BX_CPU_LEVEL >= 2
209 bx_cpu.gdtr.base = 0x00000000;
210 bx_cpu.gdtr.limit = 0x001f;
212 // set PE bit in CR0 so that protected mode is enabled
216 else if (memory_mode == "cygmon")
218 // support for initial cygmon memory layout
220 // this section simulates the Cygmon rom monitor startup code
222 // create a global descriptor table in memory:
224 for(int i = 0; i < 16; i += 4)
225 write_data_memory_4(0x0, i, 0x0);
228 write_data_memory_4(0x0, 0x10, 0xffff0000);
229 write_data_memory_4(0x0, 0x14, 0x009bcf00);
232 write_data_memory_4(0x0, 0x18, 0xffff0000);
233 write_data_memory_4(0x0, 0x1c, 0x0093cf00);
235 // CS (Code Segment) selector and descriptor in bochs representation:
236 bx_cpu.sregs[BX_SEG_REG_CS].selector.value = 0x0010;
237 #if BX_CPU_LEVEL >= 2
238 bx_cpu.sregs[BX_SEG_REG_CS].selector.index = 0x0002;
239 bx_cpu.sregs[BX_SEG_REG_CS].selector.ti = 0;
240 bx_cpu.sregs[BX_SEG_REG_CS].selector.rpl = 0;
242 bx_cpu.sregs[BX_SEG_REG_CS].cache.valid = 1;
243 bx_cpu.sregs[BX_SEG_REG_CS].cache.p = 1;
244 bx_cpu.sregs[BX_SEG_REG_CS].cache.dpl = 0;
245 bx_cpu.sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
246 bx_cpu.sregs[BX_SEG_REG_CS].cache.type = 3; /* read/write access */
248 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; /* data/stack segment */
249 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* normal expand up */
250 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
251 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
252 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.base = 0x00000000;
253 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xfffff;
254 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xffffffff;
256 #if BX_CPU_LEVEL >= 3
257 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4Kb granular */
258 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; /* 32bit default size */
259 bx_cpu.sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
262 // DS (Data Segment) selector and descriptor in bochs representation:
263 bx_cpu.sregs[BX_SEG_REG_DS].selector.value = 0x0018;
264 #if BX_CPU_LEVEL >= 2
265 bx_cpu.sregs[BX_SEG_REG_DS].selector.index = 0x0003;
266 bx_cpu.sregs[BX_SEG_REG_DS].selector.ti = 0;
267 bx_cpu.sregs[BX_SEG_REG_DS].selector.rpl = 0;
269 bx_cpu.sregs[BX_SEG_REG_DS].cache.valid = 1;
270 bx_cpu.sregs[BX_SEG_REG_DS].cache.p = 1;
271 bx_cpu.sregs[BX_SEG_REG_DS].cache.dpl = 0;
272 bx_cpu.sregs[BX_SEG_REG_DS].cache.segment = 1; /* data/code segment */
273 bx_cpu.sregs[BX_SEG_REG_DS].cache.type = 3; /* read/write access */
275 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.executable = 0; /* data/stack segment */
276 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = 0; /* normal expand up */
277 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.r_w = 1; /* writeable */
278 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.a = 1; /* accessed */
279 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000;
280 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xfffff; // 2000
281 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xffffffff;
283 #if BX_CPU_LEVEL >= 3
284 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.g = 1; /* 4Kb granular */
285 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.d_b = 1; /* 32bit default size */
286 bx_cpu.sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
289 /* ES (Extra Segment) and descriptor cache */
290 bx_cpu.sregs[BX_SEG_REG_ES].selector.value = 0x0018;
291 #if BX_CPU_LEVEL >= 2
292 bx_cpu.sregs[BX_SEG_REG_ES].selector.index = 0x0003;
293 bx_cpu.sregs[BX_SEG_REG_ES].selector.ti = 0;
294 bx_cpu.sregs[BX_SEG_REG_ES].selector.rpl = 0;
296 bx_cpu.sregs[BX_SEG_REG_ES].cache.valid = 1;
297 bx_cpu.sregs[BX_SEG_REG_ES].cache.p = 1;
298 bx_cpu.sregs[BX_SEG_REG_ES].cache.dpl = 0;
299 bx_cpu.sregs[BX_SEG_REG_ES].cache.segment = 1; /* data/code segment */
300 bx_cpu.sregs[BX_SEG_REG_ES].cache.type = 3; /* read/write access */
302 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.executable = 0; /* data/stack segment */
303 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = 0; /* normal expand up */
304 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.r_w = 1; /* writeable */
305 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.a = 1; /* accessed */
306 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.base = 0x00000000;
307 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.limit = 0xfffff;
308 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled = 0xffffffff;
310 #if BX_CPU_LEVEL >= 3
311 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.g = 1; /* 4Kb granular */
312 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.d_b = 1; /* 32bit default size */
313 bx_cpu.sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
316 /* FS and descriptor cache */
317 #if BX_CPU_LEVEL >= 3
318 bx_cpu.sregs[BX_SEG_REG_FS].selector.value = 0x0018;
319 bx_cpu.sregs[BX_SEG_REG_FS].selector.index = 0x0003;
320 bx_cpu.sregs[BX_SEG_REG_FS].selector.ti = 0;
321 bx_cpu.sregs[BX_SEG_REG_FS].selector.rpl = 0;
323 bx_cpu.sregs[BX_SEG_REG_FS].cache.valid = 1;
324 bx_cpu.sregs[BX_SEG_REG_FS].cache.p = 1;
325 bx_cpu.sregs[BX_SEG_REG_FS].cache.dpl = 0;
326 bx_cpu.sregs[BX_SEG_REG_FS].cache.segment = 1; /* data/code segment */
327 bx_cpu.sregs[BX_SEG_REG_FS].cache.type = 3; /* read/write access */
329 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.executable = 0; /* data/stack segment */
330 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.c_ed = 0; /* normal expand up */
331 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.r_w = 1; /* writeable */
332 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.a = 1; /* accessed */
333 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.base = 0x00000000;
334 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.limit = 0xfffff;
335 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled = 0xffffffff;
336 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.g = 1; /* 4Kb granular */
337 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.d_b = 1; /* 32bit default size */
338 bx_cpu.sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
342 /* GS and descriptor cache */
343 #if BX_CPU_LEVEL >= 3
344 bx_cpu.sregs[BX_SEG_REG_GS].selector.value = 0x0018;
345 bx_cpu.sregs[BX_SEG_REG_GS].selector.index = 0x0003;
346 bx_cpu.sregs[BX_SEG_REG_GS].selector.ti = 0;
347 bx_cpu.sregs[BX_SEG_REG_GS].selector.rpl = 0;
349 bx_cpu.sregs[BX_SEG_REG_GS].cache.valid = 1;
350 bx_cpu.sregs[BX_SEG_REG_GS].cache.p = 1;
351 bx_cpu.sregs[BX_SEG_REG_GS].cache.dpl = 0;
352 bx_cpu.sregs[BX_SEG_REG_GS].cache.segment = 1; /* data/code segment */
353 bx_cpu.sregs[BX_SEG_REG_GS].cache.type = 3; /* read/write access */
355 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.executable = 0; /* data/stack segment */
356 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.c_ed = 0; /* normal expand up */
357 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.r_w = 1; /* writeable */
358 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.a = 1; /* accessed */
359 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.base = 0x00000000;
360 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.limit = 0xfffff;
361 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled = 0xffffffff;
362 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.g = 1; /* 4Kb granular */
363 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.d_b = 1; /* 32bit default size */
364 bx_cpu.sregs[BX_SEG_REG_GS].cache.u.segment.avl = 0;
367 /* SS (Stack Segment) and descriptor cache */
368 bx_cpu.sregs[BX_SEG_REG_SS].selector.value = 0x0018;
369 #if BX_CPU_LEVEL >= 2
370 bx_cpu.sregs[BX_SEG_REG_SS].selector.index = 0x0003;
371 bx_cpu.sregs[BX_SEG_REG_SS].selector.ti = 0;
372 bx_cpu.sregs[BX_SEG_REG_SS].selector.rpl = 0;
374 bx_cpu.sregs[BX_SEG_REG_SS].cache.valid = 1;
375 bx_cpu.sregs[BX_SEG_REG_SS].cache.p = 1;
376 bx_cpu.sregs[BX_SEG_REG_SS].cache.dpl = 0;
377 bx_cpu.sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
378 bx_cpu.sregs[BX_SEG_REG_SS].cache.type = 3; /* read/write access */
380 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; /* data/stack segment */
381 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; /* normal expand up */
382 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; /* writeable */
383 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; /* accessed */
384 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.base = 0x00000000;
385 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xfffff;
386 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xffffffff;
388 #if BX_CPU_LEVEL >= 3
389 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; /* 4Kb granular */
390 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; /* 32bit default size */
391 bx_cpu.sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
395 /* GDTR (Global Descriptor Table Register) */
396 #if BX_CPU_LEVEL >= 2
397 bx_cpu.gdtr.base = 0x00000000;
398 bx_cpu.gdtr.limit = 0x001f;
400 // set PE bit in CR0 so that protected mode is enabled
405 cerr << "hw-cpu-x86: unsupported memory mode" << endl;