1 /* Misc. entries in the arm description file.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2010 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
15 #include "cgen/bitset.h"
21 /* Enum declaration for . */
22 typedef enum gr_names {
23 H_GR_PC = 15, H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2
24 , H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6
25 , H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10
26 , H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14
27 , H_GR_R15 = 15, H_GR_SP = 13, H_GR_LR = 14
30 /* Enum declaration for arm cpu states. */
31 typedef enum arm_mode {
32 ARM_MODE_USER = 16, ARM_MODE_FIQ = 17, ARM_MODE_IRQ = 18, ARM_MODE_SUPERVISOR = 19
33 , ARM_MODE_ABORT = 23, ARM_MODE_UNDEFINED = 27, ARM_MODE_SYSTEM = 31
36 /* Enum declaration for operand 2 shift type. */
37 typedef enum shift_type {
38 SHIFT_TYPE_LSL = 0, SHIFT_TYPE_ASL = 0, SHIFT_TYPE_LSR = 1, SHIFT_TYPE_ASR = 2
42 /* Enum declaration for condition codes. */
43 typedef enum cond_codes {
44 COND_EQ, COND_NE, COND_CS, COND_CC
45 , COND_MI, COND_PL, COND_VS, COND_VC
46 , COND_HI, COND_LS, COND_GE, COND_LT
47 , COND_GT, COND_LE, COND_AL
50 /* Enum declaration for Arith/logic opcode enums. */
51 typedef enum al_opcode {
52 OP_AND, OP_EOR, OP_SUB, OP_RSB
53 , OP_ADD, OP_ADC, OP_SBC, OP_RSC
54 , OP_TST, OP_TEQ, OP_CMP, OP_CMN
55 , OP_ORR, OP_MOV, OP_BIC, OP_MVN
58 /* Enum declaration for PSR transfer destinations. */
59 typedef enum psr_dests {
60 PSR_CURRENT, PSR_SAVED
63 /* Enum declaration for condition code tests. */
64 typedef enum cc_tests {
65 CC_EQ, CC_NE, CC_CS, CC_CC
66 , CC_MI, CC_PL, CC_VS, CC_VC
67 , CC_HI, CC_LS, CC_GE, CC_LT
71 // Insn attribute indices.
73 /* Enum declaration for cgen_insn attrs. */
74 typedef enum cgen_insn_attr {
75 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
76 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
77 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
78 , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_R15_OFFSET, CGEN_INSN_END_NBOOLS
81 /* Number of non-boolean elements in cgen_insn_attr. */
82 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
86 /* Enum declaration for machine type selection. */
87 typedef enum mach_attr {
88 MACH_BASE, MACH_ARM7TDMI, MACH_MAX
91 /* Enum declaration for instruction set selection. */
92 typedef enum isa_attr {
93 ISA_ARM, ISA_THUMB, ISA_MAX
98 struct arm_insn_attr {
103 inline unsigned int get_mach_attr () { return mach; }
104 inline CGEN_BITSET get_isa_attr () { return isa; }
105 inline int get_r15_offset_attr () { return r15_offset; }
106 inline int get_alias_attr () { return (bools & (1<<CGEN_INSN_ALIAS)) != 0; }
107 inline int get_virtual_attr () { return (bools & (1<<CGEN_INSN_VIRTUAL)) != 0; }
108 inline int get_uncond_cti_attr () { return (bools & (1<<CGEN_INSN_UNCOND_CTI)) != 0; }
109 inline int get_cond_cti_attr () { return (bools & (1<<CGEN_INSN_COND_CTI)) != 0; }
110 inline int get_skip_cti_attr () { return (bools & (1<<CGEN_INSN_SKIP_CTI)) != 0; }
111 inline int get_delay_slot_attr () { return (bools & (1<<CGEN_INSN_DELAY_SLOT)) != 0; }
112 inline int get_relaxable_attr () { return (bools & (1<<CGEN_INSN_RELAXABLE)) != 0; }
113 inline int get_relaxed_attr () { return (bools & (1<<CGEN_INSN_RELAXED)) != 0; }
114 inline int get_no_dis_attr () { return (bools & (1<<CGEN_INSN_NO_DIS)) != 0; }
115 inline int get_pbb_attr () { return (bools & (1<<CGEN_INSN_PBB)) != 0; }
118 #define MACH_ARM7TDMI_INSN_CHUNK_BITSIZE 0
120 } // end arm namespace
122 #endif /* DESC_ARM_H */