1 /* CPU class elements for sh2a_fpu.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2005 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
12 // This file is included in the middle of the cpu class struct.
16 // CPU state information.
22 /* General purpose integer registers */
26 /* Floating point status and control register */
28 /* Single precision floating point registers */
30 /* Single/Double precision floating point registers */
32 /* floating point registers for fmov */
34 /* Current instruction set mode */
38 void stream_cgen_hardware (std::ostream &ost) const
40 ost << hardware.h_pc << ' ';
41 for (int i = 0; i < 64; i++)
42 ost << hardware.h_gr[i] << ' ';
43 ost << hardware.h_sr << ' ';
44 ost << hardware.h_fpscr << ' ';
45 for (int i = 0; i < 64; i++)
46 ost << hardware.h_fr[i] << ' ';
47 for (int i = 0; i < 16; i++)
48 ost << hardware.h_fsd[i] << ' ';
49 for (int i = 0; i < 16; i++)
50 ost << hardware.h_fmov[i] << ' ';
51 ost << hardware.h_ism << ' ';
53 void destream_cgen_hardware (std::istream &ist)
56 for (int i = 0; i < 64; i++)
57 ist >> hardware.h_gr[i];
59 ist >> hardware.h_fpscr;
60 for (int i = 0; i < 64; i++)
61 ist >> hardware.h_fr[i];
62 for (int i = 0; i < 16; i++)
63 ist >> hardware.h_fsd[i];
64 for (int i = 0; i < 16; i++)
65 ist >> hardware.h_fmov[i];
66 ist >> hardware.h_ism;
68 template <typename ST>
69 void stream_stacks (const ST &st, std::ostream &ost) const
71 for (int i = 0; i < sh2a_fpu::pipe_sz; i++)
73 ost << st[i].t << ' ';
74 for (int j = 0; j <= st[i].t; j++)
76 ost << st[i].buf[j].pc << ' ';
77 ost << st[i].buf[j].val << ' ';
78 ost << st[i].buf[j].idx0 << ' ';
83 template <typename ST>
84 void destream_stacks (ST &st, std::istream &ist)
86 for (int i = 0; i < sh2a_fpu::pipe_sz; i++)
89 for (int j = 0; j <= st[i].t; j++)
91 ist >> st[i].buf[j].pc;
92 ist >> st[i].buf[j].val;
93 ist >> st[i].buf[j].idx0;
98 void stream_cgen_write_stacks (std::ostream &ost, const sh2a_fpu::write_stacks &stacks) const
100 stream_stacks ( stacks.h_pc_writes, ost);
101 stream_stacks ( stacks.h_pr_writes, ost);
103 void destream_cgen_write_stacks (std::istream &ist, sh2a_fpu::write_stacks &stacks)
105 destream_stacks ( stacks.h_pc_writes, ist);
106 destream_stacks ( stacks.h_pr_writes, ist);
108 // C++ register access function templates
109 #define current_cpu this
111 inline UDI h_pc_get () const { return current_cpu->hardware.h_pc; }
112 inline void h_pc_set (UDI newval) { {
113 current_cpu->hardware.h_ism = ANDDI (newval, 1);
114 current_cpu->hardware.h_pc = ANDDI (newval, INVDI (1));
118 inline DI h_gr_get (UINT regno) const { return ((((regno) == (63))) ? (0) : (current_cpu->hardware.h_gr[regno])); }
119 inline void h_gr_set (UINT regno, DI newval) { if (((regno) != (63))) {
120 current_cpu->hardware.h_gr[regno] = newval;
126 inline SI h_grc_get (UINT regno) const { return ANDDI (current_cpu->hardware.h_gr[regno], ZEXTSIDI (0xffffffff)); }
127 inline void h_grc_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[regno] = EXTSIDI (newval);
130 inline SI h_sr_get () const { return this->hardware.h_sr; }
131 inline void h_sr_set (SI newval) { this->hardware.h_sr = newval; }
133 inline SI h_fpscr_get () const { return this->hardware.h_fpscr; }
134 inline void h_fpscr_set (SI newval) { this->hardware.h_fpscr = newval; }
136 inline BI h_frbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 21), 1); }
137 inline void h_frbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (21))))), SLLSI (newval, 21));
140 inline BI h_szbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 20), 1); }
141 inline void h_szbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (20))))), SLLSI (newval, 20));
144 inline BI h_prbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_fpscr, 19), 1); }
145 inline void h_prbit_set (BI newval) { current_cpu->hardware.h_fpscr = ORSI (ANDSI (current_cpu->hardware.h_fpscr, (~ (((1) << (19))))), SLLSI (newval, 19));
148 inline BI h_sbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 1), 1); }
149 inline void h_sbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (2))), SLLSI (newval, 1));
152 inline BI h_mbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 9), 1); }
153 inline void h_mbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (((1) << (9))))), SLLSI (newval, 9));
156 inline BI h_qbit_get () const { return ANDSI (SRLSI (current_cpu->hardware.h_sr, 8), 1); }
157 inline void h_qbit_set (BI newval) { current_cpu->hardware.h_sr = ORSI (ANDSI (current_cpu->hardware.h_sr, (~ (((1) << (8))))), SLLSI (newval, 8));
160 inline SF h_fr_get (UINT regno) const { return this->hardware.h_fr[regno]; }
161 inline void h_fr_set (UINT regno, SF newval) { this->hardware.h_fr[regno] = newval; }
163 inline SF h_fp_get (UINT regno) const { return current_cpu->hardware.h_fr[regno]; }
164 inline void h_fp_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[regno] = newval;
167 inline SF h_fv_get (UINT regno) const { return current_cpu->hardware.h_fr[regno]; }
168 inline void h_fv_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[regno] = newval;
171 inline DF h_dr_get (UINT regno) const { return SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (current_cpu->hardware.h_fr[regno])), 32), ZEXTSIDI (SUBWORDSFSI (current_cpu->hardware.h_fr[((regno) + (1))])))); }
172 inline void h_dr_set (UINT regno, DF newval) { {
173 current_cpu->hardware.h_fr[regno] = SUBWORDSISF (SUBWORDDFSI (newval, 0));
174 current_cpu->hardware.h_fr[((regno) + (1))] = SUBWORDSISF (SUBWORDDFSI (newval, 1));
178 inline DF h_fsd_get (UINT regno) const { return ((current_cpu->h_prbit_get ()) ? (current_cpu->h_drc_get (regno)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->hardware.h_fr[regno]))); }
179 inline void h_fsd_set (UINT regno, DF newval) { if (current_cpu->h_prbit_get ()) {
180 current_cpu->h_drc_set (regno, newval);
182 current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
186 inline DF h_fmov_get (UINT regno) const { return ((NOTBI (current_cpu->h_szbit_get ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), current_cpu->h_frc_get (regno))) : (((((((regno) & (1))) == (1))) ? (current_cpu->h_xd_get (((regno) & ((~ (1)))))) : (current_cpu->h_dr_get (regno))))); }
187 inline void h_fmov_set (UINT regno, DF newval) { if (NOTBI (current_cpu->h_szbit_get ())) {
188 current_cpu->h_frc_set (regno, CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), newval));
190 if (((((regno) & (1))) == (1))) {
191 current_cpu->h_xd_set (((regno) & ((~ (1)))), newval);
193 current_cpu->h_dr_set (regno, newval);
198 inline BI h_endian_get () const { return current_cpu->sh64_endian (); }
199 inline void h_endian_set (BI newval) { current_cpu->cgen_rtx_error ("cannot alter target byte order mid-program");
202 inline BI h_ism_get () const { return current_cpu->hardware.h_ism; }
203 inline void h_ism_set (BI newval) { current_cpu->cgen_rtx_error ("cannot set ism directly");
206 inline SF h_frc_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))]; }
207 inline void h_frc_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))] = newval;
210 inline DF h_drc_get (UINT regno) const { return current_cpu->h_dr_get (((((16) * (current_cpu->h_frbit_get ()))) + (regno))); }
211 inline void h_drc_set (UINT regno, DF newval) { current_cpu->h_dr_set (((((16) * (current_cpu->h_frbit_get ()))) + (regno)), newval);
214 inline SF h_xf_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))]; }
215 inline void h_xf_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))] = newval;
218 inline DF h_xd_get (UINT regno) const { return current_cpu->h_dr_get (((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno))); }
219 inline void h_xd_set (UINT regno, DF newval) { current_cpu->h_dr_set (((((16) * (NOTBI (current_cpu->h_frbit_get ())))) + (regno)), newval);
222 inline SF h_fvc_get (UINT regno) const { return current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))]; }
223 inline void h_fvc_set (UINT regno, SF newval) { current_cpu->hardware.h_fr[((((16) * (current_cpu->h_frbit_get ()))) + (regno))] = newval;
226 inline SI h_gbr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 16)], 1); }
227 inline void h_gbr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 16)] = EXTSIDI (newval);
230 inline SI h_vbr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 20)], 1); }
231 inline void h_vbr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 20)] = EXTSIDI (newval);
234 inline SI h_pr_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 18)], 1); }
235 inline void h_pr_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 18)] = EXTSIDI (newval);
238 inline SI h_macl_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 1); }
239 inline void h_macl_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 17)] = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 0)), 32), ZEXTSIDI (newval));
242 inline SI h_mach_get () const { return SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 0); }
243 inline void h_mach_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 17)] = ORDI (SLLDI (ZEXTSIDI (newval), 32), ZEXTSIDI (SUBWORDDISI (current_cpu->hardware.h_gr[((UINT) 17)], 1)));
246 inline BI h_tbit_get () const { return ANDBI (current_cpu->hardware.h_gr[((UINT) 19)], 1); }
247 inline void h_tbit_set (BI newval) { current_cpu->hardware.h_gr[((UINT) 19)] = ORDI (ANDDI (current_cpu->hardware.h_gr[((UINT) 19)], INVDI (1)), ZEXTBIDI (newval));