1 # utils.exp -*- Tcl -*-
2 # Utility routines for the cache component testsuite
4 # Copyright (C) 2001 Red Hat
8 return [sid_cmd "sid::component::attribute_value $victim $attr"]
11 proc miss_p {} { return [expr [sid_cmd "set thru"] == 1] }
12 proc hit_p {} { return ![miss_p] }
13 proc clear_miss_flag {} { sid_cmd "set thru 0" }
15 # Assert that a cache access causes bus activity (ie. a miss).
16 proc assert_miss {} { global test; if [miss_p] { pass "$test (miss)" } else { fail "$test (miss)" }}
18 # Assert that a cache access causes bus activity (ie. a hit).
19 proc assert_hit {} { global test; if [hit_p] { pass "$test (hit)" } else { fail "$test (hit)" }}
21 # Assert that an attribute is variant (by delta).
22 proc assert_variant {attr prior {delta 1}} {
24 set test "$attr attribute has been incremented"
25 set value [get_attr $attr]
26 if {[expr $prior + $delta] == $value} { pass $test } else { fail $test }
29 # Assert that an attribute is invariant.
30 proc assert_invariant {attr prior} {
32 set test "$attr attribute is invariant"
33 set value [get_attr $attr]
34 if {$prior == $value} { pass $test } else { fail $test }
37 # Instrument $bus as a test bus.
38 proc instrument_bus {bus} {
39 sid_cmd "if {[info exists hook_written]} { unset hook_written }"
40 sid_cmd "if {[info exists hook_read]} { unset hook_read }"
41 foreach endian {l b} {
42 foreach width {1 2 4 8} {
43 sid_cmd "set hook_read(h4,${endian}${width},$bus) { set thru 1 ; return {ok 0}}"
44 sid_cmd "set hook_written(h4,${endian}${width},$bus) { set thru 1 ; return ok}"