1 # Testsuite for the Toshiba Media Engine interrupt controller unit.
2 # Copyright (C) 2001 Red Hat
4 if {! $sidtarget(mep)} then { untested "hw-interrupt-mep not available"; return }
6 # The number of available interrupt lines.
9 # A convenience variable.
10 set all_ones 0xFFFFFFFF
12 set test "sid configuration"
13 sid_config_component_test "mep-intc.conf" \
14 "load libcache.la cache_component_library
15 load libmemory.la mem_component_library
16 load libmepfamily.la mepfamily_component_library" \
21 if {[sid_start "mep-intc.conf"]} { pass $test } else { fail $test; return }
23 set test "attribute list"
24 sid_assert_includes_all "sid::component::attribute_names $victim" \
27 set test "get interrupt output pin"
28 sid_assert_success "sid::component::find_pin $victim interrupt"
30 set test "get reset pin"
31 sid_assert_success "sid::component::find_pin $victim reset"
33 # Check for all N interrupt input lines.
35 for {set i 0} {$i < $num_lines} {incr i} {
36 set test "get interrupt-source-$i pin"
37 sid_assert ![string match [set irq_source($i) [sid_cmd "sid::component::find_pin $victim interrupt-source-$i"]] ""]
40 # Check for the presence of the register set. Record the name given to
41 # it by sid_cmd, as we'll use it throughout this testsuite.
43 set test "get register bus"
44 sid_assert ![string match [set bus [sid_cmd "sid::component::find_bus $victim registers"]] ""]
46 # A pin we use again, and again, and again.
48 set probe_pin [sid_cmd "sid::pin::new"]
50 # Overwrite IVR with all ones. Ensure that no read-only bits are
53 set test "overwrite IVR"
54 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
55 if [sid_bus_ok_p $result] {
56 set ivr0 [lindex $result 1]
57 set result [sid_cmd "sid::bus::write_h4_b4 $bus 0 $all_ones"]
58 if [sid_bus_ok_p $result] {
59 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
60 if [sid_bus_ok_p $result] {
61 set ivr1 [lindex $result 1]
62 sid_assert [expr $ivr0 | (0xf << 8) == $ivr1]
74 set result [sid_cmd "sid::bus::write_h4_b4 $bus 0 0"]
75 if [sid_bus_ok_p $result] {
76 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
77 sid_assert [sid_bus_ok_p $result]
80 # Test setting different trigger modes (edge vs. level) amongst
83 foreach pattern "0x12345678 0 0x55555555 0xAAAAAAAA $all_ones" {
84 set test "set IET to $pattern"
85 sid_assert_success "sid::bus::write_h4_b4 $bus 0xc $pattern"
86 set test "check IET for $pattern"
87 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0xc"]
88 if [sid_bus_ok_p $result] {
89 sid_assert [expr [lindex $result 1] == $pattern]
93 # Test setting different interrupt levels to ILR0..ILR3.
95 foreach reg {{ILR0 0x10} {ILR1 0x14} {ILR2 0x18} {ILR3 0x1c}} {
96 set regname [lindex $reg 0]
97 set regaddr [lindex $reg 1]
98 foreach pattern "0 0x12345678 0x55555555 0xAAAAAAAA $all_ones" {
99 set test "set $regname to $pattern"
100 sid_assert_success "sid::bus::write_h4_b4 $bus $regaddr $pattern"
101 set test "check $regname for $pattern"
102 set result [sid_cmd "sid::bus::read_h4_b4 $bus $regaddr"]
103 if [sid_bus_ok_p $result] {
104 sid_assert [expr [lindex $result 1] == $pattern]
105 } else { fail $test }
109 # Test enabling different sets of interrupt lines.
111 foreach pattern "0x0 0x12345678 0x55555555 0xAAAAAAAA $all_ones" {
112 set test "disable all interrupt lines"
113 sid_assert_success "sid::bus::write_h4_b4 $bus 8 0"
115 set test "validate all interrupt lines are disabled"
116 set result [sid_cmd "sid::bus::read_h4_b4 $bus 8"]
118 if [sid_bus_ok_p $result] {
119 sid_assert [expr [lindex $result 1] == 0]
120 } else { fail "$test (bus error)" }
122 set test "initialise set of enabled interrupt lines ($pattern)"
123 sid_assert_success "sid::bus::write_h4_b4 $bus 8 $pattern"
125 set test "validate set of enabled interrupt lines ($pattern)"
126 set result [sid_cmd "sid::bus::read_h4_b4 $bus 8"]
127 if [sid_bus_ok_p $result] {
128 sid_assert [expr [lindex $result 1] == $pattern]
129 } else { fail "$test (bus error)" }
132 # Set all interrupt levels to 1.
133 # ie. ILRx = 0x11111111
135 foreach reg {{ilr0 0x10} {ilr1 0x14} {ilr2 0x18} {ilr3 0x1c}} {
136 set regname [lindex $reg 0]
137 set regaddr [lindex $reg 1]
138 set test "set all channels to interrupt level 1 for $regname"
139 sid_assert_success "sid::bus::write_h4_b4 $bus $regaddr 0x11111111"
140 set test "validate contents of $regname"
141 set result [sid_cmd "sid::bus::read_h4_b4 $bus $regaddr"]
142 if {[sid_bus_ok_p $result] && [expr [lindex $result 1] == 0x11111111]} {
149 # Permit interrupts on one channel at a time.
150 # Generate an interrupt on each interrupt line on each iteration.
151 # For edge triggered mode, clear the interrupt by writing to the ISR.
152 # For level triggered mode, clear it by clearing the interrupt source.
154 # This is a double nested loop -- n^2 tests are performed to make sure
155 # that other interrupt lines going high does not invoke an interrupt
156 # (ie. to ensure that the masking works correctly for all cases).
158 sid_cmd "set hook_driven_h4($probe_pin) {
159 global driven_h4_value interrupted
160 set interrupted \$driven_h4_value
163 sid_cmd "sid::component::connect_pin $victim interrupt $probe_pin"
165 proc exhaustive_driven_test {triggermode} {
175 if {$triggermode == "edge"} {
176 append test "for edge-triggered interrupts"
179 append test "for level-triggered interrupts"
182 sid_assert_success "sid::bus::write_h4_b4 $bus 0xc $value"
184 set test "validate IET register"
185 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0xc"]
186 sid_assert [expr [sid_bus_ok_p $result] && [expr [lindex $result 1] == $value]]
190 for {set i 0} {$i < $num_lines} {incr i} {
192 set test "disable all interrupt lines"
193 sid_assert_success "sid::bus::write_h4_b4 $bus 8 0"
194 set test "validate all interrupt lines are disabled"
195 set result [sid_cmd "sid::bus::read_h4_b4 $bus 8"]
196 if {![sid_bus_ok_p $result] || [expr [lindex $result 1] != 0]} {
202 set test "enable interrupt line $i"
203 sid_assert_success "sid::bus::write_h4_b4 $bus 8 [expr 1 << $i]"
205 set test "validate only interrupt line $i is enabled"
206 set result [sid_cmd "sid::bus::read_h4_b4 $bus 8"]
207 if [sid_bus_ok_p $result] {
208 set val [expr 1 << $i]
210 set val [expr - $val]
212 if {[lindex $result 1] != $val} {
219 fail "$test -- [lindex $result 0]"
223 for {set j 0} {$j < $num_lines} {incr j} {
225 sid_cmd "set interrupted -1"
226 set test "clear ISR register"
227 set result [sid_cmd "sid::bus::write_h4_b4 $bus 4 0"]
228 if ![sid_bus_ok_p $result] { fail $test; break }
230 # Raise an interrupt on interrupt line j.
231 sid_cmd "sid::pin::driven_h4 $irq_source($j) 1"
233 set deferred_result [sid_cmd "set interrupted"]
235 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
236 if {![sid_bus_ok_p $result]} {
241 set ivr [lindex $result 1]
244 set test "ensure bit $j is set in the ISR"
245 set result [sid_cmd "sid::bus::read_h4_b4 $bus 4"]
246 if {![sid_bus_ok_p $result]} {
248 fail "$test ($result) not ok"
251 set val [expr 1 << $j]
253 set val [expr - $val]
255 if {[expr [lindex $result 1] != $val]} {
257 fail "$test ($result) result != $val"
261 if { $triggermode == "level" } {
263 sid_cmd "sid::pin::driven_h4 $irq_source($j) 0"
265 # signal that the interrupt is handled
266 set test "clear bit $j in the ISR"
267 set result [sid_cmd "sid::bus::write_h4_b4 $bus 4 0"]
268 if {![sid_bus_ok_p $result]} {
275 set test "verify bit $j is cleared in the ISR"
276 set result [sid_cmd "sid::bus::read_h4_b4 $bus 4"]
277 if {![sid_bus_ok_p $result] || [expr [lindex $result 1] != 0]} {
283 if {$i == $j} { set test permitting } else { set test masking }
284 append test " interrupt from interrupt $j when enabling interrupt $i only"
285 set result $deferred_result
290 fail "$test - $result"
294 set test "ensure IVR.ILV contains interrupt level (1)"
295 if [expr [expr [expr $ivr & 0xf000] >> 12] != 1] {
301 set test "ensure IVR.ICN contains interrupt channel"
302 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
303 if [expr [expr [expr $ivr & 0xf8] >> 3] != $i] {
309 if {$i != $j && $result != "-1"} {
311 fail "$test - $result"
316 if [expr !$failures] { pass "masking edge-triggered interrupts" }
319 exhaustive_driven_test edge
320 exhaustive_driven_test level
322 # Make all interrupt sources edge-triggered again.
324 set test "set all interrupt sources to edge-triggered"
325 sid_assert_success "sid::bus::write_h4_b4 $bus 0xc $all_ones"
326 set test "validate IET register"
327 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0xc"]
328 sid_assert [expr [sid_bus_ok_p $result] && [expr [lindex $result 1] == $all_ones]]
330 # Set channel 0 to interrupt level 7.
331 # Mask interrupts at or below interrupt level 7.
332 # Make sure the interrupt is ignored until we set the IML to 0.
334 set test "set channel 0 to interrupt level 7"
335 sid_assert_success "sid::bus::write_h4_b4 $bus 0x10 7"
336 set test "validate channel 0 is set to interrupt level 7"
337 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0x10"]
338 sid_assert [expr [sid_bus_ok_p $result] && [expr [lindex $result 1] == 7]]
340 set test "set IVR.IML to 7"
341 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
342 if [sid_bus_ok_p $result] {
343 set new_ivr [expr [lindex $result 1] | [expr 7 << 8]]
344 sid_assert_success "sid::bus::write_h4_b4 $bus 0 $new_ivr"
349 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
350 sid_cmd "set interrupted -1"
351 sid_cmd "sid::pin::driven_h4 $irq_source(0) 1"
352 set test "mask level 7 interrupt"
353 sid_assert [expr [sid_cmd "set interrupted"] == -1]
354 set result [sid_cmd "sid::bus::read_h4_b4 $bus 0"]
357 set test "interrupt level priority selection"
358 sid_cmd "set interrupted -1"
361 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x0 0"]] { incr failures }
362 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x4 0"]] { incr failures }
363 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x8 $all_ones"]] { incr failures }
364 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0xc $all_ones"]] { incr failures }
365 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x10 0x137f137f"]] { incr failures }
366 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x14 0"]] { incr failures }
367 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x18 0"]] { incr failures }
368 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x1c 0"]] { incr failures }
370 sid_cmd "sid::pin::driven_h4 $irq_source(5) 1"
371 sid_cmd "sid::pin::driven_h4 $irq_source(7) 1"
374 set selected [sid_cmd "set interrupted"]
375 sid_assert [expr $selected == 5]
377 set test "interrupt channel priority selection (equal levels)"
378 sid_cmd "set interrupted -1"
381 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x0 0"]] { incr failures }
382 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x4 0"]] { incr failures }
383 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x8 $all_ones"]] { incr failures }
384 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0xc $all_ones"]] { incr failures }
385 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x10 0x33333333"]] { incr failures }
386 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x14 0"]] { incr failures }
387 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x18 0"]] { incr failures }
388 if ![sid_bus_ok_p [sid_cmd "sid::bus::write_h4_b4 $bus 0x1c 0"]] { incr failures }
390 sid_cmd "sid::pin::driven_h4 $irq_source(5) 1"
391 sid_cmd "sid::pin::driven_h4 $irq_source(7) 1"
394 set selected [sid_cmd "set interrupted"]
395 sid_assert [expr ($failures == 0) && ($selected == 7)]
398 sid_cmd "sid::component::disconnect_pin $victim interrupt $probe_pin"
401 if {[sid_stop]} { pass $test } else { fail $test ; return }
403 # zap temp file if tests were successful
405 if {$exit_status == "0"} { file delete "mep-intc.conf" }