1 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
3 * configure: Regenerate.
5 2005-12-14 Chao-ying Fu <fu@mips.com>
7 * Makefile.in (SIM_OBJS): Add dsp.o.
8 (dsp.o): New dependency.
9 (IGEN_INCLUDE): Add dsp.igen.
10 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
11 mipsisa64*-*-*): Add dsp to sim_igen_machine.
12 * configure: Regenerate.
13 * mips.igen: Add dsp model and include dsp.igen.
14 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
15 because these instructions are extended in DSP ASE.
16 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
17 adding 6 DSP accumulator registers and 1 DSP control register.
18 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
19 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
20 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
21 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
22 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
23 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
24 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
25 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
26 DSPCR_CCOND_SMASK): New define.
27 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
28 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
30 2005-07-08 Ian Lance Taylor <ian@airs.com>
32 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
34 2005-06-16 David Ung <davidu@mips.com>
35 Nigel Stephens <nigel@mips.com>
37 * mips.igen: New mips16e model and include m16e.igen.
38 (check_u64): Add mips16e tag.
39 * m16e.igen: New file for MIPS16e instructions.
40 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
41 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
43 * configure: Regenerate.
45 2005-05-26 David Ung <davidu@mips.com>
47 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
48 tags to all instructions which are applicable to the new ISAs.
49 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
51 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
53 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
55 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
56 * configure: Regenerate.
58 2005-03-23 Mark Kettenis <kettenis@gnu.org>
60 * configure: Regenerate.
62 2005-01-14 Andrew Cagney <cagney@gnu.org>
64 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
65 explicit call to AC_CONFIG_HEADER.
66 * configure: Regenerate.
68 2005-01-12 Andrew Cagney <cagney@gnu.org>
70 * configure.ac: Update to use ../common/common.m4.
71 * configure: Re-generate.
73 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
75 * configure: Regenerated to track ../common/aclocal.m4 changes.
77 2005-01-07 Andrew Cagney <cagney@gnu.org>
79 * configure.ac: Rename configure.in, require autoconf 2.59.
80 * configure: Re-generate.
82 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
84 * configure: Regenerate for ../common/aclocal.m4 update.
86 2004-09-24 Monika Chaddha <monika@acmet.com>
88 Committed by Andrew Cagney.
89 * m16.igen (CMP, CMPI): Fix assembler.
91 2004-08-18 Chris Demetriou <cgd@broadcom.com>
93 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
94 * configure: Regenerate.
96 2004-06-25 Chris Demetriou <cgd@broadcom.com>
98 * configure.in (sim_m16_machine): Include mipsIII.
99 * configure: Regenerate.
101 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
103 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
105 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
107 2004-04-10 Chris Demetriou <cgd@broadcom.com>
109 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
111 2004-04-09 Chris Demetriou <cgd@broadcom.com>
113 * mips.igen (check_fmt): Remove.
114 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
115 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
116 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
117 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
118 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
119 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
120 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
121 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
122 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
123 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
125 2004-04-09 Chris Demetriou <cgd@broadcom.com>
127 * sb1.igen (check_sbx): New function.
128 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
130 2004-03-29 Chris Demetriou <cgd@broadcom.com>
131 Richard Sandiford <rsandifo@redhat.com>
133 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
134 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
135 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
136 separate implementations for mipsIV and mipsV. Use new macros to
137 determine whether the restrictions apply.
139 2004-01-19 Chris Demetriou <cgd@broadcom.com>
141 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
142 (check_mult_hilo): Improve comments.
143 (check_div_hilo): Likewise. Also, fork off a new version
144 to handle mips32/mips64 (since there are no hazards to check
147 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
149 * mips.igen (do_dmultx): Fix check for negative operands.
151 2003-05-16 Ian Lance Taylor <ian@airs.com>
153 * Makefile.in (SHELL): Make sure this is defined.
154 (various): Use $(SHELL) whenever we invoke move-if-change.
156 2003-05-03 Chris Demetriou <cgd@broadcom.com>
158 * cp1.c: Tweak attribution slightly.
161 * mdmx.igen: Likewise.
162 * mips3d.igen: Likewise.
163 * sb1.igen: Likewise.
165 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
167 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
170 2003-02-27 Andrew Cagney <cagney@redhat.com>
172 * interp.c (sim_open): Rename _bfd to bfd.
173 (sim_create_inferior): Ditto.
175 2003-01-14 Chris Demetriou <cgd@broadcom.com>
177 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
179 2003-01-14 Chris Demetriou <cgd@broadcom.com>
181 * mips.igen (EI, DI): Remove.
183 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
185 * Makefile.in (tmp-run-multi): Fix mips16 filter.
187 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
188 Andrew Cagney <ac131313@redhat.com>
189 Gavin Romig-Koch <gavin@redhat.com>
190 Graydon Hoare <graydon@redhat.com>
191 Aldy Hernandez <aldyh@redhat.com>
192 Dave Brolley <brolley@redhat.com>
193 Chris Demetriou <cgd@broadcom.com>
195 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
196 (sim_mach_default): New variable.
197 (mips64vr-*-*, mips64vrel-*-*): New configurations.
198 Add a new simulator generator, MULTI.
199 * configure: Regenerate.
200 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
201 (multi-run.o): New dependency.
202 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
203 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
204 (tmp-multi): Combine them.
205 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
206 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
207 (distclean-extra): New rule.
208 * sim-main.h: Include bfd.h.
209 (MIPS_MACH): New macro.
210 * mips.igen (vr4120, vr5400, vr5500): New models.
211 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
212 * vr.igen: Replace with new version.
214 2003-01-04 Chris Demetriou <cgd@broadcom.com>
216 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
217 * configure: Regenerate.
219 2002-12-31 Chris Demetriou <cgd@broadcom.com>
221 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
222 * mips.igen: Remove all invocations of check_branch_bug and
225 2002-12-16 Chris Demetriou <cgd@broadcom.com>
227 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
229 2002-07-30 Chris Demetriou <cgd@broadcom.com>
231 * mips.igen (do_load_double, do_store_double): New functions.
232 (LDC1, SDC1): Rename to...
233 (LDC1b, SDC1b): respectively.
234 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
236 2002-07-29 Michael Snyder <msnyder@redhat.com>
238 * cp1.c (fp_recip2): Modify initialization expression so that
239 GCC will recognize it as constant.
241 2002-06-18 Chris Demetriou <cgd@broadcom.com>
243 * mdmx.c (SD_): Delete.
244 (Unpredictable): Re-define, for now, to directly invoke
245 unpredictable_action().
246 (mdmx_acc_op): Fix error in .ob immediate handling.
248 2002-06-18 Andrew Cagney <cagney@redhat.com>
250 * interp.c (sim_firmware_command): Initialize `address'.
252 2002-06-16 Andrew Cagney <ac131313@redhat.com>
254 * configure: Regenerated to track ../common/aclocal.m4 changes.
256 2002-06-14 Chris Demetriou <cgd@broadcom.com>
257 Ed Satterthwaite <ehs@broadcom.com>
259 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
260 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
261 * mips.igen: Include mips3d.igen.
262 (mips3d): New model name for MIPS-3D ASE instructions.
263 (CVT.W.fmt): Don't use this instruction for word (source) format
265 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
266 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
267 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
268 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
269 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
270 (RSquareRoot1, RSquareRoot2): New macros.
271 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
272 (fp_rsqrt2): New functions.
273 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
274 * configure: Regenerate.
276 2002-06-13 Chris Demetriou <cgd@broadcom.com>
277 Ed Satterthwaite <ehs@broadcom.com>
279 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
280 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
281 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
282 (convert): Note that this function is not used for paired-single
284 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
285 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
286 (check_fmt_p): Enable paired-single support.
287 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
288 (PUU.PS): New instructions.
289 (CVT.S.fmt): Don't use this instruction for paired-single format
291 * sim-main.h (FP_formats): New value 'fmt_ps.'
292 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
293 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
295 2002-06-12 Chris Demetriou <cgd@broadcom.com>
297 * mips.igen: Fix formatting of function calls in
300 2002-06-12 Chris Demetriou <cgd@broadcom.com>
302 * mips.igen (MOVN, MOVZ): Trace result.
303 (TNEI): Print "tnei" as the opcode name in traces.
304 (CEIL.W): Add disassembly string for traces.
305 (RSQRT.fmt): Make location of disassembly string consistent
306 with other instructions.
308 2002-06-12 Chris Demetriou <cgd@broadcom.com>
310 * mips.igen (X): Delete unused function.
312 2002-06-08 Andrew Cagney <cagney@redhat.com>
314 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
316 2002-06-07 Chris Demetriou <cgd@broadcom.com>
317 Ed Satterthwaite <ehs@broadcom.com>
319 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
320 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
321 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
322 (fp_nmsub): New prototypes.
323 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
324 (NegMultiplySub): New defines.
325 * mips.igen (RSQRT.fmt): Use RSquareRoot().
326 (MADD.D, MADD.S): Replace with...
327 (MADD.fmt): New instruction.
328 (MSUB.D, MSUB.S): Replace with...
329 (MSUB.fmt): New instruction.
330 (NMADD.D, NMADD.S): Replace with...
331 (NMADD.fmt): New instruction.
332 (NMSUB.D, MSUB.S): Replace with...
333 (NMSUB.fmt): New instruction.
335 2002-06-07 Chris Demetriou <cgd@broadcom.com>
336 Ed Satterthwaite <ehs@broadcom.com>
338 * cp1.c: Fix more comment spelling and formatting.
339 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
340 (denorm_mode): New function.
341 (fpu_unary, fpu_binary): Round results after operation, collect
342 status from rounding operations, and update the FCSR.
343 (convert): Collect status from integer conversions and rounding
344 operations, and update the FCSR. Adjust NaN values that result
345 from conversions. Convert to use sim_io_eprintf rather than
346 fprintf, and remove some debugging code.
347 * cp1.h (fenr_FS): New define.
349 2002-06-07 Chris Demetriou <cgd@broadcom.com>
351 * cp1.c (convert): Remove unusable debugging code, and move MIPS
352 rounding mode to sim FP rounding mode flag conversion code into...
353 (rounding_mode): New function.
355 2002-06-07 Chris Demetriou <cgd@broadcom.com>
357 * cp1.c: Clean up formatting of a few comments.
358 (value_fpr): Reformat switch statement.
360 2002-06-06 Chris Demetriou <cgd@broadcom.com>
361 Ed Satterthwaite <ehs@broadcom.com>
364 * sim-main.h: Include cp1.h.
365 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
366 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
367 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
368 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
369 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
370 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
371 * cp1.c: Don't include sim-fpu.h; already included by
372 sim-main.h. Clean up formatting of some comments.
373 (NaN, Equal, Less): Remove.
374 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
375 (fp_cmp): New functions.
376 * mips.igen (do_c_cond_fmt): Remove.
377 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
378 Compare. Add result tracing.
379 (CxC1): Remove, replace with...
380 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
381 (DMxC1): Remove, replace with...
382 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
383 (MxC1): Remove, replace with...
384 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
386 2002-06-04 Chris Demetriou <cgd@broadcom.com>
388 * sim-main.h (FGRIDX): Remove, replace all uses with...
389 (FGR_BASE): New macro.
390 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
391 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
392 (NR_FGR, FGR): Likewise.
393 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
394 * mips.igen: Likewise.
396 2002-06-04 Chris Demetriou <cgd@broadcom.com>
398 * cp1.c: Add an FSF Copyright notice to this file.
400 2002-06-04 Chris Demetriou <cgd@broadcom.com>
401 Ed Satterthwaite <ehs@broadcom.com>
403 * cp1.c (Infinity): Remove.
404 * sim-main.h (Infinity): Likewise.
406 * cp1.c (fp_unary, fp_binary): New functions.
407 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
408 (fp_sqrt): New functions, implemented in terms of the above.
409 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
410 (Recip, SquareRoot): Remove (replaced by functions above).
411 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
412 (fp_recip, fp_sqrt): New prototypes.
413 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
414 (Recip, SquareRoot): Replace prototypes with #defines which
415 invoke the functions above.
417 2002-06-03 Chris Demetriou <cgd@broadcom.com>
419 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
420 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
421 file, remove PARAMS from prototypes.
422 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
423 simulator state arguments.
424 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
425 pass simulator state arguments.
426 * cp1.c (SD): Redefine as CPU_STATE(cpu).
427 (store_fpr, convert): Remove 'sd' argument.
428 (value_fpr): Likewise. Convert to use 'SD' instead.
430 2002-06-03 Chris Demetriou <cgd@broadcom.com>
432 * cp1.c (Min, Max): Remove #if 0'd functions.
433 * sim-main.h (Min, Max): Remove.
435 2002-06-03 Chris Demetriou <cgd@broadcom.com>
437 * cp1.c: fix formatting of switch case and default labels.
438 * interp.c: Likewise.
439 * sim-main.c: Likewise.
441 2002-06-03 Chris Demetriou <cgd@broadcom.com>
443 * cp1.c: Clean up comments which describe FP formats.
444 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
446 2002-06-03 Chris Demetriou <cgd@broadcom.com>
447 Ed Satterthwaite <ehs@broadcom.com>
449 * configure.in (mipsisa64sb1*-*-*): New target for supporting
450 Broadcom SiByte SB-1 processor configurations.
451 * configure: Regenerate.
452 * sb1.igen: New file.
453 * mips.igen: Include sb1.igen.
455 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
456 * mdmx.igen: Add "sb1" model to all appropriate functions and
458 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
459 (ob_func, ob_acc): Reference the above.
460 (qh_acc): Adjust to keep the same size as ob_acc.
461 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
462 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
464 2002-06-03 Chris Demetriou <cgd@broadcom.com>
466 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
468 2002-06-02 Chris Demetriou <cgd@broadcom.com>
469 Ed Satterthwaite <ehs@broadcom.com>
471 * mips.igen (mdmx): New (pseudo-)model.
472 * mdmx.c, mdmx.igen: New files.
473 * Makefile.in (SIM_OBJS): Add mdmx.o.
474 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
476 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
477 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
478 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
479 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
480 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
481 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
482 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
483 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
484 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
485 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
486 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
487 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
488 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
489 (qh_fmtsel): New macros.
490 (_sim_cpu): New member "acc".
491 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
492 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
494 2002-05-01 Chris Demetriou <cgd@broadcom.com>
496 * interp.c: Use 'deprecated' rather than 'depreciated.'
497 * sim-main.h: Likewise.
499 2002-05-01 Chris Demetriou <cgd@broadcom.com>
501 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
502 which wouldn't compile anyway.
503 * sim-main.h (unpredictable_action): New function prototype.
504 (Unpredictable): Define to call igen function unpredictable().
505 (NotWordValue): New macro to call igen function not_word_value().
506 (UndefinedResult): Remove.
507 * interp.c (undefined_result): Remove.
508 (unpredictable_action): New function.
509 * mips.igen (not_word_value, unpredictable): New functions.
510 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
511 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
512 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
513 NotWordValue() to check for unpredictable inputs, then
514 Unpredictable() to handle them.
516 2002-02-24 Chris Demetriou <cgd@broadcom.com>
518 * mips.igen: Fix formatting of calls to Unpredictable().
520 2002-04-20 Andrew Cagney <ac131313@redhat.com>
522 * interp.c (sim_open): Revert previous change.
524 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
526 * interp.c (sim_open): Disable chunk of code that wrote code in
527 vector table entries.
529 2002-03-19 Chris Demetriou <cgd@broadcom.com>
531 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
532 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
535 2002-03-19 Chris Demetriou <cgd@broadcom.com>
537 * cp1.c: Fix many formatting issues.
539 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
541 * cp1.c (fpu_format_name): New function to replace...
542 (DOFMT): This. Delete, and update all callers.
543 (fpu_rounding_mode_name): New function to replace...
544 (RMMODE): This. Delete, and update all callers.
546 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
548 * interp.c: Move FPU support routines from here to...
549 * cp1.c: Here. New file.
550 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
553 2002-03-12 Chris Demetriou <cgd@broadcom.com>
555 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
556 * mips.igen (mips32, mips64): New models, add to all instructions
557 and functions as appropriate.
558 (loadstore_ea, check_u64): New variant for model mips64.
559 (check_fmt_p): New variant for models mipsV and mips64, remove
560 mipsV model marking fro other variant.
563 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
564 for mips32 and mips64.
565 (DCLO, DCLZ): New instructions for mips64.
567 2002-03-07 Chris Demetriou <cgd@broadcom.com>
569 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
570 immediate or code as a hex value with the "%#lx" format.
571 (ANDI): Likewise, and fix printed instruction name.
573 2002-03-05 Chris Demetriou <cgd@broadcom.com>
575 * sim-main.h (UndefinedResult, Unpredictable): New macros
576 which currently do nothing.
578 2002-03-05 Chris Demetriou <cgd@broadcom.com>
580 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
581 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
582 (status_CU3): New definitions.
584 * sim-main.h (ExceptionCause): Add new values for MIPS32
585 and MIPS64: MDMX, MCheck, CacheErr. Update comments
586 for DebugBreakPoint and NMIReset to note their status in
588 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
589 (SignalExceptionCacheErr): New exception macros.
591 2002-03-05 Chris Demetriou <cgd@broadcom.com>
593 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
594 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
596 (SignalExceptionCoProcessorUnusable): Take as argument the
597 unusable coprocessor number.
599 2002-03-05 Chris Demetriou <cgd@broadcom.com>
601 * mips.igen: Fix formatting of all SignalException calls.
603 2002-03-05 Chris Demetriou <cgd@broadcom.com>
605 * sim-main.h (SIGNEXTEND): Remove.
607 2002-03-04 Chris Demetriou <cgd@broadcom.com>
609 * mips.igen: Remove gencode comment from top of file, fix
610 spelling in another comment.
612 2002-03-04 Chris Demetriou <cgd@broadcom.com>
614 * mips.igen (check_fmt, check_fmt_p): New functions to check
615 whether specific floating point formats are usable.
616 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
617 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
618 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
619 Use the new functions.
620 (do_c_cond_fmt): Remove format checks...
621 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
623 2002-03-03 Chris Demetriou <cgd@broadcom.com>
625 * mips.igen: Fix formatting of check_fpu calls.
627 2002-03-03 Chris Demetriou <cgd@broadcom.com>
629 * mips.igen (FLOOR.L.fmt): Store correct destination register.
631 2002-03-03 Chris Demetriou <cgd@broadcom.com>
633 * mips.igen: Remove whitespace at end of lines.
635 2002-03-02 Chris Demetriou <cgd@broadcom.com>
637 * mips.igen (loadstore_ea): New function to do effective
638 address calculations.
639 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
640 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
641 CACHE): Use loadstore_ea to do effective address computations.
643 2002-03-02 Chris Demetriou <cgd@broadcom.com>
645 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
646 * mips.igen (LL, CxC1, MxC1): Likewise.
648 2002-03-02 Chris Demetriou <cgd@broadcom.com>
650 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
651 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
652 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
653 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
654 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
655 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
656 Don't split opcode fields by hand, use the opcode field values
659 2002-03-01 Chris Demetriou <cgd@broadcom.com>
661 * mips.igen (do_divu): Fix spacing.
663 * mips.igen (do_dsllv): Move to be right before DSLLV,
664 to match the rest of the do_<shift> functions.
666 2002-03-01 Chris Demetriou <cgd@broadcom.com>
668 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
669 DSRL32, do_dsrlv): Trace inputs and results.
671 2002-03-01 Chris Demetriou <cgd@broadcom.com>
673 * mips.igen (CACHE): Provide instruction-printing string.
675 * interp.c (signal_exception): Comment tokens after #endif.
677 2002-02-28 Chris Demetriou <cgd@broadcom.com>
679 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
680 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
681 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
682 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
683 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
684 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
685 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
686 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
688 2002-02-28 Chris Demetriou <cgd@broadcom.com>
690 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
691 instruction-printing string.
692 (LWU): Use '64' as the filter flag.
694 2002-02-28 Chris Demetriou <cgd@broadcom.com>
696 * mips.igen (SDXC1): Fix instruction-printing string.
698 2002-02-28 Chris Demetriou <cgd@broadcom.com>
700 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
703 2002-02-27 Chris Demetriou <cgd@broadcom.com>
705 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
708 2002-02-27 Chris Demetriou <cgd@broadcom.com>
710 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
711 add a comma) so that it more closely match the MIPS ISA
712 documentation opcode partitioning.
713 (PREF): Put useful names on opcode fields, and include
714 instruction-printing string.
716 2002-02-27 Chris Demetriou <cgd@broadcom.com>
718 * mips.igen (check_u64): New function which in the future will
719 check whether 64-bit instructions are usable and signal an
720 exception if not. Currently a no-op.
721 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
722 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
723 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
724 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
726 * mips.igen (check_fpu): New function which in the future will
727 check whether FPU instructions are usable and signal an exception
728 if not. Currently a no-op.
729 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
730 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
731 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
732 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
733 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
734 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
735 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
736 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
738 2002-02-27 Chris Demetriou <cgd@broadcom.com>
740 * mips.igen (do_load_left, do_load_right): Move to be immediately
742 (do_store_left, do_store_right): Move to be immediately following
745 2002-02-27 Chris Demetriou <cgd@broadcom.com>
747 * mips.igen (mipsV): New model name. Also, add it to
748 all instructions and functions where it is appropriate.
750 2002-02-18 Chris Demetriou <cgd@broadcom.com>
752 * mips.igen: For all functions and instructions, list model
753 names that support that instruction one per line.
755 2002-02-11 Chris Demetriou <cgd@broadcom.com>
757 * mips.igen: Add some additional comments about supported
758 models, and about which instructions go where.
759 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
760 order as is used in the rest of the file.
762 2002-02-11 Chris Demetriou <cgd@broadcom.com>
764 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
765 indicating that ALU32_END or ALU64_END are there to check
767 (DADD): Likewise, but also remove previous comment about
770 2002-02-10 Chris Demetriou <cgd@broadcom.com>
772 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
773 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
774 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
775 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
776 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
777 fields (i.e., add and move commas) so that they more closely
778 match the MIPS ISA documentation opcode partitioning.
780 2002-02-10 Chris Demetriou <cgd@broadcom.com>
782 * mips.igen (ADDI): Print immediate value.
784 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
785 (SLL): Print "nop" specially, and don't run the code
786 that does the shift for the "nop" case.
788 2001-11-17 Fred Fish <fnf@redhat.com>
790 * sim-main.h (float_operation): Move enum declaration outside
791 of _sim_cpu struct declaration.
793 2001-04-12 Jim Blandy <jimb@redhat.com>
795 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
796 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
798 * sim-main.h (COCIDX): Remove definition; this isn't supported by
799 PENDING_FILL, and you can get the intended effect gracefully by
800 calling PENDING_SCHED directly.
802 2001-02-23 Ben Elliston <bje@redhat.com>
804 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
805 already defined elsewhere.
807 2001-02-19 Ben Elliston <bje@redhat.com>
809 * sim-main.h (sim_monitor): Return an int.
810 * interp.c (sim_monitor): Add return values.
811 (signal_exception): Handle error conditions from sim_monitor.
813 2001-02-08 Ben Elliston <bje@redhat.com>
815 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
816 (store_memory): Likewise, pass cia to sim_core_write*.
818 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
820 On advice from Chris G. Demetriou <cgd@sibyte.com>:
821 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
823 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
825 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
826 * Makefile.in: Don't delete *.igen when cleaning directory.
828 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
830 * m16.igen (break): Call SignalException not sim_engine_halt.
832 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
835 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
837 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
839 * mips.igen (MxC1, DMxC1): Fix printf formatting.
841 2000-05-24 Michael Hayes <mhayes@cygnus.com>
843 * mips.igen (do_dmultx): Fix typo.
845 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
847 * configure: Regenerated to track ../common/aclocal.m4 changes.
849 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
851 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
853 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
855 * sim-main.h (GPR_CLEAR): Define macro.
857 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
859 * interp.c (decode_coproc): Output long using %lx and not %s.
861 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
863 * interp.c (sim_open): Sort & extend dummy memory regions for
864 --board=jmr3904 for eCos.
866 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
868 * configure: Regenerated.
870 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
872 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
873 calls, conditional on the simulator being in verbose mode.
875 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
877 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
878 cache don't get ReservedInstruction traps.
880 1999-11-29 Mark Salter <msalter@cygnus.com>
882 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
883 to clear status bits in sdisr register. This is how the hardware works.
885 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
886 being used by cygmon.
888 1999-11-11 Andrew Haley <aph@cygnus.com>
890 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
893 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
895 * mips.igen (MULT): Correct previous mis-applied patch.
897 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
899 * mips.igen (delayslot32): Handle sequence like
900 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
901 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
902 (MULT): Actually pass the third register...
904 1999-09-03 Mark Salter <msalter@cygnus.com>
906 * interp.c (sim_open): Added more memory aliases for additional
907 hardware being touched by cygmon on jmr3904 board.
909 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
911 * configure: Regenerated to track ../common/aclocal.m4 changes.
913 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
915 * interp.c (sim_store_register): Handle case where client - GDB -
916 specifies that a 4 byte register is 8 bytes in size.
917 (sim_fetch_register): Ditto.
919 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
921 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
922 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
923 (idt_monitor_base): Base address for IDT monitor traps.
924 (pmon_monitor_base): Ditto for PMON.
925 (lsipmon_monitor_base): Ditto for LSI PMON.
926 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
927 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
928 (sim_firmware_command): New function.
929 (mips_option_handler): Call it for OPTION_FIRMWARE.
930 (sim_open): Allocate memory for idt_monitor region. If "--board"
931 option was given, add no monitor by default. Add BREAK hooks only if
932 monitors are also there.
934 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
936 * interp.c (sim_monitor): Flush output before reading input.
938 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
940 * tconfig.in (SIM_HANDLES_LMA): Always define.
942 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
944 From Mark Salter <msalter@cygnus.com>:
945 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
946 (sim_open): Add setup for BSP board.
948 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
950 * mips.igen (MULT, MULTU): Add syntax for two operand version.
951 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
952 them as unimplemented.
954 1999-05-08 Felix Lee <flee@cygnus.com>
956 * configure: Regenerated to track ../common/aclocal.m4 changes.
958 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
960 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
962 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
964 * configure.in: Any mips64vr5*-*-* target should have
965 -DTARGET_ENABLE_FR=1.
966 (default_endian): Any mips64vr*el-*-* target should default to
968 * configure: Re-generate.
970 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
972 * mips.igen (ldl): Extend from _16_, not 32.
974 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
976 * interp.c (sim_store_register): Force registers written to by GDB
977 into an un-interpreted state.
979 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
981 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
982 CPU, start periodic background I/O polls.
983 (tx3904sio_poll): New function: periodic I/O poller.
985 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
987 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
989 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
991 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
994 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
996 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
997 (load_word): Call SIM_CORE_SIGNAL hook on error.
998 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
999 starting. For exception dispatching, pass PC instead of NULL_CIA.
1000 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1001 * sim-main.h (COP0_BADVADDR): Define.
1002 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1003 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1004 (_sim_cpu): Add exc_* fields to store register value snapshots.
1005 * mips.igen (*): Replace memory-related SignalException* calls
1006 with references to SIM_CORE_SIGNAL hook.
1008 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1010 * sim-main.c (*): Minor warning cleanups.
1012 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1014 * m16.igen (DADDIU5): Correct type-o.
1016 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1018 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1021 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1023 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1025 (interp.o): Add dependency on itable.h
1026 (oengine.c, gencode): Delete remaining references.
1027 (BUILT_SRC_FROM_GEN): Clean up.
1029 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1032 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1033 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1034 tmp-run-hack) : New.
1035 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1036 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1037 Drop the "64" qualifier to get the HACK generator working.
1038 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1039 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1040 qualifier to get the hack generator working.
1041 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1042 (DSLL): Use do_dsll.
1043 (DSLLV): Use do_dsllv.
1044 (DSRA): Use do_dsra.
1045 (DSRL): Use do_dsrl.
1046 (DSRLV): Use do_dsrlv.
1047 (BC1): Move *vr4100 to get the HACK generator working.
1048 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1049 get the HACK generator working.
1050 (MACC) Rename to get the HACK generator working.
1051 (DMACC,MACCS,DMACCS): Add the 64.
1053 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1055 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1056 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1058 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1060 * mips/interp.c (DEBUG): Cleanups.
1062 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1064 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1065 (tx3904sio_tickle): fflush after a stdout character output.
1067 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1069 * interp.c (sim_close): Uninstall modules.
1071 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073 * sim-main.h, interp.c (sim_monitor): Change to global
1076 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078 * configure.in (vr4100): Only include vr4100 instructions in
1080 * configure: Re-generate.
1081 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1083 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1085 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1086 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1089 * configure.in (sim_default_gen, sim_use_gen): Replace with
1091 (--enable-sim-igen): Delete config option. Always using IGEN.
1092 * configure: Re-generate.
1094 * Makefile.in (gencode): Kill, kill, kill.
1097 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1099 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1100 bit mips16 igen simulator.
1101 * configure: Re-generate.
1103 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1104 as part of vr4100 ISA.
1105 * vr.igen: Mark all instructions as 64 bit only.
1107 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1112 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1114 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1115 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1116 * configure: Re-generate.
1118 * m16.igen (BREAK): Define breakpoint instruction.
1119 (JALX32): Mark instruction as mips16 and not r3900.
1120 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1122 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1124 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1127 insn as a debug breakpoint.
1129 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1131 (PENDING_SCHED): Clean up trace statement.
1132 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1133 (PENDING_FILL): Delay write by only one cycle.
1134 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1136 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1138 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1140 (pending_tick): Move incrementing of index to FOR statement.
1141 (pending_tick): Only update PENDING_OUT after a write has occured.
1143 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1145 * configure: Re-generate.
1147 * interp.c (sim_engine_run OLD): Delete explicit call to
1148 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1150 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1152 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1153 interrupt level number to match changed SignalExceptionInterrupt
1156 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1158 * interp.c: #include "itable.h" if WITH_IGEN.
1159 (get_insn_name): New function.
1160 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1161 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1163 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1165 * configure: Rebuilt to inhale new common/aclocal.m4.
1167 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1169 * dv-tx3904sio.c: Include sim-assert.h.
1171 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1173 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1174 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1175 Reorganize target-specific sim-hardware checks.
1176 * configure: rebuilt.
1177 * interp.c (sim_open): For tx39 target boards, set
1178 OPERATING_ENVIRONMENT, add tx3904sio devices.
1179 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1180 ROM executables. Install dv-sockser into sim-modules list.
1182 * dv-tx3904irc.c: Compiler warning clean-up.
1183 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1184 frequent hw-trace messages.
1186 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1188 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1190 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1192 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1194 * vr.igen: New file.
1195 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1196 * mips.igen: Define vr4100 model. Include vr.igen.
1197 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1199 * mips.igen (check_mf_hilo): Correct check.
1201 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1203 * sim-main.h (interrupt_event): Add prototype.
1205 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1206 register_ptr, register_value.
1207 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1209 * sim-main.h (tracefh): Make extern.
1211 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1213 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1214 Reduce unnecessarily high timer event frequency.
1215 * dv-tx3904cpu.c: Ditto for interrupt event.
1217 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1219 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1221 (interrupt_event): Made non-static.
1223 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1224 interchange of configuration values for external vs. internal
1227 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1229 * mips.igen (BREAK): Moved code to here for
1230 simulator-reserved break instructions.
1231 * gencode.c (build_instruction): Ditto.
1232 * interp.c (signal_exception): Code moved from here. Non-
1233 reserved instructions now use exception vector, rather
1235 * sim-main.h: Moved magic constants to here.
1237 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1239 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1240 register upon non-zero interrupt event level, clear upon zero
1242 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1243 by passing zero event value.
1244 (*_io_{read,write}_buffer): Endianness fixes.
1245 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1246 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1248 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1249 serial I/O and timer module at base address 0xFFFF0000.
1251 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1253 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1256 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1258 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1260 * configure: Update.
1262 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1264 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1265 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1266 * configure.in: Include tx3904tmr in hw_device list.
1267 * configure: Rebuilt.
1268 * interp.c (sim_open): Instantiate three timer instances.
1269 Fix address typo of tx3904irc instance.
1271 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1273 * interp.c (signal_exception): SystemCall exception now uses
1274 the exception vector.
1276 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1278 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1281 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1285 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1289 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1290 sim-main.h. Declare a struct hw_descriptor instead of struct
1291 hw_device_descriptor.
1293 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1295 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1296 right bits and then re-align left hand bytes to correct byte
1297 lanes. Fix incorrect computation in do_store_left when loading
1298 bytes from second word.
1300 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1302 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1303 * interp.c (sim_open): Only create a device tree when HW is
1306 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1307 * interp.c (signal_exception): Ditto.
1309 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1311 * gencode.c: Mark BEGEZALL as LIKELY.
1313 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1316 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1318 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1320 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1321 modules. Recognize TX39 target with "mips*tx39" pattern.
1322 * configure: Rebuilt.
1323 * sim-main.h (*): Added many macros defining bits in
1324 TX39 control registers.
1325 (SignalInterrupt): Send actual PC instead of NULL.
1326 (SignalNMIReset): New exception type.
1327 * interp.c (board): New variable for future use to identify
1328 a particular board being simulated.
1329 (mips_option_handler,mips_options): Added "--board" option.
1330 (interrupt_event): Send actual PC.
1331 (sim_open): Make memory layout conditional on board setting.
1332 (signal_exception): Initial implementation of hardware interrupt
1333 handling. Accept another break instruction variant for simulator
1335 (decode_coproc): Implement RFE instruction for TX39.
1336 (mips.igen): Decode RFE instruction as such.
1337 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1338 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1339 bbegin to implement memory map.
1340 * dv-tx3904cpu.c: New file.
1341 * dv-tx3904irc.c: New file.
1343 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1345 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1347 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1349 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1350 with calls to check_div_hilo.
1352 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1354 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1355 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1356 Add special r3900 version of do_mult_hilo.
1357 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1358 with calls to check_mult_hilo.
1359 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1360 with calls to check_div_hilo.
1362 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1364 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1365 Document a replacement.
1367 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1369 * interp.c (sim_monitor): Make mon_printf work.
1371 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1373 * sim-main.h (INSN_NAME): New arg `cpu'.
1375 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1377 * configure: Regenerated to track ../common/aclocal.m4 changes.
1379 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1381 * configure: Regenerated to track ../common/aclocal.m4 changes.
1384 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1386 * acconfig.h: New file.
1387 * configure.in: Reverted change of Apr 24; use sinclude again.
1389 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1391 * configure: Regenerated to track ../common/aclocal.m4 changes.
1394 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1396 * configure.in: Don't call sinclude.
1398 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1400 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1402 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404 * mips.igen (ERET): Implement.
1406 * interp.c (decode_coproc): Return sign-extended EPC.
1408 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1410 * interp.c (signal_exception): Do not ignore Trap.
1411 (signal_exception): On TRAP, restart at exception address.
1412 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1413 (signal_exception): Update.
1414 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1415 so that TRAP instructions are caught.
1417 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1419 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1420 contains HI/LO access history.
1421 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1422 (HIACCESS, LOACCESS): Delete, replace with
1423 (HIHISTORY, LOHISTORY): New macros.
1424 (CHECKHILO): Delete all, moved to mips.igen
1426 * gencode.c (build_instruction): Do not generate checks for
1427 correct HI/LO register usage.
1429 * interp.c (old_engine_run): Delete checks for correct HI/LO
1432 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1433 check_mf_cycles): New functions.
1434 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1435 do_divu, domultx, do_mult, do_multu): Use.
1437 * tx.igen ("madd", "maddu"): Use.
1439 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1441 * mips.igen (DSRAV): Use function do_dsrav.
1442 (SRAV): Use new function do_srav.
1444 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1445 (B): Sign extend 11 bit immediate.
1446 (EXT-B*): Shift 16 bit immediate left by 1.
1447 (ADDIU*): Don't sign extend immediate value.
1449 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1451 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1453 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1456 * mips.igen (delayslot32, nullify_next_insn): New functions.
1457 (m16.igen): Always include.
1458 (do_*): Add more tracing.
1460 * m16.igen (delayslot16): Add NIA argument, could be called by a
1461 32 bit MIPS16 instruction.
1463 * interp.c (ifetch16): Move function from here.
1464 * sim-main.c (ifetch16): To here.
1466 * sim-main.c (ifetch16, ifetch32): Update to match current
1467 implementations of LH, LW.
1468 (signal_exception): Don't print out incorrect hex value of illegal
1471 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1473 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1476 * m16.igen: Implement MIPS16 instructions.
1478 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1479 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1480 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1481 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1482 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1483 bodies of corresponding code from 32 bit insn to these. Also used
1484 by MIPS16 versions of functions.
1486 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1487 (IMEM16): Drop NR argument from macro.
1489 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1491 * Makefile.in (SIM_OBJS): Add sim-main.o.
1493 * sim-main.h (address_translation, load_memory, store_memory,
1494 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1496 (pr_addr, pr_uword64): Declare.
1497 (sim-main.c): Include when H_REVEALS_MODULE_P.
1499 * interp.c (address_translation, load_memory, store_memory,
1500 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1502 * sim-main.c: To here. Fix compilation problems.
1504 * configure.in: Enable inlining.
1505 * configure: Re-config.
1507 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1509 * configure: Regenerated to track ../common/aclocal.m4 changes.
1511 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513 * mips.igen: Include tx.igen.
1514 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1515 * tx.igen: New file, contains MADD and MADDU.
1517 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1518 the hardwired constant `7'.
1519 (store_memory): Ditto.
1520 (LOADDRMASK): Move definition to sim-main.h.
1522 mips.igen (MTC0): Enable for r3900.
1525 mips.igen (do_load_byte): Delete.
1526 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1527 do_store_right): New functions.
1528 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1530 configure.in: Let the tx39 use igen again.
1533 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1536 not an address sized quantity. Return zero for cache sizes.
1538 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1540 * mips.igen (r3900): r3900 does not support 64 bit integer
1543 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1545 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1547 * configure : Rebuild.
1549 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551 * configure: Regenerated to track ../common/aclocal.m4 changes.
1553 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1557 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1559 * configure: Regenerated to track ../common/aclocal.m4 changes.
1560 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1562 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564 * configure: Regenerated to track ../common/aclocal.m4 changes.
1566 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1568 * interp.c (Max, Min): Comment out functions. Not yet used.
1570 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1572 * configure: Regenerated to track ../common/aclocal.m4 changes.
1574 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1576 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1577 configurable settings for stand-alone simulator.
1579 * configure.in: Added X11 search, just in case.
1581 * configure: Regenerated.
1583 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * interp.c (sim_write, sim_read, load_memory, store_memory):
1586 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1588 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1590 * sim-main.h (GETFCC): Return an unsigned value.
1592 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1594 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1595 (DADD): Result destination is RD not RT.
1597 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1599 * sim-main.h (HIACCESS, LOACCESS): Always define.
1601 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1603 * interp.c (sim_info): Delete.
1605 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1607 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1608 (mips_option_handler): New argument `cpu'.
1609 (sim_open): Update call to sim_add_option_table.
1611 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613 * mips.igen (CxC1): Add tracing.
1615 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1617 * sim-main.h (Max, Min): Declare.
1619 * interp.c (Max, Min): New functions.
1621 * mips.igen (BC1): Add tracing.
1623 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1625 * interp.c Added memory map for stack in vr4100
1627 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1629 * interp.c (load_memory): Add missing "break"'s.
1631 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633 * interp.c (sim_store_register, sim_fetch_register): Pass in
1634 length parameter. Return -1.
1636 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1638 * interp.c: Added hardware init hook, fixed warnings.
1640 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1644 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1646 * interp.c (ifetch16): New function.
1648 * sim-main.h (IMEM32): Rename IMEM.
1649 (IMEM16_IMMED): Define.
1651 (DELAY_SLOT): Update.
1653 * m16run.c (sim_engine_run): New file.
1655 * m16.igen: All instructions except LB.
1656 (LB): Call do_load_byte.
1657 * mips.igen (do_load_byte): New function.
1658 (LB): Call do_load_byte.
1660 * mips.igen: Move spec for insn bit size and high bit from here.
1661 * Makefile.in (tmp-igen, tmp-m16): To here.
1663 * m16.dc: New file, decode mips16 instructions.
1665 * Makefile.in (SIM_NO_ALL): Define.
1666 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1668 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1670 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1671 point unit to 32 bit registers.
1672 * configure: Re-generate.
1674 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure.in (sim_use_gen): Make IGEN the default simulator
1677 generator for generic 32 and 64 bit mips targets.
1678 * configure: Re-generate.
1680 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1682 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1685 * interp.c (sim_fetch_register, sim_store_register): Read/write
1686 FGR from correct location.
1687 (sim_open): Set size of FGR's according to
1688 WITH_TARGET_FLOATING_POINT_BITSIZE.
1690 * sim-main.h (FGR): Store floating point registers in a separate
1693 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1695 * configure: Regenerated to track ../common/aclocal.m4 changes.
1697 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1699 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1701 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1703 * interp.c (pending_tick): New function. Deliver pending writes.
1705 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1706 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1707 it can handle mixed sized quantites and single bits.
1709 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1711 * interp.c (oengine.h): Do not include when building with IGEN.
1712 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1713 (sim_info): Ditto for PROCESSOR_64BIT.
1714 (sim_monitor): Replace ut_reg with unsigned_word.
1715 (*): Ditto for t_reg.
1716 (LOADDRMASK): Define.
1717 (sim_open): Remove defunct check that host FP is IEEE compliant,
1718 using software to emulate floating point.
1719 (value_fpr, ...): Always compile, was conditional on HASFPU.
1721 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1723 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1726 * interp.c (SD, CPU): Define.
1727 (mips_option_handler): Set flags in each CPU.
1728 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1729 (sim_close): Do not clear STATE, deleted anyway.
1730 (sim_write, sim_read): Assume CPU zero's vm should be used for
1732 (sim_create_inferior): Set the PC for all processors.
1733 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1735 (mips16_entry): Pass correct nr of args to store_word, load_word.
1736 (ColdReset): Cold reset all cpu's.
1737 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1738 (sim_monitor, load_memory, store_memory, signal_exception): Use
1739 `CPU' instead of STATE_CPU.
1742 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1745 * sim-main.h (signal_exception): Add sim_cpu arg.
1746 (SignalException*): Pass both SD and CPU to signal_exception.
1747 * interp.c (signal_exception): Update.
1749 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1751 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1752 address_translation): Ditto
1753 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1755 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1757 * configure: Regenerated to track ../common/aclocal.m4 changes.
1759 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1761 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1763 * mips.igen (model): Map processor names onto BFD name.
1765 * sim-main.h (CPU_CIA): Delete.
1766 (SET_CIA, GET_CIA): Define
1768 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1770 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1773 * configure.in (default_endian): Configure a big-endian simulator
1775 * configure: Re-generate.
1777 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1779 * configure: Regenerated to track ../common/aclocal.m4 changes.
1781 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1783 * interp.c (sim_monitor): Handle Densan monitor outbyte
1784 and inbyte functions.
1786 1997-12-29 Felix Lee <flee@cygnus.com>
1788 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1790 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1792 * Makefile.in (tmp-igen): Arrange for $zero to always be
1793 reset to zero after every instruction.
1795 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797 * configure: Regenerated to track ../common/aclocal.m4 changes.
1800 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1802 * mips.igen (MSUB): Fix to work like MADD.
1803 * gencode.c (MSUB): Similarly.
1805 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1807 * configure: Regenerated to track ../common/aclocal.m4 changes.
1809 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1811 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1813 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815 * sim-main.h (sim-fpu.h): Include.
1817 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1818 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1819 using host independant sim_fpu module.
1821 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (signal_exception): Report internal errors with SIGABRT
1826 * sim-main.h (C0_CONFIG): New register.
1827 (signal.h): No longer include.
1829 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1831 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1833 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1835 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1837 * mips.igen: Tag vr5000 instructions.
1838 (ANDI): Was missing mipsIV model, fix assembler syntax.
1839 (do_c_cond_fmt): New function.
1840 (C.cond.fmt): Handle mips I-III which do not support CC field
1842 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1843 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1845 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1846 vr5000 which saves LO in a GPR separatly.
1848 * configure.in (enable-sim-igen): For vr5000, select vr5000
1849 specific instructions.
1850 * configure: Re-generate.
1852 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1856 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1857 fmt_uninterpreted_64 bit cases to switch. Convert to
1860 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1862 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1863 as specified in IV3.2 spec.
1864 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1866 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1868 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1869 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1870 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1871 PENDING_FILL versions of instructions. Simplify.
1873 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1875 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1877 (MTHI, MFHI): Disable code checking HI-LO.
1879 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1881 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1883 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885 * gencode.c (build_mips16_operands): Replace IPC with cia.
1887 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1888 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1890 (UndefinedResult): Replace function with macro/function
1892 (sim_engine_run): Don't save PC in IPC.
1894 * sim-main.h (IPC): Delete.
1897 * interp.c (signal_exception, store_word, load_word,
1898 address_translation, load_memory, store_memory, cache_op,
1899 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1900 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1901 current instruction address - cia - argument.
1902 (sim_read, sim_write): Call address_translation directly.
1903 (sim_engine_run): Rename variable vaddr to cia.
1904 (signal_exception): Pass cia to sim_monitor
1906 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1907 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1908 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1910 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1911 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1914 * interp.c (signal_exception): Pass restart address to
1917 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1918 idecode.o): Add dependency.
1920 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1922 (DELAY_SLOT): Update NIA not PC with branch address.
1923 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1925 * mips.igen: Use CIA not PC in branch calculations.
1926 (illegal): Call SignalException.
1927 (BEQ, ADDIU): Fix assembler.
1929 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1931 * m16.igen (JALX): Was missing.
1933 * configure.in (enable-sim-igen): New configuration option.
1934 * configure: Re-generate.
1936 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1938 * interp.c (load_memory, store_memory): Delete parameter RAW.
1939 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1940 bypassing {load,store}_memory.
1942 * sim-main.h (ByteSwapMem): Delete definition.
1944 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1946 * interp.c (sim_do_command, sim_commands): Delete mips specific
1947 commands. Handled by module sim-options.
1949 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1950 (WITH_MODULO_MEMORY): Define.
1952 * interp.c (sim_info): Delete code printing memory size.
1954 * interp.c (mips_size): Nee sim_size, delete function.
1956 (monitor, monitor_base, monitor_size): Delete global variables.
1957 (sim_open, sim_close): Delete code creating monitor and other
1958 memory regions. Use sim-memopts module, via sim_do_commandf, to
1959 manage memory regions.
1960 (load_memory, store_memory): Use sim-core for memory model.
1962 * interp.c (address_translation): Delete all memory map code
1963 except line forcing 32 bit addresses.
1965 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1967 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1970 * interp.c (logfh, logfile): Delete globals.
1971 (sim_open, sim_close): Delete code opening & closing log file.
1972 (mips_option_handler): Delete -l and -n options.
1973 (OPTION mips_options): Ditto.
1975 * interp.c (OPTION mips_options): Rename option trace to dinero.
1976 (mips_option_handler): Update.
1978 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980 * interp.c (fetch_str): New function.
1981 (sim_monitor): Rewrite using sim_read & sim_write.
1982 (sim_open): Check magic number.
1983 (sim_open): Write monitor vectors into memory using sim_write.
1984 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1985 (sim_read, sim_write): Simplify - transfer data one byte at a
1987 (load_memory, store_memory): Clarify meaning of parameter RAW.
1989 * sim-main.h (isHOST): Defete definition.
1990 (isTARGET): Mark as depreciated.
1991 (address_translation): Delete parameter HOST.
1993 * interp.c (address_translation): Delete parameter HOST.
1995 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1999 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2000 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2002 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004 * mips.igen: Add model filter field to records.
2006 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2008 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2010 interp.c (sim_engine_run): Do not compile function sim_engine_run
2011 when WITH_IGEN == 1.
2013 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2014 target architecture.
2016 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2017 igen. Replace with configuration variables sim_igen_flags /
2020 * m16.igen: New file. Copy mips16 insns here.
2021 * mips.igen: From here.
2023 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2025 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2027 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2029 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2031 * gencode.c (build_instruction): Follow sim_write's lead in using
2032 BigEndianMem instead of !ByteSwapMem.
2034 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036 * configure.in (sim_gen): Dependent on target, select type of
2037 generator. Always select old style generator.
2039 configure: Re-generate.
2041 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2043 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2044 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2045 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2046 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2047 SIM_@sim_gen@_*, set by autoconf.
2049 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2053 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2054 CURRENT_FLOATING_POINT instead.
2056 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2057 (address_translation): Raise exception InstructionFetch when
2058 translation fails and isINSTRUCTION.
2060 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2061 sim_engine_run): Change type of of vaddr and paddr to
2063 (address_translation, prefetch, load_memory, store_memory,
2064 cache_op): Change type of vAddr and pAddr to address_word.
2066 * gencode.c (build_instruction): Change type of vaddr and paddr to
2069 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2072 macro to obtain result of ALU op.
2074 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076 * interp.c (sim_info): Call profile_print.
2078 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2082 * sim-main.h (WITH_PROFILE): Do not define, defined in
2083 common/sim-config.h. Use sim-profile module.
2084 (simPROFILE): Delete defintion.
2086 * interp.c (PROFILE): Delete definition.
2087 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2088 (sim_close): Delete code writing profile histogram.
2089 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2091 (sim_engine_run): Delete code profiling the PC.
2093 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2095 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2097 * interp.c (sim_monitor): Make register pointers of type
2100 * sim-main.h: Make registers of type unsigned_word not
2103 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2105 * interp.c (sync_operation): Rename from SyncOperation, make
2106 global, add SD argument.
2107 (prefetch): Rename from Prefetch, make global, add SD argument.
2108 (decode_coproc): Make global.
2110 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2112 * gencode.c (build_instruction): Generate DecodeCoproc not
2113 decode_coproc calls.
2115 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2116 (SizeFGR): Move to sim-main.h
2117 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2118 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2119 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2121 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2122 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2123 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2124 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2125 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2126 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2128 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2130 (sim-alu.h): Include.
2131 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2132 (sim_cia): Typedef to instruction_address.
2134 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2136 * Makefile.in (interp.o): Rename generated file engine.c to
2141 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2145 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147 * gencode.c (build_instruction): For "FPSQRT", output correct
2148 number of arguments to Recip.
2150 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2152 * Makefile.in (interp.o): Depends on sim-main.h
2154 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2156 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2157 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2158 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2159 STATE, DSSTATE): Define
2160 (GPR, FGRIDX, ..): Define.
2162 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2163 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2164 (GPR, FGRIDX, ...): Delete macros.
2166 * interp.c: Update names to match defines from sim-main.h
2168 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170 * interp.c (sim_monitor): Add SD argument.
2171 (sim_warning): Delete. Replace calls with calls to
2173 (sim_error): Delete. Replace calls with sim_io_error.
2174 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2175 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2176 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2178 (mips_size): Rename from sim_size. Add SD argument.
2180 * interp.c (simulator): Delete global variable.
2181 (callback): Delete global variable.
2182 (mips_option_handler, sim_open, sim_write, sim_read,
2183 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2184 sim_size,sim_monitor): Use sim_io_* not callback->*.
2185 (sim_open): ZALLOC simulator struct.
2186 (PROFILE): Do not define.
2188 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2190 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2191 support.h with corresponding code.
2193 * sim-main.h (word64, uword64), support.h: Move definition to
2195 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2198 * Makefile.in: Update dependencies
2199 * interp.c: Do not include.
2201 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2203 * interp.c (address_translation, load_memory, store_memory,
2204 cache_op): Rename to from AddressTranslation et.al., make global,
2207 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2210 * interp.c (SignalException): Rename to signal_exception, make
2213 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2215 * sim-main.h (SignalException, SignalExceptionInterrupt,
2216 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2217 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2218 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2221 * interp.c, support.h: Use.
2223 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2225 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2226 to value_fpr / store_fpr. Add SD argument.
2227 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2228 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2230 * sim-main.h (ValueFPR, StoreFPR): Define.
2232 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234 * interp.c (sim_engine_run): Check consistency between configure
2235 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2238 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2239 (mips_fpu): Configure WITH_FLOATING_POINT.
2240 (mips_endian): Configure WITH_TARGET_ENDIAN.
2241 * configure: Update.
2243 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2245 * configure: Regenerated to track ../common/aclocal.m4 changes.
2247 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2249 * configure: Regenerated.
2251 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2253 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2255 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257 * gencode.c (print_igen_insn_models): Assume certain architectures
2258 include all mips* instructions.
2259 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2262 * Makefile.in (tmp.igen): Add target. Generate igen input from
2265 * gencode.c (FEATURE_IGEN): Define.
2266 (main): Add --igen option. Generate output in igen format.
2267 (process_instructions): Format output according to igen option.
2268 (print_igen_insn_format): New function.
2269 (print_igen_insn_models): New function.
2270 (process_instructions): Only issue warnings and ignore
2271 instructions when no FEATURE_IGEN.
2273 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2275 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2278 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2280 * configure: Regenerated to track ../common/aclocal.m4 changes.
2282 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2284 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2285 SIM_RESERVED_BITS): Delete, moved to common.
2286 (SIM_EXTRA_CFLAGS): Update.
2288 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2290 * configure.in: Configure non-strict memory alignment.
2291 * configure: Regenerated to track ../common/aclocal.m4 changes.
2293 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295 * configure: Regenerated to track ../common/aclocal.m4 changes.
2297 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2299 * gencode.c (SDBBP,DERET): Added (3900) insns.
2300 (RFE): Turn on for 3900.
2301 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2302 (dsstate): Made global.
2303 (SUBTARGET_R3900): Added.
2304 (CANCELDELAYSLOT): New.
2305 (SignalException): Ignore SystemCall rather than ignore and
2306 terminate. Add DebugBreakPoint handling.
2307 (decode_coproc): New insns RFE, DERET; and new registers Debug
2308 and DEPC protected by SUBTARGET_R3900.
2309 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2311 * Makefile.in,configure.in: Add mips subtarget option.
2312 * configure: Update.
2314 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2316 * gencode.c: Add r3900 (tx39).
2319 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2321 * gencode.c (build_instruction): Don't need to subtract 4 for
2324 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2326 * interp.c: Correct some HASFPU problems.
2328 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2330 * configure: Regenerated to track ../common/aclocal.m4 changes.
2332 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2334 * interp.c (mips_options): Fix samples option short form, should
2337 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2339 * interp.c (sim_info): Enable info code. Was just returning.
2341 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2343 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2346 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2348 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2350 (build_instruction): Ditto for LL.
2352 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2354 * configure: Regenerated to track ../common/aclocal.m4 changes.
2356 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358 * configure: Regenerated to track ../common/aclocal.m4 changes.
2361 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363 * interp.c (sim_open): Add call to sim_analyze_program, update
2366 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2368 * interp.c (sim_kill): Delete.
2369 (sim_create_inferior): Add ABFD argument. Set PC from same.
2370 (sim_load): Move code initializing trap handlers from here.
2371 (sim_open): To here.
2372 (sim_load): Delete, use sim-hload.c.
2374 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2376 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2378 * configure: Regenerated to track ../common/aclocal.m4 changes.
2381 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2383 * interp.c (sim_open): Add ABFD argument.
2384 (sim_load): Move call to sim_config from here.
2385 (sim_open): To here. Check return status.
2387 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2389 * gencode.c (build_instruction): Two arg MADD should
2390 not assign result to $0.
2392 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2394 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2395 * sim/mips/configure.in: Regenerate.
2397 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2399 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2400 signed8, unsigned8 et.al. types.
2402 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2403 hosts when selecting subreg.
2405 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2407 * interp.c (sim_engine_run): Reset the ZERO register to zero
2408 regardless of FEATURE_WARN_ZERO.
2409 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2411 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2413 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2414 (SignalException): For BreakPoints ignore any mode bits and just
2416 (SignalException): Always set the CAUSE register.
2418 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2420 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2421 exception has been taken.
2423 * interp.c: Implement the ERET and mt/f sr instructions.
2425 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2427 * interp.c (SignalException): Don't bother restarting an
2430 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2432 * interp.c (SignalException): Really take an interrupt.
2433 (interrupt_event): Only deliver interrupts when enabled.
2435 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437 * interp.c (sim_info): Only print info when verbose.
2438 (sim_info) Use sim_io_printf for output.
2440 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2445 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2447 * interp.c (sim_do_command): Check for common commands if a
2448 simulator specific command fails.
2450 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2452 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2453 and simBE when DEBUG is defined.
2455 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2457 * interp.c (interrupt_event): New function. Pass exception event
2458 onto exception handler.
2460 * configure.in: Check for stdlib.h.
2461 * configure: Regenerate.
2463 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2464 variable declaration.
2465 (build_instruction): Initialize memval1.
2466 (build_instruction): Add UNUSED attribute to byte, bigend,
2468 (build_operands): Ditto.
2470 * interp.c: Fix GCC warnings.
2471 (sim_get_quit_code): Delete.
2473 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2474 * Makefile.in: Ditto.
2475 * configure: Re-generate.
2477 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2479 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2481 * interp.c (mips_option_handler): New function parse argumes using
2483 (myname): Replace with STATE_MY_NAME.
2484 (sim_open): Delete check for host endianness - performed by
2486 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2487 (sim_open): Move much of the initialization from here.
2488 (sim_load): To here. After the image has been loaded and
2490 (sim_open): Move ColdReset from here.
2491 (sim_create_inferior): To here.
2492 (sim_open): Make FP check less dependant on host endianness.
2494 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2496 * interp.c (sim_set_callbacks): Delete.
2498 * interp.c (membank, membank_base, membank_size): Replace with
2499 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2500 (sim_open): Remove call to callback->init. gdb/run do this.
2504 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2506 * interp.c (big_endian_p): Delete, replaced by
2507 current_target_byte_order.
2509 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2511 * interp.c (host_read_long, host_read_word, host_swap_word,
2512 host_swap_long): Delete. Using common sim-endian.
2513 (sim_fetch_register, sim_store_register): Use H2T.
2514 (pipeline_ticks): Delete. Handled by sim-events.
2516 (sim_engine_run): Update.
2518 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2520 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2522 (SignalException): To here. Signal using sim_engine_halt.
2523 (sim_stop_reason): Delete, moved to common.
2525 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2527 * interp.c (sim_open): Add callback argument.
2528 (sim_set_callbacks): Delete SIM_DESC argument.
2531 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2533 * Makefile.in (SIM_OBJS): Add common modules.
2535 * interp.c (sim_set_callbacks): Also set SD callback.
2536 (set_endianness, xfer_*, swap_*): Delete.
2537 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2538 Change to functions using sim-endian macros.
2539 (control_c, sim_stop): Delete, use common version.
2540 (simulate): Convert into.
2541 (sim_engine_run): This function.
2542 (sim_resume): Delete.
2544 * interp.c (simulation): New variable - the simulator object.
2545 (sim_kind): Delete global - merged into simulation.
2546 (sim_load): Cleanup. Move PC assignment from here.
2547 (sim_create_inferior): To here.
2549 * sim-main.h: New file.
2550 * interp.c (sim-main.h): Include.
2552 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2554 * configure: Regenerated to track ../common/aclocal.m4 changes.
2556 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2558 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2560 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2562 * gencode.c (build_instruction): DIV instructions: check
2563 for division by zero and integer overflow before using
2564 host's division operation.
2566 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2568 * Makefile.in (SIM_OBJS): Add sim-load.o.
2569 * interp.c: #include bfd.h.
2570 (target_byte_order): Delete.
2571 (sim_kind, myname, big_endian_p): New static locals.
2572 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2573 after argument parsing. Recognize -E arg, set endianness accordingly.
2574 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2575 load file into simulator. Set PC from bfd.
2576 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2577 (set_endianness): Use big_endian_p instead of target_byte_order.
2579 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * interp.c (sim_size): Delete prototype - conflicts with
2582 definition in remote-sim.h. Correct definition.
2584 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2586 * configure: Regenerated to track ../common/aclocal.m4 changes.
2589 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2591 * interp.c (sim_open): New arg `kind'.
2593 * configure: Regenerated to track ../common/aclocal.m4 changes.
2595 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2597 * configure: Regenerated to track ../common/aclocal.m4 changes.
2599 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2601 * interp.c (sim_open): Set optind to 0 before calling getopt.
2603 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2605 * configure: Regenerated to track ../common/aclocal.m4 changes.
2607 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2609 * interp.c : Replace uses of pr_addr with pr_uword64
2610 where the bit length is always 64 independent of SIM_ADDR.
2611 (pr_uword64) : added.
2613 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2615 * configure: Re-generate.
2617 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2619 * configure: Regenerate to track ../common/aclocal.m4 changes.
2621 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2623 * interp.c (sim_open): New SIM_DESC result. Argument is now
2625 (other sim_*): New SIM_DESC argument.
2627 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2629 * interp.c: Fix printing of addresses for non-64-bit targets.
2630 (pr_addr): Add function to print address based on size.
2632 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2634 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2636 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2638 * gencode.c (build_mips16_operands): Correct computation of base
2639 address for extended PC relative instruction.
2641 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2643 * interp.c (mips16_entry): Add support for floating point cases.
2644 (SignalException): Pass floating point cases to mips16_entry.
2645 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2647 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2649 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2650 and then set the state to fmt_uninterpreted.
2651 (COP_SW): Temporarily set the state to fmt_word while calling
2654 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2656 * gencode.c (build_instruction): The high order may be set in the
2657 comparison flags at any ISA level, not just ISA 4.
2659 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2661 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2662 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2663 * configure.in: sinclude ../common/aclocal.m4.
2664 * configure: Regenerated.
2666 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2668 * configure: Rebuild after change to aclocal.m4.
2670 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2672 * configure configure.in Makefile.in: Update to new configure
2673 scheme which is more compatible with WinGDB builds.
2674 * configure.in: Improve comment on how to run autoconf.
2675 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2676 * Makefile.in: Use autoconf substitution to install common
2679 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2681 * gencode.c (build_instruction): Use BigEndianCPU instead of
2684 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2686 * interp.c (sim_monitor): Make output to stdout visible in
2687 wingdb's I/O log window.
2689 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2691 * support.h: Undo previous change to SIGTRAP
2694 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2696 * interp.c (store_word, load_word): New static functions.
2697 (mips16_entry): New static function.
2698 (SignalException): Look for mips16 entry and exit instructions.
2699 (simulate): Use the correct index when setting fpr_state after
2700 doing a pending move.
2702 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2704 * interp.c: Fix byte-swapping code throughout to work on
2705 both little- and big-endian hosts.
2707 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2709 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2710 with gdb/config/i386/xm-windows.h.
2712 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2714 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2715 that messes up arithmetic shifts.
2717 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2719 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2720 SIGTRAP and SIGQUIT for _WIN32.
2722 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2724 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2725 force a 64 bit multiplication.
2726 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2727 destination register is 0, since that is the default mips16 nop
2730 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2732 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2733 (build_endian_shift): Don't check proc64.
2734 (build_instruction): Always set memval to uword64. Cast op2 to
2735 uword64 when shifting it left in memory instructions. Always use
2736 the same code for stores--don't special case proc64.
2738 * gencode.c (build_mips16_operands): Fix base PC value for PC
2740 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2742 * interp.c (simJALDELAYSLOT): Define.
2743 (JALDELAYSLOT): Define.
2744 (INDELAYSLOT, INJALDELAYSLOT): Define.
2745 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2747 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2749 * interp.c (sim_open): add flush_cache as a PMON routine
2750 (sim_monitor): handle flush_cache by ignoring it
2752 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2754 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2756 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2757 (BigEndianMem): Rename to ByteSwapMem and change sense.
2758 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2759 BigEndianMem references to !ByteSwapMem.
2760 (set_endianness): New function, with prototype.
2761 (sim_open): Call set_endianness.
2762 (sim_info): Use simBE instead of BigEndianMem.
2763 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2764 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2765 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2766 ifdefs, keeping the prototype declaration.
2767 (swap_word): Rewrite correctly.
2768 (ColdReset): Delete references to CONFIG. Delete endianness related
2769 code; moved to set_endianness.
2771 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2773 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2774 * interp.c (CHECKHILO): Define away.
2775 (simSIGINT): New macro.
2776 (membank_size): Increase from 1MB to 2MB.
2777 (control_c): New function.
2778 (sim_resume): Rename parameter signal to signal_number. Add local
2779 variable prev. Call signal before and after simulate.
2780 (sim_stop_reason): Add simSIGINT support.
2781 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2783 (sim_warning): Delete call to SignalException. Do call printf_filtered
2785 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2786 a call to sim_warning.
2788 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2790 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2791 16 bit instructions.
2793 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2795 Add support for mips16 (16 bit MIPS implementation):
2796 * gencode.c (inst_type): Add mips16 instruction encoding types.
2797 (GETDATASIZEINSN): Define.
2798 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2799 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2801 (MIPS16_DECODE): New table, for mips16 instructions.
2802 (bitmap_val): New static function.
2803 (struct mips16_op): Define.
2804 (mips16_op_table): New table, for mips16 operands.
2805 (build_mips16_operands): New static function.
2806 (process_instructions): If PC is odd, decode a mips16
2807 instruction. Break out instruction handling into new
2808 build_instruction function.
2809 (build_instruction): New static function, broken out of
2810 process_instructions. Check modifiers rather than flags for SHIFT
2811 bit count and m[ft]{hi,lo} direction.
2812 (usage): Pass program name to fprintf.
2813 (main): Remove unused variable this_option_optind. Change
2814 ``*loptarg++'' to ``loptarg++''.
2815 (my_strtoul): Parenthesize && within ||.
2816 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2817 (simulate): If PC is odd, fetch a 16 bit instruction, and
2818 increment PC by 2 rather than 4.
2819 * configure.in: Add case for mips16*-*-*.
2820 * configure: Rebuild.
2822 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2824 * interp.c: Allow -t to enable tracing in standalone simulator.
2825 Fix garbage output in trace file and error messages.
2827 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2829 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2830 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2831 * configure.in: Simplify using macros in ../common/aclocal.m4.
2832 * configure: Regenerated.
2833 * tconfig.in: New file.
2835 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2837 * interp.c: Fix bugs in 64-bit port.
2838 Use ansi function declarations for msvc compiler.
2839 Initialize and test file pointer in trace code.
2840 Prevent duplicate definition of LAST_EMED_REGNUM.
2842 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2844 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2846 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2848 * interp.c (SignalException): Check for explicit terminating
2850 * gencode.c: Pass instruction value through SignalException()
2851 calls for Trap, Breakpoint and Syscall.
2853 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2855 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2856 only used on those hosts that provide it.
2857 * configure.in: Add sqrt() to list of functions to be checked for.
2858 * config.in: Re-generated.
2859 * configure: Re-generated.
2861 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2863 * gencode.c (process_instructions): Call build_endian_shift when
2864 expanding STORE RIGHT, to fix swr.
2865 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2866 clear the high bits.
2867 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2868 Fix float to int conversions to produce signed values.
2870 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2872 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2873 (process_instructions): Correct handling of nor instruction.
2874 Correct shift count for 32 bit shift instructions. Correct sign
2875 extension for arithmetic shifts to not shift the number of bits in
2876 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2877 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2879 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2880 It's OK to have a mult follow a mult. What's not OK is to have a
2881 mult follow an mfhi.
2882 (Convert): Comment out incorrect rounding code.
2884 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2886 * interp.c (sim_monitor): Improved monitor printf
2887 simulation. Tidied up simulator warnings, and added "--log" option
2888 for directing warning message output.
2889 * gencode.c: Use sim_warning() rather than WARNING macro.
2891 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2893 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2894 getopt1.o, rather than on gencode.c. Link objects together.
2895 Don't link against -liberty.
2896 (gencode.o, getopt.o, getopt1.o): New targets.
2897 * gencode.c: Include <ctype.h> and "ansidecl.h".
2898 (AND): Undefine after including "ansidecl.h".
2899 (ULONG_MAX): Define if not defined.
2900 (OP_*): Don't define macros; now defined in opcode/mips.h.
2901 (main): Call my_strtoul rather than strtoul.
2902 (my_strtoul): New static function.
2904 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2906 * gencode.c (process_instructions): Generate word64 and uword64
2907 instead of `long long' and `unsigned long long' data types.
2908 * interp.c: #include sysdep.h to get signals, and define default
2910 * (Convert): Work around for Visual-C++ compiler bug with type
2912 * support.h: Make things compile under Visual-C++ by using
2913 __int64 instead of `long long'. Change many refs to long long
2914 into word64/uword64 typedefs.
2916 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2918 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2919 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2921 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2922 (AC_PROG_INSTALL): Added.
2923 (AC_PROG_CC): Moved to before configure.host call.
2924 * configure: Rebuilt.
2926 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2928 * configure.in: Define @SIMCONF@ depending on mips target.
2929 * configure: Rebuild.
2930 * Makefile.in (run): Add @SIMCONF@ to control simulator
2932 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2933 * interp.c: Remove some debugging, provide more detailed error
2934 messages, update memory accesses to use LOADDRMASK.
2936 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2938 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2939 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2941 * configure: Rebuild.
2942 * config.in: New file, generated by autoheader.
2943 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2944 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2945 HAVE_ANINT and HAVE_AINT, as appropriate.
2946 * Makefile.in (run): Use @LIBS@ rather than -lm.
2947 (interp.o): Depend upon config.h.
2948 (Makefile): Just rebuild Makefile.
2949 (clean): Remove stamp-h.
2950 (mostlyclean): Make the same as clean, not as distclean.
2951 (config.h, stamp-h): New targets.
2953 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2955 * interp.c (ColdReset): Fix boolean test. Make all simulator
2958 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2960 * interp.c (xfer_direct_word, xfer_direct_long,
2961 swap_direct_word, swap_direct_long, xfer_big_word,
2962 xfer_big_long, xfer_little_word, xfer_little_long,
2963 swap_word,swap_long): Added.
2964 * interp.c (ColdReset): Provide function indirection to
2965 host<->simulated_target transfer routines.
2966 * interp.c (sim_store_register, sim_fetch_register): Updated to
2967 make use of indirected transfer routines.
2969 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2971 * gencode.c (process_instructions): Ensure FP ABS instruction
2973 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2974 system call support.
2976 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2978 * interp.c (sim_do_command): Complain if callback structure not
2981 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2983 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2984 support for Sun hosts.
2985 * Makefile.in (gencode): Ensure the host compiler and libraries
2986 used for cross-hosted build.
2988 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2990 * interp.c, gencode.c: Some more (TODO) tidying.
2992 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2994 * gencode.c, interp.c: Replaced explicit long long references with
2995 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2996 * support.h (SET64LO, SET64HI): Macros added.
2998 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3000 * configure: Regenerate with autoconf 2.7.
3002 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3004 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3005 * support.h: Remove superfluous "1" from #if.
3006 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3008 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3010 * interp.c (StoreFPR): Control UndefinedResult() call on
3011 WARN_RESULT manifest.
3013 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3015 * gencode.c: Tidied instruction decoding, and added FP instruction
3018 * interp.c: Added dineroIII, and BSD profiling support. Also
3019 run-time FP handling.
3021 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3023 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3024 gencode.c, interp.c, support.h: created.