1 //Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
2 // Spec Reference: dsp32shift lshift: mix
5 .include "testutils.inc"
15 // lshift : positive data, count (+)=left (half reg)
20 R4.H = LSHIFT R0.H BY R1.L;
21 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22 R5.H = LSHIFT R2.H BY R3.L;
23 R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24 R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25 R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
26 CHECKREG r4, 0x00020002;
27 CHECKREG r5, 0x00080008;
28 CHECKREG r6, 0x00020002;
29 CHECKREG r7, 0x00080008;
31 // lshift : (full reg)
34 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35 R7 = LSHIFT R2 BY R3.L;
36 CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
37 CHECKREG r7, 0x00200020;
42 A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
43 R5 = A0.w; /* r5 = 0x00080008 */
44 CHECKREG r5, 0x00080008;
48 R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */
50 R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
51 CHECKREG r6, 0x60000006;
52 CHECKREG r7, 0xc000000c;
55 // lshift : count (-)=right (half reg)
60 R4.H = LSHIFT R0.H BY R1.L;
61 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
62 R5.H = LSHIFT R2.H BY R3.L;
63 R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
64 R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
65 R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
66 CHECKREG r4, 0x08000800;
67 CHECKREG r5, 0x04000400;
68 CHECKREG r6, 0x08000800;
69 CHECKREG r7, 0x04000400;
71 // lshift : (full reg)
74 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */
75 R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */
76 CHECKREG r6, 0x02000200;
77 CHECKREG r7, 0x01000100;
80 // lshift : NEGATIVE data, count (+)=left (half reg)
85 R4.H = LSHIFT R0.H BY R1.L;
86 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */
87 R5.H = LSHIFT R2.H BY R3.L;
88 R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
89 CHECKREG r4, 0x801e001e;
90 CHECKREG r5, 0x803c803c;
96 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
97 R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
98 CHECKREG r6, 0x80fe00f0;
99 CHECKREG r7, 0x81fc01e0;
101 imm32 r0, 0xf80fe00f;
102 imm32 r2, 0xfc0fe00f;
103 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
104 R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
105 CHECKREG r6, 0x80fe00f0;
106 CHECKREG r7, 0x81fc01e0;
110 // lshift : NEGATIVE data, count (-)=right (half reg) Working ok
111 imm32 r0, 0x80f080f0;
113 imm32 r2, 0x80f080f0;
115 R4.H = LSHIFT R0.H BY R1.L;
116 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */
117 R5.H = LSHIFT R2.H BY R3.L;
118 R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */
119 CHECKREG r4, 0x40784078;
120 CHECKREG r5, 0x203c203c;
121 R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */
122 R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */
123 CHECKREG r6, 0x40784078;
124 CHECKREG r7, 0x203c203c;
126 // lshift : (full reg)
129 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */
130 R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */
131 CHECKREG r6, 0x101e101e;
132 CHECKREG r7, 0x080f080f;