sim/testsuite/sim/bfin/c_interr_disable.S

   1 //Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
   2 // Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 //
  11 // Include Files
  12 //
  13
  14 include(std.inc)
  15 include(selfcheck.inc)
  16
  17 // Defines
  18
  19 #ifndef TCNTL
  20 #define TCNTL            0xFFE03000
  21 #endif
  22 #ifndef TPERIOD
  23 #define TPERIOD          0xFFE03004
  24 #endif
  25 #ifndef TSCALE
  26 #define TSCALE           0xFFE03008
  27 #endif
  28 #ifndef TCOUNT
  29 #define TCOUNT           0xFFE0300c
  30 #endif
  31 #ifndef EVT
  32 #define EVT              0xFFE02000
  33 #endif
  34 #ifndef EVT15
  35 #define EVT15            0xFFE0203c
  36 #endif
  37 #ifndef EVT_OVERRIDE
  38 #define EVT_OVERRIDE     0xFFE02100
  39 #endif
  40 #ifndef ITABLE
  41 #define ITABLE           0x000FF000
  42 #endif
  43 #ifndef PROGRAM_STACK
  44 #define PROGRAM_STACK    0x000FF100
  45 #endif
  46 #ifndef STACKSIZE
  47 #define STACKSIZE        0x00000300
  48 #endif
  49
  50 // Boot code
  51
  52  BOOT :
  53 INIT_R_REGS(0);                             // Initialize Dregs
  54 INIT_P_REGS(0);                             // Initialize Pregs
  55
  56      // CHECK_INIT(p5,   0x00BFFFFC);
  57      // CHECK_INIT(p5,   0xE0000000);
  58 include(symtable.inc)
  59 CHECK_INIT_DEF(p5);
  60
  61
  62 LD32(sp, 0x000FF200);
  63 LD32(p0, EVT);              // Setup Event Vectors and Handlers
  64
  65 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  66         [ P0 ++ ] = R0;
  67
  68 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  69         [ P0 ++ ] = R0;
  70
  71 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  72         [ P0 ++ ] = R0;
  73
  74 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  75         [ P0 ++ ] = R0;
  76
  77         [ P0 ++ ] = R0;                // IVT4 not used
  78
  79 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  80         [ P0 ++ ] = R0;
  81
  82 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  83         [ P0 ++ ] = R0;
  84
  85 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  86         [ P0 ++ ] = R0;
  87
  88 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  89         [ P0 ++ ] = R0;
  90
  91 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  92         [ P0 ++ ] = R0;
  93
  94 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  95         [ P0 ++ ] = R0;
  96
  97 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  98         [ P0 ++ ] = R0;
  99
 100 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
 101         [ P0 ++ ] = R0;
 102
 103 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
 104         [ P0 ++ ] = R0;
 105
 106 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
 107         [ P0 ++ ] = R0;
 108
 109 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
 110         [ P0 ++ ] = R0;
 111
 112 LD32(p0, EVT_OVERRIDE);
 113         R0 = 0;
 114         [ P0 ++ ] = R0;
 115         R0 = -1;     // Change this to mask interrupts (*)
 116         [ P0 ] = R0;   // IMASK
 117
 118 LD32_LABEL(p1, START);
 119
 120 LD32(p0, EVT15);
 121         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 122 CSYNC;
 123 RAISE 15;    // after we RTI, INT 15 should be taken
 124
 125 LD32_LABEL(r7, START);
 126 RETI = r7;
 127 NOP;        // Workaround for Bug 217
 128 RTI;
 129 NOP;
 130 NOP;
 131 NOP;
 132 NOP;
 133 NOP;
 134 NOP;
 135 NOP;
 136 NOP;
 137 DUMMY:
 138           NOP;
 139 NOP;
 140 NOP;
 141 NOP;
 142 NOP;
 143 NOP;
 144 NOP;
 145 NOP;
 146 NOP;
 147 NOP;
 148
 149 //.code 0x200
 150  START :
 151         R7 = 0x0;
 152         R6 = 0x1;
 153         [ -- SP ] = RETI;        // Enable Nested Interrupts
 154
 155 CLI R1;                                           // stop interrupt
 156 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
 157 WR_MMR(TPERIOD, 0x00000050, p0, r0);
 158 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 159 WR_MMR(TSCALE,  0x00000000, p0, r0);
 160 CSYNC;
 161         // Read the contents of the Timer
 162
 163 RD_MMR(TPERIOD, p0, r2);
 164 CHECKREG(r2,    0x00000050);
 165
 166 //      RD_MMR(TCOUNT, p0, r3);
 167 //      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
 168
 169
 170 WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
 171 CSYNC;
 172
 173 RD_MMR(TPERIOD, p0, r4);
 174 CHECKREG(r4,    0x00000050);
 175
 176 //      RD_MMR(TCNTL, p0, r5);
 177 //      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
 178
 179 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 180 CSYNC;
 181 NOP;
 182 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
 183 WR_MMR(TPERIOD, 0x00000015, p0, r0);
 184 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 185 WR_MMR(TSCALE,  0x00000002, p0, r0);
 186 WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
 187 CSYNC;
 188 NOP;
 189 NOP;
 190 NOP;
 191 NOP;
 192 NOP;
 193 NOP;
 194 NOP;
 195 NOP;
 196 NOP;
 197 NOP;
 198 NOP;
 199 NOP;
 200 NOP;
 201 NOP;
 202 NOP;
 203 JUMP.S label4;
 204         R4.L = 0x1111;                             // Will be killed
 205         R4.H = 0x1111;                             // Will be killed
 206 NOP;
 207 NOP;
 208 NOP;
 209 label5: R5.H = 0x7777;
 210         R5.L = 0x7888;
 211 JUMP.S label6;
 212         R5.L = 0x1111;                             // Will be killed
 213         R5.H = 0x1111;                             // Will be killed
 214 NOP;
 215 NOP;
 216 NOP;
 217 NOP;
 218 NOP;
 219 NOP;
 220 label4: R4.H = 0x5555;
 221         R4.L = 0x6666;
 222 NOP;
 223 JUMP.S label5;
 224         R5.L = 0x2222;     // Will be killed
 225         R5.H = 0x2222;     // Will be killed
 226 NOP;
 227 NOP;
 228 NOP;
 229 NOP;
 230 label6: R3.H = 0x7999;
 231         R3.L = 0x7aaa;
 232 NOP;
 233 NOP;
 234 NOP;
 235 NOP;
 236 NOP;
 237 NOP;
 238 NOP;
 239                                                     // With auto reload
 240         // Read the contents of the Timer
 241
 242 RD_MMR(TPERIOD, p0, r2);
 243 CHECKREG(r2,    0x00000015);
 244
 245 //      RD_MMR(TCNTL , p0, r3);
 246 //      CHECKREG(r3,    0x0000000F);
 247 CHECKREG(r7,    0x00000000);    // no interrupt being serviced
 248 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 249 CSYNC;
 250 STI R1;
 251 NOP;
 252 CHECKREG(r7,    0x00000001);    // interrupt being serviced
 253 //      WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 254 //      csync;
 255 NOP;
 256
 257
 258
 259
 260
 261 dbg_pass;        // Call Endtest Macro
 262
 263
 264
 265 //*********************************************************************
 266 //
 267 // Handlers for Events
 268 //
 269
 270 EHANDLE:            // Emulation Handler 0
 271 RTE;
 272
 273 RHANDLE:            // Reset Handler 1
 274 RTI;
 275
 276 NHANDLE:            // NMI Handler 2
 277 RTN;
 278
 279 XHANDLE:            // Exception Handler 3
 280 RTX;
 281
 282 HWHANDLE:           // HW Error Handler 5
 283 RTI;
 284
 285 THANDLE:            // Timer Handler 6
 286         R7 = R7 + R6;
 287 RTI;
 288
 289 I7HANDLE:           // IVG 7 Handler
 290 RTI;
 291
 292 I8HANDLE:           // IVG 8 Handler
 293 RTI;
 294
 295 I9HANDLE:           // IVG 9 Handler
 296 RTI;
 297
 298 I10HANDLE:          // IVG 10 Handler
 299 RTI;
 300
 301 I11HANDLE:          // IVG 11 Handler
 302 RTI;
 303
 304 I12HANDLE:          // IVG 12 Handler
 305 RTI;
 306
 307 I13HANDLE:          // IVG 13 Handler
 308 RTI;
 309
 310 I14HANDLE:          // IVG 14 Handler
 311 RTI;
 312
 313 I15HANDLE:          // IVG 15 Handler
 314         R5 = RETI;
 315         P0 = R5;
 316 JUMP ( P0 );
 317 RTI;
 318
 319 .section MEM_DATA_ADDR_1,"aw"
 320
 321 .space (STACKSIZE);
 322 STACK:
 323 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug