1 //Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp
2 // Spec Reference: c_ldstpmod store dreg lo & hi
5 .include "testutils.inc"
31 I1 = P3; P3 = I0; I3 = SP; SP = I2;
32 loadsym p5, DATA_ADDR_5, 0x00;
35 W [ P5 ++ P1 ] = R0.L;
36 W [ P5 ++ P1 ] = R1.L;
37 W [ P5 ++ P2 ] = R2.L;
38 W [ P5 ++ P3 ] = R3.L;
39 W [ P5 ++ P4 ] = R4.L;
40 W [ P5 ++ SP ] = R5.L;
41 W [ P5 ++ FP ] = R6.L;
49 I1 = P3; P3 = I0; I3 = SP; SP = I2;
50 loadsym p5, DATA_ADDR_5, 0x00;
53 R6.L = W [ P5 ++ P1 ];
54 R5.L = W [ P5 ++ P1 ];
55 R4.L = W [ P5 ++ P2 ];
56 R3.L = W [ P5 ++ P3 ];
57 R2.L = W [ P5 ++ P4 ];
58 R0.L = W [ P5 ++ SP ];
59 R1.L = W [ P5 ++ FP ];
60 CHECKREG r0, 0x600FA005;
61 CHECKREG r1, 0x700EB006;
62 CHECKREG r2, 0x800D9004;
63 CHECKREG r3, 0x900C8003;
64 CHECKREG r4, 0xA00B7002;
65 CHECKREG r5, 0xB00A6001;
66 CHECKREG r6, 0xC0095000;
83 I1 = P3; P3 = I0; I3 = SP; SP = I2;
84 loadsym p1, DATA_ADDR_1, 0x00;
86 W [ P1 ++ P5 ] = R0.H;
87 W [ P1 ++ P2 ] = R1.H;
88 W [ P1 ++ P2 ] = R2.H;
89 W [ P1 ++ P3 ] = R3.H;
90 W [ P1 ++ P4 ] = R4.H;
91 W [ P1 ++ SP ] = R5.H;
92 W [ P1 ++ FP ] = R6.H;
99 I1 = P3; P3 = I0; I3 = SP; SP = I2;
100 loadsym p1, DATA_ADDR_1, 0x00;
102 R6.H = W [ P1 ++ P5 ];
103 R5.H = W [ P1 ++ P2 ];
104 R4.H = W [ P1 ++ P2 ];
105 R3.H = W [ P1 ++ P3 ];
106 R2.H = W [ P1 ++ P4 ];
107 R0.H = W [ P1 ++ SP ];
108 R1.H = W [ P1 ++ FP ];
109 CHECKREG r0, 0x204E50A0;
110 CHECKREG r1, 0x701960A1;
111 CHECKREG r2, 0x501B70A2;
112 CHECKREG r3, 0x402C80A3;
113 CHECKREG r4, 0x300390A4;
114 CHECKREG r5, 0x204EA0A5;
115 CHECKREG r6, 0x105FB0A6;
118 imm32 r0, 0x10bf50b0;
119 imm32 r1, 0x20be60b1;
120 imm32 r2, 0x30bd70b2;
121 imm32 r3, 0x40bc80b3;
122 imm32 r4, 0x55bb90b4;
123 imm32 r5, 0x60baa0b5;
124 imm32 r6, 0x70b9b0b6;
125 imm32 r7, 0x80b8c0b7;
132 I1 = P3; P3 = I0; I3 = SP; SP = I2;
133 loadsym p2, DATA_ADDR_2, 0x02;
135 W [ P2 ++ P5 ] = R0.L;
136 W [ P2 ++ P1 ] = R0.H;
137 W [ P2 ++ P2 ] = R2.H;
138 W [ P2 ++ P3 ] = R2.H;
139 W [ P2 ++ P4 ] = R4.L;
140 W [ P2 ++ SP ] = R4.H;
141 W [ P2 ++ FP ] = R6.L;
148 I1 = P3; P3 = I0; I3 = SP; SP = I2;
149 loadsym p2, DATA_ADDR_2, 0x02;
151 R3.L = W [ P2 ++ P5 ];
152 R3.H = W [ P2 ++ P1 ];
153 R0.L = W [ P2 ++ P2 ];
154 R0.H = W [ P2 ++ P3 ];
155 R2.L = W [ P2 ++ P4 ];
156 R2.H = W [ P2 ++ SP ];
157 R6.L = W [ P2 ++ FP ];
158 CHECKREG r0, 0x30BD30BD;
159 CHECKREG r1, 0x20BE60B1;
160 CHECKREG r2, 0x2E2F2A2B;
161 CHECKREG r3, 0x10BF50B0;
162 CHECKREG r4, 0x55BB90B4;
163 CHECKREG r5, 0x60BAA0B5;
164 CHECKREG r6, 0x70B955BB;
167 imm32 r0, 0x10cf50c0;
168 imm32 r1, 0x20ce60c1;
169 imm32 r2, 0x30c370c2;
170 imm32 r3, 0x40cc80c3;
171 imm32 r4, 0x50cb90c4;
172 imm32 r5, 0x60caa0c5;
173 imm32 r6, 0x70c9b0c6;
174 imm32 r7, 0xd0c8c0c7;
181 I1 = P3; P3 = I0; I3 = SP; SP = I2;
182 loadsym i1, DATA_ADDR_3, 0x02;
184 W [ P3 ++ P5 ] = R1.H;
185 W [ P3 ++ P1 ] = R1.L;
186 W [ P3 ++ P2 ] = R3.L;
187 W [ P3 ++ P2 ] = R3.H;
188 W [ P3 ++ P4 ] = R5.H;
189 W [ P3 ++ SP ] = R6.H;
190 W [ P3 ++ FP ] = R6.L;
197 I1 = P3; P3 = I0; I3 = SP; SP = I2;
198 loadsym i1, DATA_ADDR_3, 0x02;
200 R6.L = W [ P3 ++ P5 ];
201 R6.H = W [ P3 ++ P1 ];
202 R4.H = W [ P3 ++ P2 ];
203 R4.L = W [ P3 ++ P2 ];
204 R5.L = W [ P3 ++ P4 ];
205 R5.H = W [ P3 ++ SP ];
206 R1.L = W [ P3 ++ FP ];
207 CHECKREG r0, 0x10CF50C0;
208 CHECKREG r1, 0x20CEB0C6;
209 CHECKREG r2, 0x30C370C2;
210 CHECKREG r3, 0x40CC80C3;
211 CHECKREG r4, 0x80C340CC;
212 CHECKREG r5, 0x70C960CA;
213 CHECKREG r6, 0x60C120CE;
216 imm32 r0, 0x60df50d0;
217 imm32 r1, 0x70de60d1;
218 imm32 r2, 0x80dd70d2;
219 imm32 r3, 0x90dc80d3;
220 imm32 r4, 0xa0db90d4;
221 imm32 r5, 0xb0daa0d5;
222 imm32 r6, 0xc0d9b0d6;
223 imm32 r7, 0xd0d8c0d7;
230 I1 = P3; P3 = I0; I3 = SP; SP = I2;
231 loadsym p4, DATA_ADDR_4, 0x02;
233 W [ P4 ++ P5 ] = R0.L;
234 W [ P4 ++ P1 ] = R1.H;
235 W [ P4 ++ P2 ] = R2.L;
236 W [ P4 ++ P3 ] = R3.H;
237 W [ P4 ++ P3 ] = R4.H;
238 W [ P4 ++ SP ] = R5.L;
239 W [ P4 ++ FP ] = R6.H;
246 I1 = P3; P3 = I0; I3 = SP; SP = I2;
247 loadsym p4, DATA_ADDR_4, 0x02;
249 R5.L = W [ P4 ++ P5 ];
250 R6.L = W [ P4 ++ P1 ];
251 R0.H = W [ P4 ++ P2 ];
252 R1.L = W [ P4 ++ P3 ];
253 R2.L = W [ P4 ++ P3 ];
254 R3.H = W [ P4 ++ SP ];
255 R4.H = W [ P4 ++ FP ];
256 CHECKREG r0, 0x70D250D0;
257 CHECKREG r1, 0x70DE90DC;
258 CHECKREG r2, 0x80DDA0DB;
259 CHECKREG r3, 0xA0D580D3;
260 CHECKREG r4, 0xC0D990D4;
261 CHECKREG r5, 0xB0DA50D0;
262 CHECKREG r6, 0xC0D970DE;
265 imm32 r0, 0x1e5f50e0;
266 imm32 r1, 0x2e4e60e1;
267 imm32 r2, 0x3e0370e2;
268 imm32 r3, 0x4e2c80e3;
269 imm32 r4, 0x5e1b90e4;
270 imm32 r5, 0x6e0aa0e5;
271 imm32 r6, 0x7e19b0e6;
272 imm32 r7, 0xde28c0e7;
279 I1 = P3; P3 = I0; I3 = SP; SP = I2;
280 loadsym i3, DATA_ADDR_6, 0x02;
282 W [ SP ++ P5 ] = R0.H;
283 W [ SP ++ P1 ] = R1.H;
284 W [ SP ++ P2 ] = R2.L;
285 W [ SP ++ P3 ] = R3.L;
286 W [ SP ++ P4 ] = R4.H;
287 W [ SP ++ FP ] = R5.H;
288 W [ SP ++ FP ] = R6.L;
295 I1 = P3; P3 = I0; I3 = SP; SP = I2;
296 loadsym i3, DATA_ADDR_6, 0x02;
298 R6.H = W [ SP ++ P5 ];
299 R5.H = W [ SP ++ P1 ];
300 R4.H = W [ SP ++ P2 ];
301 R3.H = W [ SP ++ P3 ];
302 R3.L = W [ SP ++ P4 ];
303 R0.L = W [ SP ++ FP ];
304 R1.L = W [ SP ++ FP ];
305 CHECKREG r0, 0x1E5FB0E6;
306 CHECKREG r1, 0x2E4E1617;
307 CHECKREG r2, 0x3E0370E2;
308 CHECKREG r3, 0x80E35E1B;
309 CHECKREG r4, 0x70E290E4;
310 CHECKREG r5, 0x2E4EA0E5;
311 CHECKREG r6, 0x1E5FB0E6;
314 imm32 r0, 0x10ff50f0;
315 imm32 r1, 0x20fe60f1;
316 imm32 r2, 0x30fd70f2;
317 imm32 r3, 0x40fc80f3;
318 imm32 r4, 0x55fb90f4;
319 imm32 r5, 0x60faa0f5;
320 imm32 r6, 0x70f9b0f6;
321 imm32 r7, 0x80f8c0f7;
328 I1 = P3; P3 = I0; I3 = SP; SP = I2;
329 loadsym fp, DATA_ADDR_7, 0x02;
331 W [ FP ++ P5 ] = R0.L;
332 W [ FP ++ P1 ] = R1.H;
333 W [ FP ++ P2 ] = R2.H;
334 W [ FP ++ P3 ] = R3.H;
335 W [ FP ++ P4 ] = R4.L;
336 W [ FP ++ SP ] = R5.L;
337 W [ FP ++ SP ] = R6.L;
344 I1 = P3; P3 = I0; I3 = SP; SP = I2;
345 loadsym fp, DATA_ADDR_7, 0x02;
347 R3.L = W [ FP ++ P5 ];
348 R4.L = W [ FP ++ P1 ];
349 R0.H = W [ FP ++ P2 ];
350 R1.H = W [ FP ++ P3 ];
351 R2.L = W [ FP ++ P4 ];
352 R5.H = W [ FP ++ SP ];
353 R6.H = W [ FP ++ SP ];
354 CHECKREG r0, 0x30FD50F0;
355 CHECKREG r1, 0x40FC60F1;
356 CHECKREG r2, 0x30FD90F4;
357 CHECKREG r3, 0x40FC50F0;
358 CHECKREG r4, 0x55FB20FE;
359 CHECKREG r5, 0xA0F5A0F5;
360 CHECKREG r6, 0x9091B0F6;
365 // Pre-load memory with known data
366 // More data is defined than will actually be used