sim/testsuite/sim/bfin/c_regmv_pr_dr.s

   1 //Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp
   2 // Spec Reference: regmv preg to dreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11
  12 imm32 r0, 0x00000001;
  13 imm32 r1, 0x00020003;
  14 imm32 r2, 0x00040005;
  15 imm32 r3, 0x00060007;
  16 imm32 r4, 0x00080009;
  17 imm32 r5, 0x000a000b;
  18 imm32 r6, 0x000c000d;
  19 imm32 r7, 0x000e000f;
  20
  21 //imm32 p0, 0x00000001;
  22 imm32 p1, 0x10082001;
  23 imm32 p2, 0x10092002;
  24 imm32 p3, 0x100a2003;
  25 imm32 p4, 0x100b2004;
  26 imm32 p5, 0x100c2005;
  27 imm32 sp, 0x100d2006;
  28 imm32 fp, 0x100e2007;
  29
  30 //--------- Preg to dreg : Rx <= Px ------
  31
  32
  33 R0 = P1;
  34 R1 = P1;
  35 R2 = P1;
  36 R3 = P1;
  37 R4 = P1;
  38 R5 = P1;
  39 R6 = P1;
  40 R7 = P1;
  41 CHECKREG r1, 0x10082001;
  42 CHECKREG r2, 0x10082001;
  43 CHECKREG r3, 0x10082001;
  44 CHECKREG r4, 0x10082001;
  45 CHECKREG r5, 0x10082001;
  46 CHECKREG r6, 0x10082001;
  47 CHECKREG r7, 0x10082001;
  48
  49 R0 = P2;
  50 R1 = P2;
  51 R2 = P2;
  52 R3 = P2;
  53 R4 = P2;
  54 R5 = P2;
  55 R6 = P2;
  56 R7 = P2;
  57 CHECKREG r0, 0x10092002;
  58 CHECKREG r1, 0x10092002;
  59 CHECKREG r2, 0x10092002;
  60 CHECKREG r3, 0x10092002;
  61 CHECKREG r4, 0x10092002;
  62 CHECKREG r5, 0x10092002;
  63 CHECKREG r6, 0x10092002;
  64 CHECKREG r7, 0x10092002;
  65
  66 R0 = P3;
  67 R1 = P3;
  68 R2 = P3;
  69 R3 = P3;
  70 R4 = P3;
  71 R5 = P3;
  72 R6 = P3;
  73 R7 = P3;
  74 CHECKREG r1, 0x100a2003;
  75 CHECKREG r2, 0x100a2003;
  76 CHECKREG r3, 0x100a2003;
  77 CHECKREG r4, 0x100a2003;
  78 CHECKREG r5, 0x100a2003;
  79 CHECKREG r6, 0x100a2003;
  80 CHECKREG r7, 0x100a2003;
  81
  82 R0 = P4;
  83 R1 = P4;
  84 R2 = P4;
  85 R3 = P4;
  86 R4 = P4;
  87 R5 = P4;
  88 R6 = P4;
  89 R7 = P4;
  90 CHECKREG r0, 0x100b2004;
  91 CHECKREG r1, 0x100b2004;
  92 CHECKREG r2, 0x100b2004;
  93 CHECKREG r3, 0x100b2004;
  94 CHECKREG r4, 0x100b2004;
  95 CHECKREG r5, 0x100b2004;
  96 CHECKREG r6, 0x100b2004;
  97 CHECKREG r7, 0x100b2004;
  98
  99 R1 = P5;
 100 R2 = P5;
 101 R3 = P5;
 102 R4 = P5;
 103 R5 = P5;
 104 R6 = P5;
 105 R7 = P5;
 106 CHECKREG r1, 0x100c2005;
 107 CHECKREG r2, 0x100c2005;
 108 CHECKREG r3, 0x100c2005;
 109 CHECKREG r4, 0x100c2005;
 110 CHECKREG r5, 0x100c2005;
 111 CHECKREG r6, 0x100c2005;
 112 CHECKREG r7, 0x100c2005;
 113
 114 R0 = SP;
 115 R1 = SP;
 116 R2 = SP;
 117 R3 = SP;
 118 R4 = SP;
 119 R5 = SP;
 120 R6 = SP;
 121 R7 = SP;
 122 CHECKREG r0, 0x100d2006;
 123 CHECKREG r1, 0x100d2006;
 124 CHECKREG r2, 0x100d2006;
 125 CHECKREG r3, 0x100d2006;
 126 CHECKREG r4, 0x100d2006;
 127 CHECKREG r5, 0x100d2006;
 128 CHECKREG r6, 0x100d2006;
 129 CHECKREG r7, 0x100d2006;
 130
 131 R0 = FP;
 132 R1 = FP;
 133 R2 = FP;
 134 R3 = FP;
 135 R4 = FP;
 136 R5 = FP;
 137 R6 = FP;
 138 R7 = FP;
 139 CHECKREG r1, 0x100e2007;
 140 CHECKREG r2, 0x100e2007;
 141 CHECKREG r3, 0x100e2007;
 142 CHECKREG r4, 0x100e2007;
 143 CHECKREG r5, 0x100e2007;
 144 CHECKREG r6, 0x100e2007;
 145 CHECKREG r7, 0x100e2007;
 146
 147 pass