simpleperf/generate_event_type_table.py

   1 #!/usr/bin/python
   2 #
   3 # Copyright (C) 2015 The Android Open Source Project
   4 #
   5 # Licensed under the Apache License, Version 2.0 (the "License");
   6 # you may not use this file except in compliance with the License.
   7 # You may obtain a copy of the License at
   8 #
   9 #      http://www.apache.org/licenses/LICENSE-2.0
  10 #
  11 # Unless required by applicable law or agreed to in writing, software
  12 # distributed under the License is distributed on an "AS IS" BASIS,
  13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14 # See the License for the specific language governing permissions and
  15 # limitations under the License.
  16 #
  17
  18
  19 def gen_event_type_entry_str(event_type_name, event_type, event_config, description='',
  20                              limited_arch=''):
  21   """
  22   return string as below:
  23   EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch)
  24   """
  25   return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % (
  26             event_type_name, event_type, event_config, description, limited_arch)
  27
  28 def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description):
  29   return gen_event_type_entry_str(event_type_name, event_type, event_config, description,
  30                                   "arm")
  31
  32
  33 def gen_hardware_events():
  34   hardware_configs = ["cpu-cycles",
  35                       "instructions",
  36                       "cache-references",
  37                       "cache-misses",
  38                       "branch-instructions",
  39                       "branch-misses",
  40                       "bus-cycles",
  41                       "stalled-cycles-frontend",
  42                       "stalled-cycles-backend",
  43                       ]
  44   generated_str = ""
  45   for config in hardware_configs:
  46     event_type_name = config
  47     event_config = "PERF_COUNT_HW_" + config.replace('-', '_').upper()
  48
  49     generated_str += gen_event_type_entry_str(
  50         event_type_name, "PERF_TYPE_HARDWARE", event_config)
  51
  52   return generated_str
  53
  54
  55 def gen_software_events():
  56   software_configs = ["cpu-clock",
  57                       "task-clock",
  58                       "page-faults",
  59                       "context-switches",
  60                       "cpu-migrations",
  61                       ["minor-faults", "PERF_COUNT_SW_PAGE_FAULTS_MIN"],
  62                       ["major-faults", "PERF_COUNT_SW_PAGE_FAULTS_MAJ"],
  63                       "alignment-faults",
  64                       "emulation-faults",
  65                       ]
  66   generated_str = ""
  67   for config in software_configs:
  68     if isinstance(config, list):
  69       event_type_name = config[0]
  70       event_config = config[1]
  71     else:
  72       event_type_name = config
  73       event_config = "PERF_COUNT_SW_" + config.replace('-', '_').upper()
  74
  75     generated_str += gen_event_type_entry_str(
  76         event_type_name, "PERF_TYPE_SOFTWARE", event_config)
  77
  78   return generated_str
  79
  80
  81 def gen_hw_cache_events():
  82   hw_cache_types = [["L1-dcache", "PERF_COUNT_HW_CACHE_L1D"],
  83                     ["L1-icache", "PERF_COUNT_HW_CACHE_L1I"],
  84                     ["LLC", "PERF_COUNT_HW_CACHE_LL"],
  85                     ["dTLB", "PERF_COUNT_HW_CACHE_DTLB"],
  86                     ["iTLB", "PERF_COUNT_HW_CACHE_ITLB"],
  87                     ["branch", "PERF_COUNT_HW_CACHE_BPU"],
  88                     ["node", "PERF_COUNT_HW_CACHE_NODE"],
  89                     ]
  90   hw_cache_ops = [["loads", "load", "PERF_COUNT_HW_CACHE_OP_READ"],
  91                   ["stores", "store", "PERF_COUNT_HW_CACHE_OP_WRITE"],
  92                   ["prefetches", "prefetch",
  93                    "PERF_COUNT_HW_CACHE_OP_PREFETCH"],
  94                   ]
  95   hw_cache_op_results = [["accesses", "PERF_COUNT_HW_CACHE_RESULT_ACCESS"],
  96                          ["misses", "PERF_COUNT_HW_CACHE_RESULT_MISS"],
  97                          ]
  98   generated_str = ""
  99   for (type_name, type_config) in hw_cache_types:
 100     for (op_name_access, op_name_miss, op_config) in hw_cache_ops:
 101       for (result_name, result_config) in hw_cache_op_results:
 102         if result_name == "accesses":
 103           event_type_name = type_name + '-' + op_name_access
 104         else:
 105           event_type_name = type_name + '-' + \
 106               op_name_miss + '-' + result_name
 107         event_config = "((%s) | (%s << 8) | (%s << 16))" % (
 108             type_config, op_config, result_config)
 109         generated_str += gen_event_type_entry_str(
 110             event_type_name, "PERF_TYPE_HW_CACHE", event_config)
 111
 112   return generated_str
 113
 114 def gen_user_space_events():
 115   generated_str = gen_event_type_entry_str("inplace-sampler",
 116                                            "SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS",
 117                                            "SIMPLEPERF_CONFIG_INPLACE_SAMPLER")
 118   return generated_str
 119
 120 def gen_arm_raw_events():
 121   # Refer to "Table D5-7 PMU event numbers" in ARMv8 specification.
 122   raw_types = [
 123                [0x00, "sw-incr", "software increment"],
 124                [0x01, "l1-icache-refill", "level 1 instruction cache refill"],
 125                [0x02, "l1-itlb-refill", "level 1 instruction TLB refill"],
 126                [0x03, "l1-dcache-refill", "level 1 data cache refill"],
 127                [0x04, "l1-dcache", "level 1 data cache access"],
 128                [0x05, "l1-dtlb-refill", "level 1 data TLB refill"],
 129                [0x06, "load-retired", "load (instruction architecturally executed)"],
 130                [0x07, "store-retired", "store (instruction architecturally executed)"],
 131                [0x08, "instruction-retired", "instructions (instruction architecturally executed)"],
 132                [0x09, "exception-taken", "exception taken"],
 133                [0x0a, "exception-return", "exception return (instruction architecturally executed)"],
 134                [0x0b, "cid-write-retired", "write to CONTEXIDR (instruction architecturally executed)"],
 135                [0x0c, "pc-write-retired", "software change of the PC (instruction architecturally executed)"],
 136                [0x0d, "br-immed-retired", "immediate branch (instruction architecturally executed)"],
 137                [0x0e, "br-return-retired", "procedure return (instruction architecturally executed)"],
 138                [0x0f, "unaligned-ldst-retired", "unaligned load or store (instruction architecturally executed)"],
 139                [0x10, "br-mis-pred", "mispredicted or not predicted branch speculatively executed"],
 140                [0x11, "cpu-cycles", "cpu cycles"],
 141                [0x12, "br-pred", "predictable branch speculatively executed"],
 142                [0x13, "mem-access", "data memory access"],
 143                [0x14, "l1-icache", "level 1 instruction cache access"],
 144                [0x15, "l1-dcache-wb", "level 1 data cache write-back"],
 145                [0x16, "l2-dcache", "level 2 data cache access"],
 146                [0x17, "l2-dcache-refill", "level 2 data cache refill"],
 147                [0x18, "l2-dcache-wb", "level 2 data cache write-back"],
 148                [0x19, "bus-access", "bus access"],
 149                [0x1a, "memory-error", "local memory error"],
 150                [0x1b, "inst-spec", "operation speculatively executed"],
 151                [0x1c, "ttbr-write-retired", "write to TTBR (instruction architecturally executed)"],
 152                [0x1d, "bus-cycles", "bus cycle"],
 153                # [0x1e, "chain", ""], // Not useful in user space.
 154                [0x1f, "l1-dcache-allocate", "level 1 data cache allocation without refill"],
 155                [0x20, "l2-dcache-allocate", "level 2 data cache allocation without refill"],
 156                [0x21, "br-retired", "branch (instruction architecturally executed)"],
 157                [0x22, "br-mis-pred-retired", "mispredicted branch (instruction architecturally executed)"],
 158                [0x23, "stall-frontend", "no operation issued due to the frontend"],
 159                [0x24, "stall-backend", "no operation issued due to the backend"],
 160                [0x25, "l1-dtlb", "level 1 data or unified TLB access"],
 161                [0x26, "l1-itlb", "level 1 instruction TLB access"],
 162                [0x27, "l2-icache", "level 2 instruction cache access"],
 163                [0x28, "l2-icache-refill", "level 2 instruction cache refill"],
 164                [0x29, "l3-dcache-allocate", "level 3 data or unified cache allocation without refill"],
 165                [0x2a, "l3-dcache-refill", "level 3 data or unified cache refill"],
 166                [0x2b, "l3-dcache", "level 3 data or unified cache access"],
 167                [0x2c, "l3-dcache-wb", "level 3 data or unified cache write-back"],
 168                [0x2d, "l2-dtlb-refill", "level 2 data or unified TLB refill"],
 169                [0x2e, "l2-itlb-refill", "level 2 instruction TLB refill"],
 170                [0x2f, "l2-dtlb", "level 2 data or unified TLB access"],
 171                [0x30, "l2-itlb", "level 2 instruction TLB access"],
 172                ]
 173   generated_str = ""
 174   for item in raw_types:
 175     event_type = 'PERF_TYPE_RAW'
 176     event_type_name = "raw-" + item[1]
 177     event_config = '0x%x' % item[0]
 178     description = item[2]
 179     generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config,
 180                                               description)
 181   return generated_str
 182
 183
 184 def gen_events():
 185   generated_str = "// This file is auto-generated by generate-event_table.py.\n\n"
 186   generated_str += gen_hardware_events() + '\n'
 187   generated_str += gen_software_events() + '\n'
 188   generated_str += gen_hw_cache_events() + '\n'
 189   generated_str += gen_user_space_events() + '\n'
 190   generated_str += gen_arm_raw_events() + '\n'
 191   return generated_str
 192
 193 generated_str = gen_events()
 194 fh = open('event_type_table.h', 'w')
 195 fh.write(generated_str)
 196 fh.close()