1 DIRS=mem cpu ppu apu clock
2 MODULES=motonesfpga_common.vhd address_decoder.vhd motones_sim.vhd
4 TEST_MODULE = testbench_motones_sim.vhd
8 GHDL_OPTION=--ieee=synopsys -fexplicit --workdir=$(WORKDIR)
10 OBJS = $(addprefix $(WORKDIR)/,$(addsuffix .o,$(basename $(MODULES) $(TEST_MODULE))))
12 BIN=$(subst .vhd,, $(TEST_MODULE))
17 ghdl -a $(GHDL_OPTION) $(subst .o,.vhd, $(subst $(WORKDIR)/,, $@))
19 $(BIN): $(DIRS) $(OBJS)
20 for dir in $(DIRS); do \
21 make -C $(ROOT_DIR)/$$dir; \
23 ghdl -e $(GHDL_OPTION) $(BIN)
28 -rm $(subst .vhd,,$(WORKDIR)/e~$(TEST_MODULE)).o
32 for dir in $(DIRS); do \
33 make -C $(ROOT_DIR)/$$dir clean; \