2 use ieee.std_logic_1164.all;
4 -- this address decoder inserts dummy setup time on write.
5 entity address_decoder is
6 generic (abus_size : integer := 16; dbus_size : integer := 8);
7 port ( phi2 : in std_logic; --dropping edge syncronized clock.
8 mem_clk : in std_logic;
9 R_nW : in std_logic; -- active high on read / active low on write.
10 addr : in std_logic_vector (abus_size - 1 downto 0);
11 d_io : in std_logic_vector (dbus_size - 1 downto 0);
12 rom_ce_n : out std_logic;
13 ram_ce_n : out std_logic;
14 ppu_ce_n : out std_logic;
15 apu_ce_n : out std_logic
21 -- * 0x0000 - 0x07FF RAM
22 -- * 0x0800 - 0x1FFF mirror RAM
23 -- * 0x2000 - 0x2007 I/O PPU
24 -- * 0x4000 - 0x401F I/O APU
25 -- * 0x6000 - 0x7FFF battery backup ram
26 -- * 0x8000 - 0xFFFF PRG-ROM
29 architecture rtl of address_decoder is
34 ce_n, oe_n, we_n : in std_logic;
35 sync_ce_n : out std_logic
39 signal ram_ce_n_in : std_logic;
40 signal r_n : std_logic;
44 rom_ce_n <= '0' when (addr(15) = '1' and R_nW = '1') else
48 when (addr(15) = '0' and addr(14) = '0' and addr(13) = '1') else
52 when (addr(15) = '0' and addr(14) = '1' and addr(13) = '0') else
56 ram_ctl_inst : ram_ctrl
57 port map (mem_clk, ram_ce_n_in, r_n, r_nw, ram_ce_n);
60 main_p : process (phi2, addr, d_io, R_nW)
62 -- ram range : 0 - 0x2000.
63 -- 0x2000 is 0010_0000_0000_0000
64 if ((addr(15) or addr(14) or addr(13)) = '0') then
65 --if (addr < "0010000000000000") then
68 --write timing slided by half clock.
69 ram_ce_n_in <= not phi2;
70 elsif (R_nW = '1') then
85 -----------------------------------------------------
86 -----------------------------------------------------
87 ---------- VRAM / CHR ROM Address Decoder -----------
88 -----------------------------------------------------
89 -----------------------------------------------------
92 use ieee.std_logic_1164.all;
94 entity v_address_decoder is
95 generic (abus_size : integer := 14; dbus_size : integer := 8);
96 port ( clk : in std_logic;
97 mem_clk : in std_logic;
101 v_addr : in std_logic_vector (13 downto 0);
102 v_data : in std_logic_vector (7 downto 0);
103 nt_v_mirror : in std_logic;
104 pt_ce_n : out std_logic;
105 nt0_ce_n : out std_logic;
106 nt1_ce_n : out std_logic
108 end v_address_decoder;
110 -- Address Size Description
111 -- $0000-$0FFF $1000 Pattern Table 0 [lower CHR bank]
112 -- $1000-$1FFF $1000 Pattern Table 1 [upper CHR bank]
113 -- $2000-$23FF $0400 Name Table #0
114 -- $2400-$27FF $0400 Name Table #1
115 -- $2800-$2BFF $0400 Name Table #2
116 -- $2C00-$2FFF $0400 Name Table #3
117 -- $3000-$3EFF $0F00 Mirrors of $2000-$2FFF
118 -- $3F00-$3F1F $0020 Palette RAM indexes [not RGB values]
119 -- $3F20-$3FFF $0080 Mirrors of $3F00-$3F1F
121 architecture rtl of v_address_decoder is
126 ce_n, oe_n, we_n : in std_logic;
127 sync_ce_n : out std_logic
131 signal nt0_ce_n_in : std_logic;
132 signal nt1_ce_n_in : std_logic;
136 pt_ce_n <= '0' when (v_addr(13) = '0' and rd_n = '0') else
139 nt0_ram_ctl : ram_ctrl
140 port map (mem_clk, nt0_ce_n_in, rd_n, wr_n, nt0_ce_n);
141 nt1_ram_ctl : ram_ctrl
142 port map (mem_clk, nt1_ce_n_in, rd_n, wr_n, nt1_ce_n);
145 main_p : process (clk, v_addr, v_data, wr_n)
147 if (v_addr(13) = '1') then
149 if ((v_addr(12) and v_addr(11) and v_addr(10)
150 and v_addr(9) and v_addr(8)) = '0') then
151 if (nt_v_mirror = '1') then
152 --bit 10 is the name table selector.
153 if (v_addr(10) = '0') then
154 --name table 0 enable.
159 elsif (rd_n = '0') then
166 --name table 1 enable.
171 elsif (rd_n = '0') then
180 --bit 11 is the name table selector.
181 if (v_addr(11) = '0') then
182 --name table 0 enable.
187 elsif (rd_n = '0') then
194 --name table 1 enable.
199 elsif (rd_n = '0') then
206 end if; --if (nt_v_mirror = '1') then
214 end if; --if (v_addr(13) = '1') then