simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sph_oe_n        : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             abs_pg_next_n   : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             stat_dec_oe_n   : out std_logic;
  43             stat_bus_oe_n   : out std_logic;
  44             stat_set_flg_n  : out std_logic;
  45             stat_flg        : out std_logic;
  46             stat_bus_all_n  : out std_logic;
  47             stat_bus_nz_n   : out std_logic;
  48             stat_alu_we_n   : out std_logic;
  49             r_nw            : out std_logic
  50             ;---for parameter check purpose!!!
  51             check_bit     : out std_logic_vector(1 to 5)
  52         );
  53 end decoder;
  54
  55 architecture rtl of decoder is
  56
  57 procedure d_print(msg : string) is
  58 use std.textio.all;
  59 use ieee.std_logic_textio.all;
  60 variable out_l : line;
  61 begin
  62     write(out_l, msg);
  63     writeline(output, out_l);
  64 end  procedure;
  65
  66 ---ival : 0x0000 - 0xffff
  67 function conv_hex8(ival : integer) return string is
  68 variable tmp1, tmp2 : integer;
  69 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  70 begin
  71     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  72     tmp1 := ival mod 16 ** 1;
  73     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  74 end;
  75
  76 --cycle bit format
  77 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T7 > T0
  78 constant T0 : std_logic_vector (5 downto 0) := "000000";
  79 constant T1 : std_logic_vector (5 downto 0) := "000001";
  80 constant T2 : std_logic_vector (5 downto 0) := "000010";
  81 constant T3 : std_logic_vector (5 downto 0) := "000011";
  82 constant T4 : std_logic_vector (5 downto 0) := "000100";
  83 constant T5 : std_logic_vector (5 downto 0) := "000101";
  84 constant T6 : std_logic_vector (5 downto 0) := "000110";
  85 constant T7 : std_logic_vector (5 downto 0) := "000111";
  86
  87 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
  88 constant R0 : std_logic_vector (5 downto 0) := "001000";
  89 constant R1 : std_logic_vector (5 downto 0) := "001001";
  90 constant R2 : std_logic_vector (5 downto 0) := "001010";
  91 constant R3 : std_logic_vector (5 downto 0) := "001011";
  92 constant R4 : std_logic_vector (5 downto 0) := "001100";
  93 constant R5 : std_logic_vector (5 downto 0) := "001101";
  94
  95 --10xxx : nmi cycle : N0 > N1 > N2 > N3 > N4 > N5 > T0
  96 constant N0 : std_logic_vector (5 downto 0) := "010000";
  97 constant N1 : std_logic_vector (5 downto 0) := "010001";
  98 constant N2 : std_logic_vector (5 downto 0) := "010010";
  99 constant N3 : std_logic_vector (5 downto 0) := "010011";
 100 constant N4 : std_logic_vector (5 downto 0) := "010100";
 101 constant N5 : std_logic_vector (5 downto 0) := "010101";
 102
 103 --11xxx : irq cycle : I0 > I1 > I2 > I3 > I4 > I5 > T0
 104 constant I0 : std_logic_vector (5 downto 0) := "011000";
 105 constant I1 : std_logic_vector (5 downto 0) := "011001";
 106 constant I2 : std_logic_vector (5 downto 0) := "011010";
 107 constant I3 : std_logic_vector (5 downto 0) := "011011";
 108 constant I4 : std_logic_vector (5 downto 0) := "011100";
 109 constant I5 : std_logic_vector (5 downto 0) := "011101";
 110
 111 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 112
 113 -- SR Flags (bit 7 to bit 0):
 114 --  7   N   ....    Negative
 115 --  6   V   ....    Overflow
 116 --  5   -   ....    ignored
 117 --  4   B   ....    Break
 118 --  3   D   ....    Decimal (use BCD for arithmetics)
 119 --  2   I   ....    Interrupt (IRQ disable)
 120 --  1   Z   ....    Zero
 121 --  0   C   ....    Carry
 122 constant st_N : integer := 7;
 123 constant st_V : integer := 6;
 124 constant st_B : integer := 4;
 125 constant st_D : integer := 3;
 126 constant st_I : integer := 2;
 127 constant st_Z : integer := 1;
 128 constant st_C : integer := 0;
 129
 130 begin
 131
 132     main_p : process (set_clk, res_n)
 133
 134 -------------------------------------------------------------
 135 -------------------------------------------------------------
 136 ----------------------- comon routines ----------------------
 137 -------------------------------------------------------------
 138 -------------------------------------------------------------
 139
 140 ----------gate_cmd format
 141 ------3 : front port oe_n
 142 ------2 : front port we_n
 143 ------1 : back port oe_n
 144 ------0 : back port we_n
 145 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 146     val : in std_logic) is
 147 begin
 148     cmd(3) <= val;
 149 end;
 150 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 151     val : in std_logic) is
 152 begin
 153     cmd(2) <= val;
 154 end;
 155 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 156     val : in std_logic) is
 157 begin
 158     cmd(1) <= val;
 159 end;
 160 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 161     val : in std_logic) is
 162 begin
 163     cmd(0) <= val;
 164 end;
 165
 166 procedure fetch_inst is
 167 begin
 168     --fetch opcode and phc increment.
 169     ad_oe_n <= '0';
 170     back_oe(pcl_cmd, '0');
 171     back_oe(pch_cmd, '0');
 172     back_we(pcl_cmd, '0');
 173     back_we(pch_cmd, '1');
 174     front_we(pcl_cmd, '1');
 175     front_we(pch_cmd, '1');
 176
 177     inst_we_n <= '0';
 178     pcl_inc_n <= '0';
 179     r_nw <= '1';
 180
 181     --disable the last opration pins.
 182     dbuf_int_oe_n <= '1';
 183     dl_al_we_n <= '1';
 184     dl_ah_we_n <= '1';
 185     dl_al_oe_n <= '1';
 186     dl_ah_oe_n <= '1';
 187     dl_dh_oe_n <= '1';
 188     pch_inc_n <= '1';
 189     sp_cmd <= "1111";
 190     sph_oe_n <= '1';
 191     sp_push_n <= '1';
 192     sp_pop_n <= '1';
 193     acc_cmd <= "1111";
 194     x_cmd <= "1111";
 195     y_cmd <= "1111";
 196
 197     abs_xy_n <= '1';
 198     abs_pg_next_n <= '1';
 199     zp_n <= '1';
 200     zp_xy_n <= '1';
 201
 202     stat_dec_oe_n <= '1';
 203     stat_bus_oe_n <= '1';
 204     stat_set_flg_n <= '1';
 205     stat_flg <= '1';
 206     stat_bus_all_n <= '1';
 207     stat_bus_nz_n <= '1';
 208     stat_alu_we_n <= '1';
 209
 210     d_print(string'("fetch 1"));
 211 end;
 212
 213 ---common routine for single byte instruction.
 214 procedure single_inst is
 215 begin
 216     back_oe(pcl_cmd, '1');
 217     back_oe(pch_cmd, '1');
 218     pcl_inc_n <= '1';
 219     next_cycle <= T0;
 220 end  procedure;
 221
 222 procedure fetch_imm is
 223 begin
 224     d_print("immediate");
 225     pcl_inc_n <= '0';
 226     back_oe(pcl_cmd, '0');
 227     back_oe(pch_cmd, '0');
 228     back_we(pcl_cmd, '0');
 229     back_we(pch_cmd, '1');
 230     --send data from data bus buffer.
 231     --receiver is instruction dependent.
 232     dbuf_int_oe_n <= '0';
 233     next_cycle <= T0;
 234 end  procedure;
 235
 236 procedure set_nz_from_bus is
 237 begin
 238     --status register n/z bit update.
 239     stat_dec_oe_n <= '1';
 240     status_reg <= "10000010";
 241     stat_bus_nz_n <= '0';
 242 end  procedure;
 243
 244 procedure set_nz_from_alu is
 245 begin
 246 end  procedure;
 247
 248 procedure set_nzc_from_alu is
 249 begin
 250 end  procedure;
 251
 252 --flag on/off instruction
 253 procedure set_flag (int_flg : in integer; val : in std_logic) is
 254 begin
 255     stat_dec_oe_n <= '1';
 256     stat_set_flg_n <= '0';
 257     --specify which to set.
 258     status_reg(7 downto int_flg + 1)
 259         <= (others =>'0');
 260     status_reg(int_flg - 1 downto 0)
 261         <= (others =>'0');
 262     status_reg(int_flg) <= '1';
 263     stat_flg <= val;
 264 end  procedure;
 265
 266 --for sec/clc
 267 procedure set_flag0 (val : in std_logic) is
 268 begin
 269     stat_dec_oe_n <= '1';
 270     stat_set_flg_n <= '0';
 271     status_reg <= "00000001";
 272     stat_flg <= val;
 273 end  procedure;
 274
 275 procedure fetch_low is
 276 begin
 277     d_print("fetch low 2");
 278     --fetch next opcode (abs low).
 279     back_oe(pcl_cmd, '0');
 280     back_we(pcl_cmd, '0');
 281     back_oe(pch_cmd, '0');
 282     pcl_inc_n <= '0';
 283     --latch abs low data.
 284     dbuf_int_oe_n <= '0';
 285     dl_al_we_n <= '0';
 286     next_cycle <= T2;
 287 end  procedure;
 288
 289 procedure abs_fetch_high is
 290 begin
 291     d_print("abs (xy) 3");
 292     dl_al_we_n <= '1';
 293
 294     --latch abs hi data.
 295     pcl_inc_n <= '0';
 296     back_oe(pcl_cmd, '0');
 297     back_we(pcl_cmd, '0');
 298     back_oe(pch_cmd, '0');
 299
 300     dbuf_int_oe_n <= '0';
 301     dl_ah_we_n <= '0';
 302     next_cycle <= T3;
 303 end  procedure;
 304
 305 procedure abs_latch_out is
 306 begin
 307     --d_print("abs 4");
 308     pcl_inc_n <= '1';
 309     back_oe(pcl_cmd, '1');
 310     back_we(pcl_cmd, '1');
 311     back_oe(pch_cmd, '1');
 312     dl_ah_we_n <= '1';
 313
 314     --latch > al/ah.
 315     dl_al_oe_n <= '0';
 316     dl_ah_oe_n <= '0';
 317 end  procedure;
 318
 319 procedure ea_x_out is
 320 begin
 321     -----calucurate and output effective addr
 322     back_oe(x_cmd, '0');
 323     dl_al_oe_n <= '0';
 324     dl_ah_oe_n <= '0';
 325     abs_xy_n <= '0';
 326 end  procedure;
 327
 328 --A.2. internal execution on memory data
 329 procedure a2_abs is
 330 begin
 331 end  procedure;
 332
 333 procedure a2_absx is
 334 begin
 335     if exec_cycle = T1 then
 336         fetch_low;
 337     elsif exec_cycle = T2 then
 338         abs_fetch_high;
 339     elsif exec_cycle = T3 then
 340         --ea calc & lda
 341         abs_latch_out;
 342         ea_x_out;
 343         dbuf_int_oe_n <= '0';
 344         --instruction specific operation wriiten in the caller position.
 345         next_cycle <= T4;
 346     elsif exec_cycle = T4 then
 347         if ea_carry = '1' then
 348             --case page boundary crossed.
 349             d_print("absx 5 (page boudary crossed.)");
 350             abs_latch_out;
 351             ea_x_out;
 352             dbuf_int_oe_n <= '0';
 353             --next page.
 354             abs_pg_next_n <= '0';
 355             --redo inst.
 356             next_cycle <= T0;
 357         else
 358             --case page boundary not crossed. do the fetch op.
 359             d_print("absx 5 (fetch)");
 360             fetch_inst;
 361             next_cycle <= T1;
 362         end if;
 363     end if;
 364 end  procedure;
 365
 366
 367 --A.3. store operation.
 368
 369 procedure a3_zp is
 370 begin
 371 end  procedure;
 372
 373 procedure a3_abs is
 374 begin
 375     if exec_cycle = T1 then
 376         fetch_low;
 377     elsif exec_cycle = T2 then
 378         abs_fetch_high;
 379     elsif exec_cycle = T3 then
 380         abs_latch_out;
 381         dbuf_int_oe_n <= '1';
 382         r_nw <= '0';
 383         next_cycle <= T0;
 384     end if;
 385 end  procedure;
 386
 387
 388 -- A.5.8 branch operations
 389 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 390 begin
 391 end  procedure;
 392
 393 -------------------------------------------------------------
 394 -------------------------------------------------------------
 395 ---------------- main state machine start.... ---------------
 396 -------------------------------------------------------------
 397 -------------------------------------------------------------
 398     begin
 399
 400         if (res_n = '0') then
 401             --pc l/h is reset vector.
 402             pcl_cmd <= "1110";
 403             pch_cmd <= "1110";
 404             next_cycle <= R0;
 405         elsif (res_n'event and res_n = '1') then
 406             pcl_cmd <= "1111";
 407             pch_cmd <= "1111";
 408         end if;
 409
 410         if (set_clk'event and set_clk = '1' and res_n = '1') then
 411             d_print(string'("-"));
 412
 413             if exec_cycle = T0 then
 414                 --cycle #1
 415                 fetch_inst;
 416                 next_cycle <= T1;
 417
 418             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 419                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or
 420                 exec_cycle = T7 then
 421                 --execute inst.
 422
 423                 ---asyncronous page change might happen.
 424                 back_we(pch_cmd, '1');
 425
 426                 if exec_cycle = T1 then
 427                     d_print("decode and execute inst: "
 428                             & conv_hex8(conv_integer(instruction)));
 429                     --disable pin since jmp instruction
 430                     --directly enters into t2 cycle.
 431                     dl_al_oe_n <= '1';
 432                     dl_ah_oe_n <= '1';
 433                     dl_dh_oe_n <= '1';
 434                     back_we(pcl_cmd, '1');
 435                     front_we(pch_cmd, '1');
 436
 437                     --grab instruction register data.
 438                     inst_we_n <= '1';
 439                 end if;
 440
 441                 --imelementation is wriiten in the order of hardware manual
 442                 --appendix A.
 443
 444
 445                 ----------------------------------------
 446                 --A.1. Single byte instruction.
 447                 ----------------------------------------
 448                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 449                     --asl acc mode.
 450                     d_print("asl");
 451
 452                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 453                     d_print("clc");
 454                     set_flag0 ('0');
 455                     single_inst;
 456
 457                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 458                     d_print("cld");
 459                     set_flag (st_D, '0');
 460                     single_inst;
 461
 462                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 463                     d_print("cli");
 464
 465                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 466                     d_print("clv");
 467
 468                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 469                     d_print("dex");
 470                     --set nz bit.
 471                     set_nz_from_alu ;
 472                     single_inst;
 473
 474                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
 475                     d_print("dey");
 476                     --set nz bit.
 477                     set_nz_from_alu ;
 478                     single_inst;
 479
 480                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
 481                     d_print("inx");
 482                     --set nz bit.
 483                     set_nz_from_alu ;
 484                     single_inst;
 485
 486                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
 487                     d_print("iny");
 488
 489                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
 490                     --lsr acc mode
 491                     d_print("lsr");
 492
 493                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
 494                     d_print("nop");
 495
 496                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
 497                     --rol acc
 498                     d_print("rol");
 499
 500                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
 501                     d_print("sec");
 502                     set_flag0 ('1');
 503                     single_inst;
 504
 505                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
 506                     d_print("sed");
 507                     set_flag (st_D, '1');
 508                     single_inst;
 509
 510                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
 511                     d_print("sei");
 512                     set_flag (st_I, '1');
 513                     single_inst;
 514
 515                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
 516                     d_print("tax");
 517                     set_nz_from_bus;
 518
 519                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
 520                     d_print("tay");
 521                     set_nz_from_bus;
 522
 523                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
 524                     d_print("tsx");
 525                     set_nz_from_bus;
 526
 527                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
 528                     d_print("txa");
 529                     set_nz_from_bus;
 530
 531                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
 532                     d_print("txs");
 533                     set_nz_from_bus;
 534                     single_inst;
 535                     front_oe(x_cmd, '0');
 536                     front_we(sp_cmd, '0');
 537
 538                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
 539                     d_print("tya");
 540                     set_nz_from_bus;
 541
 542
 543
 544                 ----------------------------------------
 545                 --A.2. internal execution on memory data
 546                 ----------------------------------------
 547                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
 548                     --imm
 549                     d_print("adc");
 550
 551                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
 552                     --zp
 553                     d_print("adc");
 554
 555                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
 556                     --zp, x
 557                     d_print("adc");
 558
 559                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
 560                     --abs
 561                     d_print("adc");
 562
 563                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
 564                     --abs, x
 565                     d_print("adc");
 566
 567                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
 568                     --abs, y
 569                     d_print("adc");
 570
 571                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
 572                     --(indir, x)
 573                     d_print("adc");
 574
 575                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
 576                     --(indir), y
 577                     d_print("adc");
 578
 579                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
 580                     --imm
 581                     d_print("and");
 582
 583                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
 584                     --zp
 585                     d_print("and");
 586
 587                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
 588                     --zp, x
 589                     d_print("and");
 590
 591                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
 592                     --abs
 593                     d_print("and");
 594
 595                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
 596                     --abs, x
 597                     d_print("and");
 598
 599                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
 600                     --abs, y
 601                     d_print("and");
 602
 603                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
 604                     --(indir, x)
 605                     d_print("and");
 606
 607                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
 608                     --(indir), y
 609                     d_print("and");
 610
 611                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
 612                     --zp
 613                     d_print("bit");
 614
 615                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
 616                     --abs
 617                     d_print("bit");
 618
 619                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
 620                     --imm
 621                     d_print("cmp");
 622                     fetch_imm;
 623                     set_nzc_from_alu;
 624
 625                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
 626                     --zp
 627                     d_print("cmp");
 628
 629                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
 630                     --zp, x
 631                     d_print("cmp");
 632
 633                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
 634                     --abs
 635                     d_print("cmp");
 636
 637                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
 638                     --abs, x
 639                     d_print("cmp");
 640
 641                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
 642                     --abs, y
 643                     d_print("cmp");
 644
 645                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
 646                     --(indir, x)
 647                     d_print("cmp");
 648
 649                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
 650                     --(indir), y
 651                     d_print("cmp");
 652
 653                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
 654                     --imm
 655                     d_print("cpx");
 656
 657                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
 658                     --zp
 659                     d_print("cpx");
 660
 661                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
 662                     --abs
 663                     d_print("cpx");
 664
 665                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
 666                     --imm
 667                     d_print("cpy");
 668
 669                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
 670                     --zp
 671                     d_print("cpy");
 672
 673                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
 674                     --abs
 675                     d_print("cpy");
 676
 677                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
 678                     --imm
 679                     d_print("eor");
 680
 681                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
 682                     --zp
 683                     d_print("eor");
 684
 685                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
 686                     --zp, x
 687                     d_print("eor");
 688
 689                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
 690                     --abs
 691                     d_print("eor");
 692
 693                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
 694                     --abs, x
 695                     d_print("eor");
 696
 697                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
 698                     --abs, y
 699                     d_print("eor");
 700
 701                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
 702                     --(indir, x)
 703                     d_print("eor");
 704
 705                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
 706                     --(indir), y
 707                     d_print("eor");
 708
 709                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
 710                     --imm
 711                     d_print("lda");
 712                     fetch_imm;
 713                     front_we(acc_cmd, '0');
 714                     set_nz_from_bus;
 715
 716                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
 717                     --zp
 718                     d_print("lda");
 719
 720                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
 721                     --zp, x
 722                     d_print("lda");
 723
 724                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
 725                     --abs
 726                     d_print("lda");
 727                     a2_abs;
 728                     if exec_cycle = T3 then
 729                         set_nz_from_bus;
 730                     end if;
 731
 732                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
 733                     --abs, x
 734                     d_print("lda");
 735                     a2_absx;
 736                     if exec_cycle = T3 then
 737                         --lda.
 738                         front_we(acc_cmd, '0');
 739                         set_nz_from_bus;
 740                     elsif exec_cycle = T4 then
 741                         if ea_carry = '1' then
 742                             --redo lda
 743                             front_we(acc_cmd, '0');
 744                             set_nz_from_bus;
 745                         end if;
 746                     end if;
 747
 748                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
 749                     --abs, y
 750                     d_print("lda");
 751
 752                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
 753                     --(indir, x)
 754                     d_print("lda");
 755
 756                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
 757                     --(indir), y
 758                     d_print("lda");
 759
 760                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
 761                     --imm
 762                     d_print("ldx");
 763                     fetch_imm;
 764                     set_nz_from_bus;
 765                     front_we(x_cmd, '0');
 766
 767                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
 768                     --zp
 769                     d_print("ldx");
 770
 771                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
 772                     --zp, y
 773                     d_print("ldx");
 774
 775                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
 776                     --abs
 777                     d_print("ldx");
 778
 779                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
 780                     --abs, y
 781                     d_print("ldx");
 782
 783                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
 784                     --imm
 785                     d_print("ldy");
 786                     fetch_imm;
 787                     set_nz_from_bus;
 788                     front_we(y_cmd, '0');
 789
 790                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
 791                     --zp
 792                     d_print("ldy");
 793
 794                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
 795                     --zp, x
 796                     d_print("ldy");
 797
 798                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
 799                     --abs
 800                     d_print("ldy");
 801
 802                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
 803                     --abs, x
 804                     d_print("ldy");
 805
 806                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
 807                     --imm
 808                     d_print("ora");
 809
 810                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
 811                     --zp
 812                     d_print("ora");
 813
 814                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
 815                     --zp, x
 816                     d_print("ora");
 817
 818                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
 819                     --abs
 820                     d_print("ora");
 821
 822                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
 823                     --abs, x
 824                     d_print("ora");
 825
 826                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
 827                     --abs, y
 828                     d_print("ora");
 829
 830                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
 831                     --(indir, x)
 832                     d_print("ora");
 833
 834                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
 835                     --(indir), y
 836                     d_print("ora");
 837
 838                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
 839                     --imm
 840                     d_print("sbc");
 841
 842                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
 843                     --zp
 844                     d_print("sbc");
 845
 846                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
 847                     --zp, x
 848                     d_print("sbc");
 849
 850                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
 851                     --abs
 852                     d_print("sbc");
 853
 854                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
 855                     --abs, x
 856                     d_print("sbc");
 857
 858                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
 859                     --abs, y
 860                     d_print("sbc");
 861
 862                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
 863                     --(indir, x)
 864                     d_print("sbc");
 865
 866                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
 867                     --(indir), y
 868                     d_print("sbc");
 869
 870
 871
 872                 ----------------------------------------
 873                 ---A.3. store operation.
 874                 ----------------------------------------
 875                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
 876                     --zp
 877                     d_print("sta");
 878                     a3_zp;
 879                     if exec_cycle = T2 then
 880                     end if;
 881
 882                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
 883                     --zp, x
 884                     d_print("sta");
 885
 886                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
 887                     --abs
 888                     d_print("sta");
 889                     a3_abs;
 890                     if exec_cycle = T3 then
 891                         front_oe(acc_cmd, '0');
 892                     end if;
 893
 894                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
 895                     --abs, x
 896                     d_print("sta");
 897
 898                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
 899                     --abs, y
 900                     d_print("sta");
 901
 902                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
 903                     --(indir, x)
 904                     d_print("sta");
 905
 906                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
 907                     --(indir), y
 908                     d_print("sta");
 909
 910                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
 911                     --zp
 912                     d_print("stx");
 913                     a3_zp;
 914                     if exec_cycle = T2 then
 915                     end if;
 916
 917                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
 918                     --zp, y
 919                     d_print("stx");
 920
 921                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
 922                     --abs
 923                     d_print("stx");
 924
 925                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
 926                     --zp
 927                     d_print("sty");
 928
 929                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
 930                     --zp, x
 931                     d_print("sty");
 932
 933                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
 934                     --abs
 935                     d_print("sty");
 936
 937
 938                 ----------------------------------------
 939                 ---A.4. read-modify-write operation
 940                 ----------------------------------------
 941                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
 942                     --zp
 943                     d_print("asl");
 944
 945                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
 946                     --zp, x
 947                     d_print("asl");
 948
 949                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
 950                     --abs
 951                     d_print("asl");
 952
 953                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
 954                     --abs, x
 955                     d_print("asl");
 956
 957                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
 958                     --zp
 959                     d_print("dec");
 960
 961                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
 962                     --zp, x
 963                     d_print("dec");
 964
 965                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
 966                     --abs
 967                     d_print("dec");
 968
 969                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
 970                     --abs, x
 971                     d_print("dec");
 972
 973                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
 974                     --zp
 975                     d_print("inc");
 976
 977                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
 978                     --zp, x
 979                     d_print("inc");
 980
 981                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
 982                     --abs
 983                     d_print("inc");
 984
 985                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
 986                     --abs, x
 987                     d_print("inc");
 988
 989                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
 990                     --zp
 991                     d_print("lsr");
 992
 993                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
 994                     --zp, x
 995                     d_print("lsr");
 996
 997                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
 998                     --abs
 999                     d_print("lsr");
1000
1001                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
1002                     --abs, x
1003                     d_print("lsr");
1004
1005                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
1006                     --zp
1007                     d_print("rol");
1008
1009                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
1010                     --zp, x
1011                     d_print("rol");
1012
1013                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
1014                     --abs
1015                     d_print("rol");
1016
1017                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
1018                     --abs, x
1019                     d_print("rol");
1020
1021                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
1022                     --zp
1023                     d_print("ror");
1024
1025                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
1026                     --zp, x
1027                     d_print("ror");
1028
1029                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
1030                     --abs
1031                     d_print("ror");
1032
1033                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
1034                     --abs, x
1035                     d_print("ror");
1036
1037
1038                 ----------------------------------------
1039                 --A.5. miscellaneous oprations.
1040                 ----------------------------------------
1041
1042                 -- A.5.1 push/pull
1043                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1044                     d_print("php");
1045
1046                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1047                     d_print("pha");
1048
1049                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1050                     d_print("plp");
1051
1052                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1053                     d_print("pla");
1054
1055
1056                 ----------------------------------------
1057                 -- A.5.3 jsr
1058                 ----------------------------------------
1059                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1060                     if exec_cycle = T1 then
1061                         d_print("jsr abs 2");
1062                         --fetch opcode.
1063                         back_oe(pcl_cmd, '0');
1064                         back_oe(pch_cmd, '0');
1065                         back_we(pcl_cmd, '0');
1066                         pcl_inc_n <= '0';
1067                         dbuf_int_oe_n <= '0';
1068                         --latch adl
1069                         dl_al_we_n <= '0';
1070                         next_cycle <= T2;
1071                     elsif exec_cycle = T2 then
1072                         d_print("jsr 3");
1073                         back_oe(pcl_cmd, '1');
1074                         back_oe(pch_cmd, '1');
1075                         back_we(pcl_cmd, '1');
1076                         pcl_inc_n <= '1';
1077                         dbuf_int_oe_n <= '1';
1078                         dl_al_we_n <= '1';
1079
1080                        --push return addr high into stack.
1081                         sp_push_n <= '0';
1082                         sph_oe_n <= '0';
1083                         front_oe(pch_cmd, '0');
1084                         back_oe(sp_cmd, '0');
1085                         back_we(sp_cmd, '0');
1086                         r_nw <= '0';
1087                         next_cycle <= T3;
1088                     elsif exec_cycle = T3 then
1089                         d_print("jsr 4");
1090                         front_oe(pch_cmd, '1');
1091
1092                        --push return addr low into stack.
1093                         sp_push_n <= '0';
1094                         sph_oe_n <= '0';
1095                         front_oe(pcl_cmd, '0');
1096                         back_oe(sp_cmd, '0');
1097                         back_we(sp_cmd, '0');
1098                         r_nw <= '0';
1099
1100                         next_cycle <= T4;
1101                     elsif exec_cycle = T4 then
1102                         d_print("jsr 5");
1103                         sp_push_n <= '1';
1104                         sph_oe_n <= '1';
1105                         front_oe(pcl_cmd, '1');
1106                         back_oe(sp_cmd, '1');
1107                         back_we(sp_cmd, '1');
1108                         r_nw <= '1';
1109
1110                         --fetch last op.
1111                         back_oe(pch_cmd, '0');
1112                         back_oe(pcl_cmd, '0');
1113                         dbuf_int_oe_n <= '0';
1114                         dl_ah_we_n <= '0';
1115
1116                         next_cycle <= T5;
1117                     elsif exec_cycle = T5 then
1118                         d_print("jsr 6");
1119
1120                         back_oe(pch_cmd, '1');
1121                         back_oe(pcl_cmd, '1');
1122                         dbuf_int_oe_n <= '1';
1123                         dl_ah_we_n <= '1';
1124
1125                         --load/output  pch
1126                         ad_oe_n <= '1';
1127                         dl_ah_oe_n <= '0';
1128                         dl_dh_oe_n <= '0';
1129                         front_we(pch_cmd, '0');
1130
1131                         --load pcl.
1132                         dl_al_oe_n <= '0';
1133                         back_we(pcl_cmd, '0');
1134
1135                         next_cycle <= T0;
1136                     end if; --if exec_cycle = T1 then
1137
1138                 -- A.5.4 break
1139                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
1140
1141                 ----------------------------------------
1142                 -- A.5.5 return from interrupt
1143                 ----------------------------------------
1144                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
1145
1146                 ----------------------------------------
1147                 -- A.5.6 jmp
1148                 ----------------------------------------
1149                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
1150                     --abs
1151                     if exec_cycle = T1 then
1152                         d_print("jmp 2");
1153                         --fetch next opcode (abs low).
1154                         back_oe(pcl_cmd, '0');
1155                         back_oe(pch_cmd, '0');
1156                         back_we(pcl_cmd, '0');
1157                         pcl_inc_n <= '0';
1158
1159                         --latch abs low data.
1160                         dbuf_int_oe_n <= '0';
1161                         dl_al_we_n <= '0';
1162                         next_cycle <= T2;
1163                     elsif exec_cycle = T2 then
1164                         d_print("jmp 3");
1165                         dl_al_we_n <= '1';
1166
1167                         --fetch abs hi
1168                         back_oe(pcl_cmd, '0');
1169                         back_oe(pch_cmd, '0');
1170                         back_we(pcl_cmd, '0');
1171                         pcl_inc_n <= '0';
1172
1173                         --latch  in dlh
1174                         dbuf_int_oe_n <= '0';
1175                         dl_ah_we_n <= '0';
1176                         next_cycle <= T3;
1177                     elsif exec_cycle = T3 then
1178                         d_print("jmp done > next fetch");
1179                         back_oe(pcl_cmd, '1');
1180                         back_oe(pch_cmd, '1');
1181                         dbuf_int_oe_n <= '1';
1182                         dl_ah_we_n <= '1';
1183
1184                         --latch > al/ah.
1185                         dl_al_oe_n <= '0';
1186                         dl_ah_oe_n <= '0';
1187                         dl_dh_oe_n <= '0';
1188
1189                         --fetch inst and goto decode next.
1190                         back_we(pcl_cmd, '0');
1191                         front_we(pch_cmd, '0');
1192                         inst_we_n <= '0';
1193                         pcl_inc_n <= '0';
1194                         next_cycle <= T1;
1195                     end if;
1196
1197                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
1198                     --(indir)
1199
1200
1201                 ----------------------------------------
1202                 -- A.5.7 return from soubroutine
1203                 ----------------------------------------
1204                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
1205                     if exec_cycle = T1 then
1206                         d_print("rts 2");
1207                         back_oe(pcl_cmd, '1');
1208                         back_oe(pch_cmd, '1');
1209                         pcl_inc_n <= '1';
1210
1211                         --pop stack (decrement only)
1212                         back_oe(sp_cmd, '0');
1213                         back_we(sp_cmd, '0');
1214                         sp_pop_n <= '0';
1215                         sph_oe_n <= '0';
1216
1217                         next_cycle <= T2;
1218                     elsif exec_cycle = T2 then
1219                         d_print("rts 3");
1220
1221                         --pop pcl
1222                         back_oe(sp_cmd, '0');
1223                         back_we(sp_cmd, '0');
1224                         sp_pop_n <= '0';
1225                         sph_oe_n <= '0';
1226
1227                         --load lo addr.
1228                         dbuf_int_oe_n <= '0';
1229                         front_we(pcl_cmd, '0');
1230
1231                         next_cycle <= T3;
1232                     elsif exec_cycle = T3 then
1233                         d_print("rts 4");
1234                         --stack decrement stop.
1235                         back_we(sp_cmd, '1');
1236                         sp_pop_n <= '1';
1237                         front_we(pcl_cmd, '1');
1238
1239                         --pop pch
1240                         back_oe(sp_cmd, '0');
1241                         sph_oe_n <= '0';
1242                         --load hi addr.
1243                         dbuf_int_oe_n <= '0';
1244                         front_we(pch_cmd, '0');
1245
1246                         next_cycle <= T4;
1247                     elsif exec_cycle = T4 then
1248                         d_print("rts 5");
1249                         back_oe(sp_cmd, '1');
1250                         sph_oe_n <= '1';
1251                         --load hi addr.
1252                         dbuf_int_oe_n <= '1';
1253                         front_we(pch_cmd, '1');
1254                         --empty cycle.
1255                         --complying h/w manual...
1256                         next_cycle <= T5;
1257                     elsif exec_cycle = T5 then
1258                         d_print("rts 6");
1259
1260                         --increment pc.
1261                         pcl_inc_n <= '0';
1262                         back_we(pcl_cmd, '0');
1263                         back_oe(pcl_cmd, '0');
1264                         back_oe(pch_cmd, '0');
1265                         next_cycle <= T0;
1266                     end if; --if exec_cycle = T1 then
1267
1268                 ----------------------------------------
1269                 -- A.5.8 branch operations
1270                 ----------------------------------------
1271                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
1272                     d_print("bcc");
1273                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
1274                     d_print("bcs");
1275                     a58_branch (st_C, '1');
1276
1277                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
1278                     d_print("beq");
1279                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
1280                     d_print("bmi");
1281                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
1282                     d_print("bne");
1283                     a58_branch (st_Z, '0');
1284
1285                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
1286                     d_print("bpl");
1287                     a58_branch (st_N, '0');
1288
1289                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
1290                     d_print("bvc");
1291                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
1292                     d_print("bvs");
1293
1294                 else
1295                     ---unknown instruction!!!!
1296                     assert false
1297                         report "======== unknow instruction "
1298                             & conv_hex8(conv_integer(instruction));
1299                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
1300
1301             elsif exec_cycle = R0 then
1302                 d_print(string'("reset"));
1303
1304                 next_cycle <= R1;
1305                 inst_we_n <= '1';
1306                 ad_oe_n <= '1';
1307                 dbuf_int_oe_n <= '1';
1308                 dl_al_we_n <= '1';
1309                 dl_ah_we_n <= '1';
1310                 dl_al_oe_n <= '1';
1311                 dl_ah_oe_n <= '1';
1312                 dl_dh_oe_n <= '1';
1313                 pcl_inc_n <= '1';
1314                 pch_inc_n <= '1';
1315                 pcl_cmd <= "1111";
1316                 pch_cmd <= "1111";
1317                 sp_cmd <= "1111";
1318                 sph_oe_n <= '1';
1319                 sp_push_n <= '1';
1320                 sp_pop_n <= '1';
1321                 acc_cmd <= "1111";
1322                 x_cmd <= "1111";
1323                 y_cmd <= "1111";
1324
1325                 abs_xy_n <= '1';
1326                 abs_pg_next_n <= '1';
1327                 zp_n <= '1';
1328                 zp_xy_n <= '1';
1329
1330                 stat_dec_oe_n <= '1';
1331                 stat_bus_oe_n <= '1';
1332                 stat_set_flg_n <= '1';
1333                 stat_flg <= '1';
1334                 stat_bus_all_n <= '1';
1335                 stat_bus_nz_n <= '1';
1336                 stat_alu_we_n <= '1';
1337
1338                 r_nw <= '1';
1339             elsif exec_cycle = R1 then
1340                 next_cycle <= R2;
1341                 front_we(pch_cmd, '1');
1342                 back_we(pcl_cmd, '1');
1343
1344             elsif exec_cycle = R2 then
1345                 next_cycle <= R3;
1346
1347             elsif exec_cycle = R3 then
1348                 next_cycle <= R4;
1349
1350             elsif exec_cycle = R4 then
1351                 next_cycle <= R5;
1352
1353             elsif exec_cycle = R5 then
1354                 next_cycle <= T0;
1355
1356             elsif exec_cycle(5) = '1' then
1357                 ---pc increment and next page.
1358                 d_print(string'("pch next page..."));
1359                 --pcl stop increment
1360                 pcl_inc_n <= '1';
1361                 back_we(pcl_cmd, '1');
1362                 --pch increment
1363                 pch_inc_n <= '0';
1364                 back_we(pch_cmd, '0');
1365
1366             end if; --if exec_cycle = T0 then
1367
1368         end if; --if (set_clk'event and set_clk = '1')
1369
1370     end process;
1371
1372 end rtl;
1373