simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sp_oe_n         : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             pg_next_n       : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             rel_calc_n      : out std_logic;
  43             indir_n         : out std_logic;
  44             indir_x_n       : out std_logic;
  45             indir_y_n       : out std_logic;
  46             arith_en_n      : out std_logic;
  47             stat_dec_oe_n   : out std_logic;
  48             stat_bus_oe_n   : out std_logic;
  49             stat_set_flg_n  : out std_logic;
  50             stat_flg        : out std_logic;
  51             stat_bus_all_n  : out std_logic;
  52             stat_bus_nz_n   : out std_logic;
  53             stat_alu_we_n   : out std_logic;
  54             r_vec_oe_n      : out std_logic;
  55             n_vec_oe_n      : out std_logic;
  56             i_vec_oe_n      : out std_logic;
  57             r_nw            : out std_logic
  58             ;---for parameter check purpose!!!
  59             check_bit     : out std_logic_vector(1 to 5)
  60         );
  61 end decoder;
  62
  63 architecture rtl of decoder is
  64
  65 component d_flip_flop_bit
  66     port (
  67             clk     : in std_logic;
  68             res_n   : in std_logic;
  69             set_n   : in std_logic;
  70             we_n    : in std_logic;
  71             d       : in std_logic;
  72             q       : out std_logic
  73         );
  74 end component;
  75
  76 procedure d_print(msg : string) is
  77 use std.textio.all;
  78 use ieee.std_logic_textio.all;
  79 variable out_l : line;
  80 begin
  81     write(out_l, msg);
  82     writeline(output, out_l);
  83 end  procedure;
  84
  85 ---ival : 0x0000 - 0xffff
  86 function conv_hex8(ival : integer) return string is
  87 variable tmp1, tmp2 : integer;
  88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  89 begin
  90     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  91     tmp1 := ival mod 16 ** 1;
  92     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  93 end;
  94
  95 --cycle bit format
  96 -- bit 5    : pcl increment carry flag
  97 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  98 -- bit 2-0  : cycle
  99
 100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
 101 constant T0 : std_logic_vector (5 downto 0) := "000000";
 102 constant T1 : std_logic_vector (5 downto 0) := "000001";
 103 constant T2 : std_logic_vector (5 downto 0) := "000010";
 104 constant T3 : std_logic_vector (5 downto 0) := "000011";
 105 constant T4 : std_logic_vector (5 downto 0) := "000100";
 106 constant T5 : std_logic_vector (5 downto 0) := "000101";
 107 constant T6 : std_logic_vector (5 downto 0) := "000110";
 108
 109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 110 constant R0 : std_logic_vector (5 downto 0) := "001000";
 111 constant R1 : std_logic_vector (5 downto 0) := "001001";
 112 constant R2 : std_logic_vector (5 downto 0) := "001010";
 113 constant R3 : std_logic_vector (5 downto 0) := "001011";
 114 constant R4 : std_logic_vector (5 downto 0) := "001100";
 115 constant R5 : std_logic_vector (5 downto 0) := "001101";
 116
 117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 118 constant N1 : std_logic_vector (5 downto 0) := "010001";
 119 constant N2 : std_logic_vector (5 downto 0) := "010010";
 120 constant N3 : std_logic_vector (5 downto 0) := "010011";
 121 constant N4 : std_logic_vector (5 downto 0) := "010100";
 122 constant N5 : std_logic_vector (5 downto 0) := "010101";
 123
 124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 125 constant I1 : std_logic_vector (5 downto 0) := "011001";
 126 constant I2 : std_logic_vector (5 downto 0) := "011010";
 127 constant I3 : std_logic_vector (5 downto 0) := "011011";
 128 constant I4 : std_logic_vector (5 downto 0) := "011100";
 129 constant I5 : std_logic_vector (5 downto 0) := "011101";
 130
 131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 132
 133 -- SR Flags (bit 7 to bit 0):
 134 --  7   N   ....    Negative
 135 --  6   V   ....    Overflow
 136 --  5   -   ....    ignored
 137 --  4   B   ....    Break
 138 --  3   D   ....    Decimal (use BCD for arithmetics)
 139 --  2   I   ....    Interrupt (IRQ disable)
 140 --  1   Z   ....    Zero
 141 --  0   C   ....    Carry
 142 constant st_N : integer := 7;
 143 constant st_V : integer := 6;
 144 constant st_B : integer := 4;
 145 constant st_D : integer := 3;
 146 constant st_I : integer := 2;
 147 constant st_Z : integer := 1;
 148 constant st_C : integer := 0;
 149
 150 ---for pch_inc_n.
 151 signal pch_inc_input : std_logic;
 152
 153 ---for nmi handling
 154 signal nmi_handled_n : std_logic;
 155
 156 -- page boundary handling
 157 signal a2_abs_xy_next_cycle     : std_logic_vector (5 downto 0);
 158 signal a2_indir_y_next_cycle    : std_logic_vector (5 downto 0);
 159 signal wait_a2_abs_xy_next      : std_logic;
 160 signal wait_a2_indir_y_next     : std_logic;
 161
 162 begin
 163
 164     ---pc page next is connected to top bit of exec_cycle
 165     pch_inc_input <= not exec_cycle(5);
 166     pch_inc_reg : d_flip_flop_bit
 167             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 168
 169     a2_abs_xy_next_cycle <= T4 when ea_carry = '1' else
 170                     T0;
 171     a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
 172                     T0;
 173
 174     main_p : process (set_clk, res_n, nmi_n, a2_abs_xy_next_cycle, a2_indir_y_next_cycle)
 175
 176 -------------------------------------------------------------
 177 -------------------------------------------------------------
 178 ----------------------- comon routines ----------------------
 179 -------------------------------------------------------------
 180 -------------------------------------------------------------
 181
 182 ----------gate_cmd format
 183 ------3 : front port oe_n
 184 ------2 : front port we_n
 185 ------1 : back port oe_n
 186 ------0 : back port we_n
 187 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 188     val : in std_logic) is
 189 begin
 190     cmd(3) <= val;
 191 end;
 192 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 193     val : in std_logic) is
 194 begin
 195     cmd(2) <= val;
 196 end;
 197 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 198     val : in std_logic) is
 199 begin
 200     cmd(1) <= val;
 201 end;
 202 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 203     val : in std_logic) is
 204 begin
 205     cmd(0) <= val;
 206 end;
 207
 208 procedure fetch_next is
 209 begin
 210     pcl_inc_n <= '0';
 211     back_oe(pcl_cmd, '0');
 212     back_oe(pch_cmd, '0');
 213     back_we(pcl_cmd, '0');
 214     back_we(pch_cmd, '1');
 215 end procedure;
 216
 217 procedure fetch_stop is
 218 begin
 219     pcl_inc_n <= '1';
 220     back_oe(pcl_cmd, '1');
 221     back_oe(pch_cmd, '1');
 222     back_we(pcl_cmd, '1');
 223 end procedure;
 224
 225 procedure read_status is
 226 begin
 227     status_reg <= (others => 'Z');
 228     stat_dec_oe_n <= '0';
 229 end  procedure;
 230
 231 procedure disable_pins is
 232 begin
 233     --disable the last opration pins.
 234     dbuf_int_oe_n <= '1';
 235     dl_al_we_n <= '1';
 236     dl_ah_we_n <= '1';
 237     dl_ah_oe_n <= '1';
 238     dl_dh_oe_n <= '1';
 239     sp_cmd <= "1111";
 240     sp_oe_n <= '1';
 241     sp_push_n <= '1';
 242     sp_pop_n <= '1';
 243     acc_cmd <= "1111";
 244     x_cmd <= "1111";
 245     y_cmd <= "1111";
 246
 247     abs_xy_n <= '1';
 248     pg_next_n <= '1';
 249     zp_n <= '1';
 250     zp_xy_n <= '1';
 251     rel_calc_n <= '1';
 252     indir_n <= '1';
 253     indir_x_n <= '1';
 254     indir_y_n <= '1';
 255     arith_en_n <= '1';
 256
 257     read_status;
 258     stat_bus_oe_n <= '1';
 259     stat_set_flg_n <= '1';
 260     stat_flg <= '1';
 261     stat_bus_all_n <= '1';
 262     stat_bus_nz_n <= '1';
 263     stat_alu_we_n <= '1';
 264
 265     r_vec_oe_n <= '1';
 266     n_vec_oe_n <= '1';
 267     i_vec_oe_n <= '1';
 268
 269     wait_a2_abs_xy_next <= '0';
 270     wait_a2_indir_y_next <= '0';
 271 end  procedure;
 272
 273 procedure fetch_inst (inc_pcl : in std_logic) is
 274 begin
 275     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 276         --if prior cycle is jump instruction,
 277         --fetch opcode from where the latch is pointing to.
 278
 279         --latch > al.
 280         dl_al_oe_n <= '0';
 281         pcl_cmd <= "1110";
 282     else
 283         --fetch opcode and pcl increment.
 284         pcl_cmd <= "1100";
 285         dl_al_oe_n <= '1';
 286     end if;
 287
 288     ad_oe_n <= '0';
 289     pch_cmd <= "1101";
 290     inst_we_n <= '0';
 291     pcl_inc_n <= inc_pcl;
 292     r_nw <= '1';
 293
 294     d_print(string'("fetch 1"));
 295 end  procedure;
 296
 297 ---T0 cycle routine
 298 ---(along with the page boundary condition, the last
 299 ---cycle is bypassed and slided to T0.)
 300 procedure t0_cycle is
 301 begin
 302     disable_pins;
 303     if (nmi_n = '0' and nmi_handled_n = '1') then
 304         --start nmi handling...
 305         fetch_inst('1');
 306         next_cycle <= N1;
 307     else
 308         fetch_inst('0');
 309         next_cycle <= T1;
 310     end if;
 311 end  procedure;
 312
 313 ---common routine for single byte instruction.
 314 procedure single_inst is
 315 begin
 316     fetch_stop;
 317     next_cycle <= T0;
 318 end  procedure;
 319
 320 procedure fetch_imm is
 321 begin
 322     d_print("immediate");
 323     fetch_next;
 324     --send data from data bus buffer.
 325     --receiver is instruction dependent.
 326     dbuf_int_oe_n <= '0';
 327     next_cycle <= T0;
 328 end  procedure;
 329
 330 procedure set_nz_from_bus is
 331 begin
 332     --status register n/z bit update.
 333     stat_bus_nz_n <= '0';
 334 end  procedure;
 335
 336 procedure set_zc_from_alu is
 337 begin
 338     --status register n/z bit update.
 339     stat_alu_we_n <= '0';
 340     stat_dec_oe_n <= '1';
 341     status_reg <= "00000011";
 342 end  procedure;
 343
 344 procedure set_nz_from_alu is
 345 begin
 346     --status register n/z/c bit update.
 347     stat_alu_we_n <= '0';
 348     stat_dec_oe_n <= '1';
 349     status_reg <= "10000010";
 350 end  procedure;
 351
 352 procedure set_nzc_from_alu is
 353 begin
 354     --status register n/z/c bit update.
 355     stat_alu_we_n <= '0';
 356     stat_dec_oe_n <= '1';
 357     status_reg <= "10000011";
 358 end  procedure;
 359
 360 procedure set_nvz_from_alu is
 361 begin
 362     --status register n/z/v bit update.
 363     stat_alu_we_n <= '0';
 364     stat_dec_oe_n <= '1';
 365     status_reg <= "11000010";
 366 end  procedure;
 367
 368 procedure set_nvzc_from_alu is
 369 begin
 370     stat_alu_we_n <= '0';
 371     stat_dec_oe_n <= '1';
 372     status_reg <= "11000011";
 373 end  procedure;
 374
 375 --flag on/off instruction
 376 procedure set_flag (int_flg : in integer; val : in std_logic) is
 377 begin
 378     stat_dec_oe_n <= '1';
 379     stat_set_flg_n <= '0';
 380     --specify which to set.
 381     status_reg(7 downto int_flg + 1)
 382         <= (others =>'0');
 383     status_reg(int_flg - 1 downto 0)
 384         <= (others =>'0');
 385     status_reg(int_flg) <= '1';
 386     stat_flg <= val;
 387 end  procedure;
 388
 389 --for sec/clc
 390 procedure set_flag0 (val : in std_logic) is
 391 begin
 392     stat_dec_oe_n <= '1';
 393     stat_set_flg_n <= '0';
 394     status_reg <= "00000001";
 395     stat_flg <= val;
 396 end  procedure;
 397
 398 procedure fetch_low is
 399 begin
 400     d_print("fetch low 2");
 401     --fetch next opcode (abs low).
 402     fetch_next;
 403     --latch abs low data.
 404     dbuf_int_oe_n <= '0';
 405     dl_al_we_n <= '0';
 406     next_cycle <= T2;
 407 end  procedure;
 408
 409 procedure abs_fetch_high is
 410 begin
 411     d_print("abs (xy) 3");
 412     dl_al_we_n <= '1';
 413
 414     --latch abs hi data.
 415     fetch_next;
 416     dbuf_int_oe_n <= '0';
 417     dl_ah_we_n <= '0';
 418     next_cycle <= T3;
 419 end  procedure;
 420
 421 procedure abs_latch_out is
 422 begin
 423     --d_print("abs 4");
 424     fetch_stop;
 425     dl_ah_we_n <= '1';
 426
 427     --latch > al/ah.
 428     dl_al_oe_n <= '0';
 429     dl_ah_oe_n <= '0';
 430 end  procedure;
 431
 432 procedure ea_x_out is
 433 begin
 434     -----calucurate and output effective addr
 435     back_oe(x_cmd, '0');
 436     abs_xy_n <= '0';
 437 end  procedure;
 438
 439 procedure ea_y_out is
 440 begin
 441     back_oe(y_cmd, '0');
 442     abs_xy_n <= '0';
 443 end  procedure;
 444
 445 --A.2. internal execution on memory data
 446
 447 procedure a2_zp is
 448 begin
 449     if exec_cycle = T1 then
 450         fetch_low;
 451     elsif exec_cycle = T2 then
 452         fetch_stop;
 453         dbuf_int_oe_n <= '0';
 454         dl_al_we_n <= '1';
 455
 456         --calc zp.
 457         dl_al_oe_n <= '0';
 458         zp_n <= '0';
 459         next_cycle <= T0;
 460     end if;
 461 end  procedure;
 462
 463 procedure a2_abs is
 464 begin
 465     if exec_cycle = T1 then
 466         fetch_low;
 467     elsif exec_cycle = T2 then
 468         abs_fetch_high;
 469     elsif exec_cycle = T3 then
 470         abs_latch_out;
 471         dbuf_int_oe_n <= '0';
 472         next_cycle <= T0;
 473     end if;
 474 end  procedure;
 475
 476 procedure a2_page_next is
 477 begin
 478     --close open gate if page boundary crossed.
 479     back_we(acc_cmd, '1');
 480     front_we(acc_cmd, '1');
 481     front_we(x_cmd, '1');
 482     front_we(y_cmd, '1');
 483 end  procedure;
 484
 485 procedure a2_abs_xy (is_x : in boolean) is
 486 begin
 487     if exec_cycle = T1 then
 488         fetch_low;
 489     elsif exec_cycle = T2 then
 490         abs_fetch_high;
 491     elsif exec_cycle = T3 then
 492         --ea calc & lda
 493         pg_next_n <= '1';
 494         abs_latch_out;
 495         if (is_x = true) then
 496             ea_x_out;
 497         else
 498             ea_y_out;
 499         end if;
 500         dbuf_int_oe_n <= '0';
 501
 502         wait_a2_abs_xy_next <= '1';
 503         next_cycle <= a2_abs_xy_next_cycle;
 504         d_print("absx step 1");
 505     elsif exec_cycle = T4 then
 506         --case page boundary crossed.
 507         --redo inst.
 508         d_print("absx 5 (page boudary crossed.)");
 509         --next page.
 510         pg_next_n <= not ea_carry;
 511         next_cycle <= T0;
 512     end if;
 513 end  procedure;
 514
 515 procedure a2_zp_xy (is_x : in boolean) is
 516 begin
 517     if exec_cycle = T1 then
 518         fetch_low;
 519     elsif exec_cycle = T2 then
 520         fetch_stop;
 521         --output BAL only
 522         dbuf_int_oe_n <= '0';
 523         dl_al_we_n <= '1';
 524
 525         --calc zp.
 526         dl_al_oe_n <= '0';
 527         zp_n <= '0';
 528         next_cycle <= T3;
 529     elsif exec_cycle = T3 then
 530         --t3 zp, xy
 531         zp_xy_n <= '0';
 532         if (is_x = true) then
 533             back_oe(x_cmd, '0');
 534         else
 535             back_oe(y_cmd, '0');
 536         end if;
 537         next_cycle <= T0;
 538     end if;
 539 end  procedure;
 540
 541 procedure a2_indir_y is
 542 begin
 543     if exec_cycle = T1 then
 544         fetch_low;
 545         --get IAL
 546         dl_al_we_n <= '0';
 547
 548     elsif exec_cycle = T2 then
 549         fetch_stop;
 550         dl_al_we_n <= '1';
 551
 552         ---address is 00:IAL
 553         --output BAL @IAL
 554         indir_y_n <= '0';
 555         dl_al_oe_n <= '0';
 556         dbuf_int_oe_n <= '0';
 557         next_cycle <= T3;
 558
 559     elsif exec_cycle = T3 then
 560         indir_y_n <= '0';
 561         dl_al_oe_n <= '0';
 562         --output BAH @IAL+1
 563         dbuf_int_oe_n <= '0';
 564         next_cycle <= T4;
 565
 566     elsif exec_cycle = T4 then
 567         dl_al_oe_n <= '1';
 568         dbuf_int_oe_n <= '1';
 569
 570         --add index y.
 571         pg_next_n <= '1';
 572         back_oe(y_cmd, '0');
 573         indir_y_n <= '0';
 574         dbuf_int_oe_n <= '0';
 575
 576         wait_a2_indir_y_next <= '1';
 577         next_cycle <= a2_indir_y_next_cycle;
 578     elsif exec_cycle = T5 then
 579         --case page boundary crossed.
 580         --redo inst.
 581         d_print("(indir), y (page boudary crossed.)");
 582         --next page.
 583         pg_next_n <= not ea_carry;
 584         next_cycle <= T0;
 585     end if;
 586 end  procedure;
 587
 588 --A.3. store operation.
 589
 590 procedure a3_zp is
 591 begin
 592     if exec_cycle = T1 then
 593         fetch_low;
 594     elsif exec_cycle = T2 then
 595         fetch_stop;
 596         dbuf_int_oe_n <= '1';
 597         dl_al_we_n <= '1';
 598
 599         --calc zp.
 600         dl_al_oe_n <= '0';
 601         zp_n <= '0';
 602         r_nw <= '0';
 603         next_cycle <= T0;
 604     end if;
 605 end  procedure;
 606
 607 procedure a3_abs is
 608 begin
 609     if exec_cycle = T1 then
 610         fetch_low;
 611     elsif exec_cycle = T2 then
 612         abs_fetch_high;
 613     elsif exec_cycle = T3 then
 614         abs_latch_out;
 615         dbuf_int_oe_n <= '1';
 616         r_nw <= '0';
 617         next_cycle <= T0;
 618     end if;
 619 end  procedure;
 620
 621 procedure a3_abs_xy (is_x : in boolean) is
 622 begin
 623     if exec_cycle = T1 then
 624         fetch_low;
 625     elsif exec_cycle = T2 then
 626         abs_fetch_high;
 627     elsif exec_cycle = T3 then
 628         --ea calc & lda
 629         pg_next_n <= '1';
 630         abs_latch_out;
 631         dbuf_int_oe_n <= '1';
 632         if (is_x = true) then
 633             ea_x_out;
 634         else
 635             ea_y_out;
 636         end if;
 637         next_cycle <= T4;
 638     elsif exec_cycle = T4 then
 639         pg_next_n <= not ea_carry;
 640         abs_latch_out;
 641         if (is_x = true) then
 642             ea_x_out;
 643         else
 644             ea_y_out;
 645         end if;
 646         r_nw <= '0';
 647         next_cycle <= T0;
 648     end if;
 649 end  procedure;
 650
 651
 652 procedure a3_indir_y is
 653 begin
 654     if exec_cycle = T1 then
 655         fetch_low;
 656         --get IAL
 657         dl_al_we_n <= '0';
 658
 659     elsif exec_cycle = T2 then
 660         fetch_stop;
 661         dl_al_we_n <= '1';
 662
 663         ---address is 00:IAL
 664         --output BAL @IAL
 665         indir_y_n <= '0';
 666         dl_al_oe_n <= '0';
 667         dbuf_int_oe_n <= '0';
 668         next_cycle <= T3;
 669
 670     elsif exec_cycle = T3 then
 671         indir_y_n <= '0';
 672         dl_al_oe_n <= '0';
 673         --output BAH @IAL+1
 674         dbuf_int_oe_n <= '0';
 675         next_cycle <= T4;
 676
 677     elsif exec_cycle = T4 then
 678         dl_al_oe_n <= '1';
 679         dbuf_int_oe_n <= '1';
 680
 681         --add index y.
 682         pg_next_n <= '1';
 683         back_oe(y_cmd, '0');
 684         indir_y_n <= '0';
 685         next_cycle <= T5;
 686
 687     elsif exec_cycle = T5 then
 688         --page handling.
 689         back_oe(y_cmd, '1');
 690         indir_y_n <= '0';
 691         pg_next_n <= not ea_carry;
 692         r_nw <= '0';
 693         next_cycle <= T0;
 694     end if;
 695 end  procedure;
 696
 697
 698 ---A.4. read-modify-write operation
 699
 700 procedure a4_zp is
 701 begin
 702     if exec_cycle = T1 then
 703         fetch_low;
 704     elsif exec_cycle = T2 then
 705         fetch_stop;
 706         dbuf_int_oe_n <= '1';
 707         dl_al_we_n <= '1';
 708
 709         --t2 cycle only read
 710         dl_al_oe_n <= '0';
 711         zp_n <= '0';
 712         next_cycle <= T3;
 713     elsif exec_cycle = T3 then
 714         dl_al_oe_n <= '0';
 715         zp_n <= '0';
 716         --keep data in the alu reg.
 717         arith_en_n <= '0';
 718         dbuf_int_oe_n <= '0';
 719         next_cycle <= T4;
 720     elsif exec_cycle = T4 then
 721         dbuf_int_oe_n <= '1';
 722
 723         --t5 cycle writes modified value.
 724         dl_al_oe_n <= '0';
 725         zp_n <= '0';
 726         r_nw <= '0';
 727         arith_en_n <= '0';
 728         next_cycle <= T0;
 729     end if;
 730 end  procedure;
 731
 732
 733 procedure a4_abs is
 734 begin
 735     if exec_cycle = T1 then
 736         fetch_low;
 737     elsif exec_cycle = T2 then
 738         abs_fetch_high;
 739     elsif exec_cycle = T3 then
 740         --T3 cycle do nothing.
 741         abs_latch_out;
 742         next_cycle <= T4;
 743     elsif exec_cycle = T4 then
 744         abs_latch_out;
 745
 746         --t4 cycle save data in the alu register only.
 747         --hardware maunual says write original data,
 748         --but this implementation doesn't write because bus shortage....
 749         arith_en_n <= '0';
 750         next_cycle <= T5;
 751     elsif exec_cycle = T5 then
 752         dbuf_int_oe_n <= '1';
 753
 754         --t5 cycle writes modified value.
 755         r_nw <= '0';
 756         arith_en_n <= '0';
 757         next_cycle <= T0;
 758     end if;
 759 end  procedure;
 760
 761 procedure a4_abs_x is
 762 begin
 763     if exec_cycle = T1 then
 764         fetch_low;
 765     elsif exec_cycle = T2 then
 766         abs_fetch_high;
 767     elsif exec_cycle = T3 then
 768         --T3 cycle discarded.
 769         pg_next_n <= '1';
 770         abs_latch_out;
 771         ea_x_out;
 772         dbuf_int_oe_n <= '0';
 773         next_cycle <= T4;
 774
 775     elsif exec_cycle = T4 then
 776         --t4 cycle fetch only.
 777         abs_latch_out;
 778         ea_x_out;
 779         pg_next_n <= not ea_carry;
 780         next_cycle <= T5;
 781
 782     elsif exec_cycle = T5 then
 783         --t4 cycle redo fetch and save data in the alu register only.
 784         arith_en_n <= '0';
 785         next_cycle <= T6;
 786
 787     elsif exec_cycle = T6 then
 788         --t5 cycle writes modified value.
 789         r_nw <= '0';
 790         arith_en_n <= '0';
 791         dbuf_int_oe_n <= '1';
 792         next_cycle <= T0;
 793
 794     end if;
 795 end  procedure;
 796
 797
 798 -- A.5.1 push stack
 799 procedure a51_push is
 800 begin
 801     if exec_cycle = T1 then
 802         fetch_stop;
 803         next_cycle <= T2;
 804     elsif exec_cycle = T2 then
 805         back_oe(sp_cmd, '0');
 806         back_we(sp_cmd, '0');
 807         sp_push_n <= '0';
 808         sp_oe_n <= '0';
 809         r_nw <= '0';
 810         next_cycle <= T0;
 811     end if;
 812 end procedure;
 813
 814 -- A.5.2 pull stack
 815 procedure a52_pull is
 816 begin
 817     if exec_cycle = T1 then
 818         fetch_stop;
 819         next_cycle <= T2;
 820
 821     elsif exec_cycle = T2 then
 822         --stack decrement first.
 823         back_oe(sp_cmd, '0');
 824         back_we(sp_cmd, '0');
 825         sp_pop_n <= '0';
 826         sp_oe_n <= '0';
 827         next_cycle <= T3;
 828
 829     elsif exec_cycle = T3 then
 830         sp_pop_n <= '1';
 831         back_we(sp_cmd, '1');
 832
 833         ---pop data from stack.
 834         back_oe(sp_cmd, '0');
 835         sp_oe_n <= '0';
 836         dbuf_int_oe_n <= '0';
 837         next_cycle <= T0;
 838     end if;
 839 end procedure;
 840
 841
 842 -- A.5.8 branch operations
 843
 844 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 845 begin
 846     if exec_cycle = T1 then
 847         fetch_next;
 848         if status_reg(int_flg) = br_cond then
 849             d_print("get rel");
 850
 851             --latch rel value.
 852             dbuf_int_oe_n <= '0';
 853             dl_ah_we_n <= '0';
 854             next_cycle <= T2;
 855         else
 856             d_print("no branch");
 857             next_cycle <= T0;
 858         end if;
 859     elsif exec_cycle = T2 then
 860         d_print("rel ea");
 861         fetch_stop;
 862         dbuf_int_oe_n <= '1';
 863         dl_ah_we_n <= '1';
 864
 865         --calc relative addr.
 866         rel_calc_n <= '0';
 867         pg_next_n <= '1';
 868         dl_dh_oe_n <= '0';
 869         back_oe(pcl_cmd, '0');
 870         back_oe(pch_cmd, '0');
 871         back_we(pcl_cmd, '0');
 872
 873         next_cycle <= T3;
 874     elsif exec_cycle = T3 then
 875         if ea_carry = '1' then
 876             d_print("page crossed.");
 877             --page crossed. adh calc.
 878             back_we(pcl_cmd, '1');
 879             back_oe(pcl_cmd, '0');
 880             back_oe(pch_cmd, '0');
 881             back_we(pch_cmd, '0');
 882             dl_dh_oe_n <= '0';
 883
 884             rel_calc_n <= '0';
 885             pg_next_n <= not ea_carry;
 886             next_cycle <= T0;
 887         else
 888             --no page boundary.
 889             --fetch cycle is done.
 890             t0_cycle;
 891         end if;
 892     end if;
 893 end  procedure;
 894
 895 -------------------------------------------------------------
 896 -------------------------------------------------------------
 897 ---------------- main state machine start.... ---------------
 898 -------------------------------------------------------------
 899 -------------------------------------------------------------
 900     begin
 901
 902         if (res_n = '0') then
 903             --pc l/h is reset vector.
 904             pcl_cmd <= "1110";
 905             pch_cmd <= "1110";
 906             next_cycle <= R0;
 907         elsif (res_n'event and res_n = '1') then
 908             pcl_cmd <= "1111";
 909             pch_cmd <= "1111";
 910         end if;
 911
 912         if (nmi_n'event and nmi_n = '1') then
 913             --reset nmi handle status
 914             nmi_handled_n <= '1';
 915         end if;
 916
 917
 918         if (a2_abs_xy_next_cycle'event) then
 919             if (wait_a2_abs_xy_next = '1') then
 920                 d_print("absx step 2");
 921                 next_cycle <= a2_abs_xy_next_cycle;
 922                 if (ea_carry = '1') then
 923                     a2_page_next;
 924                 end if;
 925             end if;
 926         end if;
 927
 928         if (a2_indir_y_next_cycle'event) then
 929             if (wait_a2_indir_y_next = '1') then
 930                 next_cycle <= a2_indir_y_next_cycle;
 931                 if (ea_carry = '1') then
 932                     a2_page_next;
 933                 end if;
 934             end if;
 935         end if;
 936
 937         if (set_clk'event and set_clk = '1' and res_n = '1') then
 938             d_print(string'("-"));
 939
 940             if exec_cycle = T0 then
 941                 --cycle #1
 942                 t0_cycle;
 943
 944             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 945                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
 946                 --execute inst.
 947
 948                 ---asyncronous page change might happen.
 949                 back_we(pch_cmd, '1');
 950
 951                 if exec_cycle = T1 then
 952                     d_print("decode and execute inst: "
 953                             & conv_hex8(conv_integer(instruction)));
 954                     --disable pin for jmp instruction
 955                     dl_al_oe_n <= '1';
 956                     back_we(pcl_cmd, '1');
 957                     front_we(pch_cmd, '1');
 958
 959                     --grab instruction register data.
 960                     inst_we_n <= '1';
 961                 end if;
 962
 963                 --imelementation is wriiten in the order of hardware manual
 964                 --appendix A.
 965
 966                 ----------------------------------------
 967                 --A.1. Single byte instruction.
 968                 ----------------------------------------
 969                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 970                     --asl acc mode.
 971                     d_print("asl");
 972                     arith_en_n <= '0';
 973                     back_oe(acc_cmd, '0');
 974                     front_we(acc_cmd, '0');
 975                     set_nzc_from_alu;
 976                     single_inst;
 977
 978                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 979                     d_print("clc");
 980                     set_flag0 ('0');
 981                     single_inst;
 982
 983                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 984                     d_print("cld");
 985                     set_flag (st_D, '0');
 986                     single_inst;
 987
 988                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 989                     d_print("cli");
 990                     set_flag (st_I, '0');
 991                     single_inst;
 992
 993                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 994                     d_print("clv");
 995                     set_flag (st_V, '0');
 996                     single_inst;
 997
 998                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 999                     d_print("dex");
1000                     arith_en_n <= '0';
1001                     back_oe(x_cmd, '0');
1002                     front_we(x_cmd, '0');
1003                     --set nz bit.
1004                     set_nz_from_bus;
1005                     single_inst;
1006
1007                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1008                     d_print("dey");
1009                     arith_en_n <= '0';
1010                     back_oe(y_cmd, '0');
1011                     front_we(y_cmd, '0');
1012                     --set nz bit.
1013                     set_nz_from_bus;
1014                     single_inst;
1015
1016                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1017                     d_print("inx");
1018                     arith_en_n <= '0';
1019                     back_oe(x_cmd, '0');
1020                     front_we(x_cmd, '0');
1021                     --set nz bit.
1022                     set_nz_from_bus;
1023                     single_inst;
1024
1025                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1026                     d_print("iny");
1027                     arith_en_n <= '0';
1028                     back_oe(y_cmd, '0');
1029                     front_we(y_cmd, '0');
1030                     set_nz_from_bus;
1031                     single_inst;
1032
1033                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1034                     --lsr acc mode
1035                     d_print("lsr");
1036                     arith_en_n <= '0';
1037                     back_oe(acc_cmd, '0');
1038                     front_we(acc_cmd, '0');
1039                     set_zc_from_alu;
1040                     single_inst;
1041
1042                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1043                     d_print("nop");
1044                     single_inst;
1045
1046                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1047                     --rol acc
1048                     d_print("rol");
1049                     arith_en_n <= '0';
1050                     back_oe(acc_cmd, '0');
1051                     front_we(acc_cmd, '0');
1052                     set_nzc_from_alu;
1053                     single_inst;
1054
1055                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1056                     --ror acc
1057                     d_print("ror");
1058                     arith_en_n <= '0';
1059                     back_oe(acc_cmd, '0');
1060                     front_we(acc_cmd, '0');
1061                     set_nzc_from_alu;
1062                     single_inst;
1063
1064                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1065                     d_print("sec");
1066                     set_flag0 ('1');
1067                     single_inst;
1068
1069                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1070                     d_print("sed");
1071                     set_flag (st_D, '1');
1072                     single_inst;
1073
1074                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1075                     d_print("sei");
1076                     set_flag (st_I, '1');
1077                     single_inst;
1078
1079                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1080                     d_print("tax");
1081                     set_nz_from_bus;
1082                     single_inst;
1083                     front_oe(acc_cmd, '0');
1084                     front_we(x_cmd, '0');
1085
1086                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1087                     d_print("tay");
1088                     set_nz_from_bus;
1089                     single_inst;
1090                     front_oe(acc_cmd, '0');
1091                     front_we(y_cmd, '0');
1092
1093                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1094                     d_print("tsx");
1095                     set_nz_from_bus;
1096
1097                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1098                     d_print("txa");
1099                     set_nz_from_bus;
1100                     single_inst;
1101                     front_oe(x_cmd, '0');
1102                     front_we(acc_cmd, '0');
1103
1104                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1105                     d_print("txs");
1106                     set_nz_from_bus;
1107                     single_inst;
1108                     front_oe(x_cmd, '0');
1109                     front_we(sp_cmd, '0');
1110
1111                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1112                     d_print("tya");
1113                     set_nz_from_bus;
1114                     single_inst;
1115                     front_oe(y_cmd, '0');
1116                     front_we(acc_cmd, '0');
1117
1118
1119
1120                 ----------------------------------------
1121                 --A.2. internal execution on memory data
1122                 ----------------------------------------
1123                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1124                     --imm
1125                     d_print("adc");
1126                     fetch_imm;
1127                     arith_en_n <= '0';
1128                     back_oe(acc_cmd, '0');
1129                     back_we(acc_cmd, '0');
1130                     set_nvzc_from_alu;
1131
1132                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1133                     --zp
1134                     d_print("adc");
1135                     a2_zp;
1136                     if exec_cycle = T2 then
1137                         arith_en_n <= '0';
1138                         back_oe(acc_cmd, '0');
1139                         back_we(acc_cmd, '0');
1140                         set_nvzc_from_alu;
1141                     end if;
1142
1143                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1144                     --zp, x
1145                     d_print("adc");
1146                     a2_zp_xy(true);
1147                     if exec_cycle = T3 then
1148                         arith_en_n <= '0';
1149                         back_oe(acc_cmd, '0');
1150                         back_we(acc_cmd, '0');
1151                         set_nvzc_from_alu;
1152                     end if;
1153
1154                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1155                     --abs
1156                     d_print("adc");
1157                     a2_abs;
1158                     if exec_cycle = T3 then
1159                         arith_en_n <= '0';
1160                         back_oe(acc_cmd, '0');
1161                         back_we(acc_cmd, '0');
1162                         set_nvzc_from_alu;
1163                     end if;
1164
1165                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1166                     --abs, x
1167                     d_print("adc");
1168                     a2_abs_xy(true);
1169                     if exec_cycle = T3 or exec_cycle = T4 then
1170                         arith_en_n <= '0';
1171                         back_oe(acc_cmd, '0');
1172                         back_we(acc_cmd, '0');
1173                         set_nvzc_from_alu;
1174                     end if;
1175
1176                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1177                     --abs, y
1178                     d_print("adc");
1179                     a2_abs_xy(false);
1180                     if exec_cycle = T3 or exec_cycle = T4 then
1181                         arith_en_n <= '0';
1182                         back_oe(acc_cmd, '0');
1183                         back_we(acc_cmd, '0');
1184                         set_nvzc_from_alu;
1185                     end if;
1186
1187                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1188                     --(indir, x)
1189                     d_print("adc");
1190
1191                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1192                     --(indir), y
1193                     d_print("adc");
1194                     a2_indir_y;
1195                     if exec_cycle = T4 or exec_cycle = T5 then
1196                         arith_en_n <= '0';
1197                         back_oe(acc_cmd, '0');
1198                         back_we(acc_cmd, '0');
1199                         set_nvzc_from_alu;
1200                     end if;
1201
1202                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1203                     --imm
1204                     d_print("and");
1205                     fetch_imm;
1206                     arith_en_n <= '0';
1207                     back_oe(acc_cmd, '0');
1208                     back_we(acc_cmd, '0');
1209                     set_nz_from_alu;
1210
1211                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1212                     --zp
1213                     d_print("and");
1214                     a2_zp;
1215                     if exec_cycle = T2 then
1216                         arith_en_n <= '0';
1217                         back_oe(acc_cmd, '0');
1218                         back_we(acc_cmd, '0');
1219                         set_nz_from_alu;
1220                     end if;
1221
1222                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1223                     --zp, x
1224                     d_print("and");
1225                     a2_zp_xy(true);
1226                     if exec_cycle = T3 then
1227                         arith_en_n <= '0';
1228                         back_oe(acc_cmd, '0');
1229                         back_we(acc_cmd, '0');
1230                         set_nz_from_alu;
1231                     end if;
1232
1233                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1234                     --abs
1235                     d_print("and");
1236                     a2_abs;
1237                     if exec_cycle = T3 then
1238                         arith_en_n <= '0';
1239                         back_oe(acc_cmd, '0');
1240                         back_we(acc_cmd, '0');
1241                         set_nz_from_alu;
1242                     end if;
1243
1244                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1245                     --abs, x
1246                     d_print("and");
1247                     a2_abs_xy(true);
1248                     if exec_cycle = T3 or exec_cycle = T4 then
1249                         arith_en_n <= '0';
1250                         back_oe(acc_cmd, '0');
1251                         back_we(acc_cmd, '0');
1252                         set_nz_from_alu;
1253                     end if;
1254
1255                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1256                     --abs, y
1257                     d_print("and");
1258                     a2_abs_xy(false);
1259                     if exec_cycle = T3 or exec_cycle = T4 then
1260                         arith_en_n <= '0';
1261                         back_oe(acc_cmd, '0');
1262                         back_we(acc_cmd, '0');
1263                         set_nz_from_alu;
1264                     end if;
1265
1266                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1267                     --(indir, x)
1268                     d_print("and");
1269
1270                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1271                     --(indir), y
1272                     d_print("and");
1273                     a2_indir_y;
1274                     if exec_cycle = T4 or exec_cycle = T5 then
1275                         arith_en_n <= '0';
1276                         back_oe(acc_cmd, '0');
1277                         back_we(acc_cmd, '0');
1278                         set_nz_from_alu;
1279                     end if;
1280
1281                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1282                     --zp
1283                     d_print("bit");
1284                     a2_zp;
1285                     if exec_cycle = T2 then
1286                         arith_en_n <= '0';
1287                         back_oe(acc_cmd, '0');
1288                         set_nvz_from_alu;
1289                     end if;
1290
1291                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1292                     --abs
1293                     d_print("bit");
1294                     a2_abs;
1295                     if exec_cycle = T3 then
1296                         arith_en_n <= '0';
1297                         back_oe(acc_cmd, '0');
1298                         set_nvz_from_alu;
1299                     end if;
1300
1301                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1302                     --imm
1303                     d_print("cmp");
1304                     fetch_imm;
1305                     arith_en_n <= '0';
1306                     back_oe(acc_cmd, '0');
1307                     set_nzc_from_alu;
1308
1309                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1310                     --zp
1311                     d_print("cmp");
1312                     a2_zp;
1313                     if exec_cycle = T2 then
1314                         arith_en_n <= '0';
1315                         back_oe(acc_cmd, '0');
1316                         set_nzc_from_alu;
1317                     end if;
1318
1319                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1320                     --zp, x
1321                     d_print("cmp");
1322
1323                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1324                     --abs
1325                     d_print("cmp");
1326
1327                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1328                     --abs, x
1329                     d_print("cmp");
1330
1331                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1332                     --abs, y
1333                     d_print("cmp");
1334                     a2_abs_xy(false);
1335                     if exec_cycle = T3 or exec_cycle = T4 then
1336                         arith_en_n <= '0';
1337                         back_oe(acc_cmd, '0');
1338                         set_nzc_from_alu;
1339                     end if;
1340
1341                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1342                     --(indir, x)
1343                     d_print("cmp");
1344
1345                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1346                     --(indir), y
1347                     d_print("cmp");
1348
1349                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1350                     --imm
1351                     d_print("cpx");
1352                     fetch_imm;
1353                     arith_en_n <= '0';
1354                     back_oe(x_cmd, '0');
1355                     set_nzc_from_alu;
1356
1357                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1358                     --zp
1359                     d_print("cpx");
1360                     a2_zp;
1361                     if exec_cycle = T2 then
1362                         arith_en_n <= '0';
1363                         back_oe(x_cmd, '0');
1364                         set_nzc_from_alu;
1365                     end if;
1366
1367                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1368                     --abs
1369                     d_print("cpx");
1370
1371                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1372                     --imm
1373                     d_print("cpy");
1374                     fetch_imm;
1375                     arith_en_n <= '0';
1376                     back_oe(y_cmd, '0');
1377                     set_nzc_from_alu;
1378
1379                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1380                     --zp
1381                     d_print("cpy");
1382
1383                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1384                     --abs
1385                     d_print("cpy");
1386
1387                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1388                     --imm
1389                     d_print("eor");
1390                     fetch_imm;
1391                     arith_en_n <= '0';
1392                     back_oe(acc_cmd, '0');
1393                     back_we(acc_cmd, '0');
1394                     set_nz_from_alu;
1395
1396                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1397                     --zp
1398                     d_print("eor");
1399                     a2_zp;
1400                     if exec_cycle = T2 then
1401                         arith_en_n <= '0';
1402                         back_oe(acc_cmd, '0');
1403                         back_we(acc_cmd, '0');
1404                         set_nz_from_alu;
1405                     end if;
1406
1407                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1408                     --zp, x
1409                     d_print("eor");
1410
1411                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1412                     --abs
1413                     d_print("eor");
1414
1415                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1416                     --abs, x
1417                     d_print("eor");
1418
1419                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1420                     --abs, y
1421                     d_print("eor");
1422
1423                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1424                     --(indir, x)
1425                     d_print("eor");
1426
1427                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1428                     --(indir), y
1429                     d_print("eor");
1430
1431                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1432                     --imm
1433                     d_print("lda");
1434                     fetch_imm;
1435                     front_we(acc_cmd, '0');
1436                     set_nz_from_bus;
1437
1438                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1439                     --zp
1440                     d_print("lda");
1441                     a2_zp;
1442                     if exec_cycle = T2 then
1443                         front_we(acc_cmd, '0');
1444                         set_nz_from_bus;
1445                     end if;
1446
1447                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1448                     --zp, x
1449                     d_print("lda");
1450                     a2_zp_xy(true);
1451                     if exec_cycle = T3 then
1452                         front_we(acc_cmd, '0');
1453                         set_nz_from_bus;
1454                     end if;
1455
1456                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1457                     --abs
1458                     d_print("lda");
1459                     a2_abs;
1460                     if exec_cycle = T3 then
1461                         set_nz_from_bus;
1462                         front_we(acc_cmd, '0');
1463                     end if;
1464
1465                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1466                     --abs, x
1467                     d_print("lda");
1468                     a2_abs_xy(true);
1469                     if exec_cycle = T3 or exec_cycle = T4 then
1470                         --lda.
1471                         front_we(acc_cmd, '0');
1472                         set_nz_from_bus;
1473                     end if;
1474
1475                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1476                     --abs, y
1477                     d_print("lda");
1478                     a2_abs_xy(false);
1479                     if exec_cycle = T3 or exec_cycle = T4 then
1480                         --lda.
1481                         front_we(acc_cmd, '0');
1482                         set_nz_from_bus;
1483                     end if;
1484
1485                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1486                     --(indir, x)
1487                     d_print("lda");
1488
1489                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1490                     --(indir), y
1491                     d_print("lda");
1492                     a2_indir_y;
1493                     if exec_cycle = T4 or exec_cycle = T5 then
1494                         --lda.
1495                         front_we(acc_cmd, '0');
1496                         set_nz_from_bus;
1497                     end if;
1498
1499                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1500                     --imm
1501                     d_print("ldx");
1502                     fetch_imm;
1503                     set_nz_from_bus;
1504                     front_we(x_cmd, '0');
1505
1506                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1507                     --zp
1508                     d_print("ldx");
1509                     a2_zp;
1510                     if exec_cycle = T2 then
1511                         front_we(x_cmd, '0');
1512                         set_nz_from_bus;
1513                     end if;
1514
1515                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1516                     --zp, y
1517                     d_print("ldx");
1518
1519                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1520                     --abs
1521                     d_print("ldx");
1522                     a2_abs;
1523                     if exec_cycle = T3 then
1524                         set_nz_from_bus;
1525                         front_we(x_cmd, '0');
1526                     end if;
1527
1528                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1529                     --abs, y
1530                     d_print("ldx");
1531                     a2_abs_xy(false);
1532                     if exec_cycle = T3 or exec_cycle = T4 then
1533                         front_we(x_cmd, '0');
1534                         set_nz_from_bus;
1535                     end if;
1536
1537                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1538                     --imm
1539                     d_print("ldy");
1540                     fetch_imm;
1541                     set_nz_from_bus;
1542                     front_we(y_cmd, '0');
1543
1544                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1545                     --zp
1546                     d_print("ldy");
1547                     a2_zp;
1548                     if exec_cycle = T2 then
1549                         front_we(y_cmd, '0');
1550                         set_nz_from_bus;
1551                     end if;
1552
1553                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1554                     --zp, x
1555                     d_print("ldy");
1556                     a2_zp_xy(true);
1557                     if exec_cycle = T3 then
1558                         front_we(y_cmd, '0');
1559                         set_nz_from_bus;
1560                     end if;
1561
1562                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1563                     --abs
1564                     d_print("ldy");
1565                     a2_abs;
1566                     if exec_cycle = T3 then
1567                         set_nz_from_bus;
1568                         front_we(y_cmd, '0');
1569                     end if;
1570
1571                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1572                     --abs, x
1573                     d_print("ldy");
1574
1575                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1576                     --imm
1577                     d_print("ora");
1578                     fetch_imm;
1579                     arith_en_n <= '0';
1580                     back_oe(acc_cmd, '0');
1581                     back_we(acc_cmd, '0');
1582                     set_nz_from_alu;
1583
1584                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1585                     --zp
1586                     d_print("ora");
1587                     a2_zp;
1588                     if exec_cycle = T2 then
1589                         arith_en_n <= '0';
1590                         back_oe(acc_cmd, '0');
1591                         back_we(acc_cmd, '0');
1592                         set_nz_from_alu;
1593                     end if;
1594
1595                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1596                     --zp, x
1597                     d_print("ora");
1598
1599                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1600                     --abs
1601                     d_print("ora");
1602
1603                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1604                     --abs, x
1605                     d_print("ora");
1606
1607                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1608                     --abs, y
1609                     d_print("ora");
1610
1611                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1612                     --(indir, x)
1613                     d_print("ora");
1614
1615                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1616                     --(indir), y
1617                     d_print("ora");
1618
1619                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1620                     --imm
1621                     d_print("sbc");
1622                     fetch_imm;
1623                     arith_en_n <= '0';
1624                     back_oe(acc_cmd, '0');
1625                     back_we(acc_cmd, '0');
1626                     set_nvzc_from_alu;
1627
1628                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1629                     --zp
1630                     d_print("sbc");
1631
1632                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1633                     --zp, x
1634                     d_print("sbc");
1635
1636                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1637                     --abs
1638                     d_print("sbc");
1639
1640                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1641                     --abs, x
1642                     d_print("sbc");
1643
1644                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1645                     --abs, y
1646                     d_print("sbc");
1647                     a2_abs_xy(false);
1648                     if exec_cycle = T3 or exec_cycle = T4 then
1649                         arith_en_n <= '0';
1650                         back_oe(acc_cmd, '0');
1651                         back_we(acc_cmd, '0');
1652                         set_nvzc_from_alu;
1653                     end if;
1654
1655                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
1656                     --(indir, x)
1657                     d_print("sbc");
1658
1659                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
1660                     --(indir), y
1661                     d_print("sbc");
1662
1663
1664
1665                 ----------------------------------------
1666                 ---A.3. store operation.
1667                 ----------------------------------------
1668                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
1669                     --zp
1670                     d_print("sta");
1671                     a3_zp;
1672                     if exec_cycle = T2 then
1673                         front_oe(acc_cmd, '0');
1674                     end if;
1675
1676                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
1677                     --zp, x
1678                     d_print("sta");
1679
1680                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
1681                     --abs
1682                     d_print("sta");
1683                     a3_abs;
1684                     if exec_cycle = T3 then
1685                         front_oe(acc_cmd, '0');
1686                     end if;
1687
1688                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
1689                     --abs, x
1690                     d_print("sta");
1691                     a3_abs_xy (true);
1692                     if exec_cycle = T4 then
1693                         front_oe(acc_cmd, '0');
1694                     end if;
1695
1696                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
1697                     --abs, y
1698                     d_print("sta");
1699                     a3_abs_xy (false);
1700                     if exec_cycle = T4 then
1701                         front_oe(acc_cmd, '0');
1702                     end if;
1703
1704                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
1705                     --(indir, x)
1706                     d_print("sta");
1707
1708                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
1709                     --(indir), y
1710                     d_print("sta");
1711                     a3_indir_y;
1712                     if exec_cycle = T5 then
1713                         front_oe(acc_cmd, '0');
1714                     end if;
1715
1716                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
1717                     --zp
1718                     d_print("stx");
1719                     a3_zp;
1720                     if exec_cycle = T2 then
1721                         front_oe(x_cmd, '0');
1722                     end if;
1723
1724                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
1725                     --zp, y
1726                     d_print("stx");
1727
1728                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
1729                     --abs
1730                     d_print("stx");
1731                     a3_abs;
1732                     if exec_cycle = T3 then
1733                         front_oe(x_cmd, '0');
1734                     end if;
1735
1736                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
1737                     --zp
1738                     d_print("sty");
1739                     a3_zp;
1740                     if exec_cycle = T2 then
1741                         front_oe(y_cmd, '0');
1742                     end if;
1743
1744                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
1745                     --zp, x
1746                     d_print("sty");
1747
1748                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
1749                     --abs
1750                     d_print("sty");
1751                     a3_abs;
1752                     if exec_cycle = T3 then
1753                         front_oe(y_cmd, '0');
1754                     end if;
1755
1756
1757                 ----------------------------------------
1758                 ---A.4. read-modify-write operation
1759                 ----------------------------------------
1760                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
1761                     --zp
1762                     d_print("asl");
1763
1764                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
1765                     --zp, x
1766                     d_print("asl");
1767
1768                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
1769                     --abs
1770                     d_print("asl");
1771
1772                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
1773                     --abs, x
1774                     d_print("asl");
1775
1776                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
1777                     --zp
1778                     d_print("dec");
1779                     a4_zp;
1780                     if exec_cycle = T4 then
1781                         set_nz_from_bus;
1782                     end if;
1783
1784                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
1785                     --zp, x
1786                     d_print("dec");
1787
1788                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
1789                     --abs
1790                     d_print("dec");
1791                     a4_abs;
1792                     if exec_cycle = T5 then
1793                         set_nz_from_bus;
1794                     end if;
1795
1796                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
1797                     --abs, x
1798                     d_print("dec");
1799
1800                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
1801                     --zp
1802                     d_print("inc");
1803                     a4_zp;
1804                     if exec_cycle = T4 then
1805                         set_nz_from_bus;
1806                     end if;
1807
1808                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
1809                     --zp, x
1810                     d_print("inc");
1811
1812                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
1813                     --abs
1814                     d_print("inc");
1815                     a4_abs;
1816                     if exec_cycle = T5 then
1817                         set_nz_from_bus;
1818                     end if;
1819
1820                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
1821                     --abs, x
1822                     d_print("inc");
1823
1824                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
1825                     --zp
1826                     d_print("lsr");
1827
1828                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
1829                     --zp, x
1830                     d_print("lsr");
1831
1832                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
1833                     --abs
1834                     d_print("lsr");
1835
1836                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
1837                     --abs, x
1838                     d_print("lsr");
1839
1840                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
1841                     --zp
1842                     d_print("rol");
1843
1844                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
1845                     --zp, x
1846                     d_print("rol");
1847
1848                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
1849                     --abs
1850                     d_print("rol");
1851
1852                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
1853                     --abs, x
1854                     d_print("rol");
1855
1856                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
1857                     --zp
1858                     d_print("ror");
1859 --                    a4_zp;
1860 --                    if exec_cycle = T4 then
1861 --                        set_nzc_from_alu;
1862 --                    end if;
1863
1864                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
1865                     --zp, x
1866                     d_print("ror");
1867
1868                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
1869                     --abs
1870                     d_print("ror");
1871
1872                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
1873                     --abs, x
1874                     d_print("ror");
1875                     a4_abs_x;
1876                     if exec_cycle = T6 then
1877                         set_nzc_from_alu;
1878                     end if;
1879
1880
1881                 ----------------------------------------
1882                 --A.5. miscellaneous oprations.
1883                 ----------------------------------------
1884
1885                 -- A.5.1 push/pull
1886                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1887                     d_print("php");
1888
1889                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1890                     d_print("pha");
1891                     a51_push;
1892                     if exec_cycle = T2 then
1893                         front_oe(acc_cmd, '0');
1894                     end if;
1895
1896                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1897                     d_print("plp");
1898
1899                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1900                     d_print("pla");
1901                     a52_pull;
1902                     if exec_cycle = T3 then
1903                         front_we(acc_cmd, '0');
1904                     end if;
1905
1906
1907                 ----------------------------------------
1908                 -- A.5.3 jsr
1909                 ----------------------------------------
1910                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1911                     if exec_cycle = T1 then
1912                         d_print("jsr abs 2");
1913                         --fetch opcode.
1914                         fetch_next;
1915                         dbuf_int_oe_n <= '0';
1916                         --latch adl
1917                         dl_al_we_n <= '0';
1918                         next_cycle <= T2;
1919                     elsif exec_cycle = T2 then
1920                         d_print("jsr 3");
1921                         fetch_stop;
1922                         dbuf_int_oe_n <= '1';
1923                         dl_al_we_n <= '1';
1924
1925                        --push return addr high into stack.
1926                         sp_push_n <= '0';
1927                         sp_oe_n <= '0';
1928                         front_oe(pch_cmd, '0');
1929                         back_oe(sp_cmd, '0');
1930                         back_we(sp_cmd, '0');
1931                         r_nw <= '0';
1932                         next_cycle <= T3;
1933                     elsif exec_cycle = T3 then
1934                         d_print("jsr 4");
1935                         front_oe(pch_cmd, '1');
1936
1937                        --push return addr low into stack.
1938                         sp_push_n <= '0';
1939                         sp_oe_n <= '0';
1940                         front_oe(pcl_cmd, '0');
1941                         back_oe(sp_cmd, '0');
1942                         back_we(sp_cmd, '0');
1943                         r_nw <= '0';
1944
1945                         next_cycle <= T4;
1946                     elsif exec_cycle = T4 then
1947                         d_print("jsr 5");
1948                         sp_push_n <= '1';
1949                         sp_oe_n <= '1';
1950                         front_oe(pcl_cmd, '1');
1951                         back_oe(sp_cmd, '1');
1952                         back_we(sp_cmd, '1');
1953                         r_nw <= '1';
1954
1955                         --fetch last op.
1956                         back_oe(pch_cmd, '0');
1957                         back_oe(pcl_cmd, '0');
1958                         dbuf_int_oe_n <= '0';
1959                         dl_ah_we_n <= '0';
1960
1961                         next_cycle <= T5;
1962                     elsif exec_cycle = T5 then
1963                         d_print("jsr 6");
1964
1965                         back_oe(pch_cmd, '1');
1966                         back_oe(pcl_cmd, '1');
1967                         dbuf_int_oe_n <= '1';
1968                         dl_ah_we_n <= '1';
1969
1970                         --load/output  pch
1971                         ad_oe_n <= '1';
1972                         dl_dh_oe_n <= '0';
1973                         front_we(pch_cmd, '0');
1974
1975                         --load pcl.
1976                         dl_al_oe_n <= '0';
1977                         back_we(pcl_cmd, '0');
1978
1979                         next_cycle <= T0;
1980                     end if; --if exec_cycle = T1 then
1981
1982                 -- A.5.4 break
1983                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
1984
1985                 ----------------------------------------
1986                 -- A.5.5 return from interrupt
1987                 ----------------------------------------
1988                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
1989                     if exec_cycle = T1 then
1990                         d_print("rti 2");
1991                         fetch_stop;
1992
1993                         --pop stack (decrement only)
1994                         back_oe(sp_cmd, '0');
1995                         back_we(sp_cmd, '0');
1996                         sp_pop_n <= '0';
1997                         sp_oe_n <= '0';
1998
1999                         next_cycle <= T2;
2000                     elsif exec_cycle = T2 then
2001                         d_print("rti 3");
2002
2003                         --pop p (status)
2004                         back_oe(sp_cmd, '0');
2005                         back_we(sp_cmd, '0');
2006                         sp_pop_n <= '0';
2007                         sp_oe_n <= '0';
2008
2009                         --load status reg
2010                         stat_dec_oe_n <= '1';
2011                         dbuf_int_oe_n <= '0';
2012                         stat_bus_all_n <= '0';
2013
2014                         next_cycle <= T3;
2015                     elsif exec_cycle = T3 then
2016                         d_print("rti 4");
2017                         stat_bus_all_n <= '1';
2018
2019                         --pop pcl
2020                         back_oe(sp_cmd, '0');
2021                         back_we(sp_cmd, '0');
2022                         sp_pop_n <= '0';
2023                         sp_oe_n <= '0';
2024
2025                         --load lo addr.
2026                         dbuf_int_oe_n <= '0';
2027                         front_we(pcl_cmd, '0');
2028
2029                         next_cycle <= T4;
2030                     elsif exec_cycle = T4 then
2031                         d_print("rti 5");
2032                         --stack decrement stop.
2033                         back_we(sp_cmd, '1');
2034                         sp_pop_n <= '1';
2035                         front_we(pcl_cmd, '1');
2036
2037                         --pop pch
2038                         back_oe(sp_cmd, '0');
2039                         sp_oe_n <= '0';
2040                         --load hi addr.
2041                         dbuf_int_oe_n <= '0';
2042                         front_we(pch_cmd, '0');
2043
2044                         next_cycle <= T5;
2045                     elsif exec_cycle = T5 then
2046                         d_print("rti 6");
2047                         back_oe(sp_cmd, '1');
2048                         sp_oe_n <= '1';
2049                         --load hi addr.
2050                         dbuf_int_oe_n <= '1';
2051                         front_we(pch_cmd, '1');
2052
2053                         --increment pc.
2054                         next_cycle <= T0;
2055                     end if; --if exec_cycle = T1 then
2056
2057                 ----------------------------------------
2058                 -- A.5.6 jmp
2059                 ----------------------------------------
2060                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2061                     --abs
2062                     if exec_cycle = T1 then
2063                         d_print("jmp 2");
2064                         --fetch next opcode (abs low).
2065                         fetch_next;
2066
2067                         --latch abs low data.
2068                         dbuf_int_oe_n <= '0';
2069                         dl_al_we_n <= '0';
2070                         next_cycle <= T2;
2071                     elsif exec_cycle = T2 then
2072                         d_print("jmp 3");
2073                         dl_al_we_n <= '1';
2074
2075                         --fetch abs hi
2076                         fetch_next;
2077
2078                         --latch  in dlh
2079                         dbuf_int_oe_n <= '0';
2080                         dl_ah_we_n <= '0';
2081                         ---load pch.
2082                         front_we(pch_cmd, '0');
2083
2084                         next_cycle <= T0;
2085                     end if;
2086
2087                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2088                     --jmp (indir)
2089                     if exec_cycle = T1 then
2090                         d_print("jmp 2");
2091                         --fetch next opcode (abs low).
2092                         fetch_next;
2093
2094                         --latch abs low data.
2095                         dbuf_int_oe_n <= '0';
2096                         dl_al_we_n <= '0';
2097                         next_cycle <= T2;
2098                     elsif exec_cycle = T2 then
2099                         d_print("jmp 3");
2100                         dl_al_we_n <= '1';
2101
2102                         --fetch abs hi
2103                         fetch_next;
2104
2105                         --latch  in dlh
2106                         dbuf_int_oe_n <= '0';
2107                         dl_ah_we_n <= '0';
2108                         next_cycle <= T3;
2109
2110                     elsif exec_cycle = T3 then
2111                         fetch_stop;
2112                         dl_ah_we_n <= '1';
2113
2114                         --IAH/IAL > ADL
2115                         dl_ah_oe_n <= '0';
2116                         dl_al_oe_n <= '0';
2117                         front_we(pcl_cmd, '0');
2118                         next_cycle <= T4;
2119
2120                     elsif exec_cycle = T4 then
2121                         dl_ah_oe_n <= '0';
2122                         dl_al_oe_n <= '0';
2123                         front_we(pcl_cmd, '1');
2124
2125                         --IAH/IAL+1 > ADH
2126                         front_we(pch_cmd, '0');
2127                         indir_n <= '0';
2128
2129                         next_cycle <= T0;
2130
2131                     end if;
2132
2133
2134                 ----------------------------------------
2135                 -- A.5.7 return from soubroutine
2136                 ----------------------------------------
2137                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2138                     if exec_cycle = T1 then
2139                         d_print("rts 2");
2140                         fetch_stop;
2141
2142                         --pop stack (decrement only)
2143                         back_oe(sp_cmd, '0');
2144                         back_we(sp_cmd, '0');
2145                         sp_pop_n <= '0';
2146                         sp_oe_n <= '0';
2147
2148                         next_cycle <= T2;
2149                     elsif exec_cycle = T2 then
2150                         d_print("rts 3");
2151
2152                         --pop pcl
2153                         back_oe(sp_cmd, '0');
2154                         back_we(sp_cmd, '0');
2155                         sp_pop_n <= '0';
2156                         sp_oe_n <= '0';
2157
2158                         --load lo addr.
2159                         dbuf_int_oe_n <= '0';
2160                         front_we(pcl_cmd, '0');
2161
2162                         next_cycle <= T3;
2163                     elsif exec_cycle = T3 then
2164                         d_print("rts 4");
2165                         --stack decrement stop.
2166                         back_we(sp_cmd, '1');
2167                         sp_pop_n <= '1';
2168                         front_we(pcl_cmd, '1');
2169
2170                         --pop pch
2171                         back_oe(sp_cmd, '0');
2172                         sp_oe_n <= '0';
2173                         --load hi addr.
2174                         dbuf_int_oe_n <= '0';
2175                         front_we(pch_cmd, '0');
2176
2177                         next_cycle <= T4;
2178                     elsif exec_cycle = T4 then
2179                         d_print("rts 5");
2180                         back_oe(sp_cmd, '1');
2181                         sp_oe_n <= '1';
2182                         --load hi addr.
2183                         dbuf_int_oe_n <= '1';
2184                         front_we(pch_cmd, '1');
2185                         --empty cycle.
2186                         --complying h/w manual...
2187                         next_cycle <= T5;
2188                     elsif exec_cycle = T5 then
2189                         d_print("rts 6");
2190
2191                         --increment pc.
2192                         fetch_next;
2193                         next_cycle <= T0;
2194                     end if; --if exec_cycle = T1 then
2195
2196                 ----------------------------------------
2197                 -- A.5.8 branch operations
2198                 ----------------------------------------
2199                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2200                     d_print("bcc");
2201                     a58_branch (st_C, '0');
2202
2203                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2204                     d_print("bcs");
2205                     a58_branch (st_C, '1');
2206
2207                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2208                     d_print("beq");
2209                     a58_branch (st_Z, '1');
2210
2211                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2212                     d_print("bmi");
2213                     a58_branch (st_N, '1');
2214
2215                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2216                     d_print("bne");
2217                     a58_branch (st_Z, '0');
2218
2219                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2220                     d_print("bpl");
2221                     a58_branch (st_N, '0');
2222
2223                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2224                     d_print("bvc");
2225                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2226                     d_print("bvs");
2227
2228                 else
2229                     ---unknown instruction!!!!
2230                     assert false
2231                         report "======== unknow instruction "
2232                             & conv_hex8(conv_integer(instruction))
2233                         severity failure;
2234                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2235
2236             elsif exec_cycle = R0 then
2237                 d_print(string'("reset"));
2238
2239                 front_we(pch_cmd, '1');
2240                 back_we(pcl_cmd, '1');
2241
2242                 --initialize port...
2243                 inst_we_n <= '1';
2244                 ad_oe_n <= '1';
2245                 dbuf_int_oe_n <= '1';
2246                 dl_al_we_n <= '1';
2247                 dl_ah_we_n <= '1';
2248                 dl_al_oe_n <= '1';
2249                 dl_ah_oe_n <= '1';
2250                 dl_dh_oe_n <= '1';
2251                 pcl_inc_n <= '1';
2252                 pcl_cmd <= "1111";
2253                 pch_cmd <= "1111";
2254                 sp_cmd <= "1111";
2255                 sp_oe_n <= '1';
2256                 sp_push_n <= '1';
2257                 sp_pop_n <= '1';
2258                 acc_cmd <= "1111";
2259                 x_cmd <= "1111";
2260                 y_cmd <= "1111";
2261
2262                 abs_xy_n <= '1';
2263                 pg_next_n <= '1';
2264                 zp_n <= '1';
2265                 zp_xy_n <= '1';
2266                 rel_calc_n <= '1';
2267                 indir_n <= '1';
2268                 indir_x_n <= '1';
2269                 indir_y_n <= '1';
2270                 arith_en_n <= '1';
2271
2272                 stat_dec_oe_n <= '1';
2273                 stat_bus_oe_n <= '1';
2274                 stat_set_flg_n <= '1';
2275                 stat_flg <= '1';
2276                 stat_bus_all_n <= '1';
2277                 stat_bus_nz_n <= '1';
2278                 stat_alu_we_n <= '1';
2279
2280                 r_vec_oe_n <= '1';
2281                 n_vec_oe_n <= '1';
2282                 i_vec_oe_n <= '1';
2283                 nmi_handled_n <= '1';
2284                 r_nw <= '1';
2285
2286                 next_cycle <= R1;
2287             elsif exec_cycle = R1 or exec_cycle = N1 then
2288                 pcl_cmd <= "1111";
2289                 pcl_inc_n <= '1';
2290                 inst_we_n <= '1';
2291                 dl_al_oe_n <= '1';
2292
2293                 --push pch.
2294                 d_print("R1");
2295                 ad_oe_n <= '0';
2296                 sp_push_n <= '0';
2297                 sp_oe_n <= '0';
2298                 pch_cmd <= "0111";
2299                 --front_oe(pch_cmd, '0');
2300                 back_oe(sp_cmd, '0');
2301                 back_we(sp_cmd, '0');
2302                 r_nw <= '0';
2303
2304                 if exec_cycle = R1 then
2305                     next_cycle <= R2;
2306                 elsif exec_cycle = N1 then
2307                     next_cycle <= N2;
2308                 end if;
2309
2310             elsif exec_cycle = R2 or exec_cycle = N2 then
2311                 front_oe(pch_cmd, '1');
2312
2313                --push pcl.
2314                 sp_push_n <= '0';
2315                 sp_oe_n <= '0';
2316                 front_oe(pcl_cmd, '0');
2317                 back_oe(sp_cmd, '0');
2318                 back_we(sp_cmd, '0');
2319                 r_nw <= '0';
2320
2321                 if exec_cycle = R2 then
2322                     next_cycle <= R3;
2323                 elsif exec_cycle = N2 then
2324                     next_cycle <= N3;
2325                 end if;
2326
2327             elsif exec_cycle = R3 or exec_cycle = N3 then
2328                 front_oe(pcl_cmd, '1');
2329
2330                --push status.
2331                 sp_push_n <= '0';
2332                 sp_oe_n <= '0';
2333                 stat_bus_oe_n <= '0';
2334                 back_oe(sp_cmd, '0');
2335                 back_we(sp_cmd, '0');
2336                 r_nw <= '0';
2337
2338                 if exec_cycle = R3 then
2339                     next_cycle <= R4;
2340                 elsif exec_cycle = N3 then
2341                     next_cycle <= N4;
2342                 end if;
2343
2344             elsif exec_cycle = R4 or exec_cycle = N4 then
2345                 stat_bus_oe_n <= '1';
2346                 sp_push_n <= '1';
2347                 sp_oe_n <= '1';
2348                 front_oe(pcl_cmd, '1');
2349                 back_oe(sp_cmd, '1');
2350                 back_we(sp_cmd, '1');
2351
2352                 --fetch reset vector low
2353                 r_nw <= '1';
2354                 dbuf_int_oe_n <= '0';
2355                 front_we(pcl_cmd, '0');
2356
2357                 if exec_cycle = R4 then
2358                     r_vec_oe_n <= '0';
2359                     next_cycle <= R5;
2360                 elsif exec_cycle = N4 then
2361                     n_vec_oe_n <= '0';
2362                     next_cycle <= N5;
2363                 end if;
2364
2365             elsif exec_cycle = R5 or exec_cycle = N5 then
2366                 front_we(pcl_cmd, '1');
2367
2368                 --fetch reset vector hi
2369                 front_we(pch_cmd, '0');
2370                 indir_n <= '0';
2371
2372                 if exec_cycle = N5 then
2373                     nmi_handled_n <= '0';
2374                 end if;
2375                 --start execute cycle.
2376                 next_cycle <= T0;
2377
2378             elsif exec_cycle(5) = '1' then
2379                 ---pc increment and next page.
2380                 d_print(string'("pch next page..."));
2381                 --pcl stop increment
2382                 pcl_inc_n <= '1';
2383                 back_we(pcl_cmd, '1');
2384                 --pch increment
2385                 back_we(pch_cmd, '0');
2386                 back_oe(pch_cmd, '0');
2387
2388                 if ('0' & exec_cycle(4 downto 0) = T0) then
2389                     --do the t0 identical routine.
2390                     disable_pins;
2391                     inst_we_n <= '1';
2392                     r_nw <= '1';
2393
2394                 elsif ('0' & exec_cycle(4 downto 0) = T1) then
2395                     --if fetch cycle, preserve instrution register
2396                     inst_we_n <= '1';
2397
2398                     --TODO: must handle for jmp case???
2399                 elsif ('0' & exec_cycle(4 downto 0) = T2) then
2400                     --disable previous we_n gate.
2401                     --t1 cycle is fetch low oprand.
2402                     dl_al_we_n <= '1';
2403                 elsif ('0' & exec_cycle(4 downto 0) = T3) then
2404                     --t2 cycle is fetch high oprand.
2405                     dl_ah_we_n <= '1';
2406                 end if;
2407
2408             end if; --if exec_cycle = T0 then
2409
2410         end if; --if (set_clk'event and set_clk = '1')
2411
2412     end process;
2413
2414 end rtl;
2415