simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sp_oe_n         : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             pg_next_n       : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             rel_calc_n      : out std_logic;
  43             indir_n         : out std_logic;
  44             indir_x_n       : out std_logic;
  45             indir_y_n       : out std_logic;
  46             arith_en_n      : out std_logic;
  47             stat_dec_oe_n   : out std_logic;
  48             stat_bus_oe_n   : out std_logic;
  49             stat_set_flg_n  : out std_logic;
  50             stat_flg        : out std_logic;
  51             stat_bus_all_n  : out std_logic;
  52             stat_bus_nz_n   : out std_logic;
  53             stat_alu_we_n   : out std_logic;
  54             r_vec_oe_n      : out std_logic;
  55             n_vec_oe_n      : out std_logic;
  56             i_vec_oe_n      : out std_logic;
  57             r_nw            : out std_logic
  58             ;---for parameter check purpose!!!
  59             check_bit     : out std_logic_vector(1 to 5)
  60         );
  61 end decoder;
  62
  63 architecture rtl of decoder is
  64
  65 component d_flip_flop_bit
  66     port (
  67             clk     : in std_logic;
  68             res_n   : in std_logic;
  69             set_n   : in std_logic;
  70             we_n    : in std_logic;
  71             d       : in std_logic;
  72             q       : out std_logic
  73         );
  74 end component;
  75
  76 procedure d_print(msg : string) is
  77 use std.textio.all;
  78 use ieee.std_logic_textio.all;
  79 variable out_l : line;
  80 begin
  81     write(out_l, msg);
  82     writeline(output, out_l);
  83 end  procedure;
  84
  85 ---ival : 0x0000 - 0xffff
  86 function conv_hex8(ival : integer) return string is
  87 variable tmp1, tmp2 : integer;
  88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  89 begin
  90     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  91     tmp1 := ival mod 16 ** 1;
  92     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  93 end;
  94
  95 --cycle bit format
  96 -- bit 5    : pcl increment carry flag
  97 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  98 -- bit 2-0  : cycle
  99
 100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
 101 constant T0 : std_logic_vector (5 downto 0) := "000000";
 102 constant T1 : std_logic_vector (5 downto 0) := "000001";
 103 constant T2 : std_logic_vector (5 downto 0) := "000010";
 104 constant T3 : std_logic_vector (5 downto 0) := "000011";
 105 constant T4 : std_logic_vector (5 downto 0) := "000100";
 106 constant T5 : std_logic_vector (5 downto 0) := "000101";
 107 constant T6 : std_logic_vector (5 downto 0) := "000110";
 108
 109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 110 constant R0 : std_logic_vector (5 downto 0) := "001000";
 111 constant R1 : std_logic_vector (5 downto 0) := "001001";
 112 constant R2 : std_logic_vector (5 downto 0) := "001010";
 113 constant R3 : std_logic_vector (5 downto 0) := "001011";
 114 constant R4 : std_logic_vector (5 downto 0) := "001100";
 115 constant R5 : std_logic_vector (5 downto 0) := "001101";
 116
 117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 118 constant N1 : std_logic_vector (5 downto 0) := "010001";
 119 constant N2 : std_logic_vector (5 downto 0) := "010010";
 120 constant N3 : std_logic_vector (5 downto 0) := "010011";
 121 constant N4 : std_logic_vector (5 downto 0) := "010100";
 122 constant N5 : std_logic_vector (5 downto 0) := "010101";
 123
 124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 125 constant I1 : std_logic_vector (5 downto 0) := "011001";
 126 constant I2 : std_logic_vector (5 downto 0) := "011010";
 127 constant I3 : std_logic_vector (5 downto 0) := "011011";
 128 constant I4 : std_logic_vector (5 downto 0) := "011100";
 129 constant I5 : std_logic_vector (5 downto 0) := "011101";
 130
 131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 132
 133 -- SR Flags (bit 7 to bit 0):
 134 --  7   N   ....    Negative
 135 --  6   V   ....    Overflow
 136 --  5   -   ....    ignored
 137 --  4   B   ....    Break
 138 --  3   D   ....    Decimal (use BCD for arithmetics)
 139 --  2   I   ....    Interrupt (IRQ disable)
 140 --  1   Z   ....    Zero
 141 --  0   C   ....    Carry
 142 constant st_N : integer := 7;
 143 constant st_V : integer := 6;
 144 constant st_B : integer := 4;
 145 constant st_D : integer := 3;
 146 constant st_I : integer := 2;
 147 constant st_Z : integer := 1;
 148 constant st_C : integer := 0;
 149
 150 ---for pch_inc_n.
 151 signal pch_inc_input : std_logic;
 152
 153 ---for nmi handling
 154 signal nmi_handled_n : std_logic;
 155
 156 begin
 157
 158
 159     ---pc page next is connected to top bit of exec_cycle
 160     pch_inc_input <= not exec_cycle(5);
 161     pch_inc_reg : d_flip_flop_bit
 162             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 163
 164     main_p : process (set_clk, res_n, nmi_n)
 165
 166 -------------------------------------------------------------
 167 -------------------------------------------------------------
 168 ----------------------- comon routines ----------------------
 169 -------------------------------------------------------------
 170 -------------------------------------------------------------
 171
 172 ----------gate_cmd format
 173 ------3 : front port oe_n
 174 ------2 : front port we_n
 175 ------1 : back port oe_n
 176 ------0 : back port we_n
 177 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 178     val : in std_logic) is
 179 begin
 180     cmd(3) <= val;
 181 end;
 182 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 183     val : in std_logic) is
 184 begin
 185     cmd(2) <= val;
 186 end;
 187 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 188     val : in std_logic) is
 189 begin
 190     cmd(1) <= val;
 191 end;
 192 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 193     val : in std_logic) is
 194 begin
 195     cmd(0) <= val;
 196 end;
 197
 198 procedure fetch_next is
 199 begin
 200     pcl_inc_n <= '0';
 201     back_oe(pcl_cmd, '0');
 202     back_oe(pch_cmd, '0');
 203     back_we(pcl_cmd, '0');
 204     back_we(pch_cmd, '1');
 205 end procedure;
 206
 207 procedure fetch_stop is
 208 begin
 209     pcl_inc_n <= '1';
 210     back_oe(pcl_cmd, '1');
 211     back_oe(pch_cmd, '1');
 212     back_we(pcl_cmd, '1');
 213 end procedure;
 214
 215 procedure read_status is
 216 begin
 217     status_reg <= (others => 'Z');
 218     stat_dec_oe_n <= '0';
 219 end  procedure;
 220
 221 procedure disable_pins is
 222 begin
 223     --disable the last opration pins.
 224     dbuf_int_oe_n <= '1';
 225     dl_al_we_n <= '1';
 226     dl_ah_we_n <= '1';
 227     dl_ah_oe_n <= '1';
 228     dl_dh_oe_n <= '1';
 229     sp_cmd <= "1111";
 230     sp_oe_n <= '1';
 231     sp_push_n <= '1';
 232     sp_pop_n <= '1';
 233     acc_cmd <= "1111";
 234     x_cmd <= "1111";
 235     y_cmd <= "1111";
 236
 237     abs_xy_n <= '1';
 238     pg_next_n <= '1';
 239     zp_n <= '1';
 240     zp_xy_n <= '1';
 241     rel_calc_n <= '1';
 242     indir_n <= '1';
 243     indir_x_n <= '1';
 244     indir_y_n <= '1';
 245     arith_en_n <= '1';
 246
 247     read_status;
 248     stat_bus_oe_n <= '1';
 249     stat_set_flg_n <= '1';
 250     stat_flg <= '1';
 251     stat_bus_all_n <= '1';
 252     stat_bus_nz_n <= '1';
 253     stat_alu_we_n <= '1';
 254
 255     r_vec_oe_n <= '1';
 256     n_vec_oe_n <= '1';
 257     i_vec_oe_n <= '1';
 258
 259 end  procedure;
 260
 261 procedure fetch_inst is
 262 begin
 263     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 264         --if prior cycle is jump instruction,
 265         --fetch opcode from where the latch is pointing to.
 266
 267         --latch > al.
 268         dl_al_oe_n <= '0';
 269         pcl_cmd <= "1110";
 270     else
 271         --fetch opcode and phc increment.
 272         pcl_cmd <= "1100";
 273         dl_al_oe_n <= '1';
 274     end if;
 275
 276     ad_oe_n <= '0';
 277     pch_cmd <= "1101";
 278     inst_we_n <= '0';
 279     pcl_inc_n <= '0';
 280     r_nw <= '1';
 281
 282     disable_pins;
 283     d_print(string'("fetch 1"));
 284 end  procedure;
 285
 286 ---T0 cycle routine
 287 ---(along with the page boundary condition, the last
 288 ---cycle is bypassed and slided to T0.)
 289 procedure t0_cycle is
 290 begin
 291     if (nmi_n = '0' and nmi_handled_n = '1') then
 292         disable_pins;
 293         pcl_cmd <= "1111";
 294         pch_cmd <= "1111";
 295         pcl_inc_n <= '1';
 296         inst_we_n <= '1';
 297         r_nw <= '1';
 298         next_cycle <= N1;
 299     else
 300         fetch_inst;
 301         next_cycle <= T1;
 302     end if;
 303 end  procedure;
 304
 305 ---common routine for single byte instruction.
 306 procedure single_inst is
 307 begin
 308     fetch_stop;
 309     next_cycle <= T0;
 310 end  procedure;
 311
 312 procedure fetch_imm is
 313 begin
 314     d_print("immediate");
 315     fetch_next;
 316     --send data from data bus buffer.
 317     --receiver is instruction dependent.
 318     dbuf_int_oe_n <= '0';
 319     next_cycle <= T0;
 320 end  procedure;
 321
 322 procedure set_nz_from_bus is
 323 begin
 324     --status register n/z bit update.
 325     stat_bus_nz_n <= '0';
 326 end  procedure;
 327
 328 procedure set_zc_from_alu is
 329 begin
 330     --status register n/z bit update.
 331     stat_alu_we_n <= '0';
 332     stat_dec_oe_n <= '1';
 333     status_reg <= "00000011";
 334 end  procedure;
 335
 336 procedure set_nz_from_alu is
 337 begin
 338     --status register n/z/c bit update.
 339     stat_alu_we_n <= '0';
 340     stat_dec_oe_n <= '1';
 341     status_reg <= "10000010";
 342 end  procedure;
 343
 344 procedure set_nzc_from_alu is
 345 begin
 346     --status register n/z/c bit update.
 347     stat_alu_we_n <= '0';
 348     stat_dec_oe_n <= '1';
 349     status_reg <= "10000011";
 350 end  procedure;
 351
 352 procedure set_nvz_from_alu is
 353 begin
 354     --status register n/z/v bit update.
 355     stat_alu_we_n <= '0';
 356     stat_dec_oe_n <= '1';
 357     status_reg <= "11000010";
 358 end  procedure;
 359
 360 procedure set_nvzc_from_alu is
 361 begin
 362     stat_alu_we_n <= '0';
 363     stat_dec_oe_n <= '1';
 364     status_reg <= "11000011";
 365 end  procedure;
 366
 367 --flag on/off instruction
 368 procedure set_flag (int_flg : in integer; val : in std_logic) is
 369 begin
 370     stat_dec_oe_n <= '1';
 371     stat_set_flg_n <= '0';
 372     --specify which to set.
 373     status_reg(7 downto int_flg + 1)
 374         <= (others =>'0');
 375     status_reg(int_flg - 1 downto 0)
 376         <= (others =>'0');
 377     status_reg(int_flg) <= '1';
 378     stat_flg <= val;
 379 end  procedure;
 380
 381 --for sec/clc
 382 procedure set_flag0 (val : in std_logic) is
 383 begin
 384     stat_dec_oe_n <= '1';
 385     stat_set_flg_n <= '0';
 386     status_reg <= "00000001";
 387     stat_flg <= val;
 388 end  procedure;
 389
 390 procedure fetch_low is
 391 begin
 392     d_print("fetch low 2");
 393     --fetch next opcode (abs low).
 394     fetch_next;
 395     --latch abs low data.
 396     dbuf_int_oe_n <= '0';
 397     dl_al_we_n <= '0';
 398     next_cycle <= T2;
 399 end  procedure;
 400
 401 procedure abs_fetch_high is
 402 begin
 403     d_print("abs (xy) 3");
 404     dl_al_we_n <= '1';
 405
 406     --latch abs hi data.
 407     fetch_next;
 408     dbuf_int_oe_n <= '0';
 409     dl_ah_we_n <= '0';
 410     next_cycle <= T3;
 411 end  procedure;
 412
 413 procedure abs_latch_out is
 414 begin
 415     --d_print("abs 4");
 416     fetch_stop;
 417     dl_ah_we_n <= '1';
 418
 419     --latch > al/ah.
 420     dl_al_oe_n <= '0';
 421     dl_ah_oe_n <= '0';
 422 end  procedure;
 423
 424 procedure ea_x_out is
 425 begin
 426     -----calucurate and output effective addr
 427     back_oe(x_cmd, '0');
 428     abs_xy_n <= '0';
 429 end  procedure;
 430
 431 procedure ea_y_out is
 432 begin
 433     back_oe(y_cmd, '0');
 434     abs_xy_n <= '0';
 435 end  procedure;
 436
 437 --A.2. internal execution on memory data
 438
 439 procedure a2_zp is
 440 begin
 441     if exec_cycle = T1 then
 442         fetch_low;
 443     elsif exec_cycle = T2 then
 444         fetch_stop;
 445         dbuf_int_oe_n <= '0';
 446         dl_al_we_n <= '1';
 447
 448         --calc zp.
 449         dl_al_oe_n <= '0';
 450         zp_n <= '0';
 451         next_cycle <= T0;
 452     end if;
 453 end  procedure;
 454
 455 procedure a2_abs is
 456 begin
 457     if exec_cycle = T1 then
 458         fetch_low;
 459     elsif exec_cycle = T2 then
 460         abs_fetch_high;
 461     elsif exec_cycle = T3 then
 462         abs_latch_out;
 463         dbuf_int_oe_n <= '0';
 464         next_cycle <= T0;
 465     end if;
 466 end  procedure;
 467
 468 procedure a2_abs_xy (is_x : in boolean) is
 469 begin
 470     if exec_cycle = T1 then
 471         fetch_low;
 472     elsif exec_cycle = T2 then
 473         abs_fetch_high;
 474     elsif exec_cycle = T3 then
 475         --ea calc & lda
 476         pg_next_n <= '1';
 477         abs_latch_out;
 478         if (is_x = true) then
 479             ea_x_out;
 480         else
 481             ea_y_out;
 482         end if;
 483         dbuf_int_oe_n <= '0';
 484         --instruction specific operation wriiten in the caller position.
 485         next_cycle <= T4;
 486     elsif exec_cycle = T4 then
 487         if ea_carry = '1' then
 488             --case page boundary crossed.
 489             d_print("absx 5 (page boudary crossed.)");
 490             abs_latch_out;
 491             if (is_x = true) then
 492                 ea_x_out;
 493             else
 494                 ea_y_out;
 495             end if;
 496             dbuf_int_oe_n <= '0';
 497             --next page.
 498             pg_next_n <= not ea_carry;
 499             --redo inst.
 500             next_cycle <= T0;
 501         else
 502             --case page boundary not crossed. do the fetch op.
 503             d_print("absx 5 (fetch)");
 504             t0_cycle;
 505         end if;
 506     end if;
 507 end  procedure;
 508
 509 procedure a2_indir_y is
 510 begin
 511     if exec_cycle = T1 then
 512         fetch_low;
 513         --get IAL
 514         dl_al_we_n <= '0';
 515
 516     elsif exec_cycle = T2 then
 517         fetch_stop;
 518         dl_al_we_n <= '1';
 519
 520         ---address is 00:IAL
 521         --output BAL @IAL
 522         indir_y_n <= '0';
 523         dl_al_oe_n <= '0';
 524         dbuf_int_oe_n <= '0';
 525         next_cycle <= T3;
 526
 527     elsif exec_cycle = T3 then
 528         indir_y_n <= '0';
 529         dl_al_oe_n <= '0';
 530         --output BAH @IAL+1
 531         dbuf_int_oe_n <= '0';
 532         next_cycle <= T4;
 533
 534     elsif exec_cycle = T4 then
 535         dl_al_oe_n <= '1';
 536         dbuf_int_oe_n <= '1';
 537
 538         --add index y.
 539         pg_next_n <= '1';
 540         back_oe(y_cmd, '0');
 541         indir_y_n <= '0';
 542         dbuf_int_oe_n <= '0';
 543         next_cycle <= T5;
 544
 545     elsif exec_cycle = T5 then
 546         if ea_carry = '1' then
 547             --case page boundary crossed.
 548             d_print("(indir), y (page boudary crossed.)");
 549             back_oe(y_cmd, '1');
 550             indir_y_n <= '0';
 551             dbuf_int_oe_n <= '0';
 552             pg_next_n <= not ea_carry;
 553             next_cycle <= T0;
 554         else
 555             --case page boundary not crossed. do the fetch op.
 556             d_print("(indir), y (next fetch)");
 557             t0_cycle;
 558         end if;
 559
 560     end if;
 561 end  procedure;
 562
 563 --A.3. store operation.
 564
 565 procedure a3_zp is
 566 begin
 567     if exec_cycle = T1 then
 568         fetch_low;
 569     elsif exec_cycle = T2 then
 570         fetch_stop;
 571         dbuf_int_oe_n <= '1';
 572         dl_al_we_n <= '1';
 573
 574         --calc zp.
 575         dl_al_oe_n <= '0';
 576         zp_n <= '0';
 577         r_nw <= '0';
 578         next_cycle <= T0;
 579     end if;
 580 end  procedure;
 581
 582 procedure a3_abs is
 583 begin
 584     if exec_cycle = T1 then
 585         fetch_low;
 586     elsif exec_cycle = T2 then
 587         abs_fetch_high;
 588     elsif exec_cycle = T3 then
 589         abs_latch_out;
 590         dbuf_int_oe_n <= '1';
 591         r_nw <= '0';
 592         next_cycle <= T0;
 593     end if;
 594 end  procedure;
 595
 596 procedure a3_abs_xy (is_x : in boolean) is
 597 begin
 598     if exec_cycle = T1 then
 599         fetch_low;
 600     elsif exec_cycle = T2 then
 601         abs_fetch_high;
 602     elsif exec_cycle = T3 then
 603         --ea calc & lda
 604         pg_next_n <= '1';
 605         abs_latch_out;
 606         dbuf_int_oe_n <= '1';
 607         if (is_x = true) then
 608             ea_x_out;
 609         else
 610             ea_y_out;
 611         end if;
 612         next_cycle <= T4;
 613     elsif exec_cycle = T4 then
 614         pg_next_n <= not ea_carry;
 615         abs_latch_out;
 616         if (is_x = true) then
 617             ea_x_out;
 618         else
 619             ea_y_out;
 620         end if;
 621         r_nw <= '0';
 622         next_cycle <= T0;
 623     end if;
 624 end  procedure;
 625
 626
 627 procedure a3_indir_y is
 628 begin
 629     if exec_cycle = T1 then
 630         fetch_low;
 631         --get IAL
 632         dl_al_we_n <= '0';
 633
 634     elsif exec_cycle = T2 then
 635         fetch_stop;
 636         dl_al_we_n <= '1';
 637
 638         ---address is 00:IAL
 639         --output BAL @IAL
 640         indir_y_n <= '0';
 641         dl_al_oe_n <= '0';
 642         dbuf_int_oe_n <= '0';
 643         next_cycle <= T3;
 644
 645     elsif exec_cycle = T3 then
 646         indir_y_n <= '0';
 647         dl_al_oe_n <= '0';
 648         --output BAH @IAL+1
 649         dbuf_int_oe_n <= '0';
 650         next_cycle <= T4;
 651
 652     elsif exec_cycle = T4 then
 653         dl_al_oe_n <= '1';
 654         dbuf_int_oe_n <= '1';
 655
 656         --add index y.
 657         pg_next_n <= '1';
 658         back_oe(y_cmd, '0');
 659         indir_y_n <= '0';
 660         next_cycle <= T5;
 661
 662     elsif exec_cycle = T5 then
 663
 664         --page handling.
 665         back_oe(y_cmd, '1');
 666         indir_y_n <= '0';
 667         pg_next_n <= not ea_carry;
 668         r_nw <= '0';
 669         next_cycle <= T0;
 670     end if;
 671 end  procedure;
 672
 673
 674 ---A.4. read-modify-write operation
 675
 676 procedure a4_zp is
 677 begin
 678     if exec_cycle = T1 then
 679         fetch_low;
 680     elsif exec_cycle = T2 then
 681         fetch_stop;
 682         dbuf_int_oe_n <= '1';
 683         dl_al_we_n <= '1';
 684
 685         --t2 cycle only read
 686         dl_al_oe_n <= '0';
 687         zp_n <= '0';
 688         next_cycle <= T3;
 689     elsif exec_cycle = T3 then
 690         dl_al_oe_n <= '0';
 691         zp_n <= '0';
 692         --keep data in the alu reg.
 693         arith_en_n <= '0';
 694         dbuf_int_oe_n <= '0';
 695         next_cycle <= T4;
 696     elsif exec_cycle = T4 then
 697         dbuf_int_oe_n <= '1';
 698
 699         --t5 cycle writes modified value.
 700         dl_al_oe_n <= '0';
 701         zp_n <= '0';
 702         r_nw <= '0';
 703         arith_en_n <= '0';
 704         next_cycle <= T0;
 705     end if;
 706 end  procedure;
 707
 708
 709 procedure a4_abs is
 710 begin
 711     if exec_cycle = T1 then
 712         fetch_low;
 713     elsif exec_cycle = T2 then
 714         abs_fetch_high;
 715     elsif exec_cycle = T3 then
 716         --T3 cycle do nothing.
 717         abs_latch_out;
 718         next_cycle <= T4;
 719     elsif exec_cycle = T4 then
 720         abs_latch_out;
 721
 722         --t4 cycle save data in the alu register only.
 723         --hardware maunual says write original data,
 724         --but this implementation doesn't write because bus shortage....
 725         arith_en_n <= '0';
 726         next_cycle <= T5;
 727     elsif exec_cycle = T5 then
 728         dbuf_int_oe_n <= '1';
 729
 730         --t5 cycle writes modified value.
 731         r_nw <= '0';
 732         arith_en_n <= '0';
 733         next_cycle <= T0;
 734     end if;
 735 end  procedure;
 736
 737
 738 -- A.5.1 push stack
 739 procedure a51_push is
 740 begin
 741     if exec_cycle = T1 then
 742         fetch_stop;
 743         next_cycle <= T2;
 744     elsif exec_cycle = T2 then
 745         back_oe(sp_cmd, '0');
 746         back_we(sp_cmd, '0');
 747         sp_push_n <= '0';
 748         sp_oe_n <= '0';
 749         r_nw <= '0';
 750         next_cycle <= T0;
 751     end if;
 752 end procedure;
 753
 754 -- A.5.2 pull stack
 755 procedure a52_pull is
 756 begin
 757     if exec_cycle = T1 then
 758         fetch_stop;
 759         next_cycle <= T2;
 760
 761     elsif exec_cycle = T2 then
 762         --stack decrement first.
 763         back_oe(sp_cmd, '0');
 764         back_we(sp_cmd, '0');
 765         sp_pop_n <= '0';
 766         sp_oe_n <= '0';
 767         next_cycle <= T3;
 768
 769     elsif exec_cycle = T3 then
 770         sp_pop_n <= '1';
 771         back_we(sp_cmd, '1');
 772
 773         ---pop data from stack.
 774         back_oe(sp_cmd, '0');
 775         sp_oe_n <= '0';
 776         dbuf_int_oe_n <= '0';
 777         next_cycle <= T0;
 778     end if;
 779 end procedure;
 780
 781
 782 -- A.5.8 branch operations
 783
 784 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 785 begin
 786     if exec_cycle = T1 then
 787         fetch_next;
 788         if status_reg(int_flg) = br_cond then
 789             d_print("get rel");
 790
 791             --latch rel value.
 792             dbuf_int_oe_n <= '0';
 793             dl_ah_we_n <= '0';
 794             next_cycle <= T2;
 795         else
 796             d_print("no branch");
 797             next_cycle <= T0;
 798         end if;
 799     elsif exec_cycle = T2 then
 800         d_print("rel ea");
 801         fetch_stop;
 802         dbuf_int_oe_n <= '1';
 803         dl_ah_we_n <= '1';
 804
 805         --calc relative addr.
 806         rel_calc_n <= '0';
 807         pg_next_n <= '1';
 808         dl_dh_oe_n <= '0';
 809         back_oe(pcl_cmd, '0');
 810         back_oe(pch_cmd, '0');
 811         back_we(pcl_cmd, '0');
 812
 813         next_cycle <= T3;
 814     elsif exec_cycle = T3 then
 815
 816         if ea_carry = '1' then
 817             d_print("page crossed.");
 818             --page crossed. adh calc.
 819             back_we(pcl_cmd, '1');
 820             back_oe(pcl_cmd, '0');
 821             back_oe(pch_cmd, '0');
 822             back_we(pch_cmd, '0');
 823             dl_dh_oe_n <= '0';
 824
 825             rel_calc_n <= '0';
 826             pg_next_n <= not ea_carry;
 827             next_cycle <= T0;
 828         else
 829             --no page boundary.
 830             --fetch cycle is done.
 831             t0_cycle;
 832         end if;
 833     end if;
 834 end  procedure;
 835
 836 -------------------------------------------------------------
 837 -------------------------------------------------------------
 838 ---------------- main state machine start.... ---------------
 839 -------------------------------------------------------------
 840 -------------------------------------------------------------
 841     begin
 842
 843         if (res_n = '0') then
 844             --pc l/h is reset vector.
 845             pcl_cmd <= "1110";
 846             pch_cmd <= "1110";
 847             next_cycle <= R0;
 848         elsif (res_n'event and res_n = '1') then
 849             pcl_cmd <= "1111";
 850             pch_cmd <= "1111";
 851         end if;
 852
 853         if (nmi_n'event and nmi_n = '1') then
 854             --reset nmi handle status
 855             nmi_handled_n <= '1';
 856         end if;
 857
 858         if (set_clk'event and set_clk = '1' and res_n = '1') then
 859             d_print(string'("-"));
 860
 861             if exec_cycle = T0 then
 862                 --cycle #1
 863                 t0_cycle;
 864
 865             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 866                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
 867                 --execute inst.
 868
 869                 ---asyncronous page change might happen.
 870                 back_we(pch_cmd, '1');
 871
 872                 if exec_cycle = T1 then
 873                     d_print("decode and execute inst: "
 874                             & conv_hex8(conv_integer(instruction)));
 875                     --disable pin since jmp instruction
 876                     --directly enters into t2 cycle.
 877                     dl_al_oe_n <= '1';
 878                     back_we(pcl_cmd, '1');
 879                     front_we(pch_cmd, '1');
 880
 881                     --grab instruction register data.
 882                     inst_we_n <= '1';
 883                 end if;
 884
 885                 --imelementation is wriiten in the order of hardware manual
 886                 --appendix A.
 887
 888                 ----------------------------------------
 889                 --A.1. Single byte instruction.
 890                 ----------------------------------------
 891                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 892                     --asl acc mode.
 893                     d_print("asl");
 894
 895                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 896                     d_print("clc");
 897                     set_flag0 ('0');
 898                     single_inst;
 899
 900                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 901                     d_print("cld");
 902                     set_flag (st_D, '0');
 903                     single_inst;
 904
 905                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 906                     d_print("cli");
 907
 908                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 909                     d_print("clv");
 910
 911                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 912                     d_print("dex");
 913                     arith_en_n <= '0';
 914                     back_oe(x_cmd, '0');
 915                     front_we(x_cmd, '0');
 916                     --set nz bit.
 917                     set_nz_from_bus;
 918                     single_inst;
 919
 920                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
 921                     d_print("dey");
 922                     arith_en_n <= '0';
 923                     back_oe(y_cmd, '0');
 924                     front_we(y_cmd, '0');
 925                     --set nz bit.
 926                     set_nz_from_bus;
 927                     single_inst;
 928
 929                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
 930                     d_print("inx");
 931                     arith_en_n <= '0';
 932                     back_oe(x_cmd, '0');
 933                     front_we(x_cmd, '0');
 934                     --set nz bit.
 935                     set_nz_from_bus;
 936                     single_inst;
 937
 938                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
 939                     d_print("iny");
 940                     arith_en_n <= '0';
 941                     back_oe(y_cmd, '0');
 942                     front_we(y_cmd, '0');
 943                     set_nz_from_bus;
 944                     single_inst;
 945
 946                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
 947                     --lsr acc mode
 948                     d_print("lsr");
 949                     arith_en_n <= '0';
 950                     back_oe(acc_cmd, '0');
 951                     front_we(acc_cmd, '0');
 952                     set_zc_from_alu;
 953                     single_inst;
 954
 955                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
 956                     d_print("nop");
 957                     single_inst;
 958
 959                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
 960                     --rol acc
 961                     d_print("rol");
 962                     arith_en_n <= '0';
 963                     back_oe(acc_cmd, '0');
 964                     front_we(acc_cmd, '0');
 965                     set_nzc_from_alu;
 966                     single_inst;
 967
 968                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
 969                     d_print("sec");
 970                     set_flag0 ('1');
 971                     single_inst;
 972
 973                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
 974                     d_print("sed");
 975                     set_flag (st_D, '1');
 976                     single_inst;
 977
 978                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
 979                     d_print("sei");
 980                     set_flag (st_I, '1');
 981                     single_inst;
 982
 983                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
 984                     d_print("tax");
 985                     set_nz_from_bus;
 986                     single_inst;
 987                     front_oe(acc_cmd, '0');
 988                     front_we(x_cmd, '0');
 989
 990                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
 991                     d_print("tay");
 992                     set_nz_from_bus;
 993                     single_inst;
 994                     front_oe(acc_cmd, '0');
 995                     front_we(y_cmd, '0');
 996
 997                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
 998                     d_print("tsx");
 999                     set_nz_from_bus;
1000
1001                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1002                     d_print("txa");
1003                     set_nz_from_bus;
1004                     single_inst;
1005                     front_oe(x_cmd, '0');
1006                     front_we(acc_cmd, '0');
1007
1008                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1009                     d_print("txs");
1010                     set_nz_from_bus;
1011                     single_inst;
1012                     front_oe(x_cmd, '0');
1013                     front_we(sp_cmd, '0');
1014
1015                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1016                     d_print("tya");
1017                     set_nz_from_bus;
1018                     single_inst;
1019                     front_oe(y_cmd, '0');
1020                     front_we(acc_cmd, '0');
1021
1022
1023
1024                 ----------------------------------------
1025                 --A.2. internal execution on memory data
1026                 ----------------------------------------
1027                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1028                     --imm
1029                     d_print("adc");
1030                     fetch_imm;
1031                     arith_en_n <= '0';
1032                     back_oe(acc_cmd, '0');
1033                     back_we(acc_cmd, '0');
1034                     set_nvzc_from_alu;
1035
1036                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1037                     --zp
1038                     d_print("adc");
1039                     a2_zp;
1040                     if exec_cycle = T2 then
1041                         arith_en_n <= '0';
1042                         back_oe(acc_cmd, '0');
1043                         back_we(acc_cmd, '0');
1044                         set_nvzc_from_alu;
1045                     end if;
1046
1047                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1048                     --zp, x
1049                     d_print("adc");
1050
1051                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1052                     --abs
1053                     d_print("adc");
1054
1055                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1056                     --abs, x
1057                     d_print("adc");
1058
1059                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1060                     --abs, y
1061                     d_print("adc");
1062
1063                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1064                     --(indir, x)
1065                     d_print("adc");
1066
1067                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1068                     --(indir), y
1069                     d_print("adc");
1070
1071                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1072                     --imm
1073                     d_print("and");
1074                     fetch_imm;
1075                     arith_en_n <= '0';
1076                     back_oe(acc_cmd, '0');
1077                     back_we(acc_cmd, '0');
1078                     set_nz_from_alu;
1079
1080                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1081                     --zp
1082                     d_print("and");
1083                     a2_zp;
1084                     if exec_cycle = T2 then
1085                         arith_en_n <= '0';
1086                         back_oe(acc_cmd, '0');
1087                         back_we(acc_cmd, '0');
1088                         set_nz_from_alu;
1089                     end if;
1090
1091                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1092                     --zp, x
1093                     d_print("and");
1094
1095                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1096                     --abs
1097                     d_print("and");
1098
1099                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1100                     --abs, x
1101                     d_print("and");
1102                     a2_abs_xy(true);
1103                     if exec_cycle = T3 then
1104                         arith_en_n <= '0';
1105                         back_oe(acc_cmd, '0');
1106                         back_we(acc_cmd, '0');
1107                         set_nz_from_alu;
1108                     elsif exec_cycle = T4 then
1109                         if ea_carry = '1' then
1110                             arith_en_n <= '0';
1111                             back_oe(acc_cmd, '0');
1112                             back_we(acc_cmd, '0');
1113                             set_nz_from_alu;
1114                         end if;
1115                     end if;
1116
1117                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1118                     --abs, y
1119                     d_print("and");
1120
1121                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1122                     --(indir, x)
1123                     d_print("and");
1124
1125                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1126                     --(indir), y
1127                     d_print("and");
1128
1129                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1130                     --zp
1131                     d_print("bit");
1132
1133                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1134                     --abs
1135                     d_print("bit");
1136                     a2_abs;
1137                     if exec_cycle = T3 then
1138                         arith_en_n <= '0';
1139                         set_nvz_from_alu;
1140                     end if;
1141
1142                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1143                     --imm
1144                     d_print("cmp");
1145                     fetch_imm;
1146                     arith_en_n <= '0';
1147                     back_oe(acc_cmd, '0');
1148                     set_nzc_from_alu;
1149
1150                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1151                     --zp
1152                     d_print("cmp");
1153                     a2_zp;
1154                     if exec_cycle = T2 then
1155                         arith_en_n <= '0';
1156                         back_oe(acc_cmd, '0');
1157                         set_nzc_from_alu;
1158                     end if;
1159
1160                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1161                     --zp, x
1162                     d_print("cmp");
1163
1164                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1165                     --abs
1166                     d_print("cmp");
1167
1168                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1169                     --abs, x
1170                     d_print("cmp");
1171
1172                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1173                     --abs, y
1174                     d_print("cmp");
1175                     a2_abs_xy(false);
1176                     if exec_cycle = T3 then
1177                         arith_en_n <= '0';
1178                         back_oe(acc_cmd, '0');
1179                         set_nzc_from_alu;
1180                     elsif exec_cycle = T4 then
1181                         if ea_carry = '1' then
1182                             arith_en_n <= '0';
1183                             back_oe(acc_cmd, '0');
1184                             set_nzc_from_alu;
1185                         end if;
1186                     end if;
1187
1188                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1189                     --(indir, x)
1190                     d_print("cmp");
1191
1192                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1193                     --(indir), y
1194                     d_print("cmp");
1195
1196                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1197                     --imm
1198                     d_print("cpx");
1199                     fetch_imm;
1200                     arith_en_n <= '0';
1201                     back_oe(x_cmd, '0');
1202                     set_nzc_from_alu;
1203
1204                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1205                     --zp
1206                     d_print("cpx");
1207                     a2_zp;
1208                     if exec_cycle = T2 then
1209                         arith_en_n <= '0';
1210                         back_oe(x_cmd, '0');
1211                         set_nzc_from_alu;
1212                     end if;
1213
1214                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1215                     --abs
1216                     d_print("cpx");
1217
1218                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1219                     --imm
1220                     d_print("cpy");
1221                     fetch_imm;
1222                     arith_en_n <= '0';
1223                     back_oe(y_cmd, '0');
1224                     set_nzc_from_alu;
1225
1226                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1227                     --zp
1228                     d_print("cpy");
1229
1230                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1231                     --abs
1232                     d_print("cpy");
1233
1234                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1235                     --imm
1236                     d_print("eor");
1237                     fetch_imm;
1238                     arith_en_n <= '0';
1239                     back_oe(acc_cmd, '0');
1240                     back_we(acc_cmd, '0');
1241                     set_nz_from_alu;
1242
1243                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1244                     --zp
1245                     d_print("eor");
1246                     a2_zp;
1247                     if exec_cycle = T2 then
1248                         arith_en_n <= '0';
1249                         back_oe(acc_cmd, '0');
1250                         back_we(acc_cmd, '0');
1251                         set_nz_from_alu;
1252                     end if;
1253
1254                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1255                     --zp, x
1256                     d_print("eor");
1257
1258                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1259                     --abs
1260                     d_print("eor");
1261
1262                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1263                     --abs, x
1264                     d_print("eor");
1265
1266                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1267                     --abs, y
1268                     d_print("eor");
1269
1270                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1271                     --(indir, x)
1272                     d_print("eor");
1273
1274                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1275                     --(indir), y
1276                     d_print("eor");
1277
1278                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1279                     --imm
1280                     d_print("lda");
1281                     fetch_imm;
1282                     front_we(acc_cmd, '0');
1283                     set_nz_from_bus;
1284
1285                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1286                     --zp
1287                     d_print("lda");
1288                     a2_zp;
1289                     if exec_cycle = T2 then
1290                         front_we(acc_cmd, '0');
1291                         set_nz_from_bus;
1292                     end if;
1293
1294                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1295                     --zp, x
1296                     d_print("lda");
1297
1298                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1299                     --abs
1300                     d_print("lda");
1301                     a2_abs;
1302                     if exec_cycle = T3 then
1303                         set_nz_from_bus;
1304                         front_we(acc_cmd, '0');
1305                     end if;
1306
1307                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1308                     --abs, x
1309                     d_print("lda");
1310                     a2_abs_xy(true);
1311                     if exec_cycle = T3 then
1312                         --lda.
1313                         front_we(acc_cmd, '0');
1314                         set_nz_from_bus;
1315                     elsif exec_cycle = T4 then
1316                         if ea_carry = '1' then
1317                             --redo lda
1318                             front_we(acc_cmd, '0');
1319                             set_nz_from_bus;
1320                         end if;
1321                     end if;
1322
1323                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1324                     --abs, y
1325                     d_print("lda");
1326                     a2_abs_xy(false);
1327                     if exec_cycle = T3 then
1328                         --lda.
1329                         front_we(acc_cmd, '0');
1330                         set_nz_from_bus;
1331                     elsif exec_cycle = T4 then
1332                         if ea_carry = '1' then
1333                             --redo lda
1334                             front_we(acc_cmd, '0');
1335                             set_nz_from_bus;
1336                         end if;
1337                     end if;
1338
1339                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1340                     --(indir, x)
1341                     d_print("lda");
1342
1343                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1344                     --(indir), y
1345                     d_print("lda");
1346                     a2_indir_y;
1347                     if exec_cycle = T4 then
1348                         --lda.
1349                         front_we(acc_cmd, '0');
1350                         set_nz_from_bus;
1351                     elsif exec_cycle = T5 then
1352                         if ea_carry = '1' then
1353                             --redo lda
1354                             front_we(acc_cmd, '0');
1355                             set_nz_from_bus;
1356                         end if;
1357                     end if;
1358
1359                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1360                     --imm
1361                     d_print("ldx");
1362                     fetch_imm;
1363                     set_nz_from_bus;
1364                     front_we(x_cmd, '0');
1365
1366                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1367                     --zp
1368                     d_print("ldx");
1369                     a2_zp;
1370                     if exec_cycle = T2 then
1371                         front_we(x_cmd, '0');
1372                         set_nz_from_bus;
1373                     end if;
1374
1375                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1376                     --zp, y
1377                     d_print("ldx");
1378
1379                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1380                     --abs
1381                     d_print("ldx");
1382                     a2_abs;
1383                     if exec_cycle = T3 then
1384                         set_nz_from_bus;
1385                         front_we(x_cmd, '0');
1386                     end if;
1387
1388                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1389                     --abs, y
1390                     d_print("ldx");
1391                     a2_abs_xy(false);
1392                     if exec_cycle = T3 then
1393                         --lda.
1394                         front_we(x_cmd, '0');
1395                         set_nz_from_bus;
1396                     elsif exec_cycle = T4 then
1397                         if ea_carry = '1' then
1398                             --redo lda
1399                             front_we(x_cmd, '0');
1400                             set_nz_from_bus;
1401                         end if;
1402                     end if;
1403
1404                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1405                     --imm
1406                     d_print("ldy");
1407                     fetch_imm;
1408                     set_nz_from_bus;
1409                     front_we(y_cmd, '0');
1410
1411                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1412                     --zp
1413                     d_print("ldy");
1414
1415                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1416                     --zp, x
1417                     d_print("ldy");
1418
1419                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1420                     --abs
1421                     d_print("ldy");
1422                     a2_abs;
1423                     if exec_cycle = T3 then
1424                         set_nz_from_bus;
1425                         front_we(y_cmd, '0');
1426                     end if;
1427
1428                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1429                     --abs, x
1430                     d_print("ldy");
1431
1432                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1433                     --imm
1434                     d_print("ora");
1435                     fetch_imm;
1436                     arith_en_n <= '0';
1437                     back_oe(acc_cmd, '0');
1438                     back_we(acc_cmd, '0');
1439                     set_nz_from_alu;
1440
1441                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1442                     --zp
1443                     d_print("ora");
1444                     a2_zp;
1445                     if exec_cycle = T2 then
1446                         arith_en_n <= '0';
1447                         back_oe(acc_cmd, '0');
1448                         back_we(acc_cmd, '0');
1449                         set_nz_from_alu;
1450                     end if;
1451
1452                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1453                     --zp, x
1454                     d_print("ora");
1455
1456                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1457                     --abs
1458                     d_print("ora");
1459
1460                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1461                     --abs, x
1462                     d_print("ora");
1463
1464                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1465                     --abs, y
1466                     d_print("ora");
1467
1468                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1469                     --(indir, x)
1470                     d_print("ora");
1471
1472                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1473                     --(indir), y
1474                     d_print("ora");
1475
1476                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1477                     --imm
1478                     d_print("sbc");
1479
1480                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1481                     --zp
1482                     d_print("sbc");
1483
1484                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1485                     --zp, x
1486                     d_print("sbc");
1487
1488                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1489                     --abs
1490                     d_print("sbc");
1491
1492                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1493                     --abs, x
1494                     d_print("sbc");
1495
1496                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1497                     --abs, y
1498                     d_print("sbc");
1499                     a2_abs_xy(false);
1500                     if exec_cycle = T3 then
1501                         arith_en_n <= '0';
1502                         back_oe(acc_cmd, '0');
1503                         back_we(acc_cmd, '0');
1504                         set_nvzc_from_alu;
1505                     elsif exec_cycle = T4 then
1506                         if ea_carry = '1' then
1507                             --redo
1508                             arith_en_n <= '0';
1509                             back_oe(acc_cmd, '0');
1510                             back_we(acc_cmd, '0');
1511                             set_nvzc_from_alu;
1512                         end if;
1513                     end if;
1514
1515                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
1516                     --(indir, x)
1517                     d_print("sbc");
1518
1519                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
1520                     --(indir), y
1521                     d_print("sbc");
1522
1523
1524
1525                 ----------------------------------------
1526                 ---A.3. store operation.
1527                 ----------------------------------------
1528                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
1529                     --zp
1530                     d_print("sta");
1531                     a3_zp;
1532                     if exec_cycle = T2 then
1533                         front_oe(acc_cmd, '0');
1534                     end if;
1535
1536                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
1537                     --zp, x
1538                     d_print("sta");
1539
1540                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
1541                     --abs
1542                     d_print("sta");
1543                     a3_abs;
1544                     if exec_cycle = T3 then
1545                         front_oe(acc_cmd, '0');
1546                     end if;
1547
1548                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
1549                     --abs, x
1550                     d_print("sta");
1551                     a3_abs_xy (true);
1552                     if exec_cycle = T4 then
1553                         front_oe(acc_cmd, '0');
1554                     end if;
1555
1556                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
1557                     --abs, y
1558                     d_print("sta");
1559                     a3_abs_xy (false);
1560                     if exec_cycle = T4 then
1561                         front_oe(acc_cmd, '0');
1562                     end if;
1563
1564                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
1565                     --(indir, x)
1566                     d_print("sta");
1567
1568                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
1569                     --(indir), y
1570                     d_print("sta");
1571                     a3_indir_y;
1572                     if exec_cycle = T5 then
1573                         front_oe(acc_cmd, '0');
1574                     end if;
1575
1576                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
1577                     --zp
1578                     d_print("stx");
1579                     a3_zp;
1580                     if exec_cycle = T2 then
1581                         front_oe(x_cmd, '0');
1582                     end if;
1583
1584                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
1585                     --zp, y
1586                     d_print("stx");
1587
1588                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
1589                     --abs
1590                     d_print("stx");
1591
1592                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
1593                     --zp
1594                     d_print("sty");
1595                     a3_zp;
1596                     if exec_cycle = T2 then
1597                         front_oe(y_cmd, '0');
1598                     end if;
1599
1600                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
1601                     --zp, x
1602                     d_print("sty");
1603
1604                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
1605                     --abs
1606                     d_print("sty");
1607
1608
1609                 ----------------------------------------
1610                 ---A.4. read-modify-write operation
1611                 ----------------------------------------
1612                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
1613                     --zp
1614                     d_print("asl");
1615
1616                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
1617                     --zp, x
1618                     d_print("asl");
1619
1620                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
1621                     --abs
1622                     d_print("asl");
1623
1624                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
1625                     --abs, x
1626                     d_print("asl");
1627
1628                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
1629                     --zp
1630                     d_print("dec");
1631                     a4_zp;
1632                     if exec_cycle = T4 then
1633                         set_nz_from_bus;
1634                     end if;
1635
1636                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
1637                     --zp, x
1638                     d_print("dec");
1639
1640                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
1641                     --abs
1642                     d_print("dec");
1643
1644                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
1645                     --abs, x
1646                     d_print("dec");
1647
1648                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
1649                     --zp
1650                     d_print("inc");
1651                     a4_zp;
1652                     if exec_cycle = T4 then
1653                         set_nz_from_bus;
1654                     end if;
1655
1656                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
1657                     --zp, x
1658                     d_print("inc");
1659
1660                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
1661                     --abs
1662                     d_print("inc");
1663                     a4_abs;
1664                     if exec_cycle = T5 then
1665                         set_nz_from_bus;
1666                     end if;
1667
1668                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
1669                     --abs, x
1670                     d_print("inc");
1671
1672                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
1673                     --zp
1674                     d_print("lsr");
1675
1676                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
1677                     --zp, x
1678                     d_print("lsr");
1679
1680                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
1681                     --abs
1682                     d_print("lsr");
1683
1684                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
1685                     --abs, x
1686                     d_print("lsr");
1687
1688                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
1689                     --zp
1690                     d_print("rol");
1691
1692                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
1693                     --zp, x
1694                     d_print("rol");
1695
1696                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
1697                     --abs
1698                     d_print("rol");
1699
1700                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
1701                     --abs, x
1702                     d_print("rol");
1703
1704                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
1705                     --zp
1706                     d_print("ror");
1707 --                    a4_zp;
1708 --                    if exec_cycle = T4 then
1709 --                        set_nzc_from_alu;
1710 --                    end if;
1711
1712                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
1713                     --zp, x
1714                     d_print("ror");
1715
1716                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
1717                     --abs
1718                     d_print("ror");
1719
1720                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
1721                     --abs, x
1722                     d_print("ror");
1723
1724
1725                 ----------------------------------------
1726                 --A.5. miscellaneous oprations.
1727                 ----------------------------------------
1728
1729                 -- A.5.1 push/pull
1730                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1731                     d_print("php");
1732
1733                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1734                     d_print("pha");
1735                     a51_push;
1736                     if exec_cycle = T2 then
1737                         front_oe(acc_cmd, '0');
1738                     end if;
1739
1740                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1741                     d_print("plp");
1742
1743                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1744                     d_print("pla");
1745                     a52_pull;
1746                     if exec_cycle = T3 then
1747                         front_we(acc_cmd, '0');
1748                     end if;
1749
1750
1751                 ----------------------------------------
1752                 -- A.5.3 jsr
1753                 ----------------------------------------
1754                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1755                     if exec_cycle = T1 then
1756                         d_print("jsr abs 2");
1757                         --fetch opcode.
1758                         fetch_next;
1759                         dbuf_int_oe_n <= '0';
1760                         --latch adl
1761                         dl_al_we_n <= '0';
1762                         next_cycle <= T2;
1763                     elsif exec_cycle = T2 then
1764                         d_print("jsr 3");
1765                         fetch_stop;
1766                         dbuf_int_oe_n <= '1';
1767                         dl_al_we_n <= '1';
1768
1769                        --push return addr high into stack.
1770                         sp_push_n <= '0';
1771                         sp_oe_n <= '0';
1772                         front_oe(pch_cmd, '0');
1773                         back_oe(sp_cmd, '0');
1774                         back_we(sp_cmd, '0');
1775                         r_nw <= '0';
1776                         next_cycle <= T3;
1777                     elsif exec_cycle = T3 then
1778                         d_print("jsr 4");
1779                         front_oe(pch_cmd, '1');
1780
1781                        --push return addr low into stack.
1782                         sp_push_n <= '0';
1783                         sp_oe_n <= '0';
1784                         front_oe(pcl_cmd, '0');
1785                         back_oe(sp_cmd, '0');
1786                         back_we(sp_cmd, '0');
1787                         r_nw <= '0';
1788
1789                         next_cycle <= T4;
1790                     elsif exec_cycle = T4 then
1791                         d_print("jsr 5");
1792                         sp_push_n <= '1';
1793                         sp_oe_n <= '1';
1794                         front_oe(pcl_cmd, '1');
1795                         back_oe(sp_cmd, '1');
1796                         back_we(sp_cmd, '1');
1797                         r_nw <= '1';
1798
1799                         --fetch last op.
1800                         back_oe(pch_cmd, '0');
1801                         back_oe(pcl_cmd, '0');
1802                         dbuf_int_oe_n <= '0';
1803                         dl_ah_we_n <= '0';
1804
1805                         next_cycle <= T5;
1806                     elsif exec_cycle = T5 then
1807                         d_print("jsr 6");
1808
1809                         back_oe(pch_cmd, '1');
1810                         back_oe(pcl_cmd, '1');
1811                         dbuf_int_oe_n <= '1';
1812                         dl_ah_we_n <= '1';
1813
1814                         --load/output  pch
1815                         ad_oe_n <= '1';
1816                         dl_dh_oe_n <= '0';
1817                         front_we(pch_cmd, '0');
1818
1819                         --load pcl.
1820                         dl_al_oe_n <= '0';
1821                         back_we(pcl_cmd, '0');
1822
1823                         next_cycle <= T0;
1824                     end if; --if exec_cycle = T1 then
1825
1826                 -- A.5.4 break
1827                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
1828
1829                 ----------------------------------------
1830                 -- A.5.5 return from interrupt
1831                 ----------------------------------------
1832                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
1833
1834                 ----------------------------------------
1835                 -- A.5.6 jmp
1836                 ----------------------------------------
1837                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
1838                     --abs
1839                     if exec_cycle = T1 then
1840                         d_print("jmp 2");
1841                         --fetch next opcode (abs low).
1842                         fetch_next;
1843
1844                         --latch abs low data.
1845                         dbuf_int_oe_n <= '0';
1846                         dl_al_we_n <= '0';
1847                         next_cycle <= T2;
1848                     elsif exec_cycle = T2 then
1849                         d_print("jmp 3");
1850                         dl_al_we_n <= '1';
1851
1852                         --fetch abs hi
1853                         fetch_next;
1854
1855                         --latch  in dlh
1856                         dbuf_int_oe_n <= '0';
1857                         dl_ah_we_n <= '0';
1858                         ---load pch.
1859                         front_we(pch_cmd, '0');
1860
1861                         next_cycle <= T0;
1862                     end if;
1863
1864                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
1865                     --(indir)
1866
1867
1868                 ----------------------------------------
1869                 -- A.5.7 return from soubroutine
1870                 ----------------------------------------
1871                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
1872                     if exec_cycle = T1 then
1873                         d_print("rts 2");
1874                         fetch_stop;
1875
1876                         --pop stack (decrement only)
1877                         back_oe(sp_cmd, '0');
1878                         back_we(sp_cmd, '0');
1879                         sp_pop_n <= '0';
1880                         sp_oe_n <= '0';
1881
1882                         next_cycle <= T2;
1883                     elsif exec_cycle = T2 then
1884                         d_print("rts 3");
1885
1886                         --pop pcl
1887                         back_oe(sp_cmd, '0');
1888                         back_we(sp_cmd, '0');
1889                         sp_pop_n <= '0';
1890                         sp_oe_n <= '0';
1891
1892                         --load lo addr.
1893                         dbuf_int_oe_n <= '0';
1894                         front_we(pcl_cmd, '0');
1895
1896                         next_cycle <= T3;
1897                     elsif exec_cycle = T3 then
1898                         d_print("rts 4");
1899                         --stack decrement stop.
1900                         back_we(sp_cmd, '1');
1901                         sp_pop_n <= '1';
1902                         front_we(pcl_cmd, '1');
1903
1904                         --pop pch
1905                         back_oe(sp_cmd, '0');
1906                         sp_oe_n <= '0';
1907                         --load hi addr.
1908                         dbuf_int_oe_n <= '0';
1909                         front_we(pch_cmd, '0');
1910
1911                         next_cycle <= T4;
1912                     elsif exec_cycle = T4 then
1913                         d_print("rts 5");
1914                         back_oe(sp_cmd, '1');
1915                         sp_oe_n <= '1';
1916                         --load hi addr.
1917                         dbuf_int_oe_n <= '1';
1918                         front_we(pch_cmd, '1');
1919                         --empty cycle.
1920                         --complying h/w manual...
1921                         next_cycle <= T5;
1922                     elsif exec_cycle = T5 then
1923                         d_print("rts 6");
1924
1925                         --increment pc.
1926                         fetch_next;
1927                         next_cycle <= T0;
1928                     end if; --if exec_cycle = T1 then
1929
1930                 ----------------------------------------
1931                 -- A.5.8 branch operations
1932                 ----------------------------------------
1933                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
1934                     d_print("bcc");
1935                     a58_branch (st_C, '0');
1936
1937                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
1938                     d_print("bcs");
1939                     a58_branch (st_C, '1');
1940
1941                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
1942                     d_print("beq");
1943                     a58_branch (st_Z, '1');
1944
1945                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
1946                     d_print("bmi");
1947                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
1948                     d_print("bne");
1949                     a58_branch (st_Z, '0');
1950
1951                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
1952                     d_print("bpl");
1953                     a58_branch (st_N, '0');
1954
1955                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
1956                     d_print("bvc");
1957                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
1958                     d_print("bvs");
1959
1960                 else
1961                     ---unknown instruction!!!!
1962                     assert false
1963                         report "======== unknow instruction "
1964                             & conv_hex8(conv_integer(instruction))
1965                         severity failure;
1966                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
1967
1968             elsif exec_cycle = R0 then
1969                 d_print(string'("reset"));
1970
1971                 front_we(pch_cmd, '1');
1972                 back_we(pcl_cmd, '1');
1973
1974                 --initialize port...
1975                 inst_we_n <= '1';
1976                 ad_oe_n <= '1';
1977                 dbuf_int_oe_n <= '1';
1978                 dl_al_we_n <= '1';
1979                 dl_ah_we_n <= '1';
1980                 dl_al_oe_n <= '1';
1981                 dl_ah_oe_n <= '1';
1982                 dl_dh_oe_n <= '1';
1983                 pcl_inc_n <= '1';
1984                 pcl_cmd <= "1111";
1985                 pch_cmd <= "1111";
1986                 sp_cmd <= "1111";
1987                 sp_oe_n <= '1';
1988                 sp_push_n <= '1';
1989                 sp_pop_n <= '1';
1990                 acc_cmd <= "1111";
1991                 x_cmd <= "1111";
1992                 y_cmd <= "1111";
1993
1994                 abs_xy_n <= '1';
1995                 pg_next_n <= '1';
1996                 zp_n <= '1';
1997                 zp_xy_n <= '1';
1998                 rel_calc_n <= '1';
1999                 indir_n <= '1';
2000                 indir_x_n <= '1';
2001                 indir_y_n <= '1';
2002                 arith_en_n <= '1';
2003
2004                 stat_dec_oe_n <= '1';
2005                 stat_bus_oe_n <= '1';
2006                 stat_set_flg_n <= '1';
2007                 stat_flg <= '1';
2008                 stat_bus_all_n <= '1';
2009                 stat_bus_nz_n <= '1';
2010                 stat_alu_we_n <= '1';
2011
2012                 r_vec_oe_n <= '1';
2013                 n_vec_oe_n <= '1';
2014                 i_vec_oe_n <= '1';
2015                 nmi_handled_n <= '1';
2016                 r_nw <= '1';
2017
2018                 next_cycle <= R1;
2019             elsif exec_cycle = R1 or exec_cycle = N1 then
2020                 --push pch.
2021                 d_print("R1");
2022                 ad_oe_n <= '0';
2023                 sp_push_n <= '0';
2024                 sp_oe_n <= '0';
2025                 front_oe(pch_cmd, '0');
2026                 back_oe(sp_cmd, '0');
2027                 back_we(sp_cmd, '0');
2028                 r_nw <= '0';
2029
2030                 if exec_cycle = R1 then
2031                     next_cycle <= R2;
2032                 elsif exec_cycle = N1 then
2033                     next_cycle <= N2;
2034                 end if;
2035
2036             elsif exec_cycle = R2 or exec_cycle = N2 then
2037                 front_oe(pch_cmd, '1');
2038
2039                --push pcl.
2040                 sp_push_n <= '0';
2041                 sp_oe_n <= '0';
2042                 front_oe(pcl_cmd, '0');
2043                 back_oe(sp_cmd, '0');
2044                 back_we(sp_cmd, '0');
2045                 r_nw <= '0';
2046
2047                 if exec_cycle = R2 then
2048                     next_cycle <= R3;
2049                 elsif exec_cycle = N2 then
2050                     next_cycle <= N3;
2051                 end if;
2052
2053             elsif exec_cycle = R3 or exec_cycle = N3 then
2054                 front_oe(pcl_cmd, '1');
2055
2056                --push status.
2057                 sp_push_n <= '0';
2058                 sp_oe_n <= '0';
2059                 stat_bus_oe_n <= '0';
2060                 back_oe(sp_cmd, '0');
2061                 back_we(sp_cmd, '0');
2062                 r_nw <= '0';
2063
2064                 if exec_cycle = R3 then
2065                     next_cycle <= R4;
2066                 elsif exec_cycle = N3 then
2067                     next_cycle <= N4;
2068                 end if;
2069
2070             elsif exec_cycle = R4 or exec_cycle = N4 then
2071                 stat_bus_oe_n <= '1';
2072                 sp_push_n <= '1';
2073                 sp_oe_n <= '1';
2074                 front_oe(pcl_cmd, '1');
2075                 back_oe(sp_cmd, '1');
2076                 back_we(sp_cmd, '1');
2077
2078                 --fetch reset vector low
2079                 r_nw <= '1';
2080                 dbuf_int_oe_n <= '0';
2081                 front_we(pcl_cmd, '0');
2082
2083                 if exec_cycle = R4 then
2084                     r_vec_oe_n <= '0';
2085                     next_cycle <= R5;
2086                 elsif exec_cycle = N4 then
2087                     n_vec_oe_n <= '0';
2088                     next_cycle <= N5;
2089                 end if;
2090
2091             elsif exec_cycle = R5 or exec_cycle = N5 then
2092                 front_we(pcl_cmd, '1');
2093
2094                 --fetch reset vector hi
2095                 front_we(pch_cmd, '0');
2096                 indir_n <= '0';
2097
2098                 if exec_cycle = N5 then
2099                     nmi_handled_n <= '0';
2100                 end if;
2101                 --start execute cycle.
2102                 next_cycle <= T0;
2103
2104             elsif exec_cycle(5) = '1' then
2105                 ---pc increment and next page.
2106                 d_print(string'("pch next page..."));
2107                 --pcl stop increment
2108                 pcl_inc_n <= '1';
2109                 back_we(pcl_cmd, '1');
2110                 --pch increment
2111                 back_we(pch_cmd, '0');
2112
2113                 if ('0' & exec_cycle(4 downto 0) = T1) then
2114                     --if fetch cycle, preserve instrution register
2115                     inst_we_n <= '1';
2116                 end if;
2117                 back_oe(pch_cmd, '0');
2118
2119             end if; --if exec_cycle = T0 then
2120
2121         end if; --if (set_clk'event and set_clk = '1')
2122
2123     end process;
2124
2125 end rtl;
2126