simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sp_oe_n         : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             pg_next_n       : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             rel_calc_n      : out std_logic;
  43             indir_n         : out std_logic;
  44             indir_x_n       : out std_logic;
  45             indir_y_n       : out std_logic;
  46             arith_en_n      : out std_logic;
  47             stat_dec_oe_n   : out std_logic;
  48             stat_bus_oe_n   : out std_logic;
  49             stat_set_flg_n  : out std_logic;
  50             stat_flg        : out std_logic;
  51             stat_bus_all_n  : out std_logic;
  52             stat_bus_nz_n   : out std_logic;
  53             stat_alu_we_n   : out std_logic;
  54             r_vec_oe_n      : out std_logic;
  55             n_vec_oe_n      : out std_logic;
  56             i_vec_oe_n      : out std_logic;
  57             r_nw            : out std_logic
  58             ;---for parameter check purpose!!!
  59             check_bit     : out std_logic_vector(1 to 5)
  60         );
  61 end decoder;
  62
  63 architecture rtl of decoder is
  64
  65 component d_flip_flop_bit
  66     port (
  67             clk     : in std_logic;
  68             res_n   : in std_logic;
  69             set_n   : in std_logic;
  70             we_n    : in std_logic;
  71             d       : in std_logic;
  72             q       : out std_logic
  73         );
  74 end component;
  75
  76 procedure d_print(msg : string) is
  77 use std.textio.all;
  78 use ieee.std_logic_textio.all;
  79 variable out_l : line;
  80 begin
  81     write(out_l, msg);
  82     writeline(output, out_l);
  83 end  procedure;
  84
  85 ---ival : 0x0000 - 0xffff
  86 function conv_hex8(ival : integer) return string is
  87 variable tmp1, tmp2 : integer;
  88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  89 begin
  90     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  91     tmp1 := ival mod 16 ** 1;
  92     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  93 end;
  94
  95 --cycle bit format
  96 -- bit 5    : pcl increment carry flag
  97 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  98 -- bit 2-0  : cycle
  99
 100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
 101 constant T0 : std_logic_vector (5 downto 0) := "000000";
 102 constant T1 : std_logic_vector (5 downto 0) := "000001";
 103 constant T2 : std_logic_vector (5 downto 0) := "000010";
 104 constant T3 : std_logic_vector (5 downto 0) := "000011";
 105 constant T4 : std_logic_vector (5 downto 0) := "000100";
 106 constant T5 : std_logic_vector (5 downto 0) := "000101";
 107 constant T6 : std_logic_vector (5 downto 0) := "000110";
 108
 109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 110 constant R0 : std_logic_vector (5 downto 0) := "001000";
 111 constant R1 : std_logic_vector (5 downto 0) := "001001";
 112 constant R2 : std_logic_vector (5 downto 0) := "001010";
 113 constant R3 : std_logic_vector (5 downto 0) := "001011";
 114 constant R4 : std_logic_vector (5 downto 0) := "001100";
 115 constant R5 : std_logic_vector (5 downto 0) := "001101";
 116
 117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 118 constant N1 : std_logic_vector (5 downto 0) := "010001";
 119 constant N2 : std_logic_vector (5 downto 0) := "010010";
 120 constant N3 : std_logic_vector (5 downto 0) := "010011";
 121 constant N4 : std_logic_vector (5 downto 0) := "010100";
 122 constant N5 : std_logic_vector (5 downto 0) := "010101";
 123
 124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 125 constant I1 : std_logic_vector (5 downto 0) := "011001";
 126 constant I2 : std_logic_vector (5 downto 0) := "011010";
 127 constant I3 : std_logic_vector (5 downto 0) := "011011";
 128 constant I4 : std_logic_vector (5 downto 0) := "011100";
 129 constant I5 : std_logic_vector (5 downto 0) := "011101";
 130
 131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 132
 133 -- SR Flags (bit 7 to bit 0):
 134 --  7   N   ....    Negative
 135 --  6   V   ....    Overflow
 136 --  5   -   ....    ignored
 137 --  4   B   ....    Break
 138 --  3   D   ....    Decimal (use BCD for arithmetics)
 139 --  2   I   ....    Interrupt (IRQ disable)
 140 --  1   Z   ....    Zero
 141 --  0   C   ....    Carry
 142 constant st_N : integer := 7;
 143 constant st_V : integer := 6;
 144 constant st_B : integer := 4;
 145 constant st_D : integer := 3;
 146 constant st_I : integer := 2;
 147 constant st_Z : integer := 1;
 148 constant st_C : integer := 0;
 149
 150 ---for pch_inc_n.
 151 signal pch_inc_input : std_logic;
 152
 153 ---for nmi handling
 154 signal nmi_handled_n : std_logic;
 155
 156 begin
 157
 158
 159     ---pc page next is connected to top bit of exec_cycle
 160     pch_inc_input <= not exec_cycle(5);
 161     pch_inc_reg : d_flip_flop_bit
 162             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 163
 164     main_p : process (set_clk, res_n, nmi_n)
 165
 166 -------------------------------------------------------------
 167 -------------------------------------------------------------
 168 ----------------------- comon routines ----------------------
 169 -------------------------------------------------------------
 170 -------------------------------------------------------------
 171
 172 ----------gate_cmd format
 173 ------3 : front port oe_n
 174 ------2 : front port we_n
 175 ------1 : back port oe_n
 176 ------0 : back port we_n
 177 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 178     val : in std_logic) is
 179 begin
 180     cmd(3) <= val;
 181 end;
 182 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 183     val : in std_logic) is
 184 begin
 185     cmd(2) <= val;
 186 end;
 187 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 188     val : in std_logic) is
 189 begin
 190     cmd(1) <= val;
 191 end;
 192 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 193     val : in std_logic) is
 194 begin
 195     cmd(0) <= val;
 196 end;
 197
 198 procedure fetch_next is
 199 begin
 200     pcl_inc_n <= '0';
 201     back_oe(pcl_cmd, '0');
 202     back_oe(pch_cmd, '0');
 203     back_we(pcl_cmd, '0');
 204     back_we(pch_cmd, '1');
 205 end procedure;
 206
 207 procedure fetch_stop is
 208 begin
 209     pcl_inc_n <= '1';
 210     back_oe(pcl_cmd, '1');
 211     back_oe(pch_cmd, '1');
 212     back_we(pcl_cmd, '1');
 213 end procedure;
 214
 215 procedure read_status is
 216 begin
 217     status_reg <= (others => 'Z');
 218     stat_dec_oe_n <= '0';
 219 end  procedure;
 220
 221 procedure disable_pins is
 222 begin
 223     --disable the last opration pins.
 224     dbuf_int_oe_n <= '1';
 225     dl_al_we_n <= '1';
 226     dl_ah_we_n <= '1';
 227     dl_ah_oe_n <= '1';
 228     dl_dh_oe_n <= '1';
 229     sp_cmd <= "1111";
 230     sp_oe_n <= '1';
 231     sp_push_n <= '1';
 232     sp_pop_n <= '1';
 233     acc_cmd <= "1111";
 234     x_cmd <= "1111";
 235     y_cmd <= "1111";
 236
 237     abs_xy_n <= '1';
 238     pg_next_n <= '1';
 239     zp_n <= '1';
 240     zp_xy_n <= '1';
 241     rel_calc_n <= '1';
 242     indir_n <= '1';
 243     indir_x_n <= '1';
 244     indir_y_n <= '1';
 245     arith_en_n <= '1';
 246
 247     read_status;
 248     stat_bus_oe_n <= '1';
 249     stat_set_flg_n <= '1';
 250     stat_flg <= '1';
 251     stat_bus_all_n <= '1';
 252     stat_bus_nz_n <= '1';
 253     stat_alu_we_n <= '1';
 254
 255     r_vec_oe_n <= '1';
 256     n_vec_oe_n <= '1';
 257     i_vec_oe_n <= '1';
 258
 259 end  procedure;
 260
 261 procedure fetch_inst is
 262 begin
 263     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 264         --if prior cycle is jump instruction,
 265         --fetch opcode from where the latch is pointing to.
 266
 267         --latch > al.
 268         dl_al_oe_n <= '0';
 269         pcl_cmd <= "1110";
 270     else
 271         --fetch opcode and phc increment.
 272         pcl_cmd <= "1100";
 273         dl_al_oe_n <= '1';
 274     end if;
 275
 276     ad_oe_n <= '0';
 277     pch_cmd <= "1101";
 278     inst_we_n <= '0';
 279     pcl_inc_n <= '0';
 280     r_nw <= '1';
 281
 282     disable_pins;
 283     d_print(string'("fetch 1"));
 284 end  procedure;
 285
 286 ---T0 cycle routine
 287 ---(along with the page boundary condition, the last
 288 ---cycle is bypassed and slided to T0.)
 289 procedure t0_cycle is
 290 begin
 291     if (nmi_n = '0' and nmi_handled_n = '1') then
 292         disable_pins;
 293         pcl_cmd <= "1111";
 294         pch_cmd <= "1111";
 295         pcl_inc_n <= '1';
 296         inst_we_n <= '1';
 297         r_nw <= '1';
 298         next_cycle <= N1;
 299     else
 300         fetch_inst;
 301         next_cycle <= T1;
 302     end if;
 303 end  procedure;
 304
 305 ---common routine for single byte instruction.
 306 procedure single_inst is
 307 begin
 308     fetch_stop;
 309     next_cycle <= T0;
 310 end  procedure;
 311
 312 procedure fetch_imm is
 313 begin
 314     d_print("immediate");
 315     fetch_next;
 316     --send data from data bus buffer.
 317     --receiver is instruction dependent.
 318     dbuf_int_oe_n <= '0';
 319     next_cycle <= T0;
 320 end  procedure;
 321
 322 procedure set_nz_from_bus is
 323 begin
 324     --status register n/z bit update.
 325     stat_dec_oe_n <= '1';
 326     status_reg <= "10000010";
 327     stat_bus_nz_n <= '0';
 328 end  procedure;
 329
 330 procedure set_nzc_from_bus is
 331 begin
 332     --status register n,z,c bit update.
 333     stat_dec_oe_n <= '1';
 334     status_reg <= "10000011";
 335     stat_bus_nz_n <= '0';
 336 end  procedure;
 337
 338 procedure set_nz_from_alu is
 339 begin
 340     --status register n/z/c bit update.
 341     stat_alu_we_n <= '0';
 342     stat_dec_oe_n <= '1';
 343     status_reg <= "10000010";
 344 end  procedure;
 345
 346 procedure set_nzc_from_alu is
 347 begin
 348     --status register n/z/c bit update.
 349     stat_alu_we_n <= '0';
 350     stat_dec_oe_n <= '1';
 351     status_reg <= "10000011";
 352 end  procedure;
 353
 354 procedure set_nvz_from_alu is
 355 begin
 356     --status register n/z/v bit update.
 357     stat_alu_we_n <= '0';
 358     stat_dec_oe_n <= '1';
 359     status_reg <= "11000010";
 360 end  procedure;
 361
 362 procedure set_nvzc_from_alu is
 363 begin
 364     stat_alu_we_n <= '0';
 365     stat_dec_oe_n <= '1';
 366     status_reg <= "11000011";
 367 end  procedure;
 368
 369 --flag on/off instruction
 370 procedure set_flag (int_flg : in integer; val : in std_logic) is
 371 begin
 372     stat_dec_oe_n <= '1';
 373     stat_set_flg_n <= '0';
 374     --specify which to set.
 375     status_reg(7 downto int_flg + 1)
 376         <= (others =>'0');
 377     status_reg(int_flg - 1 downto 0)
 378         <= (others =>'0');
 379     status_reg(int_flg) <= '1';
 380     stat_flg <= val;
 381 end  procedure;
 382
 383 --for sec/clc
 384 procedure set_flag0 (val : in std_logic) is
 385 begin
 386     stat_dec_oe_n <= '1';
 387     stat_set_flg_n <= '0';
 388     status_reg <= "00000001";
 389     stat_flg <= val;
 390 end  procedure;
 391
 392 procedure fetch_low is
 393 begin
 394     d_print("fetch low 2");
 395     --fetch next opcode (abs low).
 396     fetch_next;
 397     --latch abs low data.
 398     dbuf_int_oe_n <= '0';
 399     dl_al_we_n <= '0';
 400     next_cycle <= T2;
 401 end  procedure;
 402
 403 procedure abs_fetch_high is
 404 begin
 405     d_print("abs (xy) 3");
 406     dl_al_we_n <= '1';
 407
 408     --latch abs hi data.
 409     fetch_next;
 410     dbuf_int_oe_n <= '0';
 411     dl_ah_we_n <= '0';
 412     next_cycle <= T3;
 413 end  procedure;
 414
 415 procedure abs_latch_out is
 416 begin
 417     --d_print("abs 4");
 418     fetch_stop;
 419     dl_ah_we_n <= '1';
 420
 421     --latch > al/ah.
 422     dl_al_oe_n <= '0';
 423     dl_ah_oe_n <= '0';
 424 end  procedure;
 425
 426 procedure ea_x_out is
 427 begin
 428     -----calucurate and output effective addr
 429     back_oe(x_cmd, '0');
 430     abs_xy_n <= '0';
 431 end  procedure;
 432
 433 procedure ea_y_out is
 434 begin
 435     back_oe(y_cmd, '0');
 436     abs_xy_n <= '0';
 437 end  procedure;
 438
 439 --A.2. internal execution on memory data
 440
 441 procedure a2_zp is
 442 begin
 443     if exec_cycle = T1 then
 444         fetch_low;
 445     elsif exec_cycle = T2 then
 446         fetch_stop;
 447         dbuf_int_oe_n <= '0';
 448         dl_al_we_n <= '1';
 449
 450         --calc zp.
 451         dl_al_oe_n <= '0';
 452         zp_n <= '0';
 453         next_cycle <= T0;
 454     end if;
 455 end  procedure;
 456
 457 procedure a2_abs is
 458 begin
 459     if exec_cycle = T1 then
 460         fetch_low;
 461     elsif exec_cycle = T2 then
 462         abs_fetch_high;
 463     elsif exec_cycle = T3 then
 464         abs_latch_out;
 465         dbuf_int_oe_n <= '0';
 466         next_cycle <= T0;
 467     end if;
 468 end  procedure;
 469
 470 procedure a2_abs_xy (is_x : in boolean) is
 471 begin
 472     if exec_cycle = T1 then
 473         fetch_low;
 474     elsif exec_cycle = T2 then
 475         abs_fetch_high;
 476     elsif exec_cycle = T3 then
 477         --ea calc & lda
 478         pg_next_n <= '1';
 479         abs_latch_out;
 480         if (is_x = true) then
 481             ea_x_out;
 482         else
 483             ea_y_out;
 484         end if;
 485         dbuf_int_oe_n <= '0';
 486         --instruction specific operation wriiten in the caller position.
 487         next_cycle <= T4;
 488     elsif exec_cycle = T4 then
 489         if ea_carry = '1' then
 490             --case page boundary crossed.
 491             d_print("absx 5 (page boudary crossed.)");
 492             abs_latch_out;
 493             if (is_x = true) then
 494                 ea_x_out;
 495             else
 496                 ea_y_out;
 497             end if;
 498             dbuf_int_oe_n <= '0';
 499             --next page.
 500             pg_next_n <= not ea_carry;
 501             --redo inst.
 502             next_cycle <= T0;
 503         else
 504             --case page boundary not crossed. do the fetch op.
 505             d_print("absx 5 (fetch)");
 506             t0_cycle;
 507         end if;
 508     end if;
 509 end  procedure;
 510
 511 procedure a2_indir_y is
 512 begin
 513     if exec_cycle = T1 then
 514         fetch_low;
 515         --get IAL
 516         dl_al_we_n <= '0';
 517
 518     elsif exec_cycle = T2 then
 519         fetch_stop;
 520         dl_al_we_n <= '1';
 521
 522         ---address is 00:IAL
 523         --output BAL @IAL
 524         indir_y_n <= '0';
 525         dl_al_oe_n <= '0';
 526         dbuf_int_oe_n <= '0';
 527         next_cycle <= T3;
 528
 529     elsif exec_cycle = T3 then
 530         indir_y_n <= '0';
 531         dl_al_oe_n <= '0';
 532         --output BAH @IAL+1
 533         dbuf_int_oe_n <= '0';
 534         next_cycle <= T4;
 535
 536     elsif exec_cycle = T4 then
 537         dl_al_oe_n <= '1';
 538         dbuf_int_oe_n <= '1';
 539
 540         --add index y.
 541         pg_next_n <= '1';
 542         back_oe(y_cmd, '0');
 543         indir_y_n <= '0';
 544         dbuf_int_oe_n <= '0';
 545         next_cycle <= T5;
 546
 547     elsif exec_cycle = T5 then
 548         if ea_carry = '1' then
 549             --case page boundary crossed.
 550             d_print("(indir), y (page boudary crossed.)");
 551             back_oe(y_cmd, '1');
 552             indir_y_n <= '0';
 553             dbuf_int_oe_n <= '0';
 554             pg_next_n <= not ea_carry;
 555             next_cycle <= T0;
 556         else
 557             --case page boundary not crossed. do the fetch op.
 558             d_print("(indir), y (next fetch)");
 559             t0_cycle;
 560         end if;
 561
 562     end if;
 563 end  procedure;
 564
 565 --A.3. store operation.
 566
 567 procedure a3_zp is
 568 begin
 569     if exec_cycle = T1 then
 570         fetch_low;
 571     elsif exec_cycle = T2 then
 572         fetch_stop;
 573         dbuf_int_oe_n <= '1';
 574         dl_al_we_n <= '1';
 575
 576         --calc zp.
 577         dl_al_oe_n <= '0';
 578         zp_n <= '0';
 579         r_nw <= '0';
 580         next_cycle <= T0;
 581     end if;
 582 end  procedure;
 583
 584 procedure a3_abs is
 585 begin
 586     if exec_cycle = T1 then
 587         fetch_low;
 588     elsif exec_cycle = T2 then
 589         abs_fetch_high;
 590     elsif exec_cycle = T3 then
 591         abs_latch_out;
 592         dbuf_int_oe_n <= '1';
 593         r_nw <= '0';
 594         next_cycle <= T0;
 595     end if;
 596 end  procedure;
 597
 598 procedure a3_abs_xy (is_x : in boolean) is
 599 begin
 600     if exec_cycle = T1 then
 601         fetch_low;
 602     elsif exec_cycle = T2 then
 603         abs_fetch_high;
 604     elsif exec_cycle = T3 then
 605         --ea calc & lda
 606         pg_next_n <= '1';
 607         abs_latch_out;
 608         dbuf_int_oe_n <= '1';
 609         if (is_x = true) then
 610             ea_x_out;
 611         else
 612             ea_y_out;
 613         end if;
 614         next_cycle <= T4;
 615     elsif exec_cycle = T4 then
 616         pg_next_n <= not ea_carry;
 617         abs_latch_out;
 618         if (is_x = true) then
 619             ea_x_out;
 620         else
 621             ea_y_out;
 622         end if;
 623         r_nw <= '0';
 624         next_cycle <= T0;
 625     end if;
 626 end  procedure;
 627
 628
 629 procedure a3_indir_y is
 630 begin
 631     if exec_cycle = T1 then
 632         fetch_low;
 633         --get IAL
 634         dl_al_we_n <= '0';
 635
 636     elsif exec_cycle = T2 then
 637         fetch_stop;
 638         dl_al_we_n <= '1';
 639
 640         ---address is 00:IAL
 641         --output BAL @IAL
 642         indir_y_n <= '0';
 643         dl_al_oe_n <= '0';
 644         dbuf_int_oe_n <= '0';
 645         next_cycle <= T3;
 646
 647     elsif exec_cycle = T3 then
 648         indir_y_n <= '0';
 649         dl_al_oe_n <= '0';
 650         --output BAH @IAL+1
 651         dbuf_int_oe_n <= '0';
 652         next_cycle <= T4;
 653
 654     elsif exec_cycle = T4 then
 655         dl_al_oe_n <= '1';
 656         dbuf_int_oe_n <= '1';
 657
 658         --add index y.
 659         pg_next_n <= '1';
 660         back_oe(y_cmd, '0');
 661         indir_y_n <= '0';
 662         next_cycle <= T5;
 663
 664     elsif exec_cycle = T5 then
 665
 666         --page handling.
 667         back_oe(y_cmd, '1');
 668         indir_y_n <= '0';
 669         pg_next_n <= not ea_carry;
 670         r_nw <= '0';
 671         next_cycle <= T0;
 672     end if;
 673 end  procedure;
 674
 675
 676 ---A.4. read-modify-write operation
 677
 678 procedure a4_zp is
 679 begin
 680     if exec_cycle = T1 then
 681         fetch_low;
 682     elsif exec_cycle = T2 then
 683         fetch_stop;
 684         dbuf_int_oe_n <= '1';
 685         dl_al_we_n <= '1';
 686
 687         --t2 cycle only read
 688         dl_al_oe_n <= '0';
 689         zp_n <= '0';
 690         next_cycle <= T3;
 691     elsif exec_cycle = T3 then
 692         dl_al_oe_n <= '0';
 693         zp_n <= '0';
 694         --keep data in the alu reg.
 695         arith_en_n <= '0';
 696         dbuf_int_oe_n <= '0';
 697         next_cycle <= T4;
 698     elsif exec_cycle = T4 then
 699         dbuf_int_oe_n <= '1';
 700
 701         --t5 cycle writes modified value.
 702         dl_al_oe_n <= '0';
 703         zp_n <= '0';
 704         r_nw <= '0';
 705         arith_en_n <= '0';
 706         next_cycle <= T0;
 707     end if;
 708 end  procedure;
 709
 710
 711 procedure a4_abs is
 712 begin
 713     if exec_cycle = T1 then
 714         fetch_low;
 715     elsif exec_cycle = T2 then
 716         abs_fetch_high;
 717     elsif exec_cycle = T3 then
 718         --T3 cycle do nothing.
 719         abs_latch_out;
 720         next_cycle <= T4;
 721     elsif exec_cycle = T4 then
 722         abs_latch_out;
 723
 724         --t4 cycle save data in the alu register only.
 725         --hardware maunual says write original data,
 726         --but this implementation doesn't write because bus shortage....
 727         arith_en_n <= '0';
 728         next_cycle <= T5;
 729     elsif exec_cycle = T5 then
 730         dbuf_int_oe_n <= '1';
 731
 732         --t5 cycle writes modified value.
 733         r_nw <= '0';
 734         arith_en_n <= '0';
 735         next_cycle <= T0;
 736     end if;
 737 end  procedure;
 738
 739
 740 -- A.5.1 push stack
 741 procedure a51_push is
 742 begin
 743     if exec_cycle = T1 then
 744         fetch_stop;
 745         next_cycle <= T2;
 746     elsif exec_cycle = T2 then
 747         back_oe(sp_cmd, '0');
 748         back_we(sp_cmd, '0');
 749         sp_push_n <= '0';
 750         sp_oe_n <= '0';
 751         r_nw <= '0';
 752         next_cycle <= T0;
 753     end if;
 754 end procedure;
 755
 756 -- A.5.2 pull stack
 757 procedure a52_pull is
 758 begin
 759     if exec_cycle = T1 then
 760         fetch_stop;
 761         next_cycle <= T2;
 762
 763     elsif exec_cycle = T2 then
 764         --stack decrement first.
 765         back_oe(sp_cmd, '0');
 766         back_we(sp_cmd, '0');
 767         sp_pop_n <= '0';
 768         sp_oe_n <= '0';
 769         next_cycle <= T3;
 770
 771     elsif exec_cycle = T3 then
 772         sp_pop_n <= '1';
 773         back_we(sp_cmd, '1');
 774
 775         ---pop data from stack.
 776         back_oe(sp_cmd, '0');
 777         sp_oe_n <= '0';
 778         dbuf_int_oe_n <= '0';
 779         next_cycle <= T0;
 780     end if;
 781 end procedure;
 782
 783
 784 -- A.5.8 branch operations
 785
 786 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 787 begin
 788     if exec_cycle = T1 then
 789         fetch_next;
 790         if status_reg(int_flg) = br_cond then
 791             d_print("get rel");
 792
 793             --latch rel value.
 794             dbuf_int_oe_n <= '0';
 795             dl_ah_we_n <= '0';
 796             next_cycle <= T2;
 797         else
 798             d_print("no branch");
 799             next_cycle <= T0;
 800         end if;
 801     elsif exec_cycle = T2 then
 802         d_print("rel ea");
 803         fetch_stop;
 804         dbuf_int_oe_n <= '1';
 805         dl_ah_we_n <= '1';
 806
 807         --calc relative addr.
 808         rel_calc_n <= '0';
 809         pg_next_n <= '1';
 810         dl_dh_oe_n <= '0';
 811         back_oe(pcl_cmd, '0');
 812         back_oe(pch_cmd, '0');
 813         back_we(pcl_cmd, '0');
 814
 815         next_cycle <= T3;
 816     elsif exec_cycle = T3 then
 817
 818         if ea_carry = '1' then
 819             d_print("page crossed.");
 820             --page crossed. adh calc.
 821             back_we(pcl_cmd, '1');
 822             back_oe(pcl_cmd, '0');
 823             back_oe(pch_cmd, '0');
 824             back_we(pch_cmd, '0');
 825             dl_dh_oe_n <= '0';
 826
 827             rel_calc_n <= '0';
 828             pg_next_n <= not ea_carry;
 829             next_cycle <= T0;
 830         else
 831             --no page boundary.
 832             --fetch cycle is done.
 833             t0_cycle;
 834         end if;
 835     end if;
 836 end  procedure;
 837
 838 -------------------------------------------------------------
 839 -------------------------------------------------------------
 840 ---------------- main state machine start.... ---------------
 841 -------------------------------------------------------------
 842 -------------------------------------------------------------
 843     begin
 844
 845         if (res_n = '0') then
 846             --pc l/h is reset vector.
 847             pcl_cmd <= "1110";
 848             pch_cmd <= "1110";
 849             next_cycle <= R0;
 850         elsif (res_n'event and res_n = '1') then
 851             pcl_cmd <= "1111";
 852             pch_cmd <= "1111";
 853         end if;
 854
 855         if (nmi_n'event and nmi_n = '1') then
 856             --reset nmi handle status
 857             nmi_handled_n <= '1';
 858         end if;
 859
 860         if (set_clk'event and set_clk = '1' and res_n = '1') then
 861             d_print(string'("-"));
 862
 863             if exec_cycle = T0 then
 864                 --cycle #1
 865                 t0_cycle;
 866
 867             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 868                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
 869                 --execute inst.
 870
 871                 ---asyncronous page change might happen.
 872                 back_we(pch_cmd, '1');
 873
 874                 if exec_cycle = T1 then
 875                     d_print("decode and execute inst: "
 876                             & conv_hex8(conv_integer(instruction)));
 877                     --disable pin since jmp instruction
 878                     --directly enters into t2 cycle.
 879                     dl_al_oe_n <= '1';
 880                     back_we(pcl_cmd, '1');
 881                     front_we(pch_cmd, '1');
 882
 883                     --grab instruction register data.
 884                     inst_we_n <= '1';
 885                 end if;
 886
 887                 --imelementation is wriiten in the order of hardware manual
 888                 --appendix A.
 889
 890                 ----------------------------------------
 891                 --A.1. Single byte instruction.
 892                 ----------------------------------------
 893                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 894                     --asl acc mode.
 895                     d_print("asl");
 896
 897                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 898                     d_print("clc");
 899                     set_flag0 ('0');
 900                     single_inst;
 901
 902                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 903                     d_print("cld");
 904                     set_flag (st_D, '0');
 905                     single_inst;
 906
 907                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 908                     d_print("cli");
 909
 910                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 911                     d_print("clv");
 912
 913                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 914                     d_print("dex");
 915                     arith_en_n <= '0';
 916                     back_oe(x_cmd, '0');
 917                     front_we(x_cmd, '0');
 918                     --set nz bit.
 919                     set_nz_from_bus;
 920                     single_inst;
 921
 922                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
 923                     d_print("dey");
 924                     arith_en_n <= '0';
 925                     back_oe(y_cmd, '0');
 926                     front_we(y_cmd, '0');
 927                     --set nz bit.
 928                     set_nz_from_bus;
 929                     single_inst;
 930
 931                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
 932                     d_print("inx");
 933                     arith_en_n <= '0';
 934                     back_oe(x_cmd, '0');
 935                     front_we(x_cmd, '0');
 936                     --set nz bit.
 937                     set_nz_from_bus;
 938                     single_inst;
 939
 940                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
 941                     d_print("iny");
 942                     arith_en_n <= '0';
 943                     back_oe(y_cmd, '0');
 944                     front_we(y_cmd, '0');
 945                     set_nz_from_bus;
 946                     single_inst;
 947
 948                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
 949                     --lsr acc mode
 950                     d_print("lsr");
 951                     arith_en_n <= '0';
 952                     back_oe(acc_cmd, '0');
 953                     front_we(acc_cmd, '0');
 954                     set_nzc_from_bus;
 955                     single_inst;
 956
 957                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
 958                     d_print("nop");
 959                     single_inst;
 960
 961                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
 962                     --rol acc
 963                     d_print("rol");
 964
 965                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
 966                     d_print("sec");
 967                     set_flag0 ('1');
 968                     single_inst;
 969
 970                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
 971                     d_print("sed");
 972                     set_flag (st_D, '1');
 973                     single_inst;
 974
 975                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
 976                     d_print("sei");
 977                     set_flag (st_I, '1');
 978                     single_inst;
 979
 980                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
 981                     d_print("tax");
 982                     set_nz_from_bus;
 983                     single_inst;
 984                     front_oe(acc_cmd, '0');
 985                     front_we(x_cmd, '0');
 986
 987                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
 988                     d_print("tay");
 989                     set_nz_from_bus;
 990                     single_inst;
 991                     front_oe(acc_cmd, '0');
 992                     front_we(y_cmd, '0');
 993
 994                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
 995                     d_print("tsx");
 996                     set_nz_from_bus;
 997
 998                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
 999                     d_print("txa");
1000                     set_nz_from_bus;
1001                     single_inst;
1002                     front_oe(x_cmd, '0');
1003                     front_we(acc_cmd, '0');
1004
1005                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1006                     d_print("txs");
1007                     set_nz_from_bus;
1008                     single_inst;
1009                     front_oe(x_cmd, '0');
1010                     front_we(sp_cmd, '0');
1011
1012                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1013                     d_print("tya");
1014                     set_nz_from_bus;
1015                     single_inst;
1016                     front_oe(y_cmd, '0');
1017                     front_we(acc_cmd, '0');
1018
1019
1020
1021                 ----------------------------------------
1022                 --A.2. internal execution on memory data
1023                 ----------------------------------------
1024                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1025                     --imm
1026                     d_print("adc");
1027                     fetch_imm;
1028                     arith_en_n <= '0';
1029                     back_oe(acc_cmd, '0');
1030                     back_we(acc_cmd, '0');
1031                     set_nvzc_from_alu;
1032
1033                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1034                     --zp
1035                     d_print("adc");
1036                     a2_zp;
1037                     if exec_cycle = T2 then
1038                         arith_en_n <= '0';
1039                         back_oe(acc_cmd, '0');
1040                         back_we(acc_cmd, '0');
1041                         set_nvzc_from_alu;
1042                     end if;
1043
1044                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1045                     --zp, x
1046                     d_print("adc");
1047
1048                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1049                     --abs
1050                     d_print("adc");
1051
1052                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1053                     --abs, x
1054                     d_print("adc");
1055
1056                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1057                     --abs, y
1058                     d_print("adc");
1059
1060                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1061                     --(indir, x)
1062                     d_print("adc");
1063
1064                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1065                     --(indir), y
1066                     d_print("adc");
1067
1068                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1069                     --imm
1070                     d_print("and");
1071                     fetch_imm;
1072                     arith_en_n <= '0';
1073                     back_oe(acc_cmd, '0');
1074                     back_we(acc_cmd, '0');
1075                     set_nz_from_alu;
1076
1077                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1078                     --zp
1079                     d_print("and");
1080                     a2_zp;
1081                     if exec_cycle = T2 then
1082                         arith_en_n <= '0';
1083                         back_oe(acc_cmd, '0');
1084                         back_we(acc_cmd, '0');
1085                         set_nz_from_alu;
1086                     end if;
1087
1088                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1089                     --zp, x
1090                     d_print("and");
1091
1092                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1093                     --abs
1094                     d_print("and");
1095
1096                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1097                     --abs, x
1098                     d_print("and");
1099
1100                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1101                     --abs, y
1102                     d_print("and");
1103
1104                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1105                     --(indir, x)
1106                     d_print("and");
1107
1108                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1109                     --(indir), y
1110                     d_print("and");
1111
1112                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1113                     --zp
1114                     d_print("bit");
1115
1116                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1117                     --abs
1118                     d_print("bit");
1119                     a2_abs;
1120                     if exec_cycle = T3 then
1121                         arith_en_n <= '0';
1122                         set_nvz_from_alu;
1123                     end if;
1124
1125                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1126                     --imm
1127                     d_print("cmp");
1128                     fetch_imm;
1129                     arith_en_n <= '0';
1130                     back_oe(acc_cmd, '0');
1131                     set_nzc_from_alu;
1132
1133                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1134                     --zp
1135                     d_print("cmp");
1136                     a2_zp;
1137                     if exec_cycle = T2 then
1138                         arith_en_n <= '0';
1139                         back_oe(acc_cmd, '0');
1140                         set_nzc_from_alu;
1141                     end if;
1142
1143                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1144                     --zp, x
1145                     d_print("cmp");
1146
1147                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1148                     --abs
1149                     d_print("cmp");
1150
1151                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1152                     --abs, x
1153                     d_print("cmp");
1154
1155                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1156                     --abs, y
1157                     d_print("cmp");
1158                     a2_abs_xy(false);
1159                     if exec_cycle = T3 then
1160                         arith_en_n <= '0';
1161                         back_oe(acc_cmd, '0');
1162                         set_nzc_from_alu;
1163                     elsif exec_cycle = T4 then
1164                         if ea_carry = '1' then
1165                             arith_en_n <= '0';
1166                             back_oe(acc_cmd, '0');
1167                             set_nzc_from_alu;
1168                         end if;
1169                     end if;
1170
1171                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1172                     --(indir, x)
1173                     d_print("cmp");
1174
1175                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1176                     --(indir), y
1177                     d_print("cmp");
1178
1179                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1180                     --imm
1181                     d_print("cpx");
1182                     fetch_imm;
1183                     arith_en_n <= '0';
1184                     back_oe(x_cmd, '0');
1185                     set_nzc_from_alu;
1186
1187                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1188                     --zp
1189                     d_print("cpx");
1190                     a2_zp;
1191                     if exec_cycle = T2 then
1192                         arith_en_n <= '0';
1193                         back_oe(x_cmd, '0');
1194                         set_nzc_from_alu;
1195                     end if;
1196
1197                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1198                     --abs
1199                     d_print("cpx");
1200
1201                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1202                     --imm
1203                     d_print("cpy");
1204                     fetch_imm;
1205                     arith_en_n <= '0';
1206                     back_oe(y_cmd, '0');
1207                     set_nzc_from_alu;
1208
1209                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1210                     --zp
1211                     d_print("cpy");
1212
1213                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1214                     --abs
1215                     d_print("cpy");
1216
1217                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1218                     --imm
1219                     d_print("eor");
1220                     fetch_imm;
1221                     arith_en_n <= '0';
1222                     back_oe(acc_cmd, '0');
1223                     back_we(acc_cmd, '0');
1224                     set_nz_from_alu;
1225
1226                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1227                     --zp
1228                     d_print("eor");
1229                     a2_zp;
1230                     if exec_cycle = T2 then
1231                         arith_en_n <= '0';
1232                         back_oe(acc_cmd, '0');
1233                         back_we(acc_cmd, '0');
1234                         set_nz_from_alu;
1235                     end if;
1236
1237                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1238                     --zp, x
1239                     d_print("eor");
1240
1241                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1242                     --abs
1243                     d_print("eor");
1244
1245                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1246                     --abs, x
1247                     d_print("eor");
1248
1249                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1250                     --abs, y
1251                     d_print("eor");
1252
1253                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1254                     --(indir, x)
1255                     d_print("eor");
1256
1257                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1258                     --(indir), y
1259                     d_print("eor");
1260
1261                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1262                     --imm
1263                     d_print("lda");
1264                     fetch_imm;
1265                     front_we(acc_cmd, '0');
1266                     set_nz_from_bus;
1267
1268                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1269                     --zp
1270                     d_print("lda");
1271                     a2_zp;
1272                     if exec_cycle = T2 then
1273                         front_we(acc_cmd, '0');
1274                         set_nz_from_bus;
1275                     end if;
1276
1277                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1278                     --zp, x
1279                     d_print("lda");
1280
1281                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1282                     --abs
1283                     d_print("lda");
1284                     a2_abs;
1285                     if exec_cycle = T3 then
1286                         set_nz_from_bus;
1287                         front_we(acc_cmd, '0');
1288                     end if;
1289
1290                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1291                     --abs, x
1292                     d_print("lda");
1293                     a2_abs_xy(true);
1294                     if exec_cycle = T3 then
1295                         --lda.
1296                         front_we(acc_cmd, '0');
1297                         set_nz_from_bus;
1298                     elsif exec_cycle = T4 then
1299                         if ea_carry = '1' then
1300                             --redo lda
1301                             front_we(acc_cmd, '0');
1302                             set_nz_from_bus;
1303                         end if;
1304                     end if;
1305
1306                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1307                     --abs, y
1308                     d_print("lda");
1309                     a2_abs_xy(false);
1310                     if exec_cycle = T3 then
1311                         --lda.
1312                         front_we(acc_cmd, '0');
1313                         set_nz_from_bus;
1314                     elsif exec_cycle = T4 then
1315                         if ea_carry = '1' then
1316                             --redo lda
1317                             front_we(acc_cmd, '0');
1318                             set_nz_from_bus;
1319                         end if;
1320                     end if;
1321
1322                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1323                     --(indir, x)
1324                     d_print("lda");
1325
1326                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1327                     --(indir), y
1328                     d_print("lda");
1329                     a2_indir_y;
1330                     if exec_cycle = T4 then
1331                         --lda.
1332                         front_we(acc_cmd, '0');
1333                         set_nz_from_bus;
1334                     elsif exec_cycle = T5 then
1335                         if ea_carry = '1' then
1336                             --redo lda
1337                             front_we(acc_cmd, '0');
1338                             set_nz_from_bus;
1339                         end if;
1340                     end if;
1341
1342                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1343                     --imm
1344                     d_print("ldx");
1345                     fetch_imm;
1346                     set_nz_from_bus;
1347                     front_we(x_cmd, '0');
1348
1349                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1350                     --zp
1351                     d_print("ldx");
1352                     a2_zp;
1353                     if exec_cycle = T2 then
1354                         front_we(x_cmd, '0');
1355                         set_nz_from_bus;
1356                     end if;
1357
1358                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1359                     --zp, y
1360                     d_print("ldx");
1361
1362                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1363                     --abs
1364                     d_print("ldx");
1365                     a2_abs;
1366                     if exec_cycle = T3 then
1367                         set_nz_from_bus;
1368                         front_we(x_cmd, '0');
1369                     end if;
1370
1371                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1372                     --abs, y
1373                     d_print("ldx");
1374                     a2_abs_xy(false);
1375                     if exec_cycle = T3 then
1376                         --lda.
1377                         front_we(x_cmd, '0');
1378                         set_nz_from_bus;
1379                     elsif exec_cycle = T4 then
1380                         if ea_carry = '1' then
1381                             --redo lda
1382                             front_we(x_cmd, '0');
1383                             set_nz_from_bus;
1384                         end if;
1385                     end if;
1386
1387                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1388                     --imm
1389                     d_print("ldy");
1390                     fetch_imm;
1391                     set_nz_from_bus;
1392                     front_we(y_cmd, '0');
1393
1394                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1395                     --zp
1396                     d_print("ldy");
1397
1398                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1399                     --zp, x
1400                     d_print("ldy");
1401
1402                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1403                     --abs
1404                     d_print("ldy");
1405                     a2_abs;
1406                     if exec_cycle = T3 then
1407                         set_nz_from_bus;
1408                         front_we(y_cmd, '0');
1409                     end if;
1410
1411                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1412                     --abs, x
1413                     d_print("ldy");
1414
1415                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1416                     --imm
1417                     d_print("ora");
1418                     fetch_imm;
1419                     arith_en_n <= '0';
1420                     back_oe(acc_cmd, '0');
1421                     back_we(acc_cmd, '0');
1422                     set_nz_from_alu;
1423
1424                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1425                     --zp
1426                     d_print("ora");
1427                     a2_zp;
1428                     if exec_cycle = T2 then
1429                         arith_en_n <= '0';
1430                         back_oe(acc_cmd, '0');
1431                         back_we(acc_cmd, '0');
1432                         set_nz_from_alu;
1433                     end if;
1434
1435                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1436                     --zp, x
1437                     d_print("ora");
1438
1439                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1440                     --abs
1441                     d_print("ora");
1442
1443                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1444                     --abs, x
1445                     d_print("ora");
1446
1447                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1448                     --abs, y
1449                     d_print("ora");
1450
1451                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1452                     --(indir, x)
1453                     d_print("ora");
1454
1455                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1456                     --(indir), y
1457                     d_print("ora");
1458
1459                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1460                     --imm
1461                     d_print("sbc");
1462
1463                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1464                     --zp
1465                     d_print("sbc");
1466
1467                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1468                     --zp, x
1469                     d_print("sbc");
1470
1471                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1472                     --abs
1473                     d_print("sbc");
1474
1475                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1476                     --abs, x
1477                     d_print("sbc");
1478
1479                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1480                     --abs, y
1481                     d_print("sbc");
1482
1483                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
1484                     --(indir, x)
1485                     d_print("sbc");
1486
1487                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
1488                     --(indir), y
1489                     d_print("sbc");
1490
1491
1492
1493                 ----------------------------------------
1494                 ---A.3. store operation.
1495                 ----------------------------------------
1496                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
1497                     --zp
1498                     d_print("sta");
1499                     a3_zp;
1500                     if exec_cycle = T2 then
1501                         front_oe(acc_cmd, '0');
1502                     end if;
1503
1504                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
1505                     --zp, x
1506                     d_print("sta");
1507
1508                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
1509                     --abs
1510                     d_print("sta");
1511                     a3_abs;
1512                     if exec_cycle = T3 then
1513                         front_oe(acc_cmd, '0');
1514                     end if;
1515
1516                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
1517                     --abs, x
1518                     d_print("sta");
1519                     a3_abs_xy (true);
1520                     if exec_cycle = T4 then
1521                         front_oe(acc_cmd, '0');
1522                     end if;
1523
1524                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
1525                     --abs, y
1526                     d_print("sta");
1527                     a3_abs_xy (false);
1528                     if exec_cycle = T4 then
1529                         front_oe(acc_cmd, '0');
1530                     end if;
1531
1532                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
1533                     --(indir, x)
1534                     d_print("sta");
1535
1536                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
1537                     --(indir), y
1538                     d_print("sta");
1539                     a3_indir_y;
1540                     if exec_cycle = T5 then
1541                         front_oe(acc_cmd, '0');
1542                     end if;
1543
1544                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
1545                     --zp
1546                     d_print("stx");
1547                     a3_zp;
1548                     if exec_cycle = T2 then
1549                         front_oe(x_cmd, '0');
1550                     end if;
1551
1552                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
1553                     --zp, y
1554                     d_print("stx");
1555
1556                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
1557                     --abs
1558                     d_print("stx");
1559
1560                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
1561                     --zp
1562                     d_print("sty");
1563                     a3_zp;
1564                     if exec_cycle = T2 then
1565                         front_oe(y_cmd, '0');
1566                     end if;
1567
1568                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
1569                     --zp, x
1570                     d_print("sty");
1571
1572                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
1573                     --abs
1574                     d_print("sty");
1575
1576
1577                 ----------------------------------------
1578                 ---A.4. read-modify-write operation
1579                 ----------------------------------------
1580                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
1581                     --zp
1582                     d_print("asl");
1583
1584                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
1585                     --zp, x
1586                     d_print("asl");
1587
1588                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
1589                     --abs
1590                     d_print("asl");
1591
1592                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
1593                     --abs, x
1594                     d_print("asl");
1595
1596                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
1597                     --zp
1598                     d_print("dec");
1599                     a4_zp;
1600                     if exec_cycle = T4 then
1601                         set_nz_from_bus;
1602                     end if;
1603
1604                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
1605                     --zp, x
1606                     d_print("dec");
1607
1608                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
1609                     --abs
1610                     d_print("dec");
1611
1612                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
1613                     --abs, x
1614                     d_print("dec");
1615
1616                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
1617                     --zp
1618                     d_print("inc");
1619                     a4_zp;
1620                     if exec_cycle = T4 then
1621                         set_nz_from_bus;
1622                     end if;
1623
1624                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
1625                     --zp, x
1626                     d_print("inc");
1627
1628                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
1629                     --abs
1630                     d_print("inc");
1631                     a4_abs;
1632                     if exec_cycle = T5 then
1633                         set_nz_from_bus;
1634                     end if;
1635
1636                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
1637                     --abs, x
1638                     d_print("inc");
1639
1640                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
1641                     --zp
1642                     d_print("lsr");
1643
1644                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
1645                     --zp, x
1646                     d_print("lsr");
1647
1648                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
1649                     --abs
1650                     d_print("lsr");
1651
1652                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
1653                     --abs, x
1654                     d_print("lsr");
1655
1656                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
1657                     --zp
1658                     d_print("rol");
1659
1660                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
1661                     --zp, x
1662                     d_print("rol");
1663
1664                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
1665                     --abs
1666                     d_print("rol");
1667
1668                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
1669                     --abs, x
1670                     d_print("rol");
1671
1672                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
1673                     --zp
1674                     d_print("ror");
1675                     a4_zp;
1676                     if exec_cycle = T4 then
1677                         set_nzc_from_bus;
1678                     end if;
1679
1680                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
1681                     --zp, x
1682                     d_print("ror");
1683
1684                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
1685                     --abs
1686                     d_print("ror");
1687
1688                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
1689                     --abs, x
1690                     d_print("ror");
1691
1692
1693                 ----------------------------------------
1694                 --A.5. miscellaneous oprations.
1695                 ----------------------------------------
1696
1697                 -- A.5.1 push/pull
1698                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1699                     d_print("php");
1700
1701                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1702                     d_print("pha");
1703                     a51_push;
1704                     if exec_cycle = T2 then
1705                         front_oe(acc_cmd, '0');
1706                     end if;
1707
1708                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1709                     d_print("plp");
1710
1711                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1712                     d_print("pla");
1713                     a52_pull;
1714                     if exec_cycle = T3 then
1715                         front_we(acc_cmd, '0');
1716                     end if;
1717
1718
1719                 ----------------------------------------
1720                 -- A.5.3 jsr
1721                 ----------------------------------------
1722                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1723                     if exec_cycle = T1 then
1724                         d_print("jsr abs 2");
1725                         --fetch opcode.
1726                         fetch_next;
1727                         dbuf_int_oe_n <= '0';
1728                         --latch adl
1729                         dl_al_we_n <= '0';
1730                         next_cycle <= T2;
1731                     elsif exec_cycle = T2 then
1732                         d_print("jsr 3");
1733                         fetch_stop;
1734                         dbuf_int_oe_n <= '1';
1735                         dl_al_we_n <= '1';
1736
1737                        --push return addr high into stack.
1738                         sp_push_n <= '0';
1739                         sp_oe_n <= '0';
1740                         front_oe(pch_cmd, '0');
1741                         back_oe(sp_cmd, '0');
1742                         back_we(sp_cmd, '0');
1743                         r_nw <= '0';
1744                         next_cycle <= T3;
1745                     elsif exec_cycle = T3 then
1746                         d_print("jsr 4");
1747                         front_oe(pch_cmd, '1');
1748
1749                        --push return addr low into stack.
1750                         sp_push_n <= '0';
1751                         sp_oe_n <= '0';
1752                         front_oe(pcl_cmd, '0');
1753                         back_oe(sp_cmd, '0');
1754                         back_we(sp_cmd, '0');
1755                         r_nw <= '0';
1756
1757                         next_cycle <= T4;
1758                     elsif exec_cycle = T4 then
1759                         d_print("jsr 5");
1760                         sp_push_n <= '1';
1761                         sp_oe_n <= '1';
1762                         front_oe(pcl_cmd, '1');
1763                         back_oe(sp_cmd, '1');
1764                         back_we(sp_cmd, '1');
1765                         r_nw <= '1';
1766
1767                         --fetch last op.
1768                         back_oe(pch_cmd, '0');
1769                         back_oe(pcl_cmd, '0');
1770                         dbuf_int_oe_n <= '0';
1771                         dl_ah_we_n <= '0';
1772
1773                         next_cycle <= T5;
1774                     elsif exec_cycle = T5 then
1775                         d_print("jsr 6");
1776
1777                         back_oe(pch_cmd, '1');
1778                         back_oe(pcl_cmd, '1');
1779                         dbuf_int_oe_n <= '1';
1780                         dl_ah_we_n <= '1';
1781
1782                         --load/output  pch
1783                         ad_oe_n <= '1';
1784                         dl_dh_oe_n <= '0';
1785                         front_we(pch_cmd, '0');
1786
1787                         --load pcl.
1788                         dl_al_oe_n <= '0';
1789                         back_we(pcl_cmd, '0');
1790
1791                         next_cycle <= T0;
1792                     end if; --if exec_cycle = T1 then
1793
1794                 -- A.5.4 break
1795                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
1796
1797                 ----------------------------------------
1798                 -- A.5.5 return from interrupt
1799                 ----------------------------------------
1800                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
1801
1802                 ----------------------------------------
1803                 -- A.5.6 jmp
1804                 ----------------------------------------
1805                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
1806                     --abs
1807                     if exec_cycle = T1 then
1808                         d_print("jmp 2");
1809                         --fetch next opcode (abs low).
1810                         fetch_next;
1811
1812                         --latch abs low data.
1813                         dbuf_int_oe_n <= '0';
1814                         dl_al_we_n <= '0';
1815                         next_cycle <= T2;
1816                     elsif exec_cycle = T2 then
1817                         d_print("jmp 3");
1818                         dl_al_we_n <= '1';
1819
1820                         --fetch abs hi
1821                         fetch_next;
1822
1823                         --latch  in dlh
1824                         dbuf_int_oe_n <= '0';
1825                         dl_ah_we_n <= '0';
1826                         ---load pch.
1827                         front_we(pch_cmd, '0');
1828
1829                         next_cycle <= T0;
1830                     end if;
1831
1832                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
1833                     --(indir)
1834
1835
1836                 ----------------------------------------
1837                 -- A.5.7 return from soubroutine
1838                 ----------------------------------------
1839                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
1840                     if exec_cycle = T1 then
1841                         d_print("rts 2");
1842                         fetch_stop;
1843
1844                         --pop stack (decrement only)
1845                         back_oe(sp_cmd, '0');
1846                         back_we(sp_cmd, '0');
1847                         sp_pop_n <= '0';
1848                         sp_oe_n <= '0';
1849
1850                         next_cycle <= T2;
1851                     elsif exec_cycle = T2 then
1852                         d_print("rts 3");
1853
1854                         --pop pcl
1855                         back_oe(sp_cmd, '0');
1856                         back_we(sp_cmd, '0');
1857                         sp_pop_n <= '0';
1858                         sp_oe_n <= '0';
1859
1860                         --load lo addr.
1861                         dbuf_int_oe_n <= '0';
1862                         front_we(pcl_cmd, '0');
1863
1864                         next_cycle <= T3;
1865                     elsif exec_cycle = T3 then
1866                         d_print("rts 4");
1867                         --stack decrement stop.
1868                         back_we(sp_cmd, '1');
1869                         sp_pop_n <= '1';
1870                         front_we(pcl_cmd, '1');
1871
1872                         --pop pch
1873                         back_oe(sp_cmd, '0');
1874                         sp_oe_n <= '0';
1875                         --load hi addr.
1876                         dbuf_int_oe_n <= '0';
1877                         front_we(pch_cmd, '0');
1878
1879                         next_cycle <= T4;
1880                     elsif exec_cycle = T4 then
1881                         d_print("rts 5");
1882                         back_oe(sp_cmd, '1');
1883                         sp_oe_n <= '1';
1884                         --load hi addr.
1885                         dbuf_int_oe_n <= '1';
1886                         front_we(pch_cmd, '1');
1887                         --empty cycle.
1888                         --complying h/w manual...
1889                         next_cycle <= T5;
1890                     elsif exec_cycle = T5 then
1891                         d_print("rts 6");
1892
1893                         --increment pc.
1894                         fetch_next;
1895                         next_cycle <= T0;
1896                     end if; --if exec_cycle = T1 then
1897
1898                 ----------------------------------------
1899                 -- A.5.8 branch operations
1900                 ----------------------------------------
1901                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
1902                     d_print("bcc");
1903                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
1904                     d_print("bcs");
1905                     a58_branch (st_C, '1');
1906
1907                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
1908                     d_print("beq");
1909                     a58_branch (st_Z, '1');
1910
1911                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
1912                     d_print("bmi");
1913                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
1914                     d_print("bne");
1915                     a58_branch (st_Z, '0');
1916
1917                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
1918                     d_print("bpl");
1919                     a58_branch (st_N, '0');
1920
1921                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
1922                     d_print("bvc");
1923                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
1924                     d_print("bvs");
1925
1926                 else
1927                     ---unknown instruction!!!!
1928                     assert false
1929                         report "======== unknow instruction "
1930                             & conv_hex8(conv_integer(instruction))
1931                         severity failure;
1932                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
1933
1934             elsif exec_cycle = R0 then
1935                 d_print(string'("reset"));
1936
1937                 front_we(pch_cmd, '1');
1938                 back_we(pcl_cmd, '1');
1939
1940                 --initialize port...
1941                 inst_we_n <= '1';
1942                 ad_oe_n <= '1';
1943                 dbuf_int_oe_n <= '1';
1944                 dl_al_we_n <= '1';
1945                 dl_ah_we_n <= '1';
1946                 dl_al_oe_n <= '1';
1947                 dl_ah_oe_n <= '1';
1948                 dl_dh_oe_n <= '1';
1949                 pcl_inc_n <= '1';
1950                 pcl_cmd <= "1111";
1951                 pch_cmd <= "1111";
1952                 sp_cmd <= "1111";
1953                 sp_oe_n <= '1';
1954                 sp_push_n <= '1';
1955                 sp_pop_n <= '1';
1956                 acc_cmd <= "1111";
1957                 x_cmd <= "1111";
1958                 y_cmd <= "1111";
1959
1960                 abs_xy_n <= '1';
1961                 pg_next_n <= '1';
1962                 zp_n <= '1';
1963                 zp_xy_n <= '1';
1964                 rel_calc_n <= '1';
1965                 indir_n <= '1';
1966                 indir_x_n <= '1';
1967                 indir_y_n <= '1';
1968                 arith_en_n <= '1';
1969
1970                 stat_dec_oe_n <= '1';
1971                 stat_bus_oe_n <= '1';
1972                 stat_set_flg_n <= '1';
1973                 stat_flg <= '1';
1974                 stat_bus_all_n <= '1';
1975                 stat_bus_nz_n <= '1';
1976                 stat_alu_we_n <= '1';
1977
1978                 r_vec_oe_n <= '1';
1979                 n_vec_oe_n <= '1';
1980                 i_vec_oe_n <= '1';
1981                 nmi_handled_n <= '1';
1982                 r_nw <= '1';
1983
1984                 next_cycle <= R1;
1985             elsif exec_cycle = R1 or exec_cycle = N1 then
1986                 --push pch.
1987                 d_print("R1");
1988                 ad_oe_n <= '0';
1989                 sp_push_n <= '0';
1990                 sp_oe_n <= '0';
1991                 front_oe(pch_cmd, '0');
1992                 back_oe(sp_cmd, '0');
1993                 back_we(sp_cmd, '0');
1994                 r_nw <= '0';
1995
1996                 if exec_cycle = R1 then
1997                     next_cycle <= R2;
1998                 elsif exec_cycle = N1 then
1999                     next_cycle <= N2;
2000                 end if;
2001
2002             elsif exec_cycle = R2 or exec_cycle = N2 then
2003                 front_oe(pch_cmd, '1');
2004
2005                --push pcl.
2006                 sp_push_n <= '0';
2007                 sp_oe_n <= '0';
2008                 front_oe(pcl_cmd, '0');
2009                 back_oe(sp_cmd, '0');
2010                 back_we(sp_cmd, '0');
2011                 r_nw <= '0';
2012
2013                 if exec_cycle = R2 then
2014                     next_cycle <= R3;
2015                 elsif exec_cycle = N2 then
2016                     next_cycle <= N3;
2017                 end if;
2018
2019             elsif exec_cycle = R3 or exec_cycle = N3 then
2020                 front_oe(pcl_cmd, '1');
2021
2022                --push status.
2023                 sp_push_n <= '0';
2024                 sp_oe_n <= '0';
2025                 stat_bus_oe_n <= '0';
2026                 back_oe(sp_cmd, '0');
2027                 back_we(sp_cmd, '0');
2028                 r_nw <= '0';
2029
2030                 if exec_cycle = R3 then
2031                     next_cycle <= R4;
2032                 elsif exec_cycle = N3 then
2033                     next_cycle <= N4;
2034                 end if;
2035
2036             elsif exec_cycle = R4 or exec_cycle = N4 then
2037                 stat_bus_oe_n <= '1';
2038                 sp_push_n <= '1';
2039                 sp_oe_n <= '1';
2040                 front_oe(pcl_cmd, '1');
2041                 back_oe(sp_cmd, '1');
2042                 back_we(sp_cmd, '1');
2043
2044                 --fetch reset vector low
2045                 r_nw <= '1';
2046                 dbuf_int_oe_n <= '0';
2047                 front_we(pcl_cmd, '0');
2048
2049                 if exec_cycle = R4 then
2050                     r_vec_oe_n <= '0';
2051                     next_cycle <= R5;
2052                 elsif exec_cycle = N4 then
2053                     n_vec_oe_n <= '0';
2054                     next_cycle <= N5;
2055                 end if;
2056
2057             elsif exec_cycle = R5 or exec_cycle = N5 then
2058                 front_we(pcl_cmd, '1');
2059
2060                 --fetch reset vector hi
2061                 front_we(pch_cmd, '0');
2062                 indir_n <= '0';
2063
2064                 if exec_cycle = N5 then
2065                     nmi_handled_n <= '0';
2066                 end if;
2067                 --start execute cycle.
2068                 next_cycle <= T0;
2069
2070             elsif exec_cycle(5) = '1' then
2071                 ---pc increment and next page.
2072                 d_print(string'("pch next page..."));
2073                 --pcl stop increment
2074                 pcl_inc_n <= '1';
2075                 back_we(pcl_cmd, '1');
2076                 --pch increment
2077                 back_we(pch_cmd, '0');
2078
2079                 if ('0' & exec_cycle(4 downto 0) = T1) then
2080                     --if fetch cycle, preserve instrution register
2081                     inst_we_n <= '1';
2082                 end if;
2083                 back_oe(pch_cmd, '0');
2084
2085             end if; --if exec_cycle = T0 then
2086
2087         end if; --if (set_clk'event and set_clk = '1')
2088
2089     end process;
2090
2091 end rtl;
2092