simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             pcl_cmd         : out std_logic_vector(3 downto 0);
  21             pch_cmd         : out std_logic_vector(3 downto 0);
  22             sp_cmd          : out std_logic_vector(3 downto 0);
  23             acc_cmd         : out std_logic_vector(3 downto 0);
  24             x_cmd           : out std_logic_vector(3 downto 0);
  25             y_cmd           : out std_logic_vector(3 downto 0);
  26             r_nw            : out std_logic
  27             ;---for parameter check purpose!!!
  28             check_bit     : out std_logic_vector(1 to 5)
  29         );
  30 end decoder;
  31
  32 architecture rtl of decoder is
  33
  34 procedure d_print(msg : string) is
  35 use std.textio.all;
  36 use ieee.std_logic_textio.all;
  37 variable out_l : line;
  38 begin
  39     write(out_l, msg);
  40     writeline(output, out_l);
  41 end  procedure;
  42
  43 ---ival : 0x0000 - 0xffff
  44 function conv_hex8(ival : integer) return string is
  45 variable tmp1, tmp2 : integer;
  46 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  47 begin
  48     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  49     tmp1 := ival mod 16 ** 1;
  50     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  51 end;
  52
  53 --cycle bit format
  54 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T7 > T0
  55 constant T0 : std_logic_vector (5 downto 0) := "-00000";
  56 constant T1 : std_logic_vector (5 downto 0) := "-00001";
  57 constant T2 : std_logic_vector (5 downto 0) := "-00010";
  58 constant T3 : std_logic_vector (5 downto 0) := "-00011";
  59 constant T4 : std_logic_vector (5 downto 0) := "-00100";
  60 constant T5 : std_logic_vector (5 downto 0) := "-00101";
  61 constant T6 : std_logic_vector (5 downto 0) := "-00110";
  62 constant T7 : std_logic_vector (5 downto 0) := "-00111";
  63
  64 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
  65 constant R0 : std_logic_vector (5 downto 0) := "-01000";
  66 constant R1 : std_logic_vector (5 downto 0) := "-01001";
  67 constant R2 : std_logic_vector (5 downto 0) := "-01010";
  68 constant R3 : std_logic_vector (5 downto 0) := "-01011";
  69 constant R4 : std_logic_vector (5 downto 0) := "-01100";
  70 constant R5 : std_logic_vector (5 downto 0) := "-01101";
  71
  72 --10xxx : nmi cycle : N0 > N1 > N2 > N3 > N4 > N5 > T0
  73 constant N0 : std_logic_vector (5 downto 0) := "-10000";
  74 constant N1 : std_logic_vector (5 downto 0) := "-10001";
  75 constant N2 : std_logic_vector (5 downto 0) := "-10010";
  76 constant N3 : std_logic_vector (5 downto 0) := "-10011";
  77 constant N4 : std_logic_vector (5 downto 0) := "-10100";
  78 constant N5 : std_logic_vector (5 downto 0) := "-10101";
  79
  80 --11xxx : irq cycle : I0 > I1 > I2 > I3 > I4 > I5 > T0
  81 constant I0 : std_logic_vector (5 downto 0) := "-11000";
  82 constant I1 : std_logic_vector (5 downto 0) := "-11001";
  83 constant I2 : std_logic_vector (5 downto 0) := "-11010";
  84 constant I3 : std_logic_vector (5 downto 0) := "-11011";
  85 constant I4 : std_logic_vector (5 downto 0) := "-11100";
  86 constant I5 : std_logic_vector (5 downto 0) := "-11101";
  87
  88 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
  89
  90 -- SR Flags (bit 7 to bit 0):
  91 --  7   N   ....    Negative
  92 --  6   V   ....    Overflow
  93 --  5   -   ....    ignored
  94 --  4   B   ....    Break
  95 --  3   D   ....    Decimal (use BCD for arithmetics)
  96 --  2   I   ....    Interrupt (IRQ disable)
  97 --  1   Z   ....    Zero
  98 --  0   C   ....    Carry
  99 constant st_N : integer := 7;
 100 constant st_V : integer := 6;
 101 constant st_B : integer := 4;
 102 constant st_D : integer := 3;
 103 constant st_I : integer := 2;
 104 constant st_Z : integer := 1;
 105 constant st_C : integer := 0;
 106
 107 begin
 108
 109     main_p : process (set_clk, res_n)
 110
 111 -------------------------------------------------------------
 112 -------------------------------------------------------------
 113 ----------------------- comon routines ----------------------
 114 -------------------------------------------------------------
 115 -------------------------------------------------------------
 116
 117 ----------gate_cmd format
 118 ------3 : front port oe_n
 119 ------2 : front port we_n
 120 ------1 : back port oe_n
 121 ------0 : back port we_n
 122 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 123     val : in std_logic) is
 124 begin
 125     cmd(3) <= val;
 126 end;
 127 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 128     val : in std_logic) is
 129 begin
 130     cmd(2) <= val;
 131 end;
 132 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 133     val : in std_logic) is
 134 begin
 135     cmd(1) <= val;
 136 end;
 137 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 138     val : in std_logic) is
 139 begin
 140     cmd(0) <= val;
 141 end;
 142
 143 procedure fetch_inst is
 144 begin
 145     ad_oe_n <= '0';
 146     inst_we_n <= '0';
 147     back_oe(pcl_cmd, '0');
 148     back_oe(pch_cmd, '0');
 149     r_nw <= '1';
 150     --pcl_inc_n <= '0';
 151
 152     d_print(string'("fetch 1"));
 153 end;
 154
 155 ---common routine for single byte instruction.
 156 procedure single_inst is
 157 begin
 158 end  procedure;
 159
 160 procedure fetch_imm is
 161 begin
 162     d_print("immediate");
 163 end  procedure;
 164
 165 procedure set_nz_from_bus is
 166 begin
 167 end  procedure;
 168
 169 procedure set_nz_from_alu is
 170 begin
 171 end  procedure;
 172
 173 procedure set_nzc_from_alu is
 174 begin
 175 end  procedure;
 176
 177 --flag on/off instruction
 178 procedure set_flag (int_flg : in integer; val : in std_logic) is
 179 begin
 180 end  procedure;
 181
 182 --for sec/clc
 183 procedure set_flag0 (val : in std_logic) is
 184 begin
 185 end  procedure;
 186
 187 procedure fetch_low is
 188 begin
 189     d_print("fetch low 2");
 190 end  procedure;
 191
 192 procedure abs_fetch_high is
 193 begin
 194     d_print("abs (xy) 3");
 195 end  procedure;
 196
 197 procedure abs_latch_out is
 198 begin
 199 end  procedure;
 200
 201 procedure ea_x_out is
 202 begin
 203     -----calucurate and output effective addr
 204 end  procedure;
 205
 206 --A.2. internal execution on memory data
 207 procedure a2_abs is
 208 begin
 209 end  procedure;
 210
 211 procedure a2_absx is
 212 begin
 213 end  procedure;
 214
 215
 216 --A.3. store operation.
 217
 218 procedure a3_zp is
 219 begin
 220 end  procedure;
 221
 222 procedure a3_abs is
 223 begin
 224 end  procedure;
 225
 226
 227 -- A.5.8 branch operations
 228 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 229 begin
 230 end  procedure;
 231
 232 -------------------------------------------------------------
 233 -------------------------------------------------------------
 234 ---------------- main state machine start.... ---------------
 235 -------------------------------------------------------------
 236 -------------------------------------------------------------
 237     begin
 238
 239         if (res_n = '0') then
 240             --pc l/h is reset vector.
 241             pcl_cmd <= "1110";
 242             pch_cmd <= "1011";
 243             next_cycle <= R0;
 244         elsif (res_n'event and res_n = '1') then
 245             pcl_cmd <= "1111";
 246             pch_cmd <= "1111";
 247         end if;
 248
 249         if (set_clk'event and set_clk = '1' and res_n = '1') then
 250             d_print(string'("-"));
 251
 252             if exec_cycle = T0 then
 253                 --cycle #1
 254                 fetch_inst;
 255                 --next_cycle <= T1;
 256
 257             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 258                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or
 259                 exec_cycle = T7 then
 260                 --execute inst.
 261
 262                 if exec_cycle = T1 then
 263                     d_print("decode and execute inst: "
 264                             & conv_hex8(conv_integer(instruction)));
 265                     --grab instruction register data.
 266                     inst_we_n <= '1';
 267                 end if;
 268
 269                 --imelementation is wriiten in the order of hardware manual
 270                 --appendix A.
 271
 272
 273                 ----------------------------------------
 274                 --A.1. Single byte instruction.
 275                 ----------------------------------------
 276                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 277                     --asl acc mode.
 278                     d_print("asl");
 279
 280                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 281                     d_print("clc");
 282                     set_flag0 ('0');
 283                     single_inst;
 284
 285                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 286                     d_print("cld");
 287                     set_flag (st_D, '0');
 288                     single_inst;
 289
 290                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 291                     d_print("cli");
 292
 293                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 294                     d_print("clv");
 295
 296                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 297                     d_print("dex");
 298                     --set nz bit.
 299                     set_nz_from_alu ;
 300                     single_inst;
 301
 302                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
 303                     d_print("dey");
 304                     --set nz bit.
 305                     set_nz_from_alu ;
 306                     single_inst;
 307
 308                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
 309                     d_print("inx");
 310                     --set nz bit.
 311                     set_nz_from_alu ;
 312                     single_inst;
 313
 314                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
 315                     d_print("iny");
 316
 317                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
 318                     --lsr acc mode
 319                     d_print("lsr");
 320
 321                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
 322                     d_print("nop");
 323
 324                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
 325                     --rol acc
 326                     d_print("rol");
 327
 328                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
 329                     d_print("sec");
 330                     set_flag0 ('1');
 331                     single_inst;
 332
 333                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
 334                     d_print("sed");
 335                     set_flag (st_D, '1');
 336                     single_inst;
 337
 338                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
 339                     d_print("sei");
 340                     set_flag (st_I, '1');
 341                     single_inst;
 342
 343                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
 344                     d_print("tax");
 345                     set_nz_from_bus;
 346
 347                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
 348                     d_print("tay");
 349                     set_nz_from_bus;
 350
 351                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
 352                     d_print("tsx");
 353                     set_nz_from_bus;
 354
 355                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
 356                     d_print("txa");
 357                     set_nz_from_bus;
 358
 359                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
 360                     d_print("txs");
 361                     set_nz_from_bus;
 362                     single_inst;
 363
 364                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
 365                     d_print("tya");
 366                     set_nz_from_bus;
 367
 368
 369
 370                 ----------------------------------------
 371                 --A.2. internal execution on memory data
 372                 ----------------------------------------
 373                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
 374                     --imm
 375                     d_print("adc");
 376
 377                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
 378                     --zp
 379                     d_print("adc");
 380
 381                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
 382                     --zp, x
 383                     d_print("adc");
 384
 385                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
 386                     --abs
 387                     d_print("adc");
 388
 389                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
 390                     --abs, x
 391                     d_print("adc");
 392
 393                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
 394                     --abs, y
 395                     d_print("adc");
 396
 397                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
 398                     --(indir, x)
 399                     d_print("adc");
 400
 401                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
 402                     --(indir), y
 403                     d_print("adc");
 404
 405                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
 406                     --imm
 407                     d_print("and");
 408
 409                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
 410                     --zp
 411                     d_print("and");
 412
 413                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
 414                     --zp, x
 415                     d_print("and");
 416
 417                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
 418                     --abs
 419                     d_print("and");
 420
 421                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
 422                     --abs, x
 423                     d_print("and");
 424
 425                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
 426                     --abs, y
 427                     d_print("and");
 428
 429                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
 430                     --(indir, x)
 431                     d_print("and");
 432
 433                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
 434                     --(indir), y
 435                     d_print("and");
 436
 437                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
 438                     --zp
 439                     d_print("bit");
 440
 441                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
 442                     --abs
 443                     d_print("bit");
 444
 445                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
 446                     --imm
 447                     d_print("cmp");
 448                     fetch_imm;
 449                     set_nzc_from_alu;
 450
 451                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
 452                     --zp
 453                     d_print("cmp");
 454
 455                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
 456                     --zp, x
 457                     d_print("cmp");
 458
 459                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
 460                     --abs
 461                     d_print("cmp");
 462
 463                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
 464                     --abs, x
 465                     d_print("cmp");
 466
 467                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
 468                     --abs, y
 469                     d_print("cmp");
 470
 471                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
 472                     --(indir, x)
 473                     d_print("cmp");
 474
 475                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
 476                     --(indir), y
 477                     d_print("cmp");
 478
 479                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
 480                     --imm
 481                     d_print("cpx");
 482
 483                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
 484                     --zp
 485                     d_print("cpx");
 486
 487                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
 488                     --abs
 489                     d_print("cpx");
 490
 491                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
 492                     --imm
 493                     d_print("cpy");
 494
 495                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
 496                     --zp
 497                     d_print("cpy");
 498
 499                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
 500                     --abs
 501                     d_print("cpy");
 502
 503                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
 504                     --imm
 505                     d_print("eor");
 506
 507                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
 508                     --zp
 509                     d_print("eor");
 510
 511                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
 512                     --zp, x
 513                     d_print("eor");
 514
 515                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
 516                     --abs
 517                     d_print("eor");
 518
 519                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
 520                     --abs, x
 521                     d_print("eor");
 522
 523                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
 524                     --abs, y
 525                     d_print("eor");
 526
 527                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
 528                     --(indir, x)
 529                     d_print("eor");
 530
 531                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
 532                     --(indir), y
 533                     d_print("eor");
 534
 535                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
 536                     --imm
 537                     d_print("lda");
 538                     fetch_imm;
 539                     set_nz_from_bus;
 540
 541                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
 542                     --zp
 543                     d_print("lda");
 544
 545                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
 546                     --zp, x
 547                     d_print("lda");
 548
 549                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
 550                     --abs
 551                     d_print("lda");
 552                     a2_abs;
 553                     if exec_cycle = T3 then
 554                         set_nz_from_bus;
 555                     end if;
 556
 557                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
 558                     --abs, x
 559                     d_print("lda");
 560                     a2_absx;
 561                     if exec_cycle = T3 then
 562                         --lda.
 563                         set_nz_from_bus;
 564                     elsif exec_cycle = T4 then
 565                     end if;
 566
 567                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
 568                     --abs, y
 569                     d_print("lda");
 570
 571                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
 572                     --(indir, x)
 573                     d_print("lda");
 574
 575                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
 576                     --(indir), y
 577                     d_print("lda");
 578
 579                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
 580                     --imm
 581                     d_print("ldx");
 582                     fetch_imm;
 583                     set_nz_from_bus;
 584
 585                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
 586                     --zp
 587                     d_print("ldx");
 588
 589                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
 590                     --zp, y
 591                     d_print("ldx");
 592
 593                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
 594                     --abs
 595                     d_print("ldx");
 596
 597                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
 598                     --abs, y
 599                     d_print("ldx");
 600
 601                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
 602                     --imm
 603                     d_print("ldy");
 604                     fetch_imm;
 605                     set_nz_from_bus;
 606
 607                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
 608                     --zp
 609                     d_print("ldy");
 610
 611                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
 612                     --zp, x
 613                     d_print("ldy");
 614
 615                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
 616                     --abs
 617                     d_print("ldy");
 618
 619                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
 620                     --abs, x
 621                     d_print("ldy");
 622
 623                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
 624                     --imm
 625                     d_print("ora");
 626
 627                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
 628                     --zp
 629                     d_print("ora");
 630
 631                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
 632                     --zp, x
 633                     d_print("ora");
 634
 635                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
 636                     --abs
 637                     d_print("ora");
 638
 639                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
 640                     --abs, x
 641                     d_print("ora");
 642
 643                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
 644                     --abs, y
 645                     d_print("ora");
 646
 647                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
 648                     --(indir, x)
 649                     d_print("ora");
 650
 651                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
 652                     --(indir), y
 653                     d_print("ora");
 654
 655                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
 656                     --imm
 657                     d_print("sbc");
 658
 659                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
 660                     --zp
 661                     d_print("sbc");
 662
 663                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
 664                     --zp, x
 665                     d_print("sbc");
 666
 667                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
 668                     --abs
 669                     d_print("sbc");
 670
 671                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
 672                     --abs, x
 673                     d_print("sbc");
 674
 675                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
 676                     --abs, y
 677                     d_print("sbc");
 678
 679                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
 680                     --(indir, x)
 681                     d_print("sbc");
 682
 683                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
 684                     --(indir), y
 685                     d_print("sbc");
 686
 687
 688
 689                 ----------------------------------------
 690                 ---A.3. store operation.
 691                 ----------------------------------------
 692                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
 693                     --zp
 694                     d_print("sta");
 695                     a3_zp;
 696                     if exec_cycle = T2 then
 697                     end if;
 698
 699                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
 700                     --zp, x
 701                     d_print("sta");
 702
 703                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
 704                     --abs
 705                     d_print("sta");
 706                     a3_abs;
 707                     if exec_cycle = T3 then
 708                     end if;
 709
 710                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
 711                     --abs, x
 712                     d_print("sta");
 713
 714                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
 715                     --abs, y
 716                     d_print("sta");
 717
 718                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
 719                     --(indir, x)
 720                     d_print("sta");
 721
 722                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
 723                     --(indir), y
 724                     d_print("sta");
 725
 726                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
 727                     --zp
 728                     d_print("stx");
 729                     a3_zp;
 730                     if exec_cycle = T2 then
 731                     end if;
 732
 733                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
 734                     --zp, y
 735                     d_print("stx");
 736
 737                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
 738                     --abs
 739                     d_print("stx");
 740
 741                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
 742                     --zp
 743                     d_print("sty");
 744
 745                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
 746                     --zp, x
 747                     d_print("sty");
 748
 749                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
 750                     --abs
 751                     d_print("sty");
 752
 753
 754                 ----------------------------------------
 755                 ---A.4. read-modify-write operation
 756                 ----------------------------------------
 757                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
 758                     --zp
 759                     d_print("asl");
 760
 761                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
 762                     --zp, x
 763                     d_print("asl");
 764
 765                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
 766                     --abs
 767                     d_print("asl");
 768
 769                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
 770                     --abs, x
 771                     d_print("asl");
 772
 773                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
 774                     --zp
 775                     d_print("dec");
 776
 777                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
 778                     --zp, x
 779                     d_print("dec");
 780
 781                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
 782                     --abs
 783                     d_print("dec");
 784
 785                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
 786                     --abs, x
 787                     d_print("dec");
 788
 789                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
 790                     --zp
 791                     d_print("inc");
 792
 793                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
 794                     --zp, x
 795                     d_print("inc");
 796
 797                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
 798                     --abs
 799                     d_print("inc");
 800
 801                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
 802                     --abs, x
 803                     d_print("inc");
 804
 805                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
 806                     --zp
 807                     d_print("lsr");
 808
 809                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
 810                     --zp, x
 811                     d_print("lsr");
 812
 813                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
 814                     --abs
 815                     d_print("lsr");
 816
 817                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
 818                     --abs, x
 819                     d_print("lsr");
 820
 821                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
 822                     --zp
 823                     d_print("rol");
 824
 825                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
 826                     --zp, x
 827                     d_print("rol");
 828
 829                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
 830                     --abs
 831                     d_print("rol");
 832
 833                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
 834                     --abs, x
 835                     d_print("rol");
 836
 837                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
 838                     --zp
 839                     d_print("ror");
 840
 841                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
 842                     --zp, x
 843                     d_print("ror");
 844
 845                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
 846                     --abs
 847                     d_print("ror");
 848
 849                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
 850                     --abs, x
 851                     d_print("ror");
 852
 853
 854                 ----------------------------------------
 855                 --A.5. miscellaneous oprations.
 856                 ----------------------------------------
 857
 858                 -- A.5.1 push/pull
 859                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
 860                     d_print("php");
 861
 862                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
 863                     d_print("pha");
 864
 865                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
 866                     d_print("plp");
 867
 868                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
 869                     d_print("pla");
 870
 871
 872                 ----------------------------------------
 873                 -- A.5.3 jsr
 874                 ----------------------------------------
 875                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 876
 877                 -- A.5.4 break
 878                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
 879
 880                 ----------------------------------------
 881                 -- A.5.5 return from interrupt
 882                 ----------------------------------------
 883                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 884
 885                 ----------------------------------------
 886                 -- A.5.6 jmp
 887                 ----------------------------------------
 888                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
 889                     --abs
 890
 891                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
 892                     --(indir)
 893
 894
 895                 ----------------------------------------
 896                 -- A.5.7 return from soubroutine
 897                 ----------------------------------------
 898                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 899
 900                 ----------------------------------------
 901                 -- A.5.8 branch operations
 902                 ----------------------------------------
 903                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
 904                     d_print("bcc");
 905                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
 906                     d_print("bcs");
 907                     a58_branch (st_C, '1');
 908
 909                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
 910                     d_print("beq");
 911                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
 912                     d_print("bmi");
 913                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
 914                     d_print("bne");
 915                     a58_branch (st_Z, '0');
 916
 917                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
 918                     d_print("bpl");
 919                     a58_branch (st_N, '0');
 920
 921                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
 922                     d_print("bvc");
 923                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
 924                     d_print("bvs");
 925
 926                 else
 927                     ---unknown instruction!!!!
 928                     assert false
 929                         report "======== unknow instruction "
 930                             & conv_hex8(conv_integer(instruction));
 931                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
 932
 933             elsif exec_cycle = R0 then
 934                 d_print(string'("reset"));
 935
 936                 pcl_cmd <= "1111";
 937                 pch_cmd <= "1111";
 938                 sp_cmd <= "1111";
 939                 acc_cmd <= "1111";
 940                 x_cmd <= "1111";
 941                 y_cmd <= "1111";
 942                 r_nw <= '1';
 943
 944                 next_cycle <= R1;
 945             elsif exec_cycle = R1 then
 946                 next_cycle <= R2;
 947                 front_we(pch_cmd, '1');
 948                 back_we(pcl_cmd, '1');
 949
 950             elsif exec_cycle = R2 then
 951                 next_cycle <= R3;
 952
 953             elsif exec_cycle = R3 then
 954                 next_cycle <= R4;
 955
 956             elsif exec_cycle = R4 then
 957                 next_cycle <= R5;
 958
 959             elsif exec_cycle = R5 then
 960                 next_cycle <= T0;
 961
 962             end if; --if exec_cycle = T0 then
 963
 964         end if; --if (set_clk'event and set_clk = '1')
 965
 966     end process;
 967
 968 end rtl;
 969