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[motonesfpga/motonesfpga.git] / simulation / cpu / decoder.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.conv_std_logic_vector;
4 --use ieee.std_logic_arith.all;
5 use std.textio.all;
6 use ieee.std_logic_textio.all;
7 use ieee.std_logic_unsigned.conv_integer;
8
9 entity decoder is 
10     generic (dsize : integer := 8);
11     port (  set_clk         : in std_logic;
12             trig_clk        : in std_logic;
13             res_n           : in std_logic;
14             irq_n           : in std_logic;
15             nmi_n           : in std_logic;
16             rdy             : in std_logic;
17             instruction     : in std_logic_vector (dsize - 1 downto 0);
18             status_reg      : in std_logic_vector (dsize - 1 downto 0);
19             pcl_d_i_n       : out std_logic;
20             pcl_d_o_n       : out std_logic;
21             pcl_a_o_n       : out std_logic;
22             pch_d_i_n       : out std_logic;
23             pch_d_o_n       : out std_logic;
24             pch_a_o_n       : out std_logic;
25             pc_inc_n        : out std_logic;
26             r_nw            : out std_logic
27         );
28 end decoder;
29
30 architecture rtl of decoder is
31
32 procedure d_print(msg : string) is
33 variable out_l : line;
34 begin
35     write(out_l, msg);
36     writeline(output, out_l);
37 end  procedure;
38
39 procedure d_print(msg : string; sig : std_logic_vector) is
40 variable out_l : line;
41 begin
42     write(out_l, msg);
43     write(out_l, sig);
44     writeline(output, out_l);
45 end  procedure;
46
47 procedure d_print(msg : string; ival : integer) is
48 variable out_l : line;
49 begin
50     write(out_l, msg);
51     write(out_l, ival);
52     writeline(output, out_l);
53 end  procedure;
54
55 type dec_status is (reset0, reset1, reset2, reset3, reset4, reset5, 
56                     fetch, exec, 
57                     sei,
58                     ldx1, ldx2, ldx3,
59                     jmp1, jmp2, jmp3, jmp4,
60                     nop,
61                     unknown_stat
62                     );
63
64 signal cur_status : dec_status;
65
66 begin
67
68     main_p : process (set_clk, trig_clk, res_n)
69     begin
70         if (res_n'event and res_n = '0') then
71             d_print(string'("reset"));
72             cur_status <= reset0;
73         end if;
74
75         if (set_clk'event and set_clk = '1') then
76             d_print(string'("*"));
77
78             case cur_status is
79                 when reset0 => 
80                     cur_status <= reset1;
81                 when reset1 => 
82                     cur_status <= reset2;
83                 when reset2 => 
84                     cur_status <= reset3;
85                 when reset3 => 
86                     cur_status <= reset4;
87                 when reset4 => 
88                     cur_status <= reset5;
89                 when reset5 => 
90                     cur_status <= fetch;
91                 when fetch => 
92                     d_print(string'("fetch"));
93                     pcl_a_o_n <= '0';
94                     pch_a_o_n <= '0';
95                     r_nw <= '1';
96                     pc_inc_n <= '0';
97                     cur_status <= exec;
98                 when exec => 
99                     d_print(string'(" exec and decode "), conv_integer(instruction));
100                     ---one byte instruction decoding.
101                     if instruction = conv_std_logic_vector(16#78#, dsize) then
102                         --0x78 = 120
103                         d_print(string'("   sei"));
104                         pcl_a_o_n <= '1';
105                         pch_a_o_n <= '1';
106                         pc_inc_n <= '1';
107                         ---set flag operation here.
108                         cur_status <= fetch;
109                     elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
110                         --0xa2 = 162 
111                         d_print(string'("   ldx 0"));
112                         pcl_a_o_n <= '0';
113                         pch_a_o_n <= '0';
114                         pc_inc_n <= '0';
115                         ---load X operation here.
116                         cur_status <= fetch;
117                     elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
118                         --0x9a = 154
119                         d_print(string'("   txs"));
120                         pcl_a_o_n <= '1';
121                         pch_a_o_n <= '1';
122                         pc_inc_n <= '1';
123                         cur_status <= fetch;
124                     elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
125                         --0x4c = 76
126                         cur_status <= jmp1;
127                         d_print(string'("   jmp 0"));
128                         pc_inc_n <= '0';
129                         pcl_a_o_n <= '0';
130                         pch_a_o_n <= '0';
131                         cur_status <= jmp1;
132
133                     else
134                         cur_status <= unknown_stat;
135                         d_print(string'("unknown inst."));
136                         pc_inc_n <= '1';
137                         pcl_a_o_n <= '1';
138                         pch_a_o_n <= '1';
139                     end if;
140
141                 when ldx1 => 
142                     d_print(string'("   ldx 1"));
143                     cur_status <= unknown_stat;
144                 when jmp1 => 
145                     d_print(string'("   jmp 1"));
146                     pc_inc_n <= '0';
147                     pcl_a_o_n <= '1';
148                     pch_a_o_n <= '1';
149                     cur_status <= fetch;
150                 when jmp2 => 
151                     d_print(string'("   jmp 2"));
152
153                 when others => null;
154                     d_print(string'("unknown status."));
155                     cur_status <= unknown_stat;
156             end case;
157         end if;
158
159     end process;
160
161 end rtl;
162