simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  16             ad_oe_n         : out std_logic;
  17             pcl_d_we_n      : out std_logic;
  18             pcl_a_we_n      : out std_logic;
  19             pcl_d_oe_n      : out std_logic;
  20             pcl_a_oe_n      : out std_logic;
  21             pch_d_we_n      : out std_logic;
  22             pch_a_we_n      : out std_logic;
  23             pch_d_oe_n      : out std_logic;
  24             pch_a_oe_n      : out std_logic;
  25             pc_inc_n        : out std_logic;
  26             inst_we_n       : out std_logic;
  27             dbuf_int_oe_n   : out std_logic;
  28             dl_al_we_n      : out std_logic;
  29             dl_ah_we_n      : out std_logic;
  30             dl_dl_oe_n      : out std_logic;
  31             dl_dh_oe_n      : out std_logic;
  32             dl_al_oe_n      : out std_logic;
  33             dl_ah_oe_n      : out std_logic;
  34             sp_we_n         : out std_logic;
  35             sp_push_n       : out std_logic;
  36             sp_pop_n        : out std_logic;
  37             sp_int_d_oe_n   : out std_logic;
  38             sp_int_a_oe_n   : out std_logic;
  39             acc_d_we_n      : out std_logic;
  40             acc_alu_we_n    : out std_logic;
  41             acc_d_oe_n      : out std_logic;
  42             acc_alu_oe_n    : out std_logic;
  43             x_we_n          : out std_logic;
  44             x_oe_n          : out std_logic;
  45             x_calc_n        : out std_logic;
  46             y_we_n          : out std_logic;
  47             y_oe_n          : out std_logic;
  48             y_calc_n        : out std_logic;
  49             ea_ah_oe_n      : out std_logic;
  50             ea_al_oe_n      : out std_logic;
  51             ea_carry        : in  std_logic;
  52             stat_dec_we_n   : out std_logic;
  53             stat_dec_oe_n   : out std_logic;
  54             stat_bus_we_n   : out std_logic;
  55             stat_bus_oe_n   : out std_logic;
  56             r_nw            : out std_logic;
  57             dbg_show_pc     : out std_logic
  58         );
  59 end decoder;
  60
  61 architecture rtl of decoder is
  62
  63 procedure d_print(msg : string) is
  64 use std.textio.all;
  65 use ieee.std_logic_textio.all;
  66 variable out_l : line;
  67 begin
  68     write(out_l, msg);
  69     writeline(output, out_l);
  70 end  procedure;
  71
  72 procedure d_print(msg : string; sig : std_logic_vector) is
  73 use std.textio.all;
  74 use ieee.std_logic_textio.all;
  75 variable out_l : line;
  76 begin
  77     write(out_l, msg);
  78     write(out_l, sig);
  79     writeline(output, out_l);
  80 end  procedure;
  81
  82 procedure d_print(msg : string; ival : integer) is
  83 use std.textio.all;
  84 use ieee.std_logic_textio.all;
  85 variable out_l : line;
  86 begin
  87     write(out_l, msg);
  88     write(out_l, ival);
  89     writeline(output, out_l);
  90 end  procedure;
  91
  92 ---ival : 0x0000 - 0xffff
  93 function conv_hex16(ival : integer) return string is
  94 variable tmp1, tmp2, tmp3, tmp4 : integer;
  95 --variable ret : string (1 to 4) := "0000";
  96 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  97 begin
  98     tmp4 := ival / 16 ** 3;
  99     tmp3 := (ival mod 16 ** 3) / 16 ** 2;
 100     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
 101     tmp1 := ival mod 16 ** 1;
 102     return hex_chr(tmp4 + 1) & hex_chr(tmp3 + 1)
 103         & hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
 104 end;
 105
 106 function conv_hex8(ival : integer) return string is
 107 variable tmp1, tmp2 : integer;
 108 variable hex_chr: string (1 to 16) := "0123456789abcdef";
 109 begin
 110     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
 111     tmp1 := ival mod 16 ** 1;
 112     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
 113 end;
 114
 115
 116 type exec_cycle is (reset0, reset1, reset2, reset3, reset4, reset5,
 117                     --exec0 = fetch, exec1=decode
 118                     fetch, decode, exec2, exec3, exec4, exec5,
 119                     err_cycle);
 120
 121 type addr_mode is ( ad_imm,
 122                     ad_acc,
 123                     ad_zp, ad_zpx, ad_zpy,
 124                     ad_abs, ad_absx, ad_absy,
 125                     ad_indir_x, ad_indir_y,
 126                     ad_unknown);
 127
 128
 129 signal cur_cycle : exec_cycle;
 130
 131 -- SR Flags (bit 7 to bit 0):
 132 --  7   N   ....    Negative
 133 --  6   V   ....    Overflow
 134 --  5   -   ....    ignored
 135 --  4   B   ....    Break
 136 --  3   D   ....    Decimal (use BCD for arithmetics)
 137 --  2   I   ....    Interrupt (IRQ disable)
 138 --  1   Z   ....    Zero
 139 --  0   C   ....    Carry
 140 constant st_N : integer := 7;
 141 constant st_V : integer := 6;
 142 constant st_B : integer := 4;
 143 constant st_D : integer := 3;
 144 constant st_I : integer := 2;
 145 constant st_Z : integer := 1;
 146 constant st_C : integer := 0;
 147
 148 ---case instruction consists of aaabbbcc form,
 149 ---return addressing mode for each opcode.
 150 function decode_addr_mode (instruction : in std_logic_vector (dsize - 1 downto 0))
 151      return addr_mode is
 152 begin
 153     if instruction (1 downto 0) = "01" then
 154         if instruction (4 downto 2) = "000" then
 155             --(zero page,X)
 156             return ad_indir_x;
 157         elsif instruction (4 downto 2) = "001" then
 158             return  ad_zp;
 159         elsif instruction (4 downto 2) = "010" then
 160             return  ad_imm;
 161         elsif instruction (4 downto 2) = "011" then
 162             return  ad_abs;
 163         elsif instruction (4 downto 2) = "100" then
 164             --(zero page),Y
 165             return ad_indir_y;
 166         elsif instruction (4 downto 2) = "101" then
 167             return  ad_zpx;
 168         elsif instruction (4 downto 2) = "110" then
 169             return  ad_absy;
 170         elsif instruction (4 downto 2) = "111" then
 171             return  ad_absx;
 172         end if;
 173     elsif instruction (1 downto 0) = "10" then
 174         --d_print("cc=10");
 175         --bbb is 000, 001, 010, 011, 101, 111 only.
 176         if instruction (4 downto 2) = "000" then
 177             return  ad_imm;
 178         elsif instruction (4 downto 2) = "001" then
 179             return  ad_zp;
 180         elsif instruction (4 downto 2) = "010" then
 181             return  ad_acc;
 182         elsif instruction (4 downto 2) = "011" then
 183             return  ad_abs;
 184         elsif instruction (4 downto 2) = "101" then
 185             return  ad_zpx;
 186         elsif instruction (4 downto 2) = "111" then
 187             return  ad_absx;
 188         else
 189             return  ad_unknown;
 190         end if;
 191
 192     elsif instruction (1 downto 0) = "00" then
 193         --d_print("cc=00 group...");
 194         ---bbb part is 000, 001, 011, 101, 111 only.
 195         if instruction (4 downto 2) = "000" then
 196             return  ad_imm;
 197         elsif instruction (4 downto 2) = "001" then
 198             return  ad_zp;
 199         elsif instruction (4 downto 2) = "011" then
 200             return  ad_abs;
 201         elsif instruction (4 downto 2) = "101" then
 202             return  ad_zpx;
 203         elsif instruction (4 downto 2) = "111" then
 204             return  ad_absx;
 205         else
 206             return  ad_unknown;
 207         end if;
 208     else
 209         return  ad_unknown;
 210     end if; --if instruction (1 downto 0) = "01" then
 211 end  function;
 212
 213 begin
 214
 215     main_p : process (set_clk, trig_clk, res_n)
 216     variable single_inst : boolean;
 217     variable status_reg_old : std_logic_vector(dsize - 1 downto 0);
 218     variable cur_mode : addr_mode;
 219     begin
 220
 221         if (res_n'event and res_n = '0') then
 222             d_print(string'("reset"));
 223             cur_cycle <= reset0;
 224
 225             ad_oe_n <= '1';
 226             pcl_d_we_n <= '1';
 227             pcl_a_we_n <= '1';
 228             pcl_d_oe_n <= '1';
 229             pcl_a_oe_n <= '1';
 230             pch_d_we_n <= '1';
 231             pch_a_we_n <= '1';
 232             pch_d_oe_n <= '1';
 233             pch_a_oe_n <= '1';
 234             pc_inc_n <= '1';
 235             inst_we_n <= '1';
 236             dbuf_int_oe_n <= '1';
 237             dl_al_we_n <= '1';
 238             dl_ah_we_n <= '1';
 239             dl_dl_oe_n <= '1';
 240             dl_dh_oe_n <= '1';
 241             dl_al_oe_n <= '1';
 242             dl_ah_oe_n <= '1';
 243             sp_we_n <= '1';
 244             sp_push_n <= '1';
 245             sp_pop_n <= '1';
 246             sp_int_d_oe_n <= '1';
 247             sp_int_a_oe_n <= '1';
 248             acc_d_we_n <= '1';
 249             acc_alu_we_n <= '1';
 250             acc_d_oe_n <= '1';
 251             acc_alu_oe_n <= '1';
 252             x_we_n <= '1';
 253             x_oe_n <= '1';
 254             y_we_n <= '1';
 255             y_oe_n <= '1';
 256             stat_dec_we_n <= '1';
 257             stat_dec_oe_n <= '1';
 258             stat_bus_we_n <= '1';
 259             stat_bus_oe_n <= '1';
 260             x_calc_n <= '1';
 261             y_calc_n <= '1';
 262             ea_ah_oe_n <= '1';
 263             ea_al_oe_n <= '1';
 264
 265         end if;
 266
 267         if (set_clk'event and set_clk = '1') then
 268             d_print(string'("-"));
 269
 270             if cur_cycle = reset0 then
 271                 cur_cycle <= reset1;
 272             elsif cur_cycle = reset1 then
 273                 cur_cycle <= reset2;
 274             elsif cur_cycle = reset2 then
 275                 cur_cycle <= reset3;
 276             elsif cur_cycle = reset3 then
 277                 cur_cycle <= reset4;
 278             elsif cur_cycle = reset4 then
 279                 cur_cycle <= reset5;
 280             elsif cur_cycle = reset5 then
 281                 cur_cycle <= fetch;
 282
 283             elsif cur_cycle = fetch then
 284                 --cycle #1
 285                 d_print(string'("fetch 1"));
 286                 ad_oe_n <= '0';
 287                 pcl_a_oe_n <= '0';
 288                 pch_a_oe_n <= '0';
 289                 inst_we_n <= '0';
 290                 pc_inc_n <= '0';
 291
 292                 x_we_n <= '1';
 293                 y_we_n <= '1';
 294                 sp_we_n <= '1';
 295                 sp_push_n <= '1';
 296                 sp_pop_n <= '1';
 297                 x_oe_n <= '1';
 298                 r_nw <= '1';
 299                 dbuf_int_oe_n <= '1';
 300                 stat_dec_we_n <= '1';
 301                 stat_bus_we_n <= '1';
 302                 pch_d_we_n <= '1';
 303                 pcl_a_we_n <= '1';
 304                 dl_al_we_n <= '1';
 305                 dl_al_oe_n <= '1';
 306                 dl_ah_oe_n <= '1';
 307                 pcl_d_we_n <= '1';
 308                 acc_d_we_n <= '1';
 309                 acc_d_oe_n  <= '1';
 310                 dl_dl_oe_n <= '1';
 311                 x_calc_n <= '1';
 312                 ea_al_oe_n <= '1';
 313                 dl_dh_oe_n <= '1';
 314                 ea_ah_oe_n <= '1';
 315
 316                 cur_cycle <= decode;
 317
 318                 ---for debug....
 319                 status_reg <= (others => 'Z');
 320                 stat_dec_oe_n <= '0';
 321
 322             elsif cur_cycle = decode then
 323                 --cycle #2
 324                 d_print("decode and execute inst: "
 325                         & conv_hex8(conv_integer(instruction)));
 326
 327                 --grab instruction register data.
 328                 inst_we_n <= '1';
 329
 330                 ---single byte instruction.
 331                 single_inst := false;
 332
 333                 if instruction = conv_std_logic_vector(16#8a#, dsize) then
 334                     single_inst := true;
 335                     d_print("txa");
 336                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
 337                     single_inst := true;
 338                     d_print("txs");
 339                     sp_we_n <= '0';
 340                     x_oe_n <= '0';
 341                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
 342                     single_inst := true;
 343                     d_print("tax");
 344                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
 345                     single_inst := true;
 346                     d_print("tsx");
 347                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
 348                     single_inst := true;
 349                     d_print("dex");
 350                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
 351                     single_inst := true;
 352                     d_print("nop");
 353                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
 354                     single_inst := true;
 355                     d_print("php");
 356                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
 357                     single_inst := true;
 358                     d_print("plp");
 359                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
 360                     single_inst := true;
 361                     d_print("pha");
 362                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
 363                     single_inst := true;
 364                     d_print("pla");
 365                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
 366                     single_inst := true;
 367                     d_print("dey");
 368                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
 369                     single_inst := true;
 370                     d_print("tay");
 371                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
 372                     single_inst := true;
 373                     d_print("iny");
 374                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
 375                     single_inst := true;
 376                     d_print("inx");
 377                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 378                     single_inst := true;
 379                     d_print("clc");
 380                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
 381                     single_inst := true;
 382                     d_print("sec");
 383                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 384                     single_inst := true;
 385                     d_print("cli");
 386                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
 387                     single_inst := true;
 388                     d_print("sei");
 389                     status_reg_old := status_reg;
 390                     stat_dec_oe_n <= '1';
 391                     stat_dec_we_n <= '0';
 392                     status_reg(7 downto st_I + 1)
 393                         <= status_reg_old (7 downto st_I + 1);
 394                     status_reg(st_I - 1 downto 0)
 395                         <= status_reg_old (st_I - 1 downto 0);
 396                     status_reg(st_I) <= '1';
 397                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
 398                     single_inst := true;
 399                     d_print("tya");
 400                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 401                     single_inst := true;
 402                     d_print("clv");
 403                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 404                     single_inst := true;
 405                     d_print("cld");
 406                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
 407                     single_inst := true;
 408                     d_print("sed");
 409                 end if;
 410
 411                 if single_inst then
 412                     cur_cycle <= fetch;
 413                     pcl_a_oe_n <= '1';
 414                     pch_a_oe_n <= '1';
 415                     pc_inc_n <= '1';
 416                 else
 417
 418                     if instruction = conv_std_logic_vector(16#00#, dsize) then
 419                         d_print("brk");
 420                     elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 421                         d_print("jsr abs 2");
 422                         --fetch opcode.
 423                         pcl_a_oe_n <= '0';
 424                         pch_a_oe_n <= '0';
 425                         pc_inc_n <= '0';
 426                         dbuf_int_oe_n <= '0';
 427                         --latch data
 428                         dl_al_we_n <= '0';
 429                         cur_cycle <= exec2;
 430
 431                     elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 432                         d_print("40");
 433                     elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 434                         d_print("rts 2");
 435                         pcl_a_oe_n <= '1';
 436                         pch_a_oe_n <= '1';
 437                         pc_inc_n <= '1';
 438
 439                         --pop stack (decrement only)
 440                         sp_pop_n <= '0';
 441                         sp_int_a_oe_n <= '0';
 442
 443                         cur_cycle <= exec2;
 444                     elsif instruction (4 downto 0) = "10000" then
 445                         ---conditional branch instruction..
 446
 447                     else
 448                         ---instruction consists of aaabbbcc form.
 449
 450                         ---addressing mode identifier
 451                         cur_mode := decode_addr_mode(instruction);
 452
 453                         if cur_mode = ad_imm then
 454                             d_print("immediate");
 455                             pcl_a_oe_n <= '0';
 456                             pch_a_oe_n <= '0';
 457                             pc_inc_n <= '0';
 458                             --send data from data bus buffer.
 459                             --receiver is instruction dependent.
 460                             dbuf_int_oe_n <= '0';
 461                             cur_cycle <= fetch;
 462                         elsif cur_mode = ad_acc then
 463                         elsif cur_mode = ad_zp then
 464                         elsif cur_mode = ad_zpx then
 465                         elsif cur_mode = ad_zpy then
 466                         elsif cur_mode = ad_abs then
 467                             d_print("abs 2");
 468                             --fetch next opcode (abs low).
 469                             pcl_a_oe_n <= '0';
 470                             pch_a_oe_n <= '0';
 471                             pc_inc_n <= '0';
 472                             --latch abs low data.
 473                             dbuf_int_oe_n <= '0';
 474                             dl_al_we_n <= '0';
 475                             cur_cycle <= exec2;
 476                         elsif cur_mode = ad_absx then
 477                             d_print("absx 2");
 478                             --same as abs until cycle 3.
 479                             pcl_a_oe_n <= '0';
 480                             pch_a_oe_n <= '0';
 481                             pc_inc_n <= '0';
 482                             --latch abs low data.
 483                             dbuf_int_oe_n <= '0';
 484                             dbuf_int_oe_n <= '0';
 485                             dl_al_we_n <= '0';
 486                             cur_cycle <= exec2;
 487                         elsif cur_mode = ad_absy then
 488                         elsif cur_mode = ad_indir_x then
 489                         elsif cur_mode = ad_indir_y then
 490                         else
 491                             assert false
 492                                 report ("unknow addressing mode.") severity failure;
 493                             cur_cycle <= err_cycle;
 494                         end if; --if cur_mode = ad_imm then
 495
 496                         if instruction (1 downto 0) = "01" then
 497                             --d_print("cc=01");
 498
 499                             if instruction (7 downto 5) = "000" then
 500                                 d_print("ora");
 501                             elsif instruction (7 downto 5) = "001" then
 502                                 d_print("and");
 503                             elsif instruction (7 downto 5) = "010" then
 504                                 d_print("eor");
 505                             elsif instruction (7 downto 5) = "011" then
 506                                 d_print("adc");
 507                             elsif instruction (7 downto 5) = "100" then
 508                                 if (cur_mode = ad_imm) then
 509                                     d_print("sta");
 510                                 end if;
 511                             elsif instruction (7 downto 5) = "101" then
 512                                 if (cur_mode = ad_imm) then
 513                                     d_print("lda");
 514                                     acc_d_we_n <= '0';
 515                                     --status register n/z bit update.
 516                                     stat_dec_oe_n <= '1';
 517                                     status_reg <= "10000010";
 518                                     stat_bus_we_n <= '0';
 519                                 end if;
 520                             elsif instruction (7 downto 5) = "110" then
 521                                 d_print("cmp");
 522                             elsif instruction (7 downto 5) = "111" then
 523                                 d_print("sbc");
 524                             else
 525                                 assert false
 526                                     report ("unknow instruction") severity failure;
 527                                 cur_cycle <= err_cycle;
 528                             end if;
 529                         elsif instruction (1 downto 0) = "10" then
 530                             --d_print("cc=10");
 531
 532                             if instruction (7 downto 5) = "000" then
 533                                 d_print("asl");
 534                             elsif instruction (7 downto 5) = "001" then
 535                                 d_print("rol");
 536                             elsif instruction (7 downto 5) = "010" then
 537                                 d_print("lsr");
 538                             elsif instruction (7 downto 5) = "011" then
 539                                 d_print("ror");
 540                             elsif instruction (7 downto 5) = "100" then
 541                                 d_print("stx");
 542                             elsif instruction (7 downto 5) = "101" then
 543                                 if (cur_mode = ad_imm) then
 544                                     d_print("ldx");
 545                                     x_we_n <= '0';
 546                                     --status register n/z bit update.
 547                                     stat_dec_oe_n <= '1';
 548                                     status_reg <= "10000010";
 549                                     stat_bus_we_n <= '0';
 550                                 end if;
 551                             elsif instruction (7 downto 5) = "110" then
 552                                 d_print("dec");
 553                             elsif instruction (7 downto 5) = "111" then
 554                                 d_print("inc");
 555                             else
 556                                 assert false
 557                                     report ("unknow instruction") severity failure;
 558                                 cur_cycle <= err_cycle;
 559                             end if;
 560
 561                         elsif instruction (1 downto 0) = "00" then
 562                             --d_print("cc=00 group...");
 563
 564                             if instruction (7 downto 5) = "001" then
 565                                 d_print("bit");
 566                             elsif instruction (7 downto 5) = "010" then
 567                                 --jmp always absolute addressing
 568                                 --d_print("jmp");
 569                                 null;
 570                             elsif instruction (7 downto 5) = "011" then
 571                                 --d_print("jmp (abs) 2");
 572                                 null;
 573                             elsif instruction (7 downto 5) = "100" then
 574                                 d_print("sty");
 575                             elsif instruction (7 downto 5) = "101" then
 576                                 if (cur_mode = ad_imm) then
 577                                     d_print("ldy");
 578                                     y_we_n <= '0';
 579                                     --status register n/z bit update.
 580                                     stat_dec_oe_n <= '1';
 581                                     status_reg <= "10000010";
 582                                     stat_bus_we_n <= '0';
 583                                 end if;
 584                             elsif instruction (7 downto 5) = "110" then
 585                                 d_print("cpy");
 586                             elsif instruction (7 downto 5) = "111" then
 587                                 d_print("cpx");
 588                             else
 589                                 assert false
 590                                     report ("unknow instruction") severity failure;
 591                                 cur_cycle <= err_cycle;
 592                             end if; --if instruction (7 downto 5) = "001" then
 593                         end if; --if instruction (1 downto 0) = "01"
 594                     end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
 595                 end if; --if single_inst
 596
 597             elsif cur_cycle = exec2 then
 598                 --cycle #3
 599                 if instruction = conv_std_logic_vector(16#00#, dsize) then
 600
 601                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 602                     d_print("jsr 3");
 603                     pcl_a_oe_n <= '1';
 604                     pch_a_oe_n <= '1';
 605                     pc_inc_n <= '1';
 606                     dbuf_int_oe_n <= '1';
 607                     dl_al_we_n <= '1';
 608
 609                    --push return addr high into stack.
 610                     sp_push_n <= '0';
 611                     pch_d_oe_n <= '0';
 612                     sp_int_a_oe_n <= '0';
 613                     r_nw <= '0';
 614                     cur_cycle <= exec3;
 615                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 616                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 617                         d_print("rts 3");
 618                         --pop pcl
 619                         sp_int_a_oe_n <= '0';
 620                         sp_pop_n <= '0';
 621
 622                         cur_cycle <= exec3;
 623                 elsif instruction (4 downto 0) = "10000" then
 624                     ---conditional branch instruction..
 625                 else
 626
 627                     if cur_mode = ad_abs then
 628                         d_print("abs 3");
 629                         dl_al_we_n <= '1';
 630
 631                         --latch abs hi data.
 632                         pcl_a_oe_n <= '0';
 633                         pch_a_oe_n <= '0';
 634                         dbuf_int_oe_n <= '0';
 635                         dl_ah_we_n <= '0';
 636                         --pc_inc is '0'. only jump is '1'.
 637                         --pc_inc_n <= '0';
 638                     elsif cur_mode = ad_absx then
 639                         d_print("absx 3");
 640                         dl_al_we_n <= '1';
 641
 642                         --latch abs hi data.
 643                         pcl_a_oe_n <= '0';
 644                         pch_a_oe_n <= '0';
 645                         dbuf_int_oe_n <= '0';
 646                         dl_ah_we_n <= '0';
 647                         cur_cycle <= exec3;
 648                     end if; --if cur_mode = ad_abs then
 649
 650                     if instruction (1 downto 0) = "00" then
 651                         if instruction (7 downto 5) = "010" then
 652                         --jmp
 653                             d_print("jmp");
 654                             pc_inc_n <= '1';
 655                             --pcl set from adl bus.
 656                             dl_al_oe_n <= '0';
 657                             pcl_a_oe_n <= '1';
 658                             pcl_a_we_n <= '0';
 659                             --pch set dbus.
 660                             pch_d_we_n <= '0';
 661                             cur_cycle <= fetch;
 662                         end if; --if instruction (7 downto 5) = "010" then
 663                     elsif instruction (1 downto 0) = "01" then
 664                         if instruction (7 downto 5) = "100" then
 665                             --d_print("sta");
 666                             cur_cycle <= exec3;
 667                         end if;
 668                     end if; --if instruction (1 downto 0) = "00" then
 669                 end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
 670
 671             elsif cur_cycle = exec3 then
 672                 --cycle #4
 673                 if instruction = conv_std_logic_vector(16#00#, dsize) then
 674                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 675                     d_print("jsr 4");
 676                     pch_d_oe_n <= '1';
 677
 678                    --push return addr low into stack.
 679                     sp_push_n <= '0';
 680                     pcl_d_oe_n <= '0';
 681                     sp_int_a_oe_n <= '0';
 682                     r_nw <= '0';
 683
 684                     cur_cycle <= exec4;
 685                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 686                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 687                     d_print("rts 4");
 688                     --stack decrement stop.
 689                     sp_pop_n <= '1';
 690
 691                     --load pcl
 692                     dbuf_int_oe_n <= '0';
 693                     pcl_d_we_n <= '0';
 694
 695                     --pop pcl
 696                     sp_int_a_oe_n <= '0';
 697
 698                     cur_cycle <= exec4;
 699                 elsif instruction (4 downto 0) = "10000" then
 700                     ---conditional branch instruction..
 701                 else
 702                     if cur_mode = ad_abs then
 703                         --d_print("abs 4");
 704                         pc_inc_n <= '1';
 705                         pcl_a_oe_n <= '1';
 706                         pch_a_oe_n <= '1';
 707                         dbuf_int_oe_n <= '1';
 708                         dl_ah_we_n <= '1';
 709
 710                         --latch > al/ah.
 711                         dl_al_oe_n <= '0';
 712                         dl_ah_oe_n <= '0';
 713
 714                         cur_cycle <= fetch;
 715                     elsif cur_mode = ad_absx then
 716                         --d_print("absx 4");
 717                         pc_inc_n <= '1';
 718                         pcl_a_oe_n <= '1';
 719                         pch_a_oe_n <= '1';
 720                         dbuf_int_oe_n <= '1';
 721                         dl_ah_we_n <= '1';
 722
 723                         -----calucurate and output effective addr low
 724                         dl_dl_oe_n <= '0';
 725                         x_calc_n <= '0';
 726                         ea_al_oe_n <= '0';
 727                         dl_ah_oe_n <= '0';
 728
 729                         cur_cycle <= exec4;
 730                     end if; --if cur_mode = ad_abs then
 731
 732                     if instruction (1 downto 0) = "00" then
 733                     elsif instruction (1 downto 0) = "01" then
 734                         if instruction (7 downto 5) = "100" then
 735                             d_print("sta 4");
 736                             --output acc memory..
 737                             r_nw <= '0';
 738                             acc_d_oe_n  <= '0';
 739                         elsif instruction (7 downto 5) = "101" then
 740                             d_print("lda 4");
 741                             --if page boundary is crossed, redo in the next cycle.
 742                             acc_d_we_n  <= '0';
 743                         end if;
 744                     end if; --instruction (1 downto 0) = "00"
 745                 end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
 746
 747             elsif cur_cycle = exec4 then
 748                 --cycle #5
 749                 if instruction = conv_std_logic_vector(16#00#, dsize) then
 750                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 751                     d_print("jsr 5");
 752                     sp_push_n <= '1';
 753                     pcl_d_oe_n <= '1';
 754                     sp_int_a_oe_n <= '1';
 755                     r_nw <= '1';
 756
 757                     --fetch last op.
 758                     pcl_a_oe_n <= '0';
 759                     pch_a_oe_n <= '0';
 760
 761                     cur_cycle <= exec5;
 762
 763                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 764                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 765                     d_print("rts 5");
 766                     sp_int_a_oe_n <= '1';
 767                     pcl_d_we_n <= '1';
 768
 769                     --load pch
 770                     dbuf_int_oe_n <= '0';
 771                     pch_d_we_n <= '0';
 772
 773                     cur_cycle <= exec5;
 774                 elsif instruction (4 downto 0) = "10000" then
 775                     ---conditional branch instruction..
 776                 else
 777                     if cur_mode = ad_absx then
 778                         if ea_carry = '0' then
 779                             --case page boundary crossed.
 780                             d_print("absx 5 (page boudary crossed.)");
 781                             dl_dl_oe_n <= '1';
 782                             dl_ah_oe_n <= '1';
 783
 784                             --increment eah.
 785                             -----effective addr low is remorized in the calc.
 786                             dl_dh_oe_n <= '0';
 787                             x_calc_n <= '0';
 788                             ea_al_oe_n <= '0';
 789                             ea_ah_oe_n <= '0';
 790                             cur_cycle <= fetch;
 791                         else
 792                             --case page boundary not crossed. do the fetch op.
 793                             d_print("absx 5 (fetch)");
 794                             dl_dl_oe_n <= '1';
 795                             x_calc_n <= '1';
 796                             ea_al_oe_n <= '1';
 797                             dl_ah_oe_n <= '1';
 798                             acc_d_we_n  <= '1';
 799                             dl_al_we_n <= '1';
 800
 801                             pcl_a_oe_n <= '0';
 802                             pch_a_oe_n <= '0';
 803                             --cur_cycle <= decode;
 804                         end if;
 805                     end if;
 806                     if instruction (1 downto 0) = "00" then
 807                     elsif instruction (1 downto 0) = "01" then
 808                         if instruction (7 downto 5) = "100" then
 809                             d_print("sta 5");
 810                             --output acc memory..
 811                             r_nw <= '0';
 812                             acc_d_oe_n  <= '0';
 813                         elsif instruction (7 downto 5) = "101" then
 814                             d_print("lda 5");
 815                             --if page boundary is crossed, redo in the next cycle.
 816                             acc_d_we_n  <= '0';
 817                         end if;
 818                     end if; --instruction (1 downto 0) = "00"
 819                 end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
 820
 821             elsif cur_cycle = exec5 then
 822                 --cycle #6
 823                 if instruction = conv_std_logic_vector(16#00#, dsize) then
 824                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
 825                     d_print("jsr 6");
 826
 827                     pcl_a_oe_n <= '1';
 828                     pch_a_oe_n <= '1';
 829
 830                     --load/output  pch
 831                     ad_oe_n <= '1';
 832                     pch_d_we_n <= '0';
 833                     dbuf_int_oe_n <= '0';
 834
 835                     --load pcl.
 836                     dl_al_oe_n <= '0';
 837                     pcl_a_we_n <= '0';
 838
 839                     cur_cycle <= fetch;
 840                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
 841                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
 842                     d_print("rts 6");
 843                     dbuf_int_oe_n <= '1';
 844                     pch_d_we_n <= '1';
 845
 846                     --increment pc.
 847                     pc_inc_n <= '0';
 848                     cur_cycle <= fetch;
 849                 elsif instruction (4 downto 0) = "10000" then
 850                     ---conditional branch instruction..
 851                 else
 852                     if instruction (1 downto 0) = "00" then
 853                     end if; --instruction (1 downto 0) = "00"
 854                 end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
 855
 856             elsif cur_cycle = err_cycle then
 857                 ---stop decoding... > CPU stop.
 858             else
 859                 assert false
 860                     report ("unknow status") severity failure;
 861                 cur_cycle <= err_cycle;
 862             end if; --if cur_cycle = reset0 then
 863         end if; --if (set_clk'event and set_clk = '1')
 864
 865     end process;
 866
 867     dbg_p : process (set_clk)
 868     begin
 869         if (set_clk'event and set_clk= '0' and cur_cycle = decode) then
 870             dbg_show_pc <= '1';
 871         else
 872             dbg_show_pc <= '0';
 873         end if; --if (trigger_clk'event and trigger_clk = '1')
 874     end process;
 875 end rtl;
 876