2 use ieee.std_logic_1164.all;
5 generic ( dsize : integer := 8;
8 port ( input_clk : in std_logic; --phi0 input pin.
17 addr : out std_logic_vector ( asize - 1 downto 0);
18 d_io : inout std_logic_vector ( dsize - 1 downto 0)
22 architecture rtl of mos6502 is
27 reset_addr : integer := 0
32 pc_type : in std_logic;
33 dbus_we_n : in std_logic;
34 abus_we_n : in std_logic;
35 dbus_oe_n : in std_logic;
36 abus_oe_n : in std_logic;
37 addr_inc_n : in std_logic;
38 addr_dec_n : in std_logic;
39 add_carry : out std_logic;
40 rel_we_n : in std_logic;
41 rel_calc_n : in std_logic;
42 rel_prev : out std_logic;
43 int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
44 int_a_bus : inout std_logic_vector (dsize - 1 downto 0)
49 generic (dsize : integer := 8);
50 port ( set_clk : in std_logic;
51 trig_clk : in std_logic;
56 instruction : in std_logic_vector (dsize - 1 downto 0);
57 exec_cycle : in std_logic_vector (4 downto 0);
58 next_cycle : out std_logic_vector (4 downto 0);
59 status_reg : inout std_logic_vector (dsize - 1 downto 0);
60 inst_we_n : out std_logic;
61 alu_en_n : out std_logic;
62 ad_oe_n : out std_logic;
63 pcl_inc_n : out std_logic;
64 pcl_d_we_n : out std_logic;
65 pcl_a_we_n : out std_logic;
66 pcl_d_oe_n : out std_logic;
67 pcl_a_oe_n : out std_logic;
68 pcl_rel_we_n : out std_logic;
69 pcl_rel_calc_n : out std_logic;
70 pch_d_we_n : out std_logic;
71 pch_a_we_n : out std_logic;
72 pch_d_oe_n : out std_logic;
73 pch_a_oe_n : out std_logic;
74 rel_pg_crs_n : in std_logic;
75 dbuf_int_oe_n : out std_logic;
76 dl_al_we_n : out std_logic;
77 dl_ah_we_n : out std_logic;
78 dl_al_oe_n : out std_logic;
79 dl_ah_oe_n : out std_logic;
80 sp_we_n : out std_logic;
81 sp_push_n : out std_logic;
82 sp_pop_n : out std_logic;
83 sp_int_d_oe_n : out std_logic;
84 sp_int_a_oe_n : out std_logic;
85 acc_d_we_n : out std_logic;
86 acc_alu_we_n : out std_logic;
87 acc_d_oe_n : out std_logic;
88 x_we_n : out std_logic;
89 x_oe_n : out std_logic;
90 x_ea_oe_n : out std_logic;
91 x_inc_n : out std_logic;
92 x_dec_n : out std_logic;
93 y_we_n : out std_logic;
94 y_oe_n : out std_logic;
95 y_ea_oe_n : out std_logic;
96 y_inc_n : out std_logic;
97 y_dec_n : out std_logic;
98 ea_calc_n : out std_logic;
99 ea_zp_n : out std_logic;
100 ea_pg_next_n : out std_logic;
101 ea_carry : in std_logic;
102 stat_dec_oe_n : out std_logic;
103 stat_bus_oe_n : out std_logic;
104 stat_set_flg_n : out std_logic;
105 stat_flg : out std_logic;
106 stat_bus_all_n : out std_logic;
107 stat_bus_nz_n : out std_logic;
108 stat_alu_we_n : out std_logic;
110 ;---for parameter check purpose!!!
111 check_bit : out std_logic_vector(1 to 5)
117 generic ( dsize : integer := 8
119 port ( clk : in std_logic;
120 alu_en_n : in std_logic;
121 instruction : in std_logic_vector (dsize - 1 downto 0);
122 int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
123 acc_in : in std_logic_vector (dsize - 1 downto 0);
124 acc_out : out std_logic_vector (dsize - 1 downto 0);
125 carry_in : in std_logic;
126 negative : out std_logic;
127 zero : out std_logic;
128 carry_out : out std_logic;
129 overflow : out std_logic
133 ----------------------------------------------
134 ---------- register declareration ------------
135 ----------------------------------------------
144 d : in std_logic_vector (dsize - 1 downto 0);
145 q : out std_logic_vector (dsize - 1 downto 0)
156 int_oe_n : in std_logic;
157 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
158 ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
168 al_we_n : in std_logic;
169 ah_we_n : in std_logic;
170 al_oe_n : in std_logic;
171 ah_oe_n : in std_logic;
172 int_dbus : in std_logic_vector (dsize - 1 downto 0);
173 ea_al : out std_logic_vector (dsize - 1 downto 0);
174 ea_ah : out std_logic_vector (dsize - 1 downto 0)
185 push_n : in std_logic;
186 pop_n : in std_logic;
187 int_d_oe_n : in std_logic;
188 int_a_oe_n : in std_logic;
189 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
190 int_abus_l : out std_logic_vector (dsize - 1 downto 0);
191 int_abus_h : out std_logic_vector (dsize - 1 downto 0)
201 d : in std_logic_vector (dsize - 1 downto 0);
202 q : out std_logic_vector (dsize - 1 downto 0)
206 component processor_status
212 res_n : in std_logic;
213 dec_oe_n : in std_logic;
214 bus_oe_n : in std_logic;
215 set_flg_n : in std_logic;
216 flg_val : in std_logic;
217 load_bus_all_n : in std_logic;
218 load_bus_nz_n : in std_logic;
219 alu_we_n : in std_logic;
220 alu_n : in std_logic;
221 alu_v : in std_logic;
222 alu_z : in std_logic;
223 alu_c : in std_logic;
224 decoder : inout std_logic_vector (dsize - 1 downto 0);
225 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
229 component accumulator
235 d_we_n : in std_logic;
236 alu_we_n : in std_logic;
237 d_oe_n : in std_logic;
238 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
239 alu_in : in std_logic_vector (dsize - 1 downto 0);
240 alu_out : out std_logic_vector (dsize - 1 downto 0)
250 d_we_n : in std_logic;
251 d_oe_n : in std_logic;
252 ea_oe_n : in std_logic;
253 inc_n : in std_logic;
254 dec_n : in std_logic;
255 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
256 ea_bus : out std_logic_vector (dsize - 1 downto 0);
262 component effective_adder
263 generic ( dsize : integer := 8
266 ea_calc_n : in std_logic;
268 pg_next_n : in std_logic;
269 base_l : in std_logic_vector (dsize - 1 downto 0);
270 base_h : in std_logic_vector (dsize - 1 downto 0);
271 index : in std_logic_vector (dsize - 1 downto 0);
272 ah_bus : out std_logic_vector (dsize - 1 downto 0);
273 al_bus : out std_logic_vector (dsize - 1 downto 0);
274 carry : out std_logic
278 ----------------------------------------------
279 ------------ signal declareration ------------
280 ----------------------------------------------
281 signal set_clk : std_logic;
282 signal trigger_clk : std_logic;
284 signal pcl_inc_n : std_logic;
285 signal pcl_d_we_n : std_logic;
286 signal pcl_a_we_n : std_logic;
287 signal pcl_d_oe_n : std_logic;
288 signal pcl_a_oe_n : std_logic;
289 signal pcl_rel_we_n : std_logic;
290 signal pcl_rel_calc_n : std_logic;
291 signal pch_d_we_n : std_logic;
292 signal pch_a_we_n : std_logic;
293 signal pch_d_oe_n : std_logic;
294 signal pch_a_oe_n : std_logic;
295 signal pc_cry : std_logic;
296 signal pc_cry_n : std_logic;
297 signal dum_terminate : std_logic := 'Z';
298 signal pc_rel_prev : std_logic;
299 signal pc_rel_prev_n : std_logic;
300 signal rel_pg_crs_n : std_logic;
302 signal inst_we_n : std_logic;
303 signal dbuf_r_nw : std_logic;
304 signal dbuf_int_oe_n : std_logic;
305 signal dl_al_we_n : std_logic;
306 signal dl_ah_we_n : std_logic;
307 signal dl_al_oe_n : std_logic;
308 signal dl_ah_oe_n : std_logic;
310 signal sp_we_n : std_logic;
311 signal sp_push_n : std_logic;
312 signal sp_pop_n : std_logic;
313 signal sp_int_d_oe_n : std_logic;
314 signal sp_int_a_oe_n : std_logic;
316 signal acc_d_we_n : std_logic;
317 signal acc_alu_we_n : std_logic;
318 signal acc_d_oe_n : std_logic;
319 signal alu_en_n : std_logic;
320 signal alu_in : std_logic_vector(dsize - 1 downto 0);
321 signal alu_out : std_logic_vector(dsize - 1 downto 0);
323 signal x_we_n : std_logic;
324 signal x_oe_n : std_logic;
325 signal x_inc_n : std_logic;
326 signal x_dec_n : std_logic;
328 signal y_we_n : std_logic;
329 signal y_oe_n : std_logic;
330 signal y_inc_n : std_logic;
331 signal y_dec_n : std_logic;
333 signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
334 signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
335 signal ea_calc_n : std_logic;
336 signal ea_zp_n : std_logic;
337 signal ea_pg_next_n : std_logic;
338 signal ea_carry : std_logic;
340 signal ea_index : std_logic_vector(dsize - 1 downto 0);
341 signal x_ea_oe_n : std_logic;
342 signal y_ea_oe_n : std_logic;
344 signal stat_dec_oe_n : std_logic;
345 signal stat_bus_oe_n : std_logic;
346 signal stat_set_flg_n : std_logic;
347 signal stat_flg : std_logic;
348 signal stat_bus_all_n : std_logic;
349 signal stat_bus_nz_n : std_logic;
350 signal stat_alu_we_n : std_logic;
352 signal alu_n : std_logic;
353 signal alu_v : std_logic;
354 signal alu_z : std_logic;
355 signal alu_c : std_logic;
357 --internal bus (address hi/lo, data)
358 signal ad_oe_n : std_logic;
359 signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
360 signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
361 signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
363 signal instruction : std_logic_vector (dsize - 1 downto 0);
364 signal exec_cycle : std_logic_vector (4 downto 0);
365 signal next_cycle : std_logic_vector (4 downto 0);
366 signal status_reg : std_logic_vector (dsize - 1 downto 0);
368 signal check_bit : std_logic_vector(1 to 5);
372 ---------------------------------------
373 -------------- instances --------------
374 ---------------------------------------
375 dec_inst : decoder generic map (dsize)
436 , check_bit --check bit.
439 alu_inst : alu generic map (dsize)
440 port map (trigger_clk, alu_en_n, instruction,
441 internal_dbus, alu_in, alu_out,
443 alu_n, alu_z, alu_c, alu_v
446 --cpu execution cycle number
447 exec_cycle_inst : dff generic map (5)
448 port map(trigger_clk, '0', '0', next_cycle, exec_cycle);
451 data_bus_buffer : dbus_buf generic map (dsize)
452 port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, internal_dbus, d_io);
454 ---effective addres calcurator.
455 ea_calc: effective_adder generic map (dsize)
456 port map (ea_calc_n, ea_zp_n, ea_pg_next_n,
457 ea_base_l, ea_base_h, ea_index,
458 internal_abus_h, internal_abus_l, ea_carry);
460 --address operand data buffer.
461 input_data_latch : input_dl generic map (dsize)
462 port map(set_clk, dl_al_we_n, dl_ah_we_n, dl_al_oe_n, dl_ah_oe_n,
463 internal_dbus, ea_base_l, ea_base_h);
465 pc_l : pc generic map (dsize, 16#00#)
466 port map(trigger_clk, rst_n, '0',
467 pcl_d_we_n, pcl_a_we_n, pcl_d_oe_n, pcl_a_oe_n,
468 pcl_inc_n, '1', pc_cry,
469 pcl_rel_we_n, pcl_rel_calc_n, pc_rel_prev,
470 internal_dbus, internal_abus_l);
471 pc_h : pc generic map (dsize, 16#80#)
472 port map(trigger_clk, rst_n, '1',
473 pch_d_we_n, pch_a_we_n, pch_d_oe_n, pch_a_oe_n,
474 pc_cry_n, pc_rel_prev_n, dum_terminate,
475 '1', '1', dum_terminate,
476 internal_dbus, internal_abus_h);
478 instruction_register : dff generic map (dsize)
479 port map(trigger_clk, inst_we_n, '0', d_io, instruction);
481 stack_pointer : sp generic map (dsize)
482 port map(trigger_clk, sp_we_n, sp_push_n, sp_pop_n,
483 sp_int_d_oe_n, sp_int_a_oe_n,
484 internal_dbus, internal_abus_l, internal_abus_h);
486 status_register : processor_status generic map (dsize)
487 port map (trigger_clk, rst_n,
488 stat_dec_oe_n, stat_bus_oe_n,
489 stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n,
490 stat_alu_we_n, alu_n, alu_v, alu_z, alu_c,
491 status_reg, internal_dbus);
493 --x/y output pin is connected to effective address calcurator
494 x_reg : index_reg generic map (dsize)
495 port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n,
496 x_inc_n, x_dec_n, internal_dbus, ea_index,
499 y_reg : index_reg generic map (dsize)
500 port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n,
501 y_inc_n, y_dec_n, internal_dbus, ea_index,
504 acc_reg : accumulator generic map (dsize)
505 port map(trigger_clk,
506 acc_d_we_n, acc_alu_we_n, acc_d_oe_n,
507 internal_dbus, alu_in, alu_out);
511 phi2 <= not input_clk;
512 set_clk <= input_clk;
513 trigger_clk <= not input_clk;
515 pc_cry_n <= not pc_cry;
516 pc_rel_prev_n <= not pc_rel_prev;
519 --branch instruction page crossed?
520 rel_pg_crs_n <= pc_cry nand pc_rel_prev;
522 --adh output is controlled by decoder.
523 adh_buffer : tsb generic map (dsize)
524 port map (ad_oe_n, internal_abus_h, addr(asize - 1 downto dsize));
525 adl_buffer : tsb generic map (dsize)
526 port map (ad_oe_n, internal_abus_l, addr(dsize - 1 downto 0));
528 reset_p : process (rst_n)
530 if (rst_n'event and rst_n = '0') then
535 ------------------------------------------------------------
536 ------------------------ for debug... ----------------------
537 ------------------------------------------------------------
539 dbg_p : process (set_clk)
541 use ieee.std_logic_textio.all;
542 use ieee.std_logic_unsigned.conv_integer;
544 procedure d_print(msg : string) is
545 variable out_l : line;
548 writeline(output, out_l);
551 function conv_hex8(ival : integer) return string is
552 variable tmp1, tmp2 : integer;
553 variable hex_chr: string (1 to 16) := "0123456789abcdef";
555 tmp2 := (ival mod 16 ** 2) / 16 ** 1;
556 tmp1 := ival mod 16 ** 1;
557 return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
560 if (set_clk = '0' and exec_cycle = "00000") then
561 --show pc on the T0 (fetch) cycle.
562 d_print("pc : " & conv_hex8(conv_integer(internal_abus_h))
563 & conv_hex8(conv_integer(internal_abus_l)));