2 use ieee.std_logic_1164.all;
5 generic ( dsize : integer := 8;
8 port ( input_clk : in std_logic; --phi0 input pin.
17 addr : out std_logic_vector ( asize - 1 downto 0);
18 d_io : inout std_logic_vector ( dsize - 1 downto 0)
22 architecture rtl of mos6502 is
27 reset_addr : integer := 0
32 dbus_we_n : in std_logic;
33 abus_we_n : in std_logic;
34 dbus_oe_n : in std_logic;
35 abus_oe_n : in std_logic;
36 addr_inc_n : in std_logic;
37 add_carry : in std_logic;
38 inc_carry : out std_logic;
39 int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
40 int_a_bus : inout std_logic_vector (dsize - 1 downto 0)
45 generic (dsize : integer := 8);
46 port ( set_clk : in std_logic;
47 trig_clk : in std_logic;
52 instruction : in std_logic_vector (dsize - 1 downto 0);
53 exec_cycle : in std_logic_vector (4 downto 0);
54 next_cycle : out std_logic_vector (4 downto 0);
55 status_reg : inout std_logic_vector (dsize - 1 downto 0);
56 inst_we_n : out std_logic;
57 ad_oe_n : out std_logic;
58 pcl_d_we_n : out std_logic;
59 pcl_a_we_n : out std_logic;
60 pcl_d_oe_n : out std_logic;
61 pcl_a_oe_n : out std_logic;
62 pch_d_we_n : out std_logic;
63 pch_a_we_n : out std_logic;
64 pch_d_oe_n : out std_logic;
65 pch_a_oe_n : out std_logic;
66 pc_inc_n : out std_logic;
67 dbuf_int_oe_n : out std_logic;
68 dl_al_we_n : out std_logic;
69 dl_ah_we_n : out std_logic;
70 dl_al_oe_n : out std_logic;
71 dl_ah_oe_n : out std_logic;
72 sp_we_n : out std_logic;
73 sp_push_n : out std_logic;
74 sp_pop_n : out std_logic;
75 sp_int_d_oe_n : out std_logic;
76 sp_int_a_oe_n : out std_logic;
77 acc_d_we_n : out std_logic;
78 acc_alu_we_n : out std_logic;
79 acc_d_oe_n : out std_logic;
80 acc_alu_oe_n : out std_logic;
81 x_we_n : out std_logic;
82 x_oe_n : out std_logic;
83 x_ea_oe_n : out std_logic;
84 y_we_n : out std_logic;
85 y_oe_n : out std_logic;
86 y_ea_oe_n : out std_logic;
87 ea_calc_n : out std_logic;
88 ea_zp_n : out std_logic;
89 ea_pg_next_n : out std_logic;
90 ea_carry : in std_logic;
91 stat_dec_oe_n : out std_logic;
92 stat_bus_oe_n : out std_logic;
93 stat_set_flg_n : out std_logic;
94 stat_flg : out std_logic;
95 stat_bus_all_n : out std_logic;
96 stat_bus_nz_n : out std_logic;
97 stat_alu_we_n : out std_logic;
99 ;---for parameter check purpose!!!
100 check_bit : out std_logic_vector(1 to 5)
112 d : in std_logic_vector (dsize - 1 downto 0);
113 q : out std_logic_vector (dsize - 1 downto 0)
124 int_oe_n : in std_logic;
125 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
126 ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
136 al_we_n : in std_logic;
137 ah_we_n : in std_logic;
138 al_oe_n : in std_logic;
139 ah_oe_n : in std_logic;
140 int_dbus : in std_logic_vector (dsize - 1 downto 0);
141 ea_al : out std_logic_vector (dsize - 1 downto 0);
142 ea_ah : out std_logic_vector (dsize - 1 downto 0)
153 push_n : in std_logic;
154 pop_n : in std_logic;
155 int_d_oe_n : in std_logic;
156 int_a_oe_n : in std_logic;
157 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
158 int_abus_l : out std_logic_vector (dsize - 1 downto 0);
159 int_abus_h : out std_logic_vector (dsize - 1 downto 0)
169 d : in std_logic_vector (dsize - 1 downto 0);
170 q : out std_logic_vector (dsize - 1 downto 0)
174 component processor_status
180 res_n : in std_logic;
181 dec_oe_n : in std_logic;
182 bus_oe_n : in std_logic;
183 set_flg_n : in std_logic;
184 flg_val : in std_logic;
185 load_bus_all_n : in std_logic;
186 load_bus_nz_n : in std_logic;
187 alu_we_n : in std_logic;
188 alu_n : in std_logic;
189 alu_v : in std_logic;
190 alu_z : in std_logic;
191 alu_c : in std_logic;
192 decoder : inout std_logic_vector (dsize - 1 downto 0);
193 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
197 component accumulator
203 d_we_n : in std_logic;
204 alu_we_n : in std_logic;
205 d_oe_n : in std_logic;
206 alu_oe_n : in std_logic;
207 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
208 alu_bus : inout std_logic_vector (dsize - 1 downto 0)
218 d_we_n : in std_logic;
219 d_oe_n : in std_logic;
220 ea_oe_n : in std_logic;
221 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
222 ea_bus : out std_logic_vector (dsize - 1 downto 0)
226 component effective_adder
227 generic ( dsize : integer := 8
230 ea_calc_n : in std_logic;
232 pg_next_n : in std_logic;
233 base_l : in std_logic_vector (dsize - 1 downto 0);
234 base_h : in std_logic_vector (dsize - 1 downto 0);
235 index : in std_logic_vector (dsize - 1 downto 0);
236 ah_bus : out std_logic_vector (dsize - 1 downto 0);
237 al_bus : out std_logic_vector (dsize - 1 downto 0);
238 carry : out std_logic
242 signal set_clk : std_logic;
243 signal trigger_clk : std_logic;
245 signal pcl_d_we_n : std_logic;
246 signal pcl_a_we_n : std_logic;
247 signal pcl_d_oe_n : std_logic;
248 signal pcl_a_oe_n : std_logic;
249 signal pch_d_we_n : std_logic;
250 signal pch_a_we_n : std_logic;
251 signal pch_d_oe_n : std_logic;
252 signal pch_a_oe_n : std_logic;
253 signal pc_inc_n : std_logic;
254 signal pc_cry : std_logic;
255 signal pc_cry_n : std_logic;
256 signal dum_terminate : std_logic := 'Z';
258 signal inst_we_n : std_logic;
259 signal dbuf_r_nw : std_logic;
260 signal dbuf_int_oe_n : std_logic;
261 signal dl_al_we_n : std_logic;
262 signal dl_ah_we_n : std_logic;
263 signal dl_al_oe_n : std_logic;
264 signal dl_ah_oe_n : std_logic;
266 signal sp_we_n : std_logic;
267 signal sp_push_n : std_logic;
268 signal sp_pop_n : std_logic;
269 signal sp_int_d_oe_n : std_logic;
270 signal sp_int_a_oe_n : std_logic;
272 signal acc_d_we_n : std_logic;
273 signal acc_alu_we_n : std_logic;
274 signal acc_d_oe_n : std_logic;
275 signal acc_alu_oe_n : std_logic;
276 signal alu_bus : std_logic_vector(dsize - 1 downto 0);
278 signal x_we_n : std_logic;
279 signal x_oe_n : std_logic;
281 signal y_we_n : std_logic;
282 signal y_oe_n : std_logic;
284 signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
285 signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
286 signal ea_calc_n : std_logic;
287 signal ea_zp_n : std_logic;
288 signal ea_pg_next_n : std_logic;
289 signal ea_carry : std_logic;
291 signal ea_index : std_logic_vector(dsize - 1 downto 0);
292 signal x_ea_oe_n : std_logic;
293 signal y_ea_oe_n : std_logic;
295 signal stat_dec_oe_n : std_logic;
296 signal stat_bus_oe_n : std_logic;
297 signal stat_set_flg_n : std_logic;
298 signal stat_flg : std_logic;
299 signal stat_bus_all_n : std_logic;
300 signal stat_bus_nz_n : std_logic;
301 signal stat_alu_we_n : std_logic;
303 signal alu_n : std_logic;
304 signal alu_v : std_logic;
305 signal alu_z : std_logic;
306 signal alu_c : std_logic;
308 --internal bus (address hi/lo, data)
309 signal ad_oe_n : std_logic;
310 signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
311 signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
312 signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
314 signal instruction : std_logic_vector (dsize - 1 downto 0);
315 signal exec_cycle : std_logic_vector (4 downto 0);
316 signal next_cycle : std_logic_vector (4 downto 0);
317 signal status_reg : std_logic_vector (dsize - 1 downto 0);
319 signal check_bit : std_logic_vector(1 to 5);
323 dec_inst : decoder generic map (dsize)
381 --cpu execution cycle number
382 exec_cycle_inst : dff generic map (5)
383 port map(trigger_clk, '0', '0', next_cycle, exec_cycle);
386 data_bus_buffer : dbus_buf generic map (dsize)
387 port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, internal_dbus, d_io);
389 ---effective addres calcurator.
390 ea_calc: effective_adder generic map (dsize)
391 port map (ea_calc_n, ea_zp_n, ea_pg_next_n,
392 ea_base_l, ea_base_h, ea_index,
393 internal_abus_h, internal_abus_l, ea_carry);
395 --address operand data buffer.
396 input_data_latch : input_dl generic map (dsize)
397 port map(set_clk, dl_al_we_n, dl_ah_we_n, dl_al_oe_n, dl_ah_oe_n,
398 internal_dbus, ea_base_l, ea_base_h);
400 pc_l : pc generic map (dsize, 16#00#)
401 port map(trigger_clk, rst_n,
402 pcl_d_we_n, pcl_a_we_n, pcl_d_oe_n, pcl_a_oe_n,
403 pc_inc_n, '0', pc_cry, internal_dbus, internal_abus_l);
404 pc_h : pc generic map (dsize, 16#80#)
405 port map(trigger_clk, rst_n,
406 pch_d_we_n, pch_a_we_n, pch_d_oe_n, pch_a_oe_n,
407 pc_cry_n, pc_cry, dum_terminate, internal_dbus, internal_abus_h);
409 instruction_register : dff generic map (dsize)
410 port map(trigger_clk, inst_we_n, '0', d_io, instruction);
412 stack_pointer : sp generic map (dsize)
413 port map(trigger_clk, sp_we_n, sp_push_n, sp_pop_n,
414 sp_int_d_oe_n, sp_int_a_oe_n,
415 internal_dbus, internal_abus_l, internal_abus_h);
417 status_register : processor_status generic map (dsize)
418 port map (trigger_clk, rst_n,
419 stat_dec_oe_n, stat_bus_oe_n,
420 stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n,
421 stat_alu_we_n, alu_n, alu_v, alu_z, alu_c,
422 status_reg, internal_dbus);
424 --x/y output pin is connected to effective address calcurator
425 x_reg : index_reg generic map (dsize)
426 port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, internal_dbus, ea_index);
428 y_reg : index_reg generic map (dsize)
429 port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, internal_dbus, ea_index);
431 acc_reg : accumulator generic map (dsize)
432 port map(trigger_clk,
433 acc_d_we_n, acc_alu_we_n, acc_d_oe_n, acc_alu_oe_n,
434 internal_dbus, alu_bus);
438 phi2 <= not input_clk;
439 set_clk <= input_clk;
440 trigger_clk <= not input_clk;
441 pc_cry_n <= not pc_cry;
444 --adh output is controlled by decoder.
445 adh_buffer : tsb generic map (dsize)
446 port map (ad_oe_n, internal_abus_h, addr(asize - 1 downto dsize));
447 adl_buffer : tsb generic map (dsize)
448 port map (ad_oe_n, internal_abus_l, addr(dsize - 1 downto 0));
450 reset_p : process (rst_n)
452 if (rst_n'event and rst_n = '0') then
457 dbg_p : process (set_clk)
459 use ieee.std_logic_textio.all;
460 use ieee.std_logic_unsigned.conv_integer;
462 procedure d_print(msg : string) is
463 variable out_l : line;
466 writeline(output, out_l);
469 function conv_hex8(ival : integer) return string is
470 variable tmp1, tmp2 : integer;
471 variable hex_chr: string (1 to 16) := "0123456789abcdef";
473 tmp2 := (ival mod 16 ** 2) / 16 ** 1;
474 tmp1 := ival mod 16 ** 1;
475 return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
478 if (set_clk = '0' and exec_cycle = "00000") then
479 --show pc on the T0 (fetch) cycle.
480 d_print("pc : " & conv_hex8(conv_integer(internal_abus_h))
481 & conv_hex8(conv_integer(internal_abus_l)));