2 use ieee.std_logic_1164.all;
5 generic ( dsize : integer := 8;
8 port ( input_clk : in std_logic; --phi0 input pin.
17 addr : out std_logic_vector ( asize - 1 downto 0);
18 d_io : inout std_logic_vector ( dsize - 1 downto 0)
22 architecture rtl of mos6502 is
27 reset_addr : integer := 0
32 dbus_we_n : in std_logic;
33 abus_we_n : in std_logic;
34 dbus_oe_n : in std_logic;
35 abus_oe_n : in std_logic;
36 addr_inc_n : in std_logic;
37 add_carry : in std_logic;
38 inc_carry : out std_logic;
39 int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
40 int_a_bus : inout std_logic_vector (dsize - 1 downto 0)
45 generic (dsize : integer := 8);
46 port ( set_clk : in std_logic;
47 trig_clk : in std_logic;
52 instruction : in std_logic_vector (dsize - 1 downto 0);
53 exec_cycle : in std_logic_vector (4 downto 0);
54 next_cycle : out std_logic_vector (4 downto 0);
55 status_reg : inout std_logic_vector (dsize - 1 downto 0);
56 inst_we_n : out std_logic;
57 ad_oe_n : out std_logic;
58 pcl_d_we_n : out std_logic;
59 pcl_a_we_n : out std_logic;
60 pcl_d_oe_n : out std_logic;
61 pcl_a_oe_n : out std_logic;
62 pch_d_we_n : out std_logic;
63 pch_a_we_n : out std_logic;
64 pch_d_oe_n : out std_logic;
65 pch_a_oe_n : out std_logic;
66 pc_inc_n : out std_logic;
67 dbuf_int_oe_n : out std_logic;
68 dl_al_we_n : out std_logic;
69 dl_ah_we_n : out std_logic;
70 dl_al_oe_n : out std_logic;
71 dl_ah_oe_n : out std_logic;
72 sp_we_n : out std_logic;
73 sp_push_n : out std_logic;
74 sp_pop_n : out std_logic;
75 sp_int_d_oe_n : out std_logic;
76 sp_int_a_oe_n : out std_logic;
77 acc_d_we_n : out std_logic;
78 acc_alu_we_n : out std_logic;
79 acc_d_oe_n : out std_logic;
80 acc_alu_oe_n : out std_logic;
81 x_we_n : out std_logic;
82 x_oe_n : out std_logic;
83 x_ea_oe_n : out std_logic;
84 y_we_n : out std_logic;
85 y_oe_n : out std_logic;
86 y_ea_oe_n : out std_logic;
87 ea_calc_n : out std_logic;
88 ea_zp_n : out std_logic;
89 ea_pg_next_n : out std_logic;
90 ea_carry : in std_logic;
91 stat_dec_we_n : out std_logic;
92 stat_dec_oe_n : out std_logic;
93 stat_bus_we_n : out std_logic;
94 stat_bus_oe_n : out std_logic;
107 d : in std_logic_vector (dsize - 1 downto 0);
108 q : out std_logic_vector (dsize - 1 downto 0)
119 int_oe_n : in std_logic;
120 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
121 ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
131 al_we_n : in std_logic;
132 ah_we_n : in std_logic;
133 al_oe_n : in std_logic;
134 ah_oe_n : in std_logic;
135 int_dbus : in std_logic_vector (dsize - 1 downto 0);
136 ea_al : out std_logic_vector (dsize - 1 downto 0);
137 ea_ah : out std_logic_vector (dsize - 1 downto 0)
148 push_n : in std_logic;
149 pop_n : in std_logic;
150 int_d_oe_n : in std_logic;
151 int_a_oe_n : in std_logic;
152 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
153 int_abus_l : out std_logic_vector (dsize - 1 downto 0);
154 int_abus_h : out std_logic_vector (dsize - 1 downto 0)
164 d : in std_logic_vector (dsize - 1 downto 0);
165 q : out std_logic_vector (dsize - 1 downto 0)
169 component processor_status
175 res_n : in std_logic;
176 dec_we_n : in std_logic;
177 bus_we_n : in std_logic;
178 dec_oe_n : in std_logic;
179 bus_oe_n : in std_logic;
180 alu_c : in std_logic;
181 alu_v : in std_logic;
182 decoder : inout std_logic_vector (dsize - 1 downto 0);
183 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
187 component accumulator
193 d_we_n : in std_logic;
194 alu_we_n : in std_logic;
195 d_oe_n : in std_logic;
196 alu_oe_n : in std_logic;
197 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
198 alu_bus : inout std_logic_vector (dsize - 1 downto 0)
208 d_we_n : in std_logic;
209 d_oe_n : in std_logic;
210 ea_oe_n : in std_logic;
211 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
212 ea_bus : out std_logic_vector (dsize - 1 downto 0)
216 component effective_adder
217 generic ( dsize : integer := 8
220 ea_calc_n : in std_logic;
222 pg_next_n : in std_logic;
223 base_l : in std_logic_vector (dsize - 1 downto 0);
224 base_h : in std_logic_vector (dsize - 1 downto 0);
225 index : in std_logic_vector (dsize - 1 downto 0);
226 ah_bus : out std_logic_vector (dsize - 1 downto 0);
227 al_bus : out std_logic_vector (dsize - 1 downto 0);
228 carry : out std_logic
232 signal set_clk : std_logic;
233 signal trigger_clk : std_logic;
235 signal pcl_d_we_n : std_logic;
236 signal pcl_a_we_n : std_logic;
237 signal pcl_d_oe_n : std_logic;
238 signal pcl_a_oe_n : std_logic;
239 signal pch_d_we_n : std_logic;
240 signal pch_a_we_n : std_logic;
241 signal pch_d_oe_n : std_logic;
242 signal pch_a_oe_n : std_logic;
243 signal pc_inc_n : std_logic;
244 signal pc_cry : std_logic;
245 signal pc_cry_n : std_logic;
246 signal dum_terminate : std_logic := 'Z';
248 signal inst_we_n : std_logic;
249 signal dbuf_r_nw : std_logic;
250 signal dbuf_int_oe_n : std_logic;
251 signal dl_al_we_n : std_logic;
252 signal dl_ah_we_n : std_logic;
253 signal dl_al_oe_n : std_logic;
254 signal dl_ah_oe_n : std_logic;
256 signal sp_we_n : std_logic;
257 signal sp_push_n : std_logic;
258 signal sp_pop_n : std_logic;
259 signal sp_int_d_oe_n : std_logic;
260 signal sp_int_a_oe_n : std_logic;
262 signal acc_d_we_n : std_logic;
263 signal acc_alu_we_n : std_logic;
264 signal acc_d_oe_n : std_logic;
265 signal acc_alu_oe_n : std_logic;
266 signal alu_bus : std_logic_vector(dsize - 1 downto 0);
268 signal x_we_n : std_logic;
269 signal x_oe_n : std_logic;
271 signal y_we_n : std_logic;
272 signal y_oe_n : std_logic;
274 signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
275 signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
276 signal ea_calc_n : std_logic;
277 signal ea_zp_n : std_logic;
278 signal ea_pg_next_n : std_logic;
279 signal ea_carry : std_logic;
281 signal ea_index : std_logic_vector(dsize - 1 downto 0);
282 signal x_ea_oe_n : std_logic;
283 signal y_ea_oe_n : std_logic;
285 signal stat_dec_we_n : std_logic;
286 signal stat_dec_oe_n : std_logic;
287 signal stat_bus_we_n : std_logic;
288 signal stat_bus_oe_n : std_logic;
289 signal stat_alu_c : std_logic;
290 signal stat_alu_v : std_logic;
292 --internal bus (address hi/lo, data)
293 signal ad_oe_n : std_logic;
294 signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
295 signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
296 signal internal_dbus : std_logic_vector (dsize - 1 downto 0);
298 signal instruction : std_logic_vector (dsize - 1 downto 0);
299 signal exec_cycle : std_logic_vector (4 downto 0);
300 signal next_cycle : std_logic_vector (4 downto 0);
301 signal status_reg : std_logic_vector (dsize - 1 downto 0);
306 dec_inst : decoder generic map (dsize)
359 --cpu execution cycle number
360 exec_cycle_inst : dff generic map (5)
361 port map(trigger_clk, '0', '0', next_cycle, exec_cycle);
364 data_bus_buffer : dbus_buf generic map (dsize)
365 port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, internal_dbus, d_io);
367 ---effective addres calcurator.
368 ea_calc: effective_adder generic map (dsize)
369 port map (ea_calc_n, ea_zp_n, ea_pg_next_n,
370 ea_base_l, ea_base_h, ea_index,
371 internal_abus_h, internal_abus_l, ea_carry);
373 --address operand data buffer.
374 input_data_latch : input_dl generic map (dsize)
375 port map(set_clk, dl_al_we_n, dl_ah_we_n, dl_al_oe_n, dl_ah_oe_n,
376 internal_dbus, ea_base_l, ea_base_h);
378 pc_l : pc generic map (dsize, 16#00#)
379 port map(trigger_clk, rst_n,
380 pcl_d_we_n, pcl_a_we_n, pcl_d_oe_n, pcl_a_oe_n,
381 pc_inc_n, '0', pc_cry, internal_dbus, internal_abus_l);
382 pc_h : pc generic map (dsize, 16#80#)
383 port map(trigger_clk, rst_n,
384 pch_d_we_n, pch_a_we_n, pch_d_oe_n, pch_a_oe_n,
385 pc_cry_n, pc_cry, dum_terminate, internal_dbus, internal_abus_h);
387 instruction_register : dff generic map (dsize)
388 port map(trigger_clk, inst_we_n, '0', d_io, instruction);
390 stack_pointer : sp generic map (dsize)
391 port map(trigger_clk, sp_we_n, sp_push_n, sp_pop_n,
392 sp_int_d_oe_n, sp_int_a_oe_n,
393 internal_dbus, internal_abus_l, internal_abus_h);
395 status_register : processor_status generic map (dsize)
396 port map (trigger_clk, rst_n, stat_dec_we_n, stat_bus_we_n,
397 stat_dec_oe_n, stat_bus_oe_n,
398 stat_alu_c, stat_alu_v,
399 status_reg, internal_dbus);
401 --x/y output pin is connected to effective address calcurator
402 x_reg : index_reg generic map (dsize)
403 port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, internal_dbus, ea_index);
405 y_reg : index_reg generic map (dsize)
406 port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, internal_dbus, ea_index);
408 acc_reg : accumulator generic map (dsize)
409 port map(trigger_clk,
410 acc_d_we_n, acc_alu_we_n, acc_d_oe_n, acc_alu_oe_n,
411 internal_dbus, alu_bus);
415 phi2 <= not input_clk;
416 set_clk <= input_clk;
417 trigger_clk <= not input_clk;
418 pc_cry_n <= not pc_cry;
421 --adh output is controlled by decoder.
422 adh_buffer : tsb generic map (dsize)
423 port map (ad_oe_n, internal_abus_h, addr(asize - 1 downto dsize));
424 adl_buffer : tsb generic map (dsize)
425 port map (ad_oe_n, internal_abus_l, addr(dsize - 1 downto 0));
427 reset_p : process (rst_n)
429 if (rst_n'event and rst_n = '0') then
434 dbg_p : process (set_clk)
436 use ieee.std_logic_textio.all;
437 use ieee.std_logic_unsigned.conv_integer;
439 procedure d_print(msg : string) is
440 variable out_l : line;
443 writeline(output, out_l);
446 function conv_hex8(ival : integer) return string is
447 variable tmp1, tmp2 : integer;
448 variable hex_chr: string (1 to 16) := "0123456789abcdef";
450 tmp2 := (ival mod 16 ** 2) / 16 ** 1;
451 tmp1 := ival mod 16 ** 1;
452 return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
455 if (set_clk = '0' and exec_cycle = "00000") then
456 --show pc on the T0 (fetch) cycle.
457 d_print("pc : " & conv_hex8(conv_integer(internal_abus_h))
458 & conv_hex8(conv_integer(internal_abus_l)));