2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
11 port ( reset_n : in std_logic
15 architecture rtl of motones_sim is
16 component clock_divider
17 port ( base_clk : in std_logic;
18 reset_n : in std_logic;
19 cpu_clk : out std_logic;
20 ppu_clk : out std_logic
24 ---clock frequency = 21,477,270 (21 MHz)
25 constant base_clock_time : time := 46 ns;
27 signal base_clk : std_logic;
28 signal cpu_clk, ppu_clk : std_logic;
32 clock_inst : clock_divider port map
33 (base_clk, reset_n, cpu_clk, ppu_clk);
35 --- generate base clock.
39 wait for base_clock_time / 2;
41 wait for base_clock_time / 2;