2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
12 base_clk : in std_logic;
14 joypad1 : in std_logic_vector(7 downto 0);
15 joypad2 : in std_logic_vector(7 downto 0);
16 vga_clk : out std_logic;
17 h_sync_n : out std_logic;
18 v_sync_n : out std_logic;
19 r : out std_logic_vector(3 downto 0);
20 g : out std_logic_vector(3 downto 0);
21 b : out std_logic_vector(3 downto 0)
25 architecture rtl of motones_sim is
27 generic ( dsize : integer := 8;
30 port ( input_clk : in std_logic; --phi0 input pin.
39 addr : out std_logic_vector ( asize - 1 downto 0);
40 d_io : inout std_logic_vector ( dsize - 1 downto 0)
44 component clock_divider
45 port ( base_clk : in std_logic;
46 reset_n : in std_logic;
47 cpu_clk : out std_logic;
48 ppu_clk : out std_logic;
49 mem_clk : out std_logic;
50 vga_clk : out std_logic
54 component address_decoder
55 generic (abus_size : integer := 16; dbus_size : integer := 8);
56 port ( phi2 : in std_logic;
57 mem_clk : in std_logic;
59 addr : in std_logic_vector (abus_size - 1 downto 0);
60 d_io : inout std_logic_vector (dbus_size - 1 downto 0);
61 ppu_ce_n : out std_logic;
62 apu_ce_n : out std_logic
67 port ( clk : in std_logic;
71 cpu_addr : in std_logic_vector (2 downto 0);
72 cpu_d : inout std_logic_vector (7 downto 0);
73 vblank_n : out std_logic;
77 vram_ad : inout std_logic_vector (7 downto 0);
78 vram_a : out std_logic_vector (13 downto 8);
79 vga_clk : in std_logic;
80 h_sync_n : out std_logic;
81 v_sync_n : out std_logic;
82 r : out std_logic_vector(3 downto 0);
83 g : out std_logic_vector(3 downto 0);
84 b : out std_logic_vector(3 downto 0)
88 component v_address_decoder
89 generic (abus_size : integer := 14; dbus_size : integer := 8);
90 port ( clk : in std_logic;
94 vram_ad : inout std_logic_vector (7 downto 0);
95 vram_a : in std_logic_vector (13 downto 8)
100 port ( clk : in std_logic;
102 rst_n : in std_logic;
103 r_nw : inout std_logic;
104 cpu_addr : inout std_logic_vector (15 downto 0);
105 cpu_d : inout std_logic_vector (7 downto 0);
110 constant data_size : integer := 8;
111 constant addr_size : integer := 16;
112 constant size14 : integer := 14;
114 signal cpu_clk : std_logic;
115 signal ppu_clk : std_logic;
116 signal mem_clk : std_logic;
117 signal vga_out_clk : std_logic;
119 signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
120 signal phi1, phi2 : std_logic;
121 signal addr : std_logic_vector( addr_size - 1 downto 0);
122 signal d_io : std_logic_vector( data_size - 1 downto 0);
124 signal ppu_ce_n : std_logic;
125 signal apu_ce_n : std_logic;
126 signal rd_n : std_logic;
127 signal wr_n : std_logic;
128 signal ale : std_logic;
129 signal vram_ad : std_logic_vector (7 downto 0);
130 signal vram_a : std_logic_vector (13 downto 8);
133 signal nmi_n2 : std_logic;
138 vga_clk <= vga_out_clk;
140 --ppu/cpu clock generator
141 clock_inst : clock_divider port map
142 (base_clk, rst_n, cpu_clk, ppu_clk, mem_clk, vga_out_clk);
144 --mos 6502 cpu instance
145 cpu_inst : mos6502 generic map (data_size, addr_size)
146 port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw,
147 phi1, phi2, addr, d_io);
149 addr_dec_inst : address_decoder generic map (addr_size, data_size)
150 port map (phi2, mem_clk, r_nw, addr, d_io, ppu_ce_n, apu_ce_n);
154 port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io,
155 nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
156 vga_out_clk, h_sync_n, v_sync_n, r, g, b);
158 ppu_addr_decoder : v_address_decoder generic map (size14, data_size)
159 port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
162 port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);