2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
11 port ( rst_n : in std_logic
15 architecture rtl of motones_sim is
17 generic ( dsize : integer := 8;
20 port ( input_clk : in std_logic; --phi0 input pin.
29 addr : out std_logic_vector ( asize - 1 downto 0);
30 d_io : inout std_logic_vector ( dsize - 1 downto 0)
34 component clock_divider
35 port ( base_clk : in std_logic;
36 reset_n : in std_logic;
37 cpu_clk : out std_logic;
38 ppu_clk : out std_logic
42 component address_decoder
43 generic (abus_size : integer := 16; dbus_size : integer := 8);
44 port ( phi2 : in std_logic;
46 addr : in std_logic_vector (abus_size - 1 downto 0);
47 d_io : inout std_logic_vector (dbus_size - 1 downto 0);
48 ppu_ce_n : out std_logic
53 port ( clk : in std_logic;
57 cpu_addr : in std_logic_vector (2 downto 0);
58 cpu_d : inout std_logic_vector (7 downto 0);
59 vblank_n : out std_logic;
63 vram_ad : inout std_logic_vector (7 downto 0);
64 vram_a : out std_logic_vector (13 downto 8);
65 vga_clk : in std_logic;
66 h_sync_n : out std_logic;
67 v_sync_n : out std_logic;
68 r : out std_logic_vector(3 downto 0);
69 g : out std_logic_vector(3 downto 0);
70 b : out std_logic_vector(3 downto 0)
74 component v_address_decoder
75 generic (abus_size : integer := 14; dbus_size : integer := 8);
76 port ( clk : in std_logic;
80 vram_ad : inout std_logic_vector (7 downto 0);
81 vram_a : in std_logic_vector (13 downto 8)
86 port ( vga_clk : in std_logic;
88 h_sync_n : in std_logic;
89 v_sync_n : in std_logic;
90 r : in std_logic_vector(3 downto 0);
91 g : in std_logic_vector(3 downto 0);
92 b : in std_logic_vector(3 downto 0)
96 ---clock frequency = 21,477,270 (21 MHz)
97 constant base_clock_time : time := 46 ns;
98 constant data_size : integer := 8;
99 constant addr_size : integer := 16;
100 constant size14 : integer := 14;
102 signal base_clk : std_logic;
103 signal cpu_clk : std_logic;
104 signal ppu_clk : std_logic;
106 signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
107 signal phi1, phi2 : std_logic;
108 signal addr : std_logic_vector( addr_size - 1 downto 0);
109 signal d_io : std_logic_vector( data_size - 1 downto 0);
111 signal ppu_ce_n : std_logic;
112 signal rd_n : std_logic;
113 signal wr_n : std_logic;
114 signal ale : std_logic;
115 signal vram_ad : std_logic_vector (7 downto 0);
116 signal vram_a : std_logic_vector (13 downto 8);
118 signal vga_clk : std_logic;
119 signal h_sync_n : std_logic;
120 signal v_sync_n : std_logic;
121 signal r : std_logic_vector(3 downto 0);
122 signal g : std_logic_vector(3 downto 0);
123 signal b : std_logic_vector(3 downto 0);
130 --- generate base clock.
134 wait for base_clock_time / 2;
136 wait for base_clock_time / 2;
139 --ppu/cpu clock generator
140 clock_inst : clock_divider port map
141 (base_clk, rst_n, cpu_clk, ppu_clk);
143 --mos 6502 cpu instance
144 cpu_inst : mos6502 generic map (data_size, addr_size)
145 port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw,
146 phi1, phi2, addr, d_io);
148 addr_dec_inst : address_decoder generic map (addr_size, data_size)
149 port map (phi2, r_nw, addr, d_io, ppu_ce_n);
153 port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io,
154 nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
155 vga_clk, h_sync_n, v_sync_n, r, g, b);
157 ppu_addr_decoder : v_address_decoder generic map (size14, data_size)
158 port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
160 dummy_vga_disp : vga_device
161 port map (vga_clk, rst_n, h_sync_n, v_sync_n, r, g, b);