2 use ieee.std_logic_1164.all;
5 port ( clk : in std_logic;
9 cpu_addr : in std_logic_vector (2 downto 0);
10 cpu_d : inout std_logic_vector (7 downto 0);
11 vblank_n : out std_logic;
15 vram_ad : inout std_logic_vector (7 downto 0);
16 vram_a : out std_logic_vector (13 downto 8);
17 vga_clk : in std_logic;
18 h_sync_n : out std_logic;
19 v_sync_n : out std_logic;
20 r : out std_logic_vector(3 downto 0);
21 g : out std_logic_vector(3 downto 0);
22 b : out std_logic_vector(3 downto 0)
26 architecture rtl of ppu is
29 port ( clk : in std_logic;
34 vram_ad : inout std_logic_vector (7 downto 0);
35 vram_a : out std_logic_vector (13 downto 8);
36 pos_x : out std_logic_vector (8 downto 0);
37 pos_y : out std_logic_vector (8 downto 0);
38 r : out std_logic_vector (3 downto 0);
39 g : out std_logic_vector (3 downto 0);
40 b : out std_logic_vector (3 downto 0);
41 ppu_ctrl : in std_logic_vector (7 downto 0);
42 ppu_mask : in std_logic_vector (7 downto 0);
43 read_status : in std_logic;
44 ppu_status : out std_logic_vector (7 downto 0);
45 ppu_scroll_x : in std_logic_vector (7 downto 0);
46 ppu_scroll_y : in std_logic_vector (7 downto 0);
48 oam_bus_ce_n : in std_logic;
49 plt_bus_ce_n : in std_logic;
50 oam_plt_addr : in std_logic_vector (7 downto 0);
51 oam_plt_data : inout std_logic_vector (7 downto 0)
56 port ( ppu_clk : in std_logic;
57 vga_clk : in std_logic;
59 pos_x : in std_logic_vector (8 downto 0);
60 pos_y : in std_logic_vector (8 downto 0);
61 nes_r : in std_logic_vector (3 downto 0);
62 nes_g : in std_logic_vector (3 downto 0);
63 nes_b : in std_logic_vector (3 downto 0);
64 h_sync_n : out std_logic;
65 v_sync_n : out std_logic;
66 r : out std_logic_vector(3 downto 0);
67 g : out std_logic_vector(3 downto 0);
68 b : out std_logic_vector(3 downto 0)
81 d : in std_logic_vector (dsize - 1 downto 0);
82 q : out std_logic_vector (dsize - 1 downto 0)
86 component counter_register
91 port ( clk : in std_logic;
95 d : in std_logic_vector(dsize - 1 downto 0);
96 q : out std_logic_vector(dsize - 1 downto 0)
100 procedure d_print(msg : string) is
102 use ieee.std_logic_textio.all;
103 variable out_l : line;
106 writeline(output, out_l);
109 signal pos_x : std_logic_vector (8 downto 0);
110 signal pos_y : std_logic_vector (8 downto 0);
111 signal nes_r : std_logic_vector (3 downto 0);
112 signal nes_g : std_logic_vector (3 downto 0);
113 signal nes_b : std_logic_vector (3 downto 0);
115 constant dsize : integer := 8;
117 constant PPUCTRL : std_logic_vector(2 downto 0) := "000";
118 constant PPUMASK : std_logic_vector(2 downto 0) := "001";
119 constant PPUSTATUS : std_logic_vector(2 downto 0) := "010";
120 constant OAMADDR : std_logic_vector(2 downto 0) := "011";
121 constant OAMDATA : std_logic_vector(2 downto 0) := "100";
122 constant PPUSCROLL : std_logic_vector(2 downto 0) := "101";
123 constant PPUADDR : std_logic_vector(2 downto 0) := "110";
124 constant PPUDATA : std_logic_vector(2 downto 0) := "111";
126 constant PPUNEN : integer := 7; --nmi enable
127 constant ST_VBL : integer := 7; --vblank
129 signal clk_n : std_logic;
131 signal ppu_clk_cnt_res_n : std_logic;
132 signal ppu_clk_cnt : std_logic_vector(1 downto 0);
134 signal ppu_ctrl_we_n : std_logic;
135 signal ppu_mask_we_n : std_logic;
136 signal oam_addr_ce_n : std_logic;
137 signal oam_addr_we_n : std_logic;
138 signal oam_data_we_n : std_logic;
139 signal ppu_scroll_x_we_n : std_logic;
140 signal ppu_scroll_y_we_n : std_logic;
141 signal ppu_scroll_cnt_ce_n : std_logic;
142 signal ppu_addr_we_n : std_logic;
143 signal ppu_addr_cnt_ce_n : std_logic;
144 signal ppu_data_we_n : std_logic;
146 signal ppu_ctrl : std_logic_vector (dsize - 1 downto 0);
147 signal ppu_mask : std_logic_vector (dsize - 1 downto 0);
148 signal read_status : std_logic;
149 signal ppu_status : std_logic_vector (dsize - 1 downto 0);
150 signal ppu_stat_out : std_logic_vector (dsize - 1 downto 0);
151 signal oam_addr : std_logic_vector (dsize - 1 downto 0);
152 signal oam_data : std_logic_vector (dsize - 1 downto 0);
153 signal ppu_scroll_x : std_logic_vector (dsize - 1 downto 0);
154 signal ppu_scroll_y : std_logic_vector (dsize - 1 downto 0);
155 signal ppu_scroll_cnt : std_logic_vector (0 downto 0);
156 signal ppu_addr : std_logic_vector (13 downto 0);
157 signal ppu_addr_in : std_logic_vector (13 downto 0);
158 signal ppu_addr_cnt : std_logic_vector (0 downto 0);
159 signal ppu_data : std_logic_vector (dsize - 1 downto 0);
160 signal read_data : std_logic;
161 signal ppu_latch_rst_n : std_logic;
163 signal oam_bus_ce_n : std_logic;
164 signal plt_bus_ce_n : std_logic;
166 signal oam_plt_addr : std_logic_vector (7 downto 0);
167 signal oam_plt_data : std_logic_vector (7 downto 0);
171 render_inst : ppu_render port map (clk, rst_n,
172 rd_n, wr_n, ale, vram_ad, vram_a,
173 pos_x, pos_y, nes_r, nes_g, nes_b,
174 ppu_ctrl, ppu_mask, read_status, ppu_status, ppu_scroll_x, ppu_scroll_y,
175 r_nw, oam_bus_ce_n, plt_bus_ce_n,
176 oam_plt_addr, oam_plt_data);
178 vga_inst : vga_ctl port map (clk, vga_clk, rst_n,
179 pos_x, pos_y, nes_r, nes_g, nes_b,
180 h_sync_n, v_sync_n, r, g, b);
185 ppu_clk_cnt_inst : counter_register generic map (2, 1)
186 port map (clk_n, ppu_clk_cnt_res_n, '0', '1', (others => '0'), ppu_clk_cnt);
188 ppu_ctrl_inst : d_flip_flop generic map(dsize)
189 port map (clk_n, rst_n, '1', ppu_ctrl_we_n, cpu_d, ppu_ctrl);
191 ppu_mask_inst : d_flip_flop generic map(dsize)
192 port map (clk_n, rst_n, '1', ppu_mask_we_n, cpu_d, ppu_mask);
194 ppu_status_inst : d_flip_flop generic map(dsize)
195 port map (read_status, rst_n, '1', '0', ppu_status, ppu_stat_out);
197 oma_addr_inst : counter_register generic map(dsize, 1)
198 port map (clk_n, rst_n, oam_addr_ce_n, oam_addr_we_n, cpu_d, oam_addr);
199 oma_data_inst : d_flip_flop generic map(dsize)
200 port map (clk_n, rst_n, '1', oam_data_we_n, cpu_d, oam_data);
202 ppu_scroll_x_inst : d_flip_flop generic map(dsize)
203 port map (clk_n, rst_n, '1', ppu_scroll_x_we_n, cpu_d, ppu_scroll_x);
204 ppu_scroll_y_inst : d_flip_flop generic map(dsize)
205 port map (clk_n, rst_n, '1', ppu_scroll_y_we_n, cpu_d, ppu_scroll_y);
206 ppu_scroll_cnt_inst : counter_register generic map (1, 1)
207 port map (clk_n, ppu_latch_rst_n, ppu_scroll_cnt_ce_n,
208 '1', (others => '0'), ppu_scroll_cnt);
210 ppu_addr_inst : counter_register generic map(14, 1)
211 port map (clk_n, rst_n, ppu_data_we_n, ppu_addr_we_n, ppu_addr_in, ppu_addr);
212 ppu_addr_cnt_inst : counter_register generic map (1, 1)
213 port map (clk_n, ppu_latch_rst_n, ppu_addr_cnt_ce_n,
214 '1', (others => '0'), ppu_addr_cnt);
215 ppu_data_inst : d_flip_flop generic map(dsize)
216 port map (clk_n, rst_n, '1', ppu_data_we_n, cpu_d, ppu_data);
219 reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d,
220 ppu_status(ST_VBL), ppu_ctrl(PPUNEN))
222 if (rst_n = '0') then
223 ppu_latch_rst_n <= '0';
227 if (ppu_status(ST_VBL)'event or ppu_ctrl(PPUNEN)'event) then
228 if (ppu_status(ST_VBL) = '1' and ppu_ctrl(PPUNEN) = '1') then
237 if (rst_n = '1' and ce_n = '0') then
240 if(cpu_addr = PPUCTRL) then
241 ppu_ctrl_we_n <= '0';
243 ppu_ctrl_we_n <= '1';
246 if(cpu_addr = PPUMASK) then
247 ppu_mask_we_n <= '0';
249 ppu_mask_we_n <= '1';
252 if(cpu_addr = PPUSTATUS and r_nw = '1') then
253 --reading status resets ppu_addr/scroll cnt.
254 ppu_latch_rst_n <= '0';
255 --notify reading status
258 ppu_latch_rst_n <= '1';
262 if(cpu_addr = OAMADDR) then
263 oam_addr_we_n <= '0';
265 oam_addr_we_n <= '1';
268 if(cpu_addr = OAMDATA) then
269 oam_data_we_n <= '0';
271 oam_data_we_n <= '1';
274 if(cpu_addr = PPUSCROLL) then
275 ppu_scroll_cnt_ce_n <= '0';
276 if (ppu_scroll_cnt(0) = '0') then
277 ppu_scroll_x_we_n <= '0';
278 ppu_scroll_y_we_n <= '1';
280 ppu_scroll_y_we_n <= '0';
281 ppu_scroll_x_we_n <= '1';
284 ppu_scroll_x_we_n <= '1';
285 ppu_scroll_y_we_n <= '1';
286 ppu_scroll_cnt_ce_n <= '1';
289 if(cpu_addr = PPUADDR) then
290 ppu_addr_cnt_ce_n <= '0';
291 ppu_addr_we_n <= '0';
292 if (ppu_addr_cnt(0) = '0') then
293 ppu_addr_in <= cpu_d(5 downto 0) & ppu_addr(7 downto 0);
295 ppu_addr_in <= ppu_addr(13 downto 8) & cpu_d;
298 ppu_addr_cnt_ce_n <= '1';
299 ppu_addr_we_n <= '1';
302 ppu_ctrl_we_n <= '1';
303 ppu_mask_we_n <= '1';
304 oam_addr_we_n <= '1';
305 oam_data_we_n <= '1';
306 ppu_scroll_x_we_n <= '1';
307 ppu_scroll_y_we_n <= '1';
308 ppu_scroll_cnt_ce_n <= '1';
309 ppu_addr_we_n <= '1';
310 ppu_addr_cnt_ce_n <= '1';
314 end if; --if (rst_n = '1' and ce_n = '0')
318 --cpu and ppu clock timing adjustment...
319 clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d, clk,
320 oam_plt_data, vram_ad, ppu_stat_out)
322 if (rst_n = '1' and ce_n = '0') then
323 --set counter=0 on register write.
324 if (ce_n'event or r_nw'event or cpu_addr'event or (cpu_d'event and r_nw = '0')) then
325 ppu_clk_cnt_res_n <= '0';
326 --d_print("write event");
330 if (clk'event and clk = '0') then
331 if (ppu_clk_cnt = "10") then
332 ppu_clk_cnt_res_n <= '0';
333 elsif (ppu_clk_cnt = "00") then
334 ppu_clk_cnt_res_n <= '1';
336 --d_print("clk event");
340 if (cpu_addr = OAMDATA and ppu_clk_cnt = "00") then
342 oam_plt_addr <= oam_addr;
344 oam_plt_data <= (others => 'Z');
345 cpu_d <= oam_plt_data;
347 oam_plt_data <= cpu_d;
349 --address increment for burst write.
350 oam_addr_ce_n <= '0';
352 cpu_d <= (others => 'Z');
353 oam_addr_ce_n <= '1';
357 --vram address access.
358 if (cpu_addr = PPUADDR and ppu_clk_cnt = "00") then
359 if (ppu_addr_cnt(0) = '0') then
363 --load addr low and output vram/plt bus.
365 --if address is 3fxx, set palette table.
366 if (ppu_addr(13 downto 8) = "111111") then
367 oam_plt_addr <= cpu_d;
371 vram_a <= ppu_addr(13 downto 8);
375 elsif (cpu_addr = PPUDATA and ppu_clk_cnt = "01") then
377 if (ppu_addr(13 downto 8) = "111111") then
378 oam_plt_addr <= ppu_addr(7 downto 0);
381 vram_a <= ppu_addr(13 downto 8);
382 vram_ad <= ppu_addr(7 downto 0);
389 if (cpu_addr = PPUDATA and ppu_clk_cnt = "00") then
390 ppu_data_we_n <= '0';
391 if (ppu_addr(13 downto 8) = "111111") then
395 oam_plt_data <= cpu_d;
397 oam_plt_data <= (others => 'Z');
398 cpu_d <= oam_plt_data;
409 vram_ad <= (others => 'Z');
415 ppu_data_we_n <= '1';
420 --sustain cpu output data when reading.
421 if (cpu_addr = PPUDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
424 if (cpu_addr = OAMDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
428 if(cpu_addr = PPUSTATUS and r_nw = '1') then
429 cpu_d <= ppu_stat_out;
433 ppu_data_we_n <= '1';
435 ppu_clk_cnt_res_n <= '0';
437 oam_addr_ce_n <= '1';
442 oam_plt_data <= (others => 'Z');
443 vram_ad <= (others => 'Z');
444 vram_a <= (others => 'Z');
445 cpu_d <= (others => 'Z');