2 use ieee.std_logic_1164.all;
5 port ( clk : in std_logic;
9 cpu_addr : in std_logic_vector (2 downto 0);
10 cpu_d : inout std_logic_vector (7 downto 0);
11 vblank_n : out std_logic;
15 vram_ad : inout std_logic_vector (7 downto 0);
16 vram_a : out std_logic_vector (13 downto 8);
17 vga_clk : in std_logic;
18 h_sync_n : out std_logic;
19 v_sync_n : out std_logic;
20 r : out std_logic_vector(3 downto 0);
21 g : out std_logic_vector(3 downto 0);
22 b : out std_logic_vector(3 downto 0)
26 architecture rtl of ppu is
29 port ( clk : in std_logic;
31 vblank_n : out std_logic;
35 vram_ad : inout std_logic_vector (7 downto 0);
36 vram_a : out std_logic_vector (13 downto 8);
37 plt_bus_ce_n : in std_logic;
38 plt_r_nw : in std_logic;
39 plt_addr : in std_logic_vector (4 downto 0);
40 plt_data : inout std_logic_vector (7 downto 0);
41 pos_x : out std_logic_vector (8 downto 0);
42 pos_y : out std_logic_vector (8 downto 0);
43 r : out std_logic_vector (3 downto 0);
44 g : out std_logic_vector (3 downto 0);
45 b : out std_logic_vector (3 downto 0)
50 port ( vga_clk : in std_logic;
52 pos_x : in std_logic_vector (8 downto 0);
53 pos_y : in std_logic_vector (8 downto 0);
54 nes_r : in std_logic_vector (3 downto 0);
55 nes_g : in std_logic_vector (3 downto 0);
56 nes_b : in std_logic_vector (3 downto 0);
57 h_sync_n : out std_logic;
58 v_sync_n : out std_logic;
59 r : out std_logic_vector(3 downto 0);
60 g : out std_logic_vector(3 downto 0);
61 b : out std_logic_vector(3 downto 0)
65 signal pos_x : std_logic_vector (8 downto 0);
66 signal pos_y : std_logic_vector (8 downto 0);
67 signal nes_r : std_logic_vector (3 downto 0);
68 signal nes_g : std_logic_vector (3 downto 0);
69 signal nes_b : std_logic_vector (3 downto 0);
71 signal plt_bus_ce_n : std_logic;
72 signal plt_r_nw : std_logic;
73 signal plt_addr : std_logic_vector (4 downto 0);
74 signal plt_data : std_logic_vector (7 downto 0);
79 ---TODO: for the time being...
82 plt_addr <= (others => 'Z');
83 plt_data <= (others => 'Z');
85 render_inst : ppu_render port map (clk, rst_n, vblank_n,
86 rd_n, wr_n, ale, vram_ad, vram_a,
87 plt_bus_ce_n, plt_r_nw, plt_addr, plt_data,
88 pos_x, pos_y, nes_r, nes_g, nes_b);
90 vga_inst : vga_ctl port map (vga_clk, rst_n,
91 pos_x, pos_y, nes_r, nes_g, nes_b,
92 h_sync_n, v_sync_n, r, g, b);