2 use ieee.std_logic_1164.all;
5 port ( clk : in std_logic;
9 cpu_addr : in std_logic_vector (2 downto 0);
10 cpu_d : inout std_logic_vector (7 downto 0);
11 vblank_n : out std_logic;
15 vram_ad : inout std_logic_vector (7 downto 0);
16 vram_a : out std_logic_vector (13 downto 8)
20 architecture rtl of ppu is
24 port ( clk : in std_logic;
26 vblank_n : out std_logic;
30 vram_ad : inout std_logic_vector (7 downto 0);
31 vram_a : out std_logic_vector (13 downto 8)
37 render_inst : ppu_render port map (clk, rst_n, vblank_n,
38 rd_n, wr_n, ale, vram_ad, vram_a);