3 use IEEE.std_logic_1164.all;
4 --use ieee.std_logic_unsigned.all;
5 use ieee.std_logic_arith.all;
9 entity testbench_address_decoder is
10 end testbench_address_decoder;
12 architecture stimulus of testbench_address_decoder is
13 component address_decoder
14 generic (abus_size : integer := 16; dbus_size : integer := 8);
15 port ( phi2 : in std_logic;
17 addr : in std_logic_vector (abus_size - 1 downto 0);
18 d_io : inout std_logic_vector (dbus_size - 1 downto 0)
22 component v_address_decoder
23 generic (abus_size : integer := 14; dbus_size : integer := 8);
24 port ( clk : in std_logic;
28 vram_ad : inout std_logic_vector (7 downto 0);
29 vram_a : in std_logic_vector (13 downto 8)
42 d : in std_logic_vector (dsize - 1 downto 0);
43 q : out std_logic_vector (dsize - 1 downto 0)
47 constant cpu_clk : time := 589 ns;
48 constant size8 : integer := 8;
49 constant size16 : integer := 16;
50 constant size14 : integer := 14;
52 signal cclk : std_logic;
53 signal phi2 : std_logic;
54 signal rr_nw : std_logic;
55 signal aa16 : std_logic_vector (size16 - 1 downto 0);
56 signal dd8_io : std_logic_vector (size8 - 1 downto 0);
58 signal v_ad : std_logic_vector (size8 - 1 downto 0);
59 signal v_a : std_logic_vector (size14 - 1 downto size8);
60 signal v_addr : std_logic_vector (size14 - 1 downto 0);
61 signal v_data : std_logic_vector (size8 - 1 downto 0);
63 signal v_rd_n : std_logic;
64 signal v_wr_n : std_logic;
65 signal v_ale : std_logic;
67 signal v_dff_we_n : std_logic;
70 dut0 : address_decoder generic map (size16, size8)
71 port map (phi2, rr_nw, aa16, dd8_io);
76 variable i : integer := 0;
84 -----test for rom/ram .
86 variable i : integer := 0;
87 variable tmp : std_logic_vector (size8 - 1 downto 0);
88 constant loopcnt : integer := 5;
91 --syncronize with clock dropping edge.
94 dd8_io <= (others => 'Z');
96 for i in 0 to loopcnt loop
97 dd8_io <= conv_std_logic_vector(i, size8);
98 aa16 <= conv_std_logic_vector(i, size16);
101 dd8_io <= (others => 'Z');
119 --unknown addr at 0x4000
127 for i in 0 to loopcnt loop
129 aa16 <= conv_std_logic_vector(i, size16);
130 dd8_io <= conv_std_logic_vector(i, size8);
134 dd8_io <= (others => 'Z');
136 for i in 0 to loopcnt loop
138 aa16 <= conv_std_logic_vector(i, size16);
144 for i in 0 to loopcnt loop
146 aa16 <= conv_std_logic_vector(16#8000# + i, size16);
147 dd8_io <= conv_std_logic_vector(i * 10, size8);
149 aa16 <= conv_std_logic_vector(16#F000# + i, size16);
150 dd8_io <= conv_std_logic_vector(i * 10, size8);
155 dd8_io <= (others => 'Z');
156 for i in 0 to loopcnt loop
158 aa16 <= conv_std_logic_vector(16#8000# + i, size16);
160 aa16 <= conv_std_logic_vector(16#F000# + i, size16);
165 for i in 0 to loopcnt loop
167 aa16 <= conv_std_logic_vector(i, size16);
168 dd8_io <= conv_std_logic_vector(i ** 2, size8);
172 dd8_io <= "ZZZZZZZZ";
175 for i in 0 to loopcnt loop
177 aa16 <= conv_std_logic_vector(16#0000# + i, size16);
179 aa16 <= conv_std_logic_vector(16#0800# + i, size16);
181 aa16 <= conv_std_logic_vector(16#1000# + i, size16);
183 aa16 <= conv_std_logic_vector(16#1800# + i, size16);
185 aa16 <= conv_std_logic_vector(16#2000# + i, size16);
187 aa16 <= conv_std_logic_vector(16#4000# + i, size16);
189 aa16 <= conv_std_logic_vector(16#8000# + i, size16);
196 for i in 100 to 110 loop
198 aa16 <= conv_std_logic_vector(i, size16);
199 dd8_io <= conv_std_logic_vector(i, size8);
204 dd8_io <= "ZZZZZZZZ";
205 for i in 100 to 110 loop
207 aa16 <= conv_std_logic_vector(i, size16);
211 dd8_io <= "ZZZZZZZZ";
212 --read rom, ram, rom, ram ...
214 aa16 <= conv_std_logic_vector(100, size16);
216 aa16 <= conv_std_logic_vector(16#8010#, size16);
218 aa16 <= conv_std_logic_vector(103, size16);
220 aa16 <= conv_std_logic_vector(16#8013#, size16);
222 aa16 <= conv_std_logic_vector(109, size16);
224 aa16 <= conv_std_logic_vector(16#f0a3#, size16);
228 aa16 <= conv_std_logic_vector(100, size16);
229 dd8_io <= conv_std_logic_vector(100, size8);
232 dd8_io <= "ZZZZZZZZ";
236 aa16 <= conv_std_logic_vector(101, size16);
237 dd8_io <= conv_std_logic_vector(200, size8);
240 dd8_io <= "ZZZZZZZZ";
244 aa16 <= conv_std_logic_vector(401, size16); -- 401 = 0x191
245 dd8_io <= conv_std_logic_vector(30, size8);
249 dd8_io <= "ZZZZZZZZ";
252 --copy rom > ram > rom > ram
253 aa16 <= conv_std_logic_vector(16#f024#, size16);
256 aa16 <= conv_std_logic_vector(500, size16); -- 500 = 0x1f4
262 dd8_io <= "ZZZZZZZZ";
263 aa16 <= conv_std_logic_vector(16#8003#, size16);
266 aa16 <= conv_std_logic_vector(501, size16);
271 aa16 <= conv_std_logic_vector(16#8005#, size16);
272 dd8_io <= "ZZZZZZZZ";
275 aa16 <= conv_std_logic_vector(502, size16);
280 --read the written value
282 dd8_io <= "ZZZZZZZZ";
283 aa16 <= conv_std_logic_vector(500, size16);
286 aa16 <= conv_std_logic_vector(501, size16);
289 aa16 <= conv_std_logic_vector(502, size16);
293 for i in 0 to 50 loop
294 dd8_io <= "ZZZZZZZZ";
295 aa16 <= conv_std_logic_vector(16#8000# + i, size16);
298 aa16 <= conv_std_logic_vector(1024 + i, size16);
304 dd8_io <= "ZZZZZZZZ";
306 for i in 0 to 50 loop
307 aa16 <= conv_std_logic_vector(1024 + i, size16);
312 --fill the value in the empty address.
313 for i in 6 to 50 loop
314 aa16 <= conv_std_logic_vector(i, size16);
315 dd8_io <= conv_std_logic_vector(i**2, size8);
321 for i in 0 to 50 loop
322 dd8_io <= "ZZZZZZZZ";
323 aa16 <= conv_std_logic_vector(i, size16);
326 aa16 <= conv_std_logic_vector(2000 + i, size16);
332 dd8_io <= "ZZZZZZZZ";
334 for i in 0 to 50 loop
335 aa16 <= conv_std_logic_vector(2000 + i, size16);
342 v_ad <= v_addr(size8 - 1 downto 0);
343 v_a <= v_addr(size14 - 1 downto size8);
345 dut1 : v_address_decoder generic map (size14, size8)
346 port map (phi2, v_rd_n, v_wr_n, v_ale, v_ad, v_a);
348 dff : d_flip_flop generic map (size8)
349 port map (cclk, '1', '1', v_dff_we_n, v_ad, v_data);
351 -----test for vram/chr-rom
353 variable i : integer := 0;
354 variable tmp : std_logic_vector (size8 - 1 downto 0);
355 constant loopcnt : integer := 5;
358 --syncronize with clock dropping edge.
359 wait for cpu_clk / 2;
362 --copy from chr rom to name tbl.
363 for i in 0 to loopcnt loop
369 v_addr <= conv_std_logic_vector(16#0000# + i, size14);
372 v_addr(7 downto 0) <= (others => 'Z');
383 v_addr <= conv_std_logic_vector(16#2000# + i, size14);
385 v_addr(7 downto 0) <= (others => 'Z');
389 v_addr(7 downto 0) <= v_data;
395 for i in 0 to loopcnt loop
396 v_addr <= conv_std_logic_vector(16#2000# + i, size14);
400 v_addr(7 downto 0) <= (others => 'Z');
406 v_addr <= conv_std_logic_vector(16#2400# + i, size14);
410 v_addr(7 downto 0) <= (others => 'Z');
415 v_addr <= conv_std_logic_vector(16#2800# + i, size14);
419 v_addr(7 downto 0) <= (others => 'Z');
425 --copy from chr rom to plt tbl.
426 for i in 10 to loopcnt + 10 loop
432 v_addr <= conv_std_logic_vector(16#0000# + i, size14);
435 v_addr(7 downto 0) <= (others => 'Z');
446 v_addr <= conv_std_logic_vector(16#3f00# + i, size14);
448 v_addr(7 downto 0) <= (others => 'Z');
452 v_addr(7 downto 0) <= v_data;
458 for i in 10 to loopcnt + 10 loop
459 v_addr <= conv_std_logic_vector(16#3f00# + i, size14);
463 v_addr(7 downto 0) <= (others => 'Z');
469 v_addr <= conv_std_logic_vector(16#3ff0# + i, size14);
473 v_addr(7 downto 0) <= (others => 'Z');
480 ----all data, selctor check.
482 for i in 0 to 16#4000# - 1 loop
486 v_addr <= conv_std_logic_vector(16#0000# + i, size14);
490 v_addr(size8 - 1 downto 0) <= (others => 'Z');