sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39
  40 #ifdef CONFIG_X86
  41 /* for snoop control */
  42 #include <asm/pgtable.h>
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1); "
 166                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 167
 168 #ifdef CONFIG_PM
 169 static int param_set_xint(const char *val, const struct kernel_param *kp);
 170 static const struct kernel_param_ops param_ops_xint = {
 171         .set = param_set_xint,
 172         .get = param_get_int,
 173 };
 174 #define param_check_xint param_check_int
 175
 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 177 module_param(power_save, xint, 0644);
 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 179                  "(in second, 0 = disable).");
 180
 181 static bool pm_blacklist = true;
 182 module_param(pm_blacklist, bool, 0644);
 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 212                          "{Intel, ICH6M},"
 213                          "{Intel, ICH7},"
 214                          "{Intel, ESB2},"
 215                          "{Intel, ICH8},"
 216                          "{Intel, ICH9},"
 217                          "{Intel, ICH10},"
 218                          "{Intel, PCH},"
 219                          "{Intel, CPT},"
 220                          "{Intel, PPT},"
 221                          "{Intel, LPT},"
 222                          "{Intel, LPT_LP},"
 223                          "{Intel, WPT_LP},"
 224                          "{Intel, SPT},"
 225                          "{Intel, SPT_LP},"
 226                          "{Intel, HPT},"
 227                          "{Intel, PBG},"
 228                          "{Intel, SCH},"
 229                          "{ATI, SB450},"
 230                          "{ATI, SB600},"
 231                          "{ATI, RS600},"
 232                          "{ATI, RS690},"
 233                          "{ATI, RS780},"
 234                          "{ATI, R600},"
 235                          "{ATI, RV630},"
 236                          "{ATI, RV610},"
 237                          "{ATI, RV670},"
 238                          "{ATI, RV635},"
 239                          "{ATI, RV620},"
 240                          "{ATI, RV770},"
 241                          "{VIA, VT8251},"
 242                          "{VIA, VT8237A},"
 243                          "{SiS, SIS966},"
 244                          "{ULI, M5461}}");
 245 MODULE_DESCRIPTION("Intel HDA driver");
 246
 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 249 #define SUPPORT_VGA_SWITCHEROO
 250 #endif
 251 #endif
 252
 253
 254 /*
 255  */
 256
 257 /* driver types */
 258 enum {
 259         AZX_DRIVER_ICH,
 260         AZX_DRIVER_PCH,
 261         AZX_DRIVER_SCH,
 262         AZX_DRIVER_SKL,
 263         AZX_DRIVER_HDMI,
 264         AZX_DRIVER_ATI,
 265         AZX_DRIVER_ATIHDMI,
 266         AZX_DRIVER_ATIHDMI_NS,
 267         AZX_DRIVER_VIA,
 268         AZX_DRIVER_SIS,
 269         AZX_DRIVER_ULI,
 270         AZX_DRIVER_NVIDIA,
 271         AZX_DRIVER_TERA,
 272         AZX_DRIVER_CTX,
 273         AZX_DRIVER_CTHDA,
 274         AZX_DRIVER_CMEDIA,
 275         AZX_DRIVER_ZHAOXIN,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
 287          AZX_DCAPS_SYNC_WRITE)
 288
 289 /* quirks for Intel PCH */
 290 #define AZX_DCAPS_INTEL_PCH_BASE \
 291         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 292          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 293
 294 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 295 #define AZX_DCAPS_INTEL_PCH_NOPM \
 296         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 297
 298 /* PCH for HSW/BDW; with runtime PM */
 299 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 300 #define AZX_DCAPS_INTEL_PCH \
 301         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 302
 303 /* HSW HDMI */
 304 #define AZX_DCAPS_INTEL_HASWELL \
 305         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 306          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 307          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 308
 309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 310 #define AZX_DCAPS_INTEL_BROADWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 314
 315 #define AZX_DCAPS_INTEL_BAYTRAIL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 317
 318 #define AZX_DCAPS_INTEL_BRASWELL \
 319         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 320          AZX_DCAPS_I915_COMPONENT)
 321
 322 #define AZX_DCAPS_INTEL_SKYLAKE \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 324          AZX_DCAPS_SYNC_WRITE |\
 325          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 326
 327 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 328
 329 /* quirks for ATI SB / AMD Hudson */
 330 #define AZX_DCAPS_PRESET_ATI_SB \
 331         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 332          AZX_DCAPS_SNOOP_TYPE(ATI))
 333
 334 /* quirks for ATI/AMD HDMI */
 335 #define AZX_DCAPS_PRESET_ATI_HDMI \
 336         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 337          AZX_DCAPS_NO_MSI64)
 338
 339 /* quirks for ATI HDMI with snoop off */
 340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 341         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 342
 343 /* quirks for AMD SB */
 344 #define AZX_DCAPS_PRESET_AMD_SB \
 345         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 346          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 347
 348 /* quirks for Nvidia */
 349 #define AZX_DCAPS_PRESET_NVIDIA \
 350         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 351          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 352
 353 #define AZX_DCAPS_PRESET_CTHDA \
 354         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 355          AZX_DCAPS_NO_64BIT |\
 356          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 357
 358 /*
 359  * vga_switcheroo support
 360  */
 361 #ifdef SUPPORT_VGA_SWITCHEROO
 362 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 363 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 364 #else
 365 #define use_vga_switcheroo(chip)        0
 366 #define needs_eld_notify_link(chip)     false
 367 #endif
 368
 369 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 370                                         ((pci)->device == 0x0c0c) || \
 371                                         ((pci)->device == 0x0d0c) || \
 372                                         ((pci)->device == 0x160c))
 373
 374 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 375
 376 static const char * const driver_short_names[] = {
 377         [AZX_DRIVER_ICH] = "HDA Intel",
 378         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 379         [AZX_DRIVER_SCH] = "HDA Intel MID",
 380         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 381         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 382         [AZX_DRIVER_ATI] = "HDA ATI SB",
 383         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 384         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 385         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 386         [AZX_DRIVER_SIS] = "HDA SIS966",
 387         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 388         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 389         [AZX_DRIVER_TERA] = "HDA Teradici",
 390         [AZX_DRIVER_CTX] = "HDA Creative",
 391         [AZX_DRIVER_CTHDA] = "HDA Creative",
 392         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 393         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 394         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 395 };
 396
 397 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 398 static void set_default_power_save(struct azx *chip);
 399
 400 /*
 401  * initialize the PCI registers
 402  */
 403 /* update bits in a PCI register byte */
 404 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 405                             unsigned char mask, unsigned char val)
 406 {
 407         unsigned char data;
 408
 409         pci_read_config_byte(pci, reg, &data);
 410         data &= ~mask;
 411         data |= (val & mask);
 412         pci_write_config_byte(pci, reg, data);
 413 }
 414
 415 static void azx_init_pci(struct azx *chip)
 416 {
 417         int snoop_type = azx_get_snoop_type(chip);
 418
 419         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 420          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 421          * Ensuring these bits are 0 clears playback static on some HD Audio
 422          * codecs.
 423          * The PCI register TCSEL is defined in the Intel manuals.
 424          */
 425         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 426                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 427                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 428         }
 429
 430         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 431          * we need to enable snoop.
 432          */
 433         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 434                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 435                         azx_snoop(chip));
 436                 update_pci_byte(chip->pci,
 437                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 438                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 439         }
 440
 441         /* For NVIDIA HDA, enable snoop */
 442         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 443                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 444                         azx_snoop(chip));
 445                 update_pci_byte(chip->pci,
 446                                 NVIDIA_HDA_TRANSREG_ADDR,
 447                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 448                 update_pci_byte(chip->pci,
 449                                 NVIDIA_HDA_ISTRM_COH,
 450                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 451                 update_pci_byte(chip->pci,
 452                                 NVIDIA_HDA_OSTRM_COH,
 453                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 454         }
 455
 456         /* Enable SCH/PCH snoop if needed */
 457         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 458                 unsigned short snoop;
 459                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 460                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 461                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 462                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 463                         if (!azx_snoop(chip))
 464                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 465                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 466                         pci_read_config_word(chip->pci,
 467                                 INTEL_SCH_HDA_DEVC, &snoop);
 468                 }
 469                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 470                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 471                         "Disabled" : "Enabled");
 472         }
 473 }
 474
 475 /*
 476  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 477  * and makes an audio stream sensitive to system latencies when
 478  * 24/32 bits are playing.
 479  * Adjusting threshold of DMA fifo to force the DMA request
 480  * sooner to improve latency tolerance at the expense of power.
 481  */
 482 static void bxt_reduce_dma_latency(struct azx *chip)
 483 {
 484         u32 val;
 485
 486         val = azx_readl(chip, VS_EM4L);
 487         val &= (0x3 << 20);
 488         azx_writel(chip, VS_EM4L, val);
 489 }
 490
 491 /*
 492  * ML_LCAP bits:
 493  *  bit 0: 6 MHz Supported
 494  *  bit 1: 12 MHz Supported
 495  *  bit 2: 24 MHz Supported
 496  *  bit 3: 48 MHz Supported
 497  *  bit 4: 96 MHz Supported
 498  *  bit 5: 192 MHz Supported
 499  */
 500 static int intel_get_lctl_scf(struct azx *chip)
 501 {
 502         struct hdac_bus *bus = azx_bus(chip);
 503         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 504         u32 val, t;
 505         int i;
 506
 507         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 508
 509         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 510                 t = preferred_bits[i];
 511                 if (val & (1 << t))
 512                         return t;
 513         }
 514
 515         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 516         return 0;
 517 }
 518
 519 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 520 {
 521         struct hdac_bus *bus = azx_bus(chip);
 522         u32 val;
 523         int timeout;
 524
 525         /*
 526          * the codecs are sharing the first link setting by default
 527          * If other links are enabled for stream, they need similar fix
 528          */
 529         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 530         val &= ~AZX_MLCTL_SPA;
 531         val |= state << AZX_MLCTL_SPA_SHIFT;
 532         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 533         /* wait for CPA */
 534         timeout = 50;
 535         while (timeout) {
 536                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 537                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 538                         return 0;
 539                 timeout--;
 540                 udelay(10);
 541         }
 542
 543         return -1;
 544 }
 545
 546 static void intel_init_lctl(struct azx *chip)
 547 {
 548         struct hdac_bus *bus = azx_bus(chip);
 549         u32 val;
 550         int ret;
 551
 552         /* 0. check lctl register value is correct or not */
 553         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 554         /* if SCF is already set, let's use it */
 555         if ((val & ML_LCTL_SCF_MASK) != 0)
 556                 return;
 557
 558         /*
 559          * Before operating on SPA, CPA must match SPA.
 560          * Any deviation may result in undefined behavior.
 561          */
 562         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 563                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 564                 return;
 565
 566         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 567         ret = intel_ml_lctl_set_power(chip, 0);
 568         udelay(100);
 569         if (ret)
 570                 goto set_spa;
 571
 572         /* 2. update SCF to select a properly audio clock*/
 573         val &= ~ML_LCTL_SCF_MASK;
 574         val |= intel_get_lctl_scf(chip);
 575         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 576
 577 set_spa:
 578         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 579         intel_ml_lctl_set_power(chip, 1);
 580         udelay(100);
 581 }
 582
 583 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 584 {
 585         struct hdac_bus *bus = azx_bus(chip);
 586         struct pci_dev *pci = chip->pci;
 587         u32 val;
 588
 589         snd_hdac_set_codec_wakeup(bus, true);
 590         if (chip->driver_type == AZX_DRIVER_SKL) {
 591                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 592                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 593                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 594         }
 595         azx_init_chip(chip, full_reset);
 596         if (chip->driver_type == AZX_DRIVER_SKL) {
 597                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 598                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 599                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 600         }
 601
 602         snd_hdac_set_codec_wakeup(bus, false);
 603
 604         /* reduce dma latency to avoid noise */
 605         if (IS_BXT(pci))
 606                 bxt_reduce_dma_latency(chip);
 607
 608         if (bus->mlcap != NULL)
 609                 intel_init_lctl(chip);
 610 }
 611
 612 /* calculate runtime delay from LPIB */
 613 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 614                                    unsigned int pos)
 615 {
 616         struct snd_pcm_substream *substream = azx_dev->core.substream;
 617         int stream = substream->stream;
 618         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 619         int delay;
 620
 621         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 622                 delay = pos - lpib_pos;
 623         else
 624                 delay = lpib_pos - pos;
 625         if (delay < 0) {
 626                 if (delay >= azx_dev->core.delay_negative_threshold)
 627                         delay = 0;
 628                 else
 629                         delay += azx_dev->core.bufsize;
 630         }
 631
 632         if (delay >= azx_dev->core.period_bytes) {
 633                 dev_info(chip->card->dev,
 634                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 635                          delay, azx_dev->core.period_bytes);
 636                 delay = 0;
 637                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 638                 chip->get_delay[stream] = NULL;
 639         }
 640
 641         return bytes_to_frames(substream->runtime, delay);
 642 }
 643
 644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 645
 646 /* called from IRQ */
 647 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 648 {
 649         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 650         int ok;
 651
 652         ok = azx_position_ok(chip, azx_dev);
 653         if (ok == 1) {
 654                 azx_dev->irq_pending = 0;
 655                 return ok;
 656         } else if (ok == 0) {
 657                 /* bogus IRQ, process it later */
 658                 azx_dev->irq_pending = 1;
 659                 schedule_work(&hda->irq_pending_work);
 660         }
 661         return 0;
 662 }
 663
 664 #define display_power(chip, enable) \
 665         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 666
 667 /*
 668  * Check whether the current DMA position is acceptable for updating
 669  * periods.  Returns non-zero if it's OK.
 670  *
 671  * Many HD-audio controllers appear pretty inaccurate about
 672  * the update-IRQ timing.  The IRQ is issued before actually the
 673  * data is processed.  So, we need to process it afterwords in a
 674  * workqueue.
 675  */
 676 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 677 {
 678         struct snd_pcm_substream *substream = azx_dev->core.substream;
 679         int stream = substream->stream;
 680         u32 wallclk;
 681         unsigned int pos;
 682
 683         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 684         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 685                 return -1;      /* bogus (too early) interrupt */
 686
 687         if (chip->get_position[stream])
 688                 pos = chip->get_position[stream](chip, azx_dev);
 689         else { /* use the position buffer as default */
 690                 pos = azx_get_pos_posbuf(chip, azx_dev);
 691                 if (!pos || pos == (u32)-1) {
 692                         dev_info(chip->card->dev,
 693                                  "Invalid position buffer, using LPIB read method instead.\n");
 694                         chip->get_position[stream] = azx_get_pos_lpib;
 695                         if (chip->get_position[0] == azx_get_pos_lpib &&
 696                             chip->get_position[1] == azx_get_pos_lpib)
 697                                 azx_bus(chip)->use_posbuf = false;
 698                         pos = azx_get_pos_lpib(chip, azx_dev);
 699                         chip->get_delay[stream] = NULL;
 700                 } else {
 701                         chip->get_position[stream] = azx_get_pos_posbuf;
 702                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 703                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 704                 }
 705         }
 706
 707         if (pos >= azx_dev->core.bufsize)
 708                 pos = 0;
 709
 710         if (WARN_ONCE(!azx_dev->core.period_bytes,
 711                       "hda-intel: zero azx_dev->period_bytes"))
 712                 return -1; /* this shouldn't happen! */
 713         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 714             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 715                 /* NG - it's below the first next period boundary */
 716                 return chip->bdl_pos_adj ? 0 : -1;
 717         azx_dev->core.start_wallclk += wallclk;
 718         return 1; /* OK, it's fine */
 719 }
 720
 721 /*
 722  * The work for pending PCM period updates.
 723  */
 724 static void azx_irq_pending_work(struct work_struct *work)
 725 {
 726         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 727         struct azx *chip = &hda->chip;
 728         struct hdac_bus *bus = azx_bus(chip);
 729         struct hdac_stream *s;
 730         int pending, ok;
 731
 732         if (!hda->irq_pending_warned) {
 733                 dev_info(chip->card->dev,
 734                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 735                          chip->card->number);
 736                 hda->irq_pending_warned = 1;
 737         }
 738
 739         for (;;) {
 740                 pending = 0;
 741                 spin_lock_irq(&bus->reg_lock);
 742                 list_for_each_entry(s, &bus->stream_list, list) {
 743                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 744                         if (!azx_dev->irq_pending ||
 745                             !s->substream ||
 746                             !s->running)
 747                                 continue;
 748                         ok = azx_position_ok(chip, azx_dev);
 749                         if (ok > 0) {
 750                                 azx_dev->irq_pending = 0;
 751                                 spin_unlock(&bus->reg_lock);
 752                                 snd_pcm_period_elapsed(s->substream);
 753                                 spin_lock(&bus->reg_lock);
 754                         } else if (ok < 0) {
 755                                 pending = 0;    /* too early */
 756                         } else
 757                                 pending++;
 758                 }
 759                 spin_unlock_irq(&bus->reg_lock);
 760                 if (!pending)
 761                         return;
 762                 msleep(1);
 763         }
 764 }
 765
 766 /* clear irq_pending flags and assure no on-going workq */
 767 static void azx_clear_irq_pending(struct azx *chip)
 768 {
 769         struct hdac_bus *bus = azx_bus(chip);
 770         struct hdac_stream *s;
 771
 772         spin_lock_irq(&bus->reg_lock);
 773         list_for_each_entry(s, &bus->stream_list, list) {
 774                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 775                 azx_dev->irq_pending = 0;
 776         }
 777         spin_unlock_irq(&bus->reg_lock);
 778 }
 779
 780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 781 {
 782         struct hdac_bus *bus = azx_bus(chip);
 783
 784         if (request_irq(chip->pci->irq, azx_interrupt,
 785                         chip->msi ? 0 : IRQF_SHARED,
 786                         chip->card->irq_descr, chip)) {
 787                 dev_err(chip->card->dev,
 788                         "unable to grab IRQ %d, disabling device\n",
 789                         chip->pci->irq);
 790                 if (do_disconnect)
 791                         snd_card_disconnect(chip->card);
 792                 return -1;
 793         }
 794         bus->irq = chip->pci->irq;
 795         chip->card->sync_irq = bus->irq;
 796         pci_intx(chip->pci, !chip->msi);
 797         return 0;
 798 }
 799
 800 /* get the current DMA position with correction on VIA chips */
 801 static unsigned int azx_via_get_position(struct azx *chip,
 802                                          struct azx_dev *azx_dev)
 803 {
 804         unsigned int link_pos, mini_pos, bound_pos;
 805         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 806         unsigned int fifo_size;
 807
 808         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 809         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 810                 /* Playback, no problem using link position */
 811                 return link_pos;
 812         }
 813
 814         /* Capture */
 815         /* For new chipset,
 816          * use mod to get the DMA position just like old chipset
 817          */
 818         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 819         mod_dma_pos %= azx_dev->core.period_bytes;
 820
 821         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 822
 823         if (azx_dev->insufficient) {
 824                 /* Link position never gather than FIFO size */
 825                 if (link_pos <= fifo_size)
 826                         return 0;
 827
 828                 azx_dev->insufficient = 0;
 829         }
 830
 831         if (link_pos <= fifo_size)
 832                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 833         else
 834                 mini_pos = link_pos - fifo_size;
 835
 836         /* Find nearest previous boudary */
 837         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 838         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 839         if (mod_link_pos >= fifo_size)
 840                 bound_pos = link_pos - mod_link_pos;
 841         else if (mod_dma_pos >= mod_mini_pos)
 842                 bound_pos = mini_pos - mod_mini_pos;
 843         else {
 844                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 845                 if (bound_pos >= azx_dev->core.bufsize)
 846                         bound_pos = 0;
 847         }
 848
 849         /* Calculate real DMA position we want */
 850         return bound_pos + mod_dma_pos;
 851 }
 852
 853 #define AMD_FIFO_SIZE   32
 854
 855 /* get the current DMA position with FIFO size correction */
 856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 857 {
 858         struct snd_pcm_substream *substream = azx_dev->core.substream;
 859         struct snd_pcm_runtime *runtime = substream->runtime;
 860         unsigned int pos, delay;
 861
 862         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 863         if (!runtime)
 864                 return pos;
 865
 866         runtime->delay = AMD_FIFO_SIZE;
 867         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 868         if (azx_dev->insufficient) {
 869                 if (pos < delay) {
 870                         delay = pos;
 871                         runtime->delay = bytes_to_frames(runtime, pos);
 872                 } else {
 873                         azx_dev->insufficient = 0;
 874                 }
 875         }
 876
 877         /* correct the DMA position for capture stream */
 878         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 879                 if (pos < delay)
 880                         pos += azx_dev->core.bufsize;
 881                 pos -= delay;
 882         }
 883
 884         return pos;
 885 }
 886
 887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 888                                    unsigned int pos)
 889 {
 890         struct snd_pcm_substream *substream = azx_dev->core.substream;
 891
 892         /* just read back the calculated value in the above */
 893         return substream->runtime->delay;
 894 }
 895
 896 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 897                                          struct azx_dev *azx_dev)
 898 {
 899         return _snd_hdac_chip_readl(azx_bus(chip),
 900                                     AZX_REG_VS_SDXDPIB_XBASE +
 901                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 902                                      azx_dev->core.index));
 903 }
 904
 905 /* get the current DMA position with correction on SKL+ chips */
 906 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 907 {
 908         /* DPIB register gives a more accurate position for playback */
 909         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 910                 return azx_skl_get_dpib_pos(chip, azx_dev);
 911
 912         /* For capture, we need to read posbuf, but it requires a delay
 913          * for the possible boundary overlap; the read of DPIB fetches the
 914          * actual posbuf
 915          */
 916         udelay(20);
 917         azx_skl_get_dpib_pos(chip, azx_dev);
 918         return azx_get_pos_posbuf(chip, azx_dev);
 919 }
 920
 921 #ifdef CONFIG_PM
 922 static DEFINE_MUTEX(card_list_lock);
 923 static LIST_HEAD(card_list);
 924
 925 static void azx_add_card_list(struct azx *chip)
 926 {
 927         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 928         mutex_lock(&card_list_lock);
 929         list_add(&hda->list, &card_list);
 930         mutex_unlock(&card_list_lock);
 931 }
 932
 933 static void azx_del_card_list(struct azx *chip)
 934 {
 935         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 936         mutex_lock(&card_list_lock);
 937         list_del_init(&hda->list);
 938         mutex_unlock(&card_list_lock);
 939 }
 940
 941 /* trigger power-save check at writing parameter */
 942 static int param_set_xint(const char *val, const struct kernel_param *kp)
 943 {
 944         struct hda_intel *hda;
 945         struct azx *chip;
 946         int prev = power_save;
 947         int ret = param_set_int(val, kp);
 948
 949         if (ret || prev == power_save)
 950                 return ret;
 951
 952         mutex_lock(&card_list_lock);
 953         list_for_each_entry(hda, &card_list, list) {
 954                 chip = &hda->chip;
 955                 if (!hda->probe_continued || chip->disabled)
 956                         continue;
 957                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 958         }
 959         mutex_unlock(&card_list_lock);
 960         return 0;
 961 }
 962
 963 /*
 964  * power management
 965  */
 966 static bool azx_is_pm_ready(struct snd_card *card)
 967 {
 968         struct azx *chip;
 969         struct hda_intel *hda;
 970
 971         if (!card)
 972                 return false;
 973         chip = card->private_data;
 974         hda = container_of(chip, struct hda_intel, chip);
 975         if (chip->disabled || hda->init_failed || !chip->running)
 976                 return false;
 977         return true;
 978 }
 979
 980 static void __azx_runtime_suspend(struct azx *chip)
 981 {
 982         azx_stop_chip(chip);
 983         azx_enter_link_reset(chip);
 984         azx_clear_irq_pending(chip);
 985         display_power(chip, false);
 986 }
 987
 988 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 989 {
 990         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 991         struct hdac_bus *bus = azx_bus(chip);
 992         struct hda_codec *codec;
 993         int status;
 994
 995         display_power(chip, true);
 996         if (hda->need_i915_power)
 997                 snd_hdac_i915_set_bclk(bus);
 998
 999         /* Read STATESTS before controller reset */
1000         status = azx_readw(chip, STATESTS);
1001
1002         azx_init_pci(chip);
1003         hda_intel_init_chip(chip, true);
1004
1005         if (status && from_rt) {
1006                 list_for_each_codec(codec, &chip->bus)
1007                         if (status & (1 << codec->addr))
1008                                 schedule_delayed_work(&codec->jackpoll_work,
1009                                                       codec->jackpoll_interval);
1010         }
1011
1012         /* power down again for link-controlled chips */
1013         if (!hda->need_i915_power)
1014                 display_power(chip, false);
1015 }
1016
1017 #ifdef CONFIG_PM_SLEEP
1018 static int azx_suspend(struct device *dev)
1019 {
1020         struct snd_card *card = dev_get_drvdata(dev);
1021         struct azx *chip;
1022         struct hdac_bus *bus;
1023
1024         if (!azx_is_pm_ready(card))
1025                 return 0;
1026
1027         chip = card->private_data;
1028         bus = azx_bus(chip);
1029         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1030         pm_runtime_force_suspend(dev);
1031         if (bus->irq >= 0) {
1032                 free_irq(bus->irq, chip);
1033                 bus->irq = -1;
1034                 chip->card->sync_irq = -1;
1035         }
1036
1037         if (chip->msi)
1038                 pci_disable_msi(chip->pci);
1039
1040         trace_azx_suspend(chip);
1041         return 0;
1042 }
1043
1044 static int azx_resume(struct device *dev)
1045 {
1046         struct snd_card *card = dev_get_drvdata(dev);
1047         struct hda_codec *codec;
1048         struct azx *chip;
1049         bool forced_resume = false;
1050
1051         if (!azx_is_pm_ready(card))
1052                 return 0;
1053
1054         chip = card->private_data;
1055         if (chip->msi)
1056                 if (pci_enable_msi(chip->pci) < 0)
1057                         chip->msi = 0;
1058         if (azx_acquire_irq(chip, 1) < 0)
1059                 return -EIO;
1060
1061         /* check for the forced resume */
1062         list_for_each_codec(codec, &chip->bus) {
1063                 if (hda_codec_need_resume(codec)) {
1064                         forced_resume = true;
1065                         break;
1066                 }
1067         }
1068
1069         if (forced_resume)
1070                 pm_runtime_get_noresume(dev);
1071         pm_runtime_force_resume(dev);
1072         if (forced_resume)
1073                 pm_runtime_put(dev);
1074         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1075
1076         trace_azx_resume(chip);
1077         return 0;
1078 }
1079
1080 /* put codec down to D3 at hibernation for Intel SKL+;
1081  * otherwise BIOS may still access the codec and screw up the driver
1082  */
1083 static int azx_freeze_noirq(struct device *dev)
1084 {
1085         struct snd_card *card = dev_get_drvdata(dev);
1086         struct azx *chip = card->private_data;
1087         struct pci_dev *pci = to_pci_dev(dev);
1088
1089         if (!azx_is_pm_ready(card))
1090                 return 0;
1091         if (chip->driver_type == AZX_DRIVER_SKL)
1092                 pci_set_power_state(pci, PCI_D3hot);
1093
1094         return 0;
1095 }
1096
1097 static int azx_thaw_noirq(struct device *dev)
1098 {
1099         struct snd_card *card = dev_get_drvdata(dev);
1100         struct azx *chip = card->private_data;
1101         struct pci_dev *pci = to_pci_dev(dev);
1102
1103         if (!azx_is_pm_ready(card))
1104                 return 0;
1105         if (chip->driver_type == AZX_DRIVER_SKL)
1106                 pci_set_power_state(pci, PCI_D0);
1107
1108         return 0;
1109 }
1110 #endif /* CONFIG_PM_SLEEP */
1111
1112 static int azx_runtime_suspend(struct device *dev)
1113 {
1114         struct snd_card *card = dev_get_drvdata(dev);
1115         struct azx *chip;
1116
1117         if (!azx_is_pm_ready(card))
1118                 return 0;
1119         chip = card->private_data;
1120
1121         /* enable controller wake up event */
1122         if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) {
1123                 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1124                            STATESTS_INT_MASK);
1125         }
1126
1127         __azx_runtime_suspend(chip);
1128         trace_azx_runtime_suspend(chip);
1129         return 0;
1130 }
1131
1132 static int azx_runtime_resume(struct device *dev)
1133 {
1134         struct snd_card *card = dev_get_drvdata(dev);
1135         struct azx *chip;
1136         bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0;
1137
1138         if (!azx_is_pm_ready(card))
1139                 return 0;
1140         chip = card->private_data;
1141         __azx_runtime_resume(chip, from_rt);
1142
1143         /* disable controller Wake Up event*/
1144         if (from_rt) {
1145                 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1146                            ~STATESTS_INT_MASK);
1147         }
1148
1149         trace_azx_runtime_resume(chip);
1150         return 0;
1151 }
1152
1153 static int azx_runtime_idle(struct device *dev)
1154 {
1155         struct snd_card *card = dev_get_drvdata(dev);
1156         struct azx *chip;
1157         struct hda_intel *hda;
1158
1159         if (!card)
1160                 return 0;
1161
1162         chip = card->private_data;
1163         hda = container_of(chip, struct hda_intel, chip);
1164         if (chip->disabled || hda->init_failed)
1165                 return 0;
1166
1167         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1168             azx_bus(chip)->codec_powered || !chip->running)
1169                 return -EBUSY;
1170
1171         /* ELD notification gets broken when HD-audio bus is off */
1172         if (needs_eld_notify_link(chip))
1173                 return -EBUSY;
1174
1175         return 0;
1176 }
1177
1178 static const struct dev_pm_ops azx_pm = {
1179         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1180 #ifdef CONFIG_PM_SLEEP
1181         .freeze_noirq = azx_freeze_noirq,
1182         .thaw_noirq = azx_thaw_noirq,
1183 #endif
1184         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1185 };
1186
1187 #define AZX_PM_OPS      &azx_pm
1188 #else
1189 #define azx_add_card_list(chip) /* NOP */
1190 #define azx_del_card_list(chip) /* NOP */
1191 #define AZX_PM_OPS      NULL
1192 #endif /* CONFIG_PM */
1193
1194
1195 static int azx_probe_continue(struct azx *chip);
1196
1197 #ifdef SUPPORT_VGA_SWITCHEROO
1198 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1199
1200 static void azx_vs_set_state(struct pci_dev *pci,
1201                              enum vga_switcheroo_state state)
1202 {
1203         struct snd_card *card = pci_get_drvdata(pci);
1204         struct azx *chip = card->private_data;
1205         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1206         struct hda_codec *codec;
1207         bool disabled;
1208
1209         wait_for_completion(&hda->probe_wait);
1210         if (hda->init_failed)
1211                 return;
1212
1213         disabled = (state == VGA_SWITCHEROO_OFF);
1214         if (chip->disabled == disabled)
1215                 return;
1216
1217         if (!hda->probe_continued) {
1218                 chip->disabled = disabled;
1219                 if (!disabled) {
1220                         dev_info(chip->card->dev,
1221                                  "Start delayed initialization\n");
1222                         if (azx_probe_continue(chip) < 0)
1223                                 dev_err(chip->card->dev, "initialization error\n");
1224                 }
1225         } else {
1226                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1227                          disabled ? "Disabling" : "Enabling");
1228                 if (disabled) {
1229                         list_for_each_codec(codec, &chip->bus) {
1230                                 pm_runtime_suspend(hda_codec_dev(codec));
1231                                 pm_runtime_disable(hda_codec_dev(codec));
1232                         }
1233                         pm_runtime_suspend(card->dev);
1234                         pm_runtime_disable(card->dev);
1235                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1236                          * however we have no ACPI handle, so pci/acpi can't put us there,
1237                          * put ourselves there */
1238                         pci->current_state = PCI_D3cold;
1239                         chip->disabled = true;
1240                         if (snd_hda_lock_devices(&chip->bus))
1241                                 dev_warn(chip->card->dev,
1242                                          "Cannot lock devices!\n");
1243                 } else {
1244                         snd_hda_unlock_devices(&chip->bus);
1245                         chip->disabled = false;
1246                         pm_runtime_enable(card->dev);
1247                         list_for_each_codec(codec, &chip->bus) {
1248                                 pm_runtime_enable(hda_codec_dev(codec));
1249                                 pm_runtime_resume(hda_codec_dev(codec));
1250                         }
1251                 }
1252         }
1253 }
1254
1255 static bool azx_vs_can_switch(struct pci_dev *pci)
1256 {
1257         struct snd_card *card = pci_get_drvdata(pci);
1258         struct azx *chip = card->private_data;
1259         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260
1261         wait_for_completion(&hda->probe_wait);
1262         if (hda->init_failed)
1263                 return false;
1264         if (chip->disabled || !hda->probe_continued)
1265                 return true;
1266         if (snd_hda_lock_devices(&chip->bus))
1267                 return false;
1268         snd_hda_unlock_devices(&chip->bus);
1269         return true;
1270 }
1271
1272 /*
1273  * The discrete GPU cannot power down unless the HDA controller runtime
1274  * suspends, so activate runtime PM on codecs even if power_save == 0.
1275  */
1276 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1277 {
1278         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1279         struct hda_codec *codec;
1280
1281         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1282                 list_for_each_codec(codec, &chip->bus)
1283                         codec->auto_runtime_pm = 1;
1284                 /* reset the power save setup */
1285                 if (chip->running)
1286                         set_default_power_save(chip);
1287         }
1288 }
1289
1290 static void azx_vs_gpu_bound(struct pci_dev *pci,
1291                              enum vga_switcheroo_client_id client_id)
1292 {
1293         struct snd_card *card = pci_get_drvdata(pci);
1294         struct azx *chip = card->private_data;
1295
1296         if (client_id == VGA_SWITCHEROO_DIS)
1297                 chip->bus.keep_power = 0;
1298         setup_vga_switcheroo_runtime_pm(chip);
1299 }
1300
1301 static void init_vga_switcheroo(struct azx *chip)
1302 {
1303         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1304         struct pci_dev *p = get_bound_vga(chip->pci);
1305         struct pci_dev *parent;
1306         if (p) {
1307                 dev_info(chip->card->dev,
1308                          "Handle vga_switcheroo audio client\n");
1309                 hda->use_vga_switcheroo = 1;
1310
1311                 /* cleared in either gpu_bound op or codec probe, or when its
1312                  * upstream port has _PR3 (i.e. dGPU).
1313                  */
1314                 parent = pci_upstream_bridge(p);
1315                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1316                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1317                 pci_dev_put(p);
1318         }
1319 }
1320
1321 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1322         .set_gpu_state = azx_vs_set_state,
1323         .can_switch = azx_vs_can_switch,
1324         .gpu_bound = azx_vs_gpu_bound,
1325 };
1326
1327 static int register_vga_switcheroo(struct azx *chip)
1328 {
1329         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1330         struct pci_dev *p;
1331         int err;
1332
1333         if (!hda->use_vga_switcheroo)
1334                 return 0;
1335
1336         p = get_bound_vga(chip->pci);
1337         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1338         pci_dev_put(p);
1339
1340         if (err < 0)
1341                 return err;
1342         hda->vga_switcheroo_registered = 1;
1343
1344         return 0;
1345 }
1346 #else
1347 #define init_vga_switcheroo(chip)               /* NOP */
1348 #define register_vga_switcheroo(chip)           0
1349 #define check_hdmi_disabled(pci)        false
1350 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1351 #endif /* SUPPORT_VGA_SWITCHER */
1352
1353 /*
1354  * destructor
1355  */
1356 static void azx_free(struct azx *chip)
1357 {
1358         struct pci_dev *pci = chip->pci;
1359         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1360         struct hdac_bus *bus = azx_bus(chip);
1361
1362         if (hda->freed)
1363                 return;
1364
1365         if (azx_has_pm_runtime(chip) && chip->running)
1366                 pm_runtime_get_noresume(&pci->dev);
1367         chip->running = 0;
1368
1369         azx_del_card_list(chip);
1370
1371         hda->init_failed = 1; /* to be sure */
1372         complete_all(&hda->probe_wait);
1373
1374         if (use_vga_switcheroo(hda)) {
1375                 if (chip->disabled && hda->probe_continued)
1376                         snd_hda_unlock_devices(&chip->bus);
1377                 if (hda->vga_switcheroo_registered)
1378                         vga_switcheroo_unregister_client(chip->pci);
1379         }
1380
1381         if (bus->chip_init) {
1382                 azx_clear_irq_pending(chip);
1383                 azx_stop_all_streams(chip);
1384                 azx_stop_chip(chip);
1385         }
1386
1387         if (bus->irq >= 0)
1388                 free_irq(bus->irq, (void*)chip);
1389         if (chip->msi)
1390                 pci_disable_msi(chip->pci);
1391         iounmap(bus->remap_addr);
1392
1393         azx_free_stream_pages(chip);
1394         azx_free_streams(chip);
1395         snd_hdac_bus_exit(bus);
1396
1397         if (chip->region_requested)
1398                 pci_release_regions(chip->pci);
1399
1400         pci_disable_device(chip->pci);
1401 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1402         release_firmware(chip->fw);
1403 #endif
1404         display_power(chip, false);
1405
1406         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1407                 snd_hdac_i915_exit(bus);
1408
1409         hda->freed = 1;
1410 }
1411
1412 static int azx_dev_disconnect(struct snd_device *device)
1413 {
1414         struct azx *chip = device->device_data;
1415         struct hdac_bus *bus = azx_bus(chip);
1416
1417         chip->bus.shutdown = 1;
1418         cancel_work_sync(&bus->unsol_work);
1419
1420         return 0;
1421 }
1422
1423 static int azx_dev_free(struct snd_device *device)
1424 {
1425         azx_free(device->device_data);
1426         return 0;
1427 }
1428
1429 #ifdef SUPPORT_VGA_SWITCHEROO
1430 #ifdef CONFIG_ACPI
1431 /* ATPX is in the integrated GPU's namespace */
1432 static bool atpx_present(void)
1433 {
1434         struct pci_dev *pdev = NULL;
1435         acpi_handle dhandle, atpx_handle;
1436         acpi_status status;
1437
1438         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1439                 dhandle = ACPI_HANDLE(&pdev->dev);
1440                 if (dhandle) {
1441                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1442                         if (!ACPI_FAILURE(status)) {
1443                                 pci_dev_put(pdev);
1444                                 return true;
1445                         }
1446                 }
1447         }
1448         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1449                 dhandle = ACPI_HANDLE(&pdev->dev);
1450                 if (dhandle) {
1451                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1452                         if (!ACPI_FAILURE(status)) {
1453                                 pci_dev_put(pdev);
1454                                 return true;
1455                         }
1456                 }
1457         }
1458         return false;
1459 }
1460 #else
1461 static bool atpx_present(void)
1462 {
1463         return false;
1464 }
1465 #endif
1466
1467 /*
1468  * Check of disabled HDMI controller by vga_switcheroo
1469  */
1470 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1471 {
1472         struct pci_dev *p;
1473
1474         /* check only discrete GPU */
1475         switch (pci->vendor) {
1476         case PCI_VENDOR_ID_ATI:
1477         case PCI_VENDOR_ID_AMD:
1478                 if (pci->devfn == 1) {
1479                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1480                                                         pci->bus->number, 0);
1481                         if (p) {
1482                                 /* ATPX is in the integrated GPU's ACPI namespace
1483                                  * rather than the dGPU's namespace. However,
1484                                  * the dGPU is the one who is involved in
1485                                  * vgaswitcheroo.
1486                                  */
1487                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1488                                     atpx_present())
1489                                         return p;
1490                                 pci_dev_put(p);
1491                         }
1492                 }
1493                 break;
1494         case PCI_VENDOR_ID_NVIDIA:
1495                 if (pci->devfn == 1) {
1496                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1497                                                         pci->bus->number, 0);
1498                         if (p) {
1499                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1500                                         return p;
1501                                 pci_dev_put(p);
1502                         }
1503                 }
1504                 break;
1505         }
1506         return NULL;
1507 }
1508
1509 static bool check_hdmi_disabled(struct pci_dev *pci)
1510 {
1511         bool vga_inactive = false;
1512         struct pci_dev *p = get_bound_vga(pci);
1513
1514         if (p) {
1515                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1516                         vga_inactive = true;
1517                 pci_dev_put(p);
1518         }
1519         return vga_inactive;
1520 }
1521 #endif /* SUPPORT_VGA_SWITCHEROO */
1522
1523 /*
1524  * white/black-listing for position_fix
1525  */
1526 static const struct snd_pci_quirk position_fix_list[] = {
1527         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1528         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1529         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1530         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1531         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1532         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1533         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1534         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1535         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1536         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1537         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1538         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1539         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1540         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1541         {}
1542 };
1543
1544 static int check_position_fix(struct azx *chip, int fix)
1545 {
1546         const struct snd_pci_quirk *q;
1547
1548         switch (fix) {
1549         case POS_FIX_AUTO:
1550         case POS_FIX_LPIB:
1551         case POS_FIX_POSBUF:
1552         case POS_FIX_VIACOMBO:
1553         case POS_FIX_COMBO:
1554         case POS_FIX_SKL:
1555         case POS_FIX_FIFO:
1556                 return fix;
1557         }
1558
1559         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1560         if (q) {
1561                 dev_info(chip->card->dev,
1562                          "position_fix set to %d for device %04x:%04x\n",
1563                          q->value, q->subvendor, q->subdevice);
1564                 return q->value;
1565         }
1566
1567         /* Check VIA/ATI HD Audio Controller exist */
1568         if (chip->driver_type == AZX_DRIVER_VIA) {
1569                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1570                 return POS_FIX_VIACOMBO;
1571         }
1572         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1573                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1574                 return POS_FIX_FIFO;
1575         }
1576         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1577                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1578                 return POS_FIX_LPIB;
1579         }
1580         if (chip->driver_type == AZX_DRIVER_SKL) {
1581                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1582                 return POS_FIX_SKL;
1583         }
1584         return POS_FIX_AUTO;
1585 }
1586
1587 static void assign_position_fix(struct azx *chip, int fix)
1588 {
1589         static const azx_get_pos_callback_t callbacks[] = {
1590                 [POS_FIX_AUTO] = NULL,
1591                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1592                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1593                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1594                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1595                 [POS_FIX_SKL] = azx_get_pos_skl,
1596                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1597         };
1598
1599         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1600
1601         /* combo mode uses LPIB only for playback */
1602         if (fix == POS_FIX_COMBO)
1603                 chip->get_position[1] = NULL;
1604
1605         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1606             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1607                 chip->get_delay[0] = chip->get_delay[1] =
1608                         azx_get_delay_from_lpib;
1609         }
1610
1611         if (fix == POS_FIX_FIFO)
1612                 chip->get_delay[0] = chip->get_delay[1] =
1613                         azx_get_delay_from_fifo;
1614 }
1615
1616 /*
1617  * black-lists for probe_mask
1618  */
1619 static const struct snd_pci_quirk probe_mask_list[] = {
1620         /* Thinkpad often breaks the controller communication when accessing
1621          * to the non-working (or non-existing) modem codec slot.
1622          */
1623         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1624         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1625         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1626         /* broken BIOS */
1627         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1628         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1629         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1630         /* forced codec slots */
1631         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1632         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1633         /* WinFast VP200 H (Teradici) user reported broken communication */
1634         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1635         {}
1636 };
1637
1638 #define AZX_FORCE_CODEC_MASK    0x100
1639
1640 static void check_probe_mask(struct azx *chip, int dev)
1641 {
1642         const struct snd_pci_quirk *q;
1643
1644         chip->codec_probe_mask = probe_mask[dev];
1645         if (chip->codec_probe_mask == -1) {
1646                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1647                 if (q) {
1648                         dev_info(chip->card->dev,
1649                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1650                                  q->value, q->subvendor, q->subdevice);
1651                         chip->codec_probe_mask = q->value;
1652                 }
1653         }
1654
1655         /* check forced option */
1656         if (chip->codec_probe_mask != -1 &&
1657             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1658                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1659                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1660                          (int)azx_bus(chip)->codec_mask);
1661         }
1662 }
1663
1664 /*
1665  * white/black-list for enable_msi
1666  */
1667 static const struct snd_pci_quirk msi_black_list[] = {
1668         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1669         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1670         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1671         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1672         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1673         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1674         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1675         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1676         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1677         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1678         {}
1679 };
1680
1681 static void check_msi(struct azx *chip)
1682 {
1683         const struct snd_pci_quirk *q;
1684
1685         if (enable_msi >= 0) {
1686                 chip->msi = !!enable_msi;
1687                 return;
1688         }
1689         chip->msi = 1;  /* enable MSI as default */
1690         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1691         if (q) {
1692                 dev_info(chip->card->dev,
1693                          "msi for device %04x:%04x set to %d\n",
1694                          q->subvendor, q->subdevice, q->value);
1695                 chip->msi = q->value;
1696                 return;
1697         }
1698
1699         /* NVidia chipsets seem to cause troubles with MSI */
1700         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1701                 dev_info(chip->card->dev, "Disabling MSI\n");
1702                 chip->msi = 0;
1703         }
1704 }
1705
1706 /* check the snoop mode availability */
1707 static void azx_check_snoop_available(struct azx *chip)
1708 {
1709         int snoop = hda_snoop;
1710
1711         if (snoop >= 0) {
1712                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1713                          snoop ? "snoop" : "non-snoop");
1714                 chip->snoop = snoop;
1715                 chip->uc_buffer = !snoop;
1716                 return;
1717         }
1718
1719         snoop = true;
1720         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1721             chip->driver_type == AZX_DRIVER_VIA) {
1722                 /* force to non-snoop mode for a new VIA controller
1723                  * when BIOS is set
1724                  */
1725                 u8 val;
1726                 pci_read_config_byte(chip->pci, 0x42, &val);
1727                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1728                                       chip->pci->revision == 0x20))
1729                         snoop = false;
1730         }
1731
1732         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1733                 snoop = false;
1734
1735         chip->snoop = snoop;
1736         if (!snoop) {
1737                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1738                 /* C-Media requires non-cached pages only for CORB/RIRB */
1739                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1740                         chip->uc_buffer = true;
1741         }
1742 }
1743
1744 static void azx_probe_work(struct work_struct *work)
1745 {
1746         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1747         azx_probe_continue(&hda->chip);
1748 }
1749
1750 static int default_bdl_pos_adj(struct azx *chip)
1751 {
1752         /* some exceptions: Atoms seem problematic with value 1 */
1753         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1754                 switch (chip->pci->device) {
1755                 case 0x0f04: /* Baytrail */
1756                 case 0x2284: /* Braswell */
1757                         return 32;
1758                 }
1759         }
1760
1761         switch (chip->driver_type) {
1762         case AZX_DRIVER_ICH:
1763         case AZX_DRIVER_PCH:
1764                 return 1;
1765         default:
1766                 return 32;
1767         }
1768 }
1769
1770 /*
1771  * constructor
1772  */
1773 static const struct hda_controller_ops pci_hda_ops;
1774
1775 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1776                       int dev, unsigned int driver_caps,
1777                       struct azx **rchip)
1778 {
1779         static const struct snd_device_ops ops = {
1780                 .dev_disconnect = azx_dev_disconnect,
1781                 .dev_free = azx_dev_free,
1782         };
1783         struct hda_intel *hda;
1784         struct azx *chip;
1785         int err;
1786
1787         *rchip = NULL;
1788
1789         err = pci_enable_device(pci);
1790         if (err < 0)
1791                 return err;
1792
1793         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1794         if (!hda) {
1795                 pci_disable_device(pci);
1796                 return -ENOMEM;
1797         }
1798
1799         chip = &hda->chip;
1800         mutex_init(&chip->open_mutex);
1801         chip->card = card;
1802         chip->pci = pci;
1803         chip->ops = &pci_hda_ops;
1804         chip->driver_caps = driver_caps;
1805         chip->driver_type = driver_caps & 0xff;
1806         check_msi(chip);
1807         chip->dev_index = dev;
1808         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1809                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1810         INIT_LIST_HEAD(&chip->pcm_list);
1811         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1812         INIT_LIST_HEAD(&hda->list);
1813         init_vga_switcheroo(chip);
1814         init_completion(&hda->probe_wait);
1815
1816         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1817
1818         check_probe_mask(chip, dev);
1819
1820         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1821                 chip->fallback_to_single_cmd = 1;
1822         else /* explicitly set to single_cmd or not */
1823                 chip->single_cmd = single_cmd;
1824
1825         azx_check_snoop_available(chip);
1826
1827         if (bdl_pos_adj[dev] < 0)
1828                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1829         else
1830                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1831
1832         err = azx_bus_init(chip, model[dev]);
1833         if (err < 0) {
1834                 pci_disable_device(pci);
1835                 return err;
1836         }
1837
1838         /* use the non-cached pages in non-snoop mode */
1839         if (!azx_snoop(chip))
1840                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1841
1842         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1843                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1844                 chip->bus.core.needs_damn_long_delay = 1;
1845         }
1846
1847         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1848         if (err < 0) {
1849                 dev_err(card->dev, "Error creating device [card]!\n");
1850                 azx_free(chip);
1851                 return err;
1852         }
1853
1854         /* continue probing in work context as may trigger request module */
1855         INIT_WORK(&hda->probe_work, azx_probe_work);
1856
1857         *rchip = chip;
1858
1859         return 0;
1860 }
1861
1862 static int azx_first_init(struct azx *chip)
1863 {
1864         int dev = chip->dev_index;
1865         struct pci_dev *pci = chip->pci;
1866         struct snd_card *card = chip->card;
1867         struct hdac_bus *bus = azx_bus(chip);
1868         int err;
1869         unsigned short gcap;
1870         unsigned int dma_bits = 64;
1871
1872 #if BITS_PER_LONG != 64
1873         /* Fix up base address on ULI M5461 */
1874         if (chip->driver_type == AZX_DRIVER_ULI) {
1875                 u16 tmp3;
1876                 pci_read_config_word(pci, 0x40, &tmp3);
1877                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1878                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1879         }
1880 #endif
1881
1882         err = pci_request_regions(pci, "ICH HD audio");
1883         if (err < 0)
1884                 return err;
1885         chip->region_requested = 1;
1886
1887         bus->addr = pci_resource_start(pci, 0);
1888         bus->remap_addr = pci_ioremap_bar(pci, 0);
1889         if (bus->remap_addr == NULL) {
1890                 dev_err(card->dev, "ioremap error\n");
1891                 return -ENXIO;
1892         }
1893
1894         if (chip->driver_type == AZX_DRIVER_SKL)
1895                 snd_hdac_bus_parse_capabilities(bus);
1896
1897         /*
1898          * Some Intel CPUs has always running timer (ART) feature and
1899          * controller may have Global time sync reporting capability, so
1900          * check both of these before declaring synchronized time reporting
1901          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1902          */
1903         chip->gts_present = false;
1904
1905 #ifdef CONFIG_X86
1906         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1907                 chip->gts_present = true;
1908 #endif
1909
1910         if (chip->msi) {
1911                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1912                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1913                         pci->no_64bit_msi = true;
1914                 }
1915                 if (pci_enable_msi(pci) < 0)
1916                         chip->msi = 0;
1917         }
1918
1919         pci_set_master(pci);
1920
1921         gcap = azx_readw(chip, GCAP);
1922         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1923
1924         /* AMD devices support 40 or 48bit DMA, take the safe one */
1925         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1926                 dma_bits = 40;
1927
1928         /* disable SB600 64bit support for safety */
1929         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1930                 struct pci_dev *p_smbus;
1931                 dma_bits = 40;
1932                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1933                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1934                                          NULL);
1935                 if (p_smbus) {
1936                         if (p_smbus->revision < 0x30)
1937                                 gcap &= ~AZX_GCAP_64OK;
1938                         pci_dev_put(p_smbus);
1939                 }
1940         }
1941
1942         /* NVidia hardware normally only supports up to 40 bits of DMA */
1943         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1944                 dma_bits = 40;
1945
1946         /* disable 64bit DMA address on some devices */
1947         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1948                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1949                 gcap &= ~AZX_GCAP_64OK;
1950         }
1951
1952         /* disable buffer size rounding to 128-byte multiples if supported */
1953         if (align_buffer_size >= 0)
1954                 chip->align_buffer_size = !!align_buffer_size;
1955         else {
1956                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1957                         chip->align_buffer_size = 0;
1958                 else
1959                         chip->align_buffer_size = 1;
1960         }
1961
1962         /* allow 64bit DMA address if supported by H/W */
1963         if (!(gcap & AZX_GCAP_64OK))
1964                 dma_bits = 32;
1965         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1966                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1967         } else {
1968                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1969                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1970         }
1971
1972         /* read number of streams from GCAP register instead of using
1973          * hardcoded value
1974          */
1975         chip->capture_streams = (gcap >> 8) & 0x0f;
1976         chip->playback_streams = (gcap >> 12) & 0x0f;
1977         if (!chip->playback_streams && !chip->capture_streams) {
1978                 /* gcap didn't give any info, switching to old method */
1979
1980                 switch (chip->driver_type) {
1981                 case AZX_DRIVER_ULI:
1982                         chip->playback_streams = ULI_NUM_PLAYBACK;
1983                         chip->capture_streams = ULI_NUM_CAPTURE;
1984                         break;
1985                 case AZX_DRIVER_ATIHDMI:
1986                 case AZX_DRIVER_ATIHDMI_NS:
1987                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1988                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1989                         break;
1990                 case AZX_DRIVER_GENERIC:
1991                 default:
1992                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1993                         chip->capture_streams = ICH6_NUM_CAPTURE;
1994                         break;
1995                 }
1996         }
1997         chip->capture_index_offset = 0;
1998         chip->playback_index_offset = chip->capture_streams;
1999         chip->num_streams = chip->playback_streams + chip->capture_streams;
2000
2001         /* sanity check for the SDxCTL.STRM field overflow */
2002         if (chip->num_streams > 15 &&
2003             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2004                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2005                          "forcing separate stream tags", chip->num_streams);
2006                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2007         }
2008
2009         /* initialize streams */
2010         err = azx_init_streams(chip);
2011         if (err < 0)
2012                 return err;
2013
2014         err = azx_alloc_stream_pages(chip);
2015         if (err < 0)
2016                 return err;
2017
2018         /* initialize chip */
2019         azx_init_pci(chip);
2020
2021         snd_hdac_i915_set_bclk(bus);
2022
2023         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2024
2025         /* codec detection */
2026         if (!azx_bus(chip)->codec_mask) {
2027                 dev_err(card->dev, "no codecs found!\n");
2028                 /* keep running the rest for the runtime PM */
2029         }
2030
2031         if (azx_acquire_irq(chip, 0) < 0)
2032                 return -EBUSY;
2033
2034         strcpy(card->driver, "HDA-Intel");
2035         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2036                 sizeof(card->shortname));
2037         snprintf(card->longname, sizeof(card->longname),
2038                  "%s at 0x%lx irq %i",
2039                  card->shortname, bus->addr, bus->irq);
2040
2041         return 0;
2042 }
2043
2044 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2045 /* callback from request_firmware_nowait() */
2046 static void azx_firmware_cb(const struct firmware *fw, void *context)
2047 {
2048         struct snd_card *card = context;
2049         struct azx *chip = card->private_data;
2050
2051         if (fw)
2052                 chip->fw = fw;
2053         else
2054                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2055         if (!chip->disabled) {
2056                 /* continue probing */
2057                 azx_probe_continue(chip);
2058         }
2059 }
2060 #endif
2061
2062 static int disable_msi_reset_irq(struct azx *chip)
2063 {
2064         struct hdac_bus *bus = azx_bus(chip);
2065         int err;
2066
2067         free_irq(bus->irq, chip);
2068         bus->irq = -1;
2069         chip->card->sync_irq = -1;
2070         pci_disable_msi(chip->pci);
2071         chip->msi = 0;
2072         err = azx_acquire_irq(chip, 1);
2073         if (err < 0)
2074                 return err;
2075
2076         return 0;
2077 }
2078
2079 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2080                              struct vm_area_struct *area)
2081 {
2082 #ifdef CONFIG_X86
2083         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2084         struct azx *chip = apcm->chip;
2085         if (chip->uc_buffer)
2086                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2087 #endif
2088 }
2089
2090 /* Blacklist for skipping the whole probe:
2091  * some HD-audio PCI entries are exposed without any codecs, and such devices
2092  * should be ignored from the beginning.
2093  */
2094 static const struct snd_pci_quirk driver_blacklist[] = {
2095         SND_PCI_QUIRK(0x1043, 0x874f, "ASUS ROG Zenith II / Strix", 0),
2096         SND_PCI_QUIRK(0x1462, 0xcb59, "MSI TRX40 Creator", 0),
2097         SND_PCI_QUIRK(0x1462, 0xcb60, "MSI TRX40", 0),
2098         {}
2099 };
2100
2101 static const struct hda_controller_ops pci_hda_ops = {
2102         .disable_msi_reset_irq = disable_msi_reset_irq,
2103         .pcm_mmap_prepare = pcm_mmap_prepare,
2104         .position_check = azx_position_check,
2105 };
2106
2107 static int azx_probe(struct pci_dev *pci,
2108                      const struct pci_device_id *pci_id)
2109 {
2110         static int dev;
2111         struct snd_card *card;
2112         struct hda_intel *hda;
2113         struct azx *chip;
2114         bool schedule_probe;
2115         int err;
2116
2117         if (snd_pci_quirk_lookup(pci, driver_blacklist)) {
2118                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2119                 return -ENODEV;
2120         }
2121
2122         if (dev >= SNDRV_CARDS)
2123                 return -ENODEV;
2124         if (!enable[dev]) {
2125                 dev++;
2126                 return -ENOENT;
2127         }
2128
2129         /*
2130          * stop probe if another Intel's DSP driver should be activated
2131          */
2132         if (dmic_detect) {
2133                 err = snd_intel_dsp_driver_probe(pci);
2134                 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2135                     err != SND_INTEL_DSP_DRIVER_LEGACY)
2136                         return -ENODEV;
2137         } else {
2138                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2139         }
2140
2141         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2142                            0, &card);
2143         if (err < 0) {
2144                 dev_err(&pci->dev, "Error creating card!\n");
2145                 return err;
2146         }
2147
2148         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2149         if (err < 0)
2150                 goto out_free;
2151         card->private_data = chip;
2152         hda = container_of(chip, struct hda_intel, chip);
2153
2154         pci_set_drvdata(pci, card);
2155
2156         err = register_vga_switcheroo(chip);
2157         if (err < 0) {
2158                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2159                 goto out_free;
2160         }
2161
2162         if (check_hdmi_disabled(pci)) {
2163                 dev_info(card->dev, "VGA controller is disabled\n");
2164                 dev_info(card->dev, "Delaying initialization\n");
2165                 chip->disabled = true;
2166         }
2167
2168         schedule_probe = !chip->disabled;
2169
2170 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2171         if (patch[dev] && *patch[dev]) {
2172                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2173                          patch[dev]);
2174                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2175                                               &pci->dev, GFP_KERNEL, card,
2176                                               azx_firmware_cb);
2177                 if (err < 0)
2178                         goto out_free;
2179                 schedule_probe = false; /* continued in azx_firmware_cb() */
2180         }
2181 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2182
2183 #ifndef CONFIG_SND_HDA_I915
2184         if (CONTROLLER_IN_GPU(pci))
2185                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2186 #endif
2187
2188         if (schedule_probe)
2189                 schedule_work(&hda->probe_work);
2190
2191         dev++;
2192         if (chip->disabled)
2193                 complete_all(&hda->probe_wait);
2194         return 0;
2195
2196 out_free:
2197         snd_card_free(card);
2198         return err;
2199 }
2200
2201 #ifdef CONFIG_PM
2202 /* On some boards setting power_save to a non 0 value leads to clicking /
2203  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2204  * figure out how to avoid these sounds, but that is not always feasible.
2205  * So we keep a list of devices where we disable powersaving as its known
2206  * to causes problems on these devices.
2207  */
2208 static const struct snd_pci_quirk power_save_blacklist[] = {
2209         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2210         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2211         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2212         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2213         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2214         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2215         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2216         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2217         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2218         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2219         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2220         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2221         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2222         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2223         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2224         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2225         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2226         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2227         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2228         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2229         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2230         /* https://bugs.launchpad.net/bugs/1821663 */
2231         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2232         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2233         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2234         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2235         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2236         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2237         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2238         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2239         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2240         /* https://bugs.launchpad.net/bugs/1821663 */
2241         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2242         {}
2243 };
2244 #endif /* CONFIG_PM */
2245
2246 static void set_default_power_save(struct azx *chip)
2247 {
2248         int val = power_save;
2249
2250 #ifdef CONFIG_PM
2251         if (pm_blacklist) {
2252                 const struct snd_pci_quirk *q;
2253
2254                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2255                 if (q && val) {
2256                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2257                                  q->subvendor, q->subdevice);
2258                         val = 0;
2259                 }
2260         }
2261 #endif /* CONFIG_PM */
2262         snd_hda_set_power_save(&chip->bus, val * 1000);
2263 }
2264
2265 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2266 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2267         [AZX_DRIVER_NVIDIA] = 8,
2268         [AZX_DRIVER_TERA] = 1,
2269 };
2270
2271 static int azx_probe_continue(struct azx *chip)
2272 {
2273         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2274         struct hdac_bus *bus = azx_bus(chip);
2275         struct pci_dev *pci = chip->pci;
2276         int dev = chip->dev_index;
2277         int err;
2278
2279         to_hda_bus(bus)->bus_probing = 1;
2280         hda->probe_continued = 1;
2281
2282         /* bind with i915 if needed */
2283         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2284                 err = snd_hdac_i915_init(bus);
2285                 if (err < 0) {
2286                         /* if the controller is bound only with HDMI/DP
2287                          * (for HSW and BDW), we need to abort the probe;
2288                          * for other chips, still continue probing as other
2289                          * codecs can be on the same link.
2290                          */
2291                         if (CONTROLLER_IN_GPU(pci)) {
2292                                 dev_err(chip->card->dev,
2293                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2294                                 goto out_free;
2295                         } else {
2296                                 /* don't bother any longer */
2297                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2298                         }
2299                 }
2300
2301                 /* HSW/BDW controllers need this power */
2302                 if (CONTROLLER_IN_GPU(pci))
2303                         hda->need_i915_power = 1;
2304         }
2305
2306         /* Request display power well for the HDA controller or codec. For
2307          * Haswell/Broadwell, both the display HDA controller and codec need
2308          * this power. For other platforms, like Baytrail/Braswell, only the
2309          * display codec needs the power and it can be released after probe.
2310          */
2311         display_power(chip, true);
2312
2313         err = azx_first_init(chip);
2314         if (err < 0)
2315                 goto out_free;
2316
2317 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2318         chip->beep_mode = beep_mode[dev];
2319 #endif
2320
2321         /* create codec instances */
2322         if (bus->codec_mask) {
2323                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2324                 if (err < 0)
2325                         goto out_free;
2326         }
2327
2328 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2329         if (chip->fw) {
2330                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2331                                          chip->fw->data);
2332                 if (err < 0)
2333                         goto out_free;
2334 #ifndef CONFIG_PM
2335                 release_firmware(chip->fw); /* no longer needed */
2336                 chip->fw = NULL;
2337 #endif
2338         }
2339 #endif
2340         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2341                 err = azx_codec_configure(chip);
2342                 if (err < 0)
2343                         goto out_free;
2344         }
2345
2346         err = snd_card_register(chip->card);
2347         if (err < 0)
2348                 goto out_free;
2349
2350         setup_vga_switcheroo_runtime_pm(chip);
2351
2352         chip->running = 1;
2353         azx_add_card_list(chip);
2354
2355         set_default_power_save(chip);
2356
2357         if (azx_has_pm_runtime(chip))
2358                 pm_runtime_put_autosuspend(&pci->dev);
2359
2360 out_free:
2361         if (err < 0) {
2362                 azx_free(chip);
2363                 return err;
2364         }
2365
2366         if (!hda->need_i915_power)
2367                 display_power(chip, false);
2368         complete_all(&hda->probe_wait);
2369         to_hda_bus(bus)->bus_probing = 0;
2370         return 0;
2371 }
2372
2373 static void azx_remove(struct pci_dev *pci)
2374 {
2375         struct snd_card *card = pci_get_drvdata(pci);
2376         struct azx *chip;
2377         struct hda_intel *hda;
2378
2379         if (card) {
2380                 /* cancel the pending probing work */
2381                 chip = card->private_data;
2382                 hda = container_of(chip, struct hda_intel, chip);
2383                 /* FIXME: below is an ugly workaround.
2384                  * Both device_release_driver() and driver_probe_device()
2385                  * take *both* the device's and its parent's lock before
2386                  * calling the remove() and probe() callbacks.  The codec
2387                  * probe takes the locks of both the codec itself and its
2388                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2389                  * the PCI controller is unbound, it takes its lock, too
2390                  * ==> ouch, a deadlock!
2391                  * As a workaround, we unlock temporarily here the controller
2392                  * device during cancel_work_sync() call.
2393                  */
2394                 device_unlock(&pci->dev);
2395                 cancel_work_sync(&hda->probe_work);
2396                 device_lock(&pci->dev);
2397
2398                 snd_card_free(card);
2399         }
2400 }
2401
2402 static void azx_shutdown(struct pci_dev *pci)
2403 {
2404         struct snd_card *card = pci_get_drvdata(pci);
2405         struct azx *chip;
2406
2407         if (!card)
2408                 return;
2409         chip = card->private_data;
2410         if (chip && chip->running)
2411                 azx_stop_chip(chip);
2412 }
2413
2414 /* PCI IDs */
2415 static const struct pci_device_id azx_ids[] = {
2416         /* CPT */
2417         { PCI_DEVICE(0x8086, 0x1c20),
2418           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2419         /* PBG */
2420         { PCI_DEVICE(0x8086, 0x1d20),
2421           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2422         /* Panther Point */
2423         { PCI_DEVICE(0x8086, 0x1e20),
2424           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2425         /* Lynx Point */
2426         { PCI_DEVICE(0x8086, 0x8c20),
2427           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2428         /* 9 Series */
2429         { PCI_DEVICE(0x8086, 0x8ca0),
2430           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2431         /* Wellsburg */
2432         { PCI_DEVICE(0x8086, 0x8d20),
2433           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434         { PCI_DEVICE(0x8086, 0x8d21),
2435           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2436         /* Lewisburg */
2437         { PCI_DEVICE(0x8086, 0xa1f0),
2438           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2439         { PCI_DEVICE(0x8086, 0xa270),
2440           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2441         /* Lynx Point-LP */
2442         { PCI_DEVICE(0x8086, 0x9c20),
2443           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2444         /* Lynx Point-LP */
2445         { PCI_DEVICE(0x8086, 0x9c21),
2446           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2447         /* Wildcat Point-LP */
2448         { PCI_DEVICE(0x8086, 0x9ca0),
2449           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2450         /* Sunrise Point */
2451         { PCI_DEVICE(0x8086, 0xa170),
2452           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2453         /* Sunrise Point-LP */
2454         { PCI_DEVICE(0x8086, 0x9d70),
2455           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2456         /* Kabylake */
2457         { PCI_DEVICE(0x8086, 0xa171),
2458           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2459         /* Kabylake-LP */
2460         { PCI_DEVICE(0x8086, 0x9d71),
2461           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2462         /* Kabylake-H */
2463         { PCI_DEVICE(0x8086, 0xa2f0),
2464           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2465         /* Coffelake */
2466         { PCI_DEVICE(0x8086, 0xa348),
2467           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468         /* Cannonlake */
2469         { PCI_DEVICE(0x8086, 0x9dc8),
2470           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471         /* CometLake-LP */
2472         { PCI_DEVICE(0x8086, 0x02C8),
2473           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2474         /* CometLake-H */
2475         { PCI_DEVICE(0x8086, 0x06C8),
2476           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477         /* CometLake-S */
2478         { PCI_DEVICE(0x8086, 0xa3f0),
2479           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2480         /* Icelake */
2481         { PCI_DEVICE(0x8086, 0x34c8),
2482           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2483         /* Jasperlake */
2484         { PCI_DEVICE(0x8086, 0x38c8),
2485           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2486         { PCI_DEVICE(0x8086, 0x4dc8),
2487           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2488         /* Tigerlake */
2489         { PCI_DEVICE(0x8086, 0xa0c8),
2490           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491         /* Elkhart Lake */
2492         { PCI_DEVICE(0x8086, 0x4b55),
2493           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494         /* Broxton-P(Apollolake) */
2495         { PCI_DEVICE(0x8086, 0x5a98),
2496           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2497         /* Broxton-T */
2498         { PCI_DEVICE(0x8086, 0x1a98),
2499           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2500         /* Gemini-Lake */
2501         { PCI_DEVICE(0x8086, 0x3198),
2502           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2503         /* Haswell */
2504         { PCI_DEVICE(0x8086, 0x0a0c),
2505           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2506         { PCI_DEVICE(0x8086, 0x0c0c),
2507           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2508         { PCI_DEVICE(0x8086, 0x0d0c),
2509           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2510         /* Broadwell */
2511         { PCI_DEVICE(0x8086, 0x160c),
2512           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2513         /* 5 Series/3400 */
2514         { PCI_DEVICE(0x8086, 0x3b56),
2515           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2516         /* Poulsbo */
2517         { PCI_DEVICE(0x8086, 0x811b),
2518           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2519         /* Oaktrail */
2520         { PCI_DEVICE(0x8086, 0x080a),
2521           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2522         /* BayTrail */
2523         { PCI_DEVICE(0x8086, 0x0f04),
2524           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2525         /* Braswell */
2526         { PCI_DEVICE(0x8086, 0x2284),
2527           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2528         /* ICH6 */
2529         { PCI_DEVICE(0x8086, 0x2668),
2530           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2531         /* ICH7 */
2532         { PCI_DEVICE(0x8086, 0x27d8),
2533           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2534         /* ESB2 */
2535         { PCI_DEVICE(0x8086, 0x269a),
2536           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2537         /* ICH8 */
2538         { PCI_DEVICE(0x8086, 0x284b),
2539           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2540         /* ICH9 */
2541         { PCI_DEVICE(0x8086, 0x293e),
2542           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2543         /* ICH9 */
2544         { PCI_DEVICE(0x8086, 0x293f),
2545           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2546         /* ICH10 */
2547         { PCI_DEVICE(0x8086, 0x3a3e),
2548           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2549         /* ICH10 */
2550         { PCI_DEVICE(0x8086, 0x3a6e),
2551           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2552         /* Generic Intel */
2553         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2554           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2555           .class_mask = 0xffffff,
2556           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2557         /* ATI SB 450/600/700/800/900 */
2558         { PCI_DEVICE(0x1002, 0x437b),
2559           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2560         { PCI_DEVICE(0x1002, 0x4383),
2561           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2562         /* AMD Hudson */
2563         { PCI_DEVICE(0x1022, 0x780d),
2564           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2565         /* AMD, X370 & co */
2566         { PCI_DEVICE(0x1022, 0x1457),
2567           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2568         /* AMD, X570 & co */
2569         { PCI_DEVICE(0x1022, 0x1487),
2570           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2571         /* AMD Stoney */
2572         { PCI_DEVICE(0x1022, 0x157a),
2573           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2574                          AZX_DCAPS_PM_RUNTIME },
2575         /* AMD Raven */
2576         { PCI_DEVICE(0x1022, 0x15e3),
2577           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2578         /* ATI HDMI */
2579         { PCI_DEVICE(0x1002, 0x0002),
2580           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2581         { PCI_DEVICE(0x1002, 0x1308),
2582           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2583         { PCI_DEVICE(0x1002, 0x157a),
2584           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2585         { PCI_DEVICE(0x1002, 0x15b3),
2586           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2587         { PCI_DEVICE(0x1002, 0x793b),
2588           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589         { PCI_DEVICE(0x1002, 0x7919),
2590           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591         { PCI_DEVICE(0x1002, 0x960f),
2592           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593         { PCI_DEVICE(0x1002, 0x970f),
2594           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595         { PCI_DEVICE(0x1002, 0x9840),
2596           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2597         { PCI_DEVICE(0x1002, 0xaa00),
2598           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599         { PCI_DEVICE(0x1002, 0xaa08),
2600           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601         { PCI_DEVICE(0x1002, 0xaa10),
2602           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603         { PCI_DEVICE(0x1002, 0xaa18),
2604           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605         { PCI_DEVICE(0x1002, 0xaa20),
2606           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607         { PCI_DEVICE(0x1002, 0xaa28),
2608           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609         { PCI_DEVICE(0x1002, 0xaa30),
2610           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611         { PCI_DEVICE(0x1002, 0xaa38),
2612           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613         { PCI_DEVICE(0x1002, 0xaa40),
2614           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615         { PCI_DEVICE(0x1002, 0xaa48),
2616           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617         { PCI_DEVICE(0x1002, 0xaa50),
2618           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619         { PCI_DEVICE(0x1002, 0xaa58),
2620           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621         { PCI_DEVICE(0x1002, 0xaa60),
2622           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623         { PCI_DEVICE(0x1002, 0xaa68),
2624           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(0x1002, 0xaa80),
2626           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627         { PCI_DEVICE(0x1002, 0xaa88),
2628           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629         { PCI_DEVICE(0x1002, 0xaa90),
2630           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631         { PCI_DEVICE(0x1002, 0xaa98),
2632           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633         { PCI_DEVICE(0x1002, 0x9902),
2634           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2635         { PCI_DEVICE(0x1002, 0xaaa0),
2636           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2637         { PCI_DEVICE(0x1002, 0xaaa8),
2638           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2639         { PCI_DEVICE(0x1002, 0xaab0),
2640           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2641         { PCI_DEVICE(0x1002, 0xaac0),
2642           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2643         { PCI_DEVICE(0x1002, 0xaac8),
2644           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2645         { PCI_DEVICE(0x1002, 0xaad8),
2646           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647           AZX_DCAPS_PM_RUNTIME },
2648         { PCI_DEVICE(0x1002, 0xaae0),
2649           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650           AZX_DCAPS_PM_RUNTIME },
2651         { PCI_DEVICE(0x1002, 0xaae8),
2652           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653           AZX_DCAPS_PM_RUNTIME },
2654         { PCI_DEVICE(0x1002, 0xaaf0),
2655           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2656           AZX_DCAPS_PM_RUNTIME },
2657         { PCI_DEVICE(0x1002, 0xaaf8),
2658           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2659           AZX_DCAPS_PM_RUNTIME },
2660         { PCI_DEVICE(0x1002, 0xab00),
2661           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2662           AZX_DCAPS_PM_RUNTIME },
2663         { PCI_DEVICE(0x1002, 0xab08),
2664           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665           AZX_DCAPS_PM_RUNTIME },
2666         { PCI_DEVICE(0x1002, 0xab10),
2667           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2668           AZX_DCAPS_PM_RUNTIME },
2669         { PCI_DEVICE(0x1002, 0xab18),
2670           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2671           AZX_DCAPS_PM_RUNTIME },
2672         { PCI_DEVICE(0x1002, 0xab20),
2673           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2674           AZX_DCAPS_PM_RUNTIME },
2675         { PCI_DEVICE(0x1002, 0xab38),
2676           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2677           AZX_DCAPS_PM_RUNTIME },
2678         /* VIA VT8251/VT8237A */
2679         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2680         /* VIA GFX VT7122/VX900 */
2681         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2682         /* VIA GFX VT6122/VX11 */
2683         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2684         /* SIS966 */
2685         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2686         /* ULI M5461 */
2687         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2688         /* NVIDIA MCP */
2689         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2690           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2691           .class_mask = 0xffffff,
2692           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2693         /* Teradici */
2694         { PCI_DEVICE(0x6549, 0x1200),
2695           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2696         { PCI_DEVICE(0x6549, 0x2200),
2697           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2698         /* Creative X-Fi (CA0110-IBG) */
2699         /* CTHDA chips */
2700         { PCI_DEVICE(0x1102, 0x0010),
2701           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2702         { PCI_DEVICE(0x1102, 0x0012),
2703           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2704 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2705         /* the following entry conflicts with snd-ctxfi driver,
2706          * as ctxfi driver mutates from HD-audio to native mode with
2707          * a special command sequence.
2708          */
2709         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2710           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2711           .class_mask = 0xffffff,
2712           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2713           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2714 #else
2715         /* this entry seems still valid -- i.e. without emu20kx chip */
2716         { PCI_DEVICE(0x1102, 0x0009),
2717           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2718           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2719 #endif
2720         /* CM8888 */
2721         { PCI_DEVICE(0x13f6, 0x5011),
2722           .driver_data = AZX_DRIVER_CMEDIA |
2723           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2724         /* Vortex86MX */
2725         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2726         /* VMware HDAudio */
2727         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2728         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2729         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2730           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2731           .class_mask = 0xffffff,
2732           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2733         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2734           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2735           .class_mask = 0xffffff,
2736           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2737         /* Zhaoxin */
2738         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2739         { 0, }
2740 };
2741 MODULE_DEVICE_TABLE(pci, azx_ids);
2742
2743 /* pci_driver definition */
2744 static struct pci_driver azx_driver = {
2745         .name = KBUILD_MODNAME,
2746         .id_table = azx_ids,
2747         .probe = azx_probe,
2748         .remove = azx_remove,
2749         .shutdown = azx_shutdown,
2750         .driver = {
2751                 .pm = AZX_PM_OPS,
2752         },
2753 };
2754
2755 module_pci_driver(azx_driver);