sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include <sound/hda_codec.h>
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 static bool pm_blacklist = true;
 190 module_param(pm_blacklist, bool, 0644);
 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 192
 193 /* reset the HD-audio controller in power save mode.
 194  * this may give more power-saving, but will take longer time to
 195  * wake up.
 196  */
 197 static bool power_save_controller = 1;
 198 module_param(power_save_controller, bool, 0644);
 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 200 #else
 201 #define power_save      0
 202 #endif /* CONFIG_PM */
 203
 204 static int align_buffer_size = -1;
 205 module_param(align_buffer_size, bint, 0644);
 206 MODULE_PARM_DESC(align_buffer_size,
 207                 "Force buffer and period sizes to be multiple of 128 bytes.");
 208
 209 #ifdef CONFIG_X86
 210 static int hda_snoop = -1;
 211 module_param_named(snoop, hda_snoop, bint, 0444);
 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 213 #else
 214 #define hda_snoop               true
 215 #endif
 216
 217
 218 MODULE_LICENSE("GPL");
 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 220                          "{Intel, ICH6M},"
 221                          "{Intel, ICH7},"
 222                          "{Intel, ESB2},"
 223                          "{Intel, ICH8},"
 224                          "{Intel, ICH9},"
 225                          "{Intel, ICH10},"
 226                          "{Intel, PCH},"
 227                          "{Intel, CPT},"
 228                          "{Intel, PPT},"
 229                          "{Intel, LPT},"
 230                          "{Intel, LPT_LP},"
 231                          "{Intel, WPT_LP},"
 232                          "{Intel, SPT},"
 233                          "{Intel, SPT_LP},"
 234                          "{Intel, HPT},"
 235                          "{Intel, PBG},"
 236                          "{Intel, SCH},"
 237                          "{ATI, SB450},"
 238                          "{ATI, SB600},"
 239                          "{ATI, RS600},"
 240                          "{ATI, RS690},"
 241                          "{ATI, RS780},"
 242                          "{ATI, R600},"
 243                          "{ATI, RV630},"
 244                          "{ATI, RV610},"
 245                          "{ATI, RV670},"
 246                          "{ATI, RV635},"
 247                          "{ATI, RV620},"
 248                          "{ATI, RV770},"
 249                          "{VIA, VT8251},"
 250                          "{VIA, VT8237A},"
 251                          "{SiS, SIS966},"
 252                          "{ULI, M5461}}");
 253 MODULE_DESCRIPTION("Intel HDA driver");
 254
 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 257 #define SUPPORT_VGA_SWITCHEROO
 258 #endif
 259 #endif
 260
 261
 262 /*
 263  */
 264
 265 /* driver types */
 266 enum {
 267         AZX_DRIVER_ICH,
 268         AZX_DRIVER_PCH,
 269         AZX_DRIVER_SCH,
 270         AZX_DRIVER_SKL,
 271         AZX_DRIVER_HDMI,
 272         AZX_DRIVER_ATI,
 273         AZX_DRIVER_ATIHDMI,
 274         AZX_DRIVER_ATIHDMI_NS,
 275         AZX_DRIVER_VIA,
 276         AZX_DRIVER_SIS,
 277         AZX_DRIVER_ULI,
 278         AZX_DRIVER_NVIDIA,
 279         AZX_DRIVER_TERA,
 280         AZX_DRIVER_CTX,
 281         AZX_DRIVER_CTHDA,
 282         AZX_DRIVER_CMEDIA,
 283         AZX_DRIVER_GENERIC,
 284         AZX_NUM_DRIVERS, /* keep this as last entry */
 285 };
 286
 287 #define azx_get_snoop_type(chip) \
 288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 290
 291 /* quirks for old Intel chipsets */
 292 #define AZX_DCAPS_INTEL_ICH \
 293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 294
 295 /* quirks for Intel PCH */
 296 #define AZX_DCAPS_INTEL_PCH_BASE \
 297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 301 #define AZX_DCAPS_INTEL_PCH_NOPM \
 302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 303
 304 /* PCH for HSW/BDW; with runtime PM */
 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 306 #define AZX_DCAPS_INTEL_PCH \
 307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 308
 309 /* HSW HDMI */
 310 #define AZX_DCAPS_INTEL_HASWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 316 #define AZX_DCAPS_INTEL_BROADWELL \
 317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 319          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 320
 321 #define AZX_DCAPS_INTEL_BAYTRAIL \
 322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 323          AZX_DCAPS_I915_POWERWELL)
 324
 325 #define AZX_DCAPS_INTEL_BRASWELL \
 326         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 327          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 328
 329 #define AZX_DCAPS_INTEL_SKYLAKE \
 330         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 331          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 332          AZX_DCAPS_I915_POWERWELL)
 333
 334 #define AZX_DCAPS_INTEL_BROXTON \
 335         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 336          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 337          AZX_DCAPS_I915_POWERWELL)
 338
 339 /* quirks for ATI SB / AMD Hudson */
 340 #define AZX_DCAPS_PRESET_ATI_SB \
 341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 342          AZX_DCAPS_SNOOP_TYPE(ATI))
 343
 344 /* quirks for ATI/AMD HDMI */
 345 #define AZX_DCAPS_PRESET_ATI_HDMI \
 346         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 347          AZX_DCAPS_NO_MSI64)
 348
 349 /* quirks for ATI HDMI with snoop off */
 350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 351         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 352
 353 /* quirks for Nvidia */
 354 #define AZX_DCAPS_PRESET_NVIDIA \
 355         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 356          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 357
 358 #define AZX_DCAPS_PRESET_CTHDA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 360          AZX_DCAPS_NO_64BIT |\
 361          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 362
 363 /*
 364  * vga_switcheroo support
 365  */
 366 #ifdef SUPPORT_VGA_SWITCHEROO
 367 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 368 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 369 #else
 370 #define use_vga_switcheroo(chip)        0
 371 #define needs_eld_notify_link(chip)     false
 372 #endif
 373
 374 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 375                                         ((pci)->device == 0x0c0c) || \
 376                                         ((pci)->device == 0x0d0c) || \
 377                                         ((pci)->device == 0x160c))
 378
 379 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 380 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 381
 382 static char *driver_short_names[] = {
 383         [AZX_DRIVER_ICH] = "HDA Intel",
 384         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 385         [AZX_DRIVER_SCH] = "HDA Intel MID",
 386         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 387         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 388         [AZX_DRIVER_ATI] = "HDA ATI SB",
 389         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 390         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 391         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 392         [AZX_DRIVER_SIS] = "HDA SIS966",
 393         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 394         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 395         [AZX_DRIVER_TERA] = "HDA Teradici",
 396         [AZX_DRIVER_CTX] = "HDA Creative",
 397         [AZX_DRIVER_CTHDA] = "HDA Creative",
 398         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 399         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 400 };
 401
 402 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 403 static void set_default_power_save(struct azx *chip);
 404
 405 /*
 406  * initialize the PCI registers
 407  */
 408 /* update bits in a PCI register byte */
 409 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 410                             unsigned char mask, unsigned char val)
 411 {
 412         unsigned char data;
 413
 414         pci_read_config_byte(pci, reg, &data);
 415         data &= ~mask;
 416         data |= (val & mask);
 417         pci_write_config_byte(pci, reg, data);
 418 }
 419
 420 static void azx_init_pci(struct azx *chip)
 421 {
 422         int snoop_type = azx_get_snoop_type(chip);
 423
 424         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 425          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 426          * Ensuring these bits are 0 clears playback static on some HD Audio
 427          * codecs.
 428          * The PCI register TCSEL is defined in the Intel manuals.
 429          */
 430         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 431                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 432                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 433         }
 434
 435         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 436          * we need to enable snoop.
 437          */
 438         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 439                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 440                         azx_snoop(chip));
 441                 update_pci_byte(chip->pci,
 442                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 443                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 444         }
 445
 446         /* For NVIDIA HDA, enable snoop */
 447         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 448                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 449                         azx_snoop(chip));
 450                 update_pci_byte(chip->pci,
 451                                 NVIDIA_HDA_TRANSREG_ADDR,
 452                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 453                 update_pci_byte(chip->pci,
 454                                 NVIDIA_HDA_ISTRM_COH,
 455                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 456                 update_pci_byte(chip->pci,
 457                                 NVIDIA_HDA_OSTRM_COH,
 458                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 459         }
 460
 461         /* Enable SCH/PCH snoop if needed */
 462         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 463                 unsigned short snoop;
 464                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 465                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 466                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 467                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 468                         if (!azx_snoop(chip))
 469                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 470                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 471                         pci_read_config_word(chip->pci,
 472                                 INTEL_SCH_HDA_DEVC, &snoop);
 473                 }
 474                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 475                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 476                         "Disabled" : "Enabled");
 477         }
 478 }
 479
 480 /*
 481  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 482  * and makes an audio stream sensitive to system latencies when
 483  * 24/32 bits are playing.
 484  * Adjusting threshold of DMA fifo to force the DMA request
 485  * sooner to improve latency tolerance at the expense of power.
 486  */
 487 static void bxt_reduce_dma_latency(struct azx *chip)
 488 {
 489         u32 val;
 490
 491         val = azx_readl(chip, VS_EM4L);
 492         val &= (0x3 << 20);
 493         azx_writel(chip, VS_EM4L, val);
 494 }
 495
 496 /*
 497  * ML_LCAP bits:
 498  *  bit 0: 6 MHz Supported
 499  *  bit 1: 12 MHz Supported
 500  *  bit 2: 24 MHz Supported
 501  *  bit 3: 48 MHz Supported
 502  *  bit 4: 96 MHz Supported
 503  *  bit 5: 192 MHz Supported
 504  */
 505 static int intel_get_lctl_scf(struct azx *chip)
 506 {
 507         struct hdac_bus *bus = azx_bus(chip);
 508         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 509         u32 val, t;
 510         int i;
 511
 512         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 513
 514         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 515                 t = preferred_bits[i];
 516                 if (val & (1 << t))
 517                         return t;
 518         }
 519
 520         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 521         return 0;
 522 }
 523
 524 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 525 {
 526         struct hdac_bus *bus = azx_bus(chip);
 527         u32 val;
 528         int timeout;
 529
 530         /*
 531          * the codecs are sharing the first link setting by default
 532          * If other links are enabled for stream, they need similar fix
 533          */
 534         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 535         val &= ~AZX_MLCTL_SPA;
 536         val |= state << AZX_MLCTL_SPA_SHIFT;
 537         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 538         /* wait for CPA */
 539         timeout = 50;
 540         while (timeout) {
 541                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 542                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 543                         return 0;
 544                 timeout--;
 545                 udelay(10);
 546         }
 547
 548         return -1;
 549 }
 550
 551 static void intel_init_lctl(struct azx *chip)
 552 {
 553         struct hdac_bus *bus = azx_bus(chip);
 554         u32 val;
 555         int ret;
 556
 557         /* 0. check lctl register value is correct or not */
 558         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 559         /* if SCF is already set, let's use it */
 560         if ((val & ML_LCTL_SCF_MASK) != 0)
 561                 return;
 562
 563         /*
 564          * Before operating on SPA, CPA must match SPA.
 565          * Any deviation may result in undefined behavior.
 566          */
 567         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 568                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 569                 return;
 570
 571         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 572         ret = intel_ml_lctl_set_power(chip, 0);
 573         udelay(100);
 574         if (ret)
 575                 goto set_spa;
 576
 577         /* 2. update SCF to select a properly audio clock*/
 578         val &= ~ML_LCTL_SCF_MASK;
 579         val |= intel_get_lctl_scf(chip);
 580         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 581
 582 set_spa:
 583         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 584         intel_ml_lctl_set_power(chip, 1);
 585         udelay(100);
 586 }
 587
 588 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 589 {
 590         struct hdac_bus *bus = azx_bus(chip);
 591         struct pci_dev *pci = chip->pci;
 592         u32 val;
 593
 594         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 595                 snd_hdac_set_codec_wakeup(bus, true);
 596         if (chip->driver_type == AZX_DRIVER_SKL) {
 597                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 598                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 599                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 600         }
 601         azx_init_chip(chip, full_reset);
 602         if (chip->driver_type == AZX_DRIVER_SKL) {
 603                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 604                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 605                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 606         }
 607         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 608                 snd_hdac_set_codec_wakeup(bus, false);
 609
 610         /* reduce dma latency to avoid noise */
 611         if (IS_BXT(pci))
 612                 bxt_reduce_dma_latency(chip);
 613
 614         if (bus->mlcap != NULL)
 615                 intel_init_lctl(chip);
 616 }
 617
 618 /* calculate runtime delay from LPIB */
 619 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 620                                    unsigned int pos)
 621 {
 622         struct snd_pcm_substream *substream = azx_dev->core.substream;
 623         int stream = substream->stream;
 624         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 625         int delay;
 626
 627         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 628                 delay = pos - lpib_pos;
 629         else
 630                 delay = lpib_pos - pos;
 631         if (delay < 0) {
 632                 if (delay >= azx_dev->core.delay_negative_threshold)
 633                         delay = 0;
 634                 else
 635                         delay += azx_dev->core.bufsize;
 636         }
 637
 638         if (delay >= azx_dev->core.period_bytes) {
 639                 dev_info(chip->card->dev,
 640                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 641                          delay, azx_dev->core.period_bytes);
 642                 delay = 0;
 643                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 644                 chip->get_delay[stream] = NULL;
 645         }
 646
 647         return bytes_to_frames(substream->runtime, delay);
 648 }
 649
 650 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 651
 652 /* called from IRQ */
 653 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 654 {
 655         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 656         int ok;
 657
 658         ok = azx_position_ok(chip, azx_dev);
 659         if (ok == 1) {
 660                 azx_dev->irq_pending = 0;
 661                 return ok;
 662         } else if (ok == 0) {
 663                 /* bogus IRQ, process it later */
 664                 azx_dev->irq_pending = 1;
 665                 schedule_work(&hda->irq_pending_work);
 666         }
 667         return 0;
 668 }
 669
 670 /* Enable/disable i915 display power for the link */
 671 static int azx_intel_link_power(struct azx *chip, bool enable)
 672 {
 673         struct hdac_bus *bus = azx_bus(chip);
 674
 675         return snd_hdac_display_power(bus, enable);
 676 }
 677
 678 /*
 679  * Check whether the current DMA position is acceptable for updating
 680  * periods.  Returns non-zero if it's OK.
 681  *
 682  * Many HD-audio controllers appear pretty inaccurate about
 683  * the update-IRQ timing.  The IRQ is issued before actually the
 684  * data is processed.  So, we need to process it afterwords in a
 685  * workqueue.
 686  */
 687 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 688 {
 689         struct snd_pcm_substream *substream = azx_dev->core.substream;
 690         int stream = substream->stream;
 691         u32 wallclk;
 692         unsigned int pos;
 693
 694         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 695         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 696                 return -1;      /* bogus (too early) interrupt */
 697
 698         if (chip->get_position[stream])
 699                 pos = chip->get_position[stream](chip, azx_dev);
 700         else { /* use the position buffer as default */
 701                 pos = azx_get_pos_posbuf(chip, azx_dev);
 702                 if (!pos || pos == (u32)-1) {
 703                         dev_info(chip->card->dev,
 704                                  "Invalid position buffer, using LPIB read method instead.\n");
 705                         chip->get_position[stream] = azx_get_pos_lpib;
 706                         if (chip->get_position[0] == azx_get_pos_lpib &&
 707                             chip->get_position[1] == azx_get_pos_lpib)
 708                                 azx_bus(chip)->use_posbuf = false;
 709                         pos = azx_get_pos_lpib(chip, azx_dev);
 710                         chip->get_delay[stream] = NULL;
 711                 } else {
 712                         chip->get_position[stream] = azx_get_pos_posbuf;
 713                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 714                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 715                 }
 716         }
 717
 718         if (pos >= azx_dev->core.bufsize)
 719                 pos = 0;
 720
 721         if (WARN_ONCE(!azx_dev->core.period_bytes,
 722                       "hda-intel: zero azx_dev->period_bytes"))
 723                 return -1; /* this shouldn't happen! */
 724         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 725             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 726                 /* NG - it's below the first next period boundary */
 727                 return chip->bdl_pos_adj ? 0 : -1;
 728         azx_dev->core.start_wallclk += wallclk;
 729         return 1; /* OK, it's fine */
 730 }
 731
 732 /*
 733  * The work for pending PCM period updates.
 734  */
 735 static void azx_irq_pending_work(struct work_struct *work)
 736 {
 737         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 738         struct azx *chip = &hda->chip;
 739         struct hdac_bus *bus = azx_bus(chip);
 740         struct hdac_stream *s;
 741         int pending, ok;
 742
 743         if (!hda->irq_pending_warned) {
 744                 dev_info(chip->card->dev,
 745                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 746                          chip->card->number);
 747                 hda->irq_pending_warned = 1;
 748         }
 749
 750         for (;;) {
 751                 pending = 0;
 752                 spin_lock_irq(&bus->reg_lock);
 753                 list_for_each_entry(s, &bus->stream_list, list) {
 754                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 755                         if (!azx_dev->irq_pending ||
 756                             !s->substream ||
 757                             !s->running)
 758                                 continue;
 759                         ok = azx_position_ok(chip, azx_dev);
 760                         if (ok > 0) {
 761                                 azx_dev->irq_pending = 0;
 762                                 spin_unlock(&bus->reg_lock);
 763                                 snd_pcm_period_elapsed(s->substream);
 764                                 spin_lock(&bus->reg_lock);
 765                         } else if (ok < 0) {
 766                                 pending = 0;    /* too early */
 767                         } else
 768                                 pending++;
 769                 }
 770                 spin_unlock_irq(&bus->reg_lock);
 771                 if (!pending)
 772                         return;
 773                 msleep(1);
 774         }
 775 }
 776
 777 /* clear irq_pending flags and assure no on-going workq */
 778 static void azx_clear_irq_pending(struct azx *chip)
 779 {
 780         struct hdac_bus *bus = azx_bus(chip);
 781         struct hdac_stream *s;
 782
 783         spin_lock_irq(&bus->reg_lock);
 784         list_for_each_entry(s, &bus->stream_list, list) {
 785                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 786                 azx_dev->irq_pending = 0;
 787         }
 788         spin_unlock_irq(&bus->reg_lock);
 789 }
 790
 791 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 792 {
 793         struct hdac_bus *bus = azx_bus(chip);
 794
 795         if (request_irq(chip->pci->irq, azx_interrupt,
 796                         chip->msi ? 0 : IRQF_SHARED,
 797                         chip->card->irq_descr, chip)) {
 798                 dev_err(chip->card->dev,
 799                         "unable to grab IRQ %d, disabling device\n",
 800                         chip->pci->irq);
 801                 if (do_disconnect)
 802                         snd_card_disconnect(chip->card);
 803                 return -1;
 804         }
 805         bus->irq = chip->pci->irq;
 806         pci_intx(chip->pci, !chip->msi);
 807         return 0;
 808 }
 809
 810 /* get the current DMA position with correction on VIA chips */
 811 static unsigned int azx_via_get_position(struct azx *chip,
 812                                          struct azx_dev *azx_dev)
 813 {
 814         unsigned int link_pos, mini_pos, bound_pos;
 815         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 816         unsigned int fifo_size;
 817
 818         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 819         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 820                 /* Playback, no problem using link position */
 821                 return link_pos;
 822         }
 823
 824         /* Capture */
 825         /* For new chipset,
 826          * use mod to get the DMA position just like old chipset
 827          */
 828         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 829         mod_dma_pos %= azx_dev->core.period_bytes;
 830
 831         /* azx_dev->fifo_size can't get FIFO size of in stream.
 832          * Get from base address + offset.
 833          */
 834         fifo_size = readw(azx_bus(chip)->remap_addr +
 835                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 836
 837         if (azx_dev->insufficient) {
 838                 /* Link position never gather than FIFO size */
 839                 if (link_pos <= fifo_size)
 840                         return 0;
 841
 842                 azx_dev->insufficient = 0;
 843         }
 844
 845         if (link_pos <= fifo_size)
 846                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 847         else
 848                 mini_pos = link_pos - fifo_size;
 849
 850         /* Find nearest previous boudary */
 851         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 852         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 853         if (mod_link_pos >= fifo_size)
 854                 bound_pos = link_pos - mod_link_pos;
 855         else if (mod_dma_pos >= mod_mini_pos)
 856                 bound_pos = mini_pos - mod_mini_pos;
 857         else {
 858                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 859                 if (bound_pos >= azx_dev->core.bufsize)
 860                         bound_pos = 0;
 861         }
 862
 863         /* Calculate real DMA position we want */
 864         return bound_pos + mod_dma_pos;
 865 }
 866
 867 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 868                                          struct azx_dev *azx_dev)
 869 {
 870         return _snd_hdac_chip_readl(azx_bus(chip),
 871                                     AZX_REG_VS_SDXDPIB_XBASE +
 872                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 873                                      azx_dev->core.index));
 874 }
 875
 876 /* get the current DMA position with correction on SKL+ chips */
 877 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 878 {
 879         /* DPIB register gives a more accurate position for playback */
 880         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 881                 return azx_skl_get_dpib_pos(chip, azx_dev);
 882
 883         /* For capture, we need to read posbuf, but it requires a delay
 884          * for the possible boundary overlap; the read of DPIB fetches the
 885          * actual posbuf
 886          */
 887         udelay(20);
 888         azx_skl_get_dpib_pos(chip, azx_dev);
 889         return azx_get_pos_posbuf(chip, azx_dev);
 890 }
 891
 892 #ifdef CONFIG_PM
 893 static DEFINE_MUTEX(card_list_lock);
 894 static LIST_HEAD(card_list);
 895
 896 static void azx_add_card_list(struct azx *chip)
 897 {
 898         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 899         mutex_lock(&card_list_lock);
 900         list_add(&hda->list, &card_list);
 901         mutex_unlock(&card_list_lock);
 902 }
 903
 904 static void azx_del_card_list(struct azx *chip)
 905 {
 906         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 907         mutex_lock(&card_list_lock);
 908         list_del_init(&hda->list);
 909         mutex_unlock(&card_list_lock);
 910 }
 911
 912 /* trigger power-save check at writing parameter */
 913 static int param_set_xint(const char *val, const struct kernel_param *kp)
 914 {
 915         struct hda_intel *hda;
 916         struct azx *chip;
 917         int prev = power_save;
 918         int ret = param_set_int(val, kp);
 919
 920         if (ret || prev == power_save)
 921                 return ret;
 922
 923         mutex_lock(&card_list_lock);
 924         list_for_each_entry(hda, &card_list, list) {
 925                 chip = &hda->chip;
 926                 if (!hda->probe_continued || chip->disabled)
 927                         continue;
 928                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 929         }
 930         mutex_unlock(&card_list_lock);
 931         return 0;
 932 }
 933 #else
 934 #define azx_add_card_list(chip) /* NOP */
 935 #define azx_del_card_list(chip) /* NOP */
 936 #endif /* CONFIG_PM */
 937
 938 #ifdef CONFIG_PM_SLEEP
 939 /*
 940  * power management
 941  */
 942 static int azx_suspend(struct device *dev)
 943 {
 944         struct snd_card *card = dev_get_drvdata(dev);
 945         struct azx *chip;
 946         struct hda_intel *hda;
 947         struct hdac_bus *bus;
 948
 949         if (!card)
 950                 return 0;
 951
 952         chip = card->private_data;
 953         hda = container_of(chip, struct hda_intel, chip);
 954         if (chip->disabled || hda->init_failed || !chip->running)
 955                 return 0;
 956
 957         bus = azx_bus(chip);
 958         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 959         azx_clear_irq_pending(chip);
 960         azx_stop_chip(chip);
 961         azx_enter_link_reset(chip);
 962         if (bus->irq >= 0) {
 963                 free_irq(bus->irq, chip);
 964                 bus->irq = -1;
 965         }
 966
 967         if (chip->msi)
 968                 pci_disable_msi(chip->pci);
 969         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 970                 && hda->need_i915_power)
 971                 snd_hdac_display_power(bus, false);
 972
 973         trace_azx_suspend(chip);
 974         return 0;
 975 }
 976
 977 static int azx_resume(struct device *dev)
 978 {
 979         struct pci_dev *pci = to_pci_dev(dev);
 980         struct snd_card *card = dev_get_drvdata(dev);
 981         struct azx *chip;
 982         struct hda_intel *hda;
 983         struct hdac_bus *bus;
 984
 985         if (!card)
 986                 return 0;
 987
 988         chip = card->private_data;
 989         hda = container_of(chip, struct hda_intel, chip);
 990         bus = azx_bus(chip);
 991         if (chip->disabled || hda->init_failed || !chip->running)
 992                 return 0;
 993
 994         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 995                 snd_hdac_display_power(bus, true);
 996                 if (hda->need_i915_power)
 997                         snd_hdac_i915_set_bclk(bus);
 998         }
 999
1000         if (chip->msi)
1001                 if (pci_enable_msi(pci) < 0)
1002                         chip->msi = 0;
1003         if (azx_acquire_irq(chip, 1) < 0)
1004                 return -EIO;
1005         azx_init_pci(chip);
1006
1007         hda_intel_init_chip(chip, true);
1008
1009         /* power down again for link-controlled chips */
1010         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1011             !hda->need_i915_power)
1012                 snd_hdac_display_power(bus, false);
1013
1014         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1015
1016         trace_azx_resume(chip);
1017         return 0;
1018 }
1019
1020 /* put codec down to D3 at hibernation for Intel SKL+;
1021  * otherwise BIOS may still access the codec and screw up the driver
1022  */
1023 static int azx_freeze_noirq(struct device *dev)
1024 {
1025         struct snd_card *card = dev_get_drvdata(dev);
1026         struct azx *chip = card->private_data;
1027         struct pci_dev *pci = to_pci_dev(dev);
1028
1029         if (chip->driver_type == AZX_DRIVER_SKL)
1030                 pci_set_power_state(pci, PCI_D3hot);
1031
1032         return 0;
1033 }
1034
1035 static int azx_thaw_noirq(struct device *dev)
1036 {
1037         struct snd_card *card = dev_get_drvdata(dev);
1038         struct azx *chip = card->private_data;
1039         struct pci_dev *pci = to_pci_dev(dev);
1040
1041         if (chip->driver_type == AZX_DRIVER_SKL)
1042                 pci_set_power_state(pci, PCI_D0);
1043
1044         return 0;
1045 }
1046 #endif /* CONFIG_PM_SLEEP */
1047
1048 #ifdef CONFIG_PM
1049 static int azx_runtime_suspend(struct device *dev)
1050 {
1051         struct snd_card *card = dev_get_drvdata(dev);
1052         struct azx *chip;
1053         struct hda_intel *hda;
1054
1055         if (!card)
1056                 return 0;
1057
1058         chip = card->private_data;
1059         hda = container_of(chip, struct hda_intel, chip);
1060         if (chip->disabled || hda->init_failed)
1061                 return 0;
1062
1063         if (!azx_has_pm_runtime(chip))
1064                 return 0;
1065
1066         /* enable controller wake up event */
1067         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1068                   STATESTS_INT_MASK);
1069
1070         azx_stop_chip(chip);
1071         azx_enter_link_reset(chip);
1072         azx_clear_irq_pending(chip);
1073         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1074                 && hda->need_i915_power)
1075                 snd_hdac_display_power(azx_bus(chip), false);
1076
1077         trace_azx_runtime_suspend(chip);
1078         return 0;
1079 }
1080
1081 static int azx_runtime_resume(struct device *dev)
1082 {
1083         struct snd_card *card = dev_get_drvdata(dev);
1084         struct azx *chip;
1085         struct hda_intel *hda;
1086         struct hdac_bus *bus;
1087         struct hda_codec *codec;
1088         int status;
1089
1090         if (!card)
1091                 return 0;
1092
1093         chip = card->private_data;
1094         hda = container_of(chip, struct hda_intel, chip);
1095         bus = azx_bus(chip);
1096         if (chip->disabled || hda->init_failed)
1097                 return 0;
1098
1099         if (!azx_has_pm_runtime(chip))
1100                 return 0;
1101
1102         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1103                 snd_hdac_display_power(bus, true);
1104                 if (hda->need_i915_power)
1105                         snd_hdac_i915_set_bclk(bus);
1106         }
1107
1108         /* Read STATESTS before controller reset */
1109         status = azx_readw(chip, STATESTS);
1110
1111         azx_init_pci(chip);
1112         hda_intel_init_chip(chip, true);
1113
1114         if (status) {
1115                 list_for_each_codec(codec, &chip->bus)
1116                         if (status & (1 << codec->addr))
1117                                 schedule_delayed_work(&codec->jackpoll_work,
1118                                                       codec->jackpoll_interval);
1119         }
1120
1121         /* disable controller Wake Up event*/
1122         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1123                         ~STATESTS_INT_MASK);
1124
1125         /* power down again for link-controlled chips */
1126         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1127             !hda->need_i915_power)
1128                 snd_hdac_display_power(bus, false);
1129
1130         trace_azx_runtime_resume(chip);
1131         return 0;
1132 }
1133
1134 static int azx_runtime_idle(struct device *dev)
1135 {
1136         struct snd_card *card = dev_get_drvdata(dev);
1137         struct azx *chip;
1138         struct hda_intel *hda;
1139
1140         if (!card)
1141                 return 0;
1142
1143         chip = card->private_data;
1144         hda = container_of(chip, struct hda_intel, chip);
1145         if (chip->disabled || hda->init_failed)
1146                 return 0;
1147
1148         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1149             azx_bus(chip)->codec_powered || !chip->running)
1150                 return -EBUSY;
1151
1152         /* ELD notification gets broken when HD-audio bus is off */
1153         if (needs_eld_notify_link(hda))
1154                 return -EBUSY;
1155
1156         return 0;
1157 }
1158
1159 static const struct dev_pm_ops azx_pm = {
1160         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1161 #ifdef CONFIG_PM_SLEEP
1162         .freeze_noirq = azx_freeze_noirq,
1163         .thaw_noirq = azx_thaw_noirq,
1164 #endif
1165         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1166 };
1167
1168 #define AZX_PM_OPS      &azx_pm
1169 #else
1170 #define AZX_PM_OPS      NULL
1171 #endif /* CONFIG_PM */
1172
1173
1174 static int azx_probe_continue(struct azx *chip);
1175
1176 #ifdef SUPPORT_VGA_SWITCHEROO
1177 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1178
1179 static void azx_vs_set_state(struct pci_dev *pci,
1180                              enum vga_switcheroo_state state)
1181 {
1182         struct snd_card *card = pci_get_drvdata(pci);
1183         struct azx *chip = card->private_data;
1184         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1185         struct hda_codec *codec;
1186         bool disabled;
1187
1188         wait_for_completion(&hda->probe_wait);
1189         if (hda->init_failed)
1190                 return;
1191
1192         disabled = (state == VGA_SWITCHEROO_OFF);
1193         if (chip->disabled == disabled)
1194                 return;
1195
1196         if (!hda->probe_continued) {
1197                 chip->disabled = disabled;
1198                 if (!disabled) {
1199                         dev_info(chip->card->dev,
1200                                  "Start delayed initialization\n");
1201                         if (azx_probe_continue(chip) < 0) {
1202                                 dev_err(chip->card->dev, "initialization error\n");
1203                                 hda->init_failed = true;
1204                         }
1205                 }
1206         } else {
1207                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1208                          disabled ? "Disabling" : "Enabling");
1209                 if (disabled) {
1210                         list_for_each_codec(codec, &chip->bus) {
1211                                 pm_runtime_suspend(hda_codec_dev(codec));
1212                                 pm_runtime_disable(hda_codec_dev(codec));
1213                         }
1214                         pm_runtime_suspend(card->dev);
1215                         pm_runtime_disable(card->dev);
1216                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1217                          * however we have no ACPI handle, so pci/acpi can't put us there,
1218                          * put ourselves there */
1219                         pci->current_state = PCI_D3cold;
1220                         chip->disabled = true;
1221                         if (snd_hda_lock_devices(&chip->bus))
1222                                 dev_warn(chip->card->dev,
1223                                          "Cannot lock devices!\n");
1224                 } else {
1225                         snd_hda_unlock_devices(&chip->bus);
1226                         chip->disabled = false;
1227                         pm_runtime_enable(card->dev);
1228                         list_for_each_codec(codec, &chip->bus) {
1229                                 pm_runtime_enable(hda_codec_dev(codec));
1230                                 pm_runtime_resume(hda_codec_dev(codec));
1231                         }
1232                 }
1233         }
1234 }
1235
1236 static bool azx_vs_can_switch(struct pci_dev *pci)
1237 {
1238         struct snd_card *card = pci_get_drvdata(pci);
1239         struct azx *chip = card->private_data;
1240         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1241
1242         wait_for_completion(&hda->probe_wait);
1243         if (hda->init_failed)
1244                 return false;
1245         if (chip->disabled || !hda->probe_continued)
1246                 return true;
1247         if (snd_hda_lock_devices(&chip->bus))
1248                 return false;
1249         snd_hda_unlock_devices(&chip->bus);
1250         return true;
1251 }
1252
1253 /*
1254  * The discrete GPU cannot power down unless the HDA controller runtime
1255  * suspends, so activate runtime PM on codecs even if power_save == 0.
1256  */
1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1258 {
1259         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260         struct hda_codec *codec;
1261
1262         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1263                 list_for_each_codec(codec, &chip->bus)
1264                         codec->auto_runtime_pm = 1;
1265                 /* reset the power save setup */
1266                 if (chip->running)
1267                         set_default_power_save(chip);
1268         }
1269 }
1270
1271 static void azx_vs_gpu_bound(struct pci_dev *pci,
1272                              enum vga_switcheroo_client_id client_id)
1273 {
1274         struct snd_card *card = pci_get_drvdata(pci);
1275         struct azx *chip = card->private_data;
1276         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1277
1278         if (client_id == VGA_SWITCHEROO_DIS)
1279                 hda->need_eld_notify_link = 0;
1280         setup_vga_switcheroo_runtime_pm(chip);
1281 }
1282
1283 static void init_vga_switcheroo(struct azx *chip)
1284 {
1285         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1286         struct pci_dev *p = get_bound_vga(chip->pci);
1287         if (p) {
1288                 dev_info(chip->card->dev,
1289                          "Handle vga_switcheroo audio client\n");
1290                 hda->use_vga_switcheroo = 1;
1291                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1292                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1293                 pci_dev_put(p);
1294         }
1295 }
1296
1297 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1298         .set_gpu_state = azx_vs_set_state,
1299         .can_switch = azx_vs_can_switch,
1300         .gpu_bound = azx_vs_gpu_bound,
1301 };
1302
1303 static int register_vga_switcheroo(struct azx *chip)
1304 {
1305         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1306         struct pci_dev *p;
1307         int err;
1308
1309         if (!hda->use_vga_switcheroo)
1310                 return 0;
1311
1312         p = get_bound_vga(chip->pci);
1313         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1314         pci_dev_put(p);
1315
1316         if (err < 0)
1317                 return err;
1318         hda->vga_switcheroo_registered = 1;
1319
1320         return 0;
1321 }
1322 #else
1323 #define init_vga_switcheroo(chip)               /* NOP */
1324 #define register_vga_switcheroo(chip)           0
1325 #define check_hdmi_disabled(pci)        false
1326 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1327 #endif /* SUPPORT_VGA_SWITCHER */
1328
1329 /*
1330  * destructor
1331  */
1332 static int azx_free(struct azx *chip)
1333 {
1334         struct pci_dev *pci = chip->pci;
1335         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1336         struct hdac_bus *bus = azx_bus(chip);
1337
1338         if (azx_has_pm_runtime(chip) && chip->running)
1339                 pm_runtime_get_noresume(&pci->dev);
1340         chip->running = 0;
1341
1342         azx_del_card_list(chip);
1343
1344         hda->init_failed = 1; /* to be sure */
1345         complete_all(&hda->probe_wait);
1346
1347         if (use_vga_switcheroo(hda)) {
1348                 if (chip->disabled && hda->probe_continued)
1349                         snd_hda_unlock_devices(&chip->bus);
1350                 if (hda->vga_switcheroo_registered)
1351                         vga_switcheroo_unregister_client(chip->pci);
1352         }
1353
1354         if (bus->chip_init) {
1355                 azx_clear_irq_pending(chip);
1356                 azx_stop_all_streams(chip);
1357                 azx_stop_chip(chip);
1358         }
1359
1360         if (bus->irq >= 0)
1361                 free_irq(bus->irq, (void*)chip);
1362         if (chip->msi)
1363                 pci_disable_msi(chip->pci);
1364         iounmap(bus->remap_addr);
1365
1366         azx_free_stream_pages(chip);
1367         azx_free_streams(chip);
1368         snd_hdac_bus_exit(bus);
1369
1370         if (chip->region_requested)
1371                 pci_release_regions(chip->pci);
1372
1373         pci_disable_device(chip->pci);
1374 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1375         release_firmware(chip->fw);
1376 #endif
1377
1378         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1379                 if (hda->need_i915_power)
1380                         snd_hdac_display_power(bus, false);
1381         }
1382         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1383                 snd_hdac_i915_exit(bus);
1384         kfree(hda);
1385
1386         return 0;
1387 }
1388
1389 static int azx_dev_disconnect(struct snd_device *device)
1390 {
1391         struct azx *chip = device->device_data;
1392
1393         chip->bus.shutdown = 1;
1394         return 0;
1395 }
1396
1397 static int azx_dev_free(struct snd_device *device)
1398 {
1399         return azx_free(device->device_data);
1400 }
1401
1402 #ifdef SUPPORT_VGA_SWITCHEROO
1403 /*
1404  * Check of disabled HDMI controller by vga_switcheroo
1405  */
1406 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1407 {
1408         struct pci_dev *p;
1409
1410         /* check only discrete GPU */
1411         switch (pci->vendor) {
1412         case PCI_VENDOR_ID_ATI:
1413         case PCI_VENDOR_ID_AMD:
1414         case PCI_VENDOR_ID_NVIDIA:
1415                 if (pci->devfn == 1) {
1416                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1417                                                         pci->bus->number, 0);
1418                         if (p) {
1419                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1420                                         return p;
1421                                 pci_dev_put(p);
1422                         }
1423                 }
1424                 break;
1425         }
1426         return NULL;
1427 }
1428
1429 static bool check_hdmi_disabled(struct pci_dev *pci)
1430 {
1431         bool vga_inactive = false;
1432         struct pci_dev *p = get_bound_vga(pci);
1433
1434         if (p) {
1435                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1436                         vga_inactive = true;
1437                 pci_dev_put(p);
1438         }
1439         return vga_inactive;
1440 }
1441 #endif /* SUPPORT_VGA_SWITCHEROO */
1442
1443 /*
1444  * white/black-listing for position_fix
1445  */
1446 static struct snd_pci_quirk position_fix_list[] = {
1447         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1448         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1449         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1450         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1451         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1452         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1453         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1454         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1455         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1456         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1457         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1458         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1459         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1460         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1461         {}
1462 };
1463
1464 static int check_position_fix(struct azx *chip, int fix)
1465 {
1466         const struct snd_pci_quirk *q;
1467
1468         switch (fix) {
1469         case POS_FIX_AUTO:
1470         case POS_FIX_LPIB:
1471         case POS_FIX_POSBUF:
1472         case POS_FIX_VIACOMBO:
1473         case POS_FIX_COMBO:
1474         case POS_FIX_SKL:
1475                 return fix;
1476         }
1477
1478         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1479         if (q) {
1480                 dev_info(chip->card->dev,
1481                          "position_fix set to %d for device %04x:%04x\n",
1482                          q->value, q->subvendor, q->subdevice);
1483                 return q->value;
1484         }
1485
1486         /* Check VIA/ATI HD Audio Controller exist */
1487         if (chip->driver_type == AZX_DRIVER_VIA) {
1488                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1489                 return POS_FIX_VIACOMBO;
1490         }
1491         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1492                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1493                 return POS_FIX_LPIB;
1494         }
1495         if (chip->driver_type == AZX_DRIVER_SKL) {
1496                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1497                 return POS_FIX_SKL;
1498         }
1499         return POS_FIX_AUTO;
1500 }
1501
1502 static void assign_position_fix(struct azx *chip, int fix)
1503 {
1504         static azx_get_pos_callback_t callbacks[] = {
1505                 [POS_FIX_AUTO] = NULL,
1506                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1507                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1508                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1509                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1510                 [POS_FIX_SKL] = azx_get_pos_skl,
1511         };
1512
1513         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1514
1515         /* combo mode uses LPIB only for playback */
1516         if (fix == POS_FIX_COMBO)
1517                 chip->get_position[1] = NULL;
1518
1519         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1520             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1521                 chip->get_delay[0] = chip->get_delay[1] =
1522                         azx_get_delay_from_lpib;
1523         }
1524
1525 }
1526
1527 /*
1528  * black-lists for probe_mask
1529  */
1530 static struct snd_pci_quirk probe_mask_list[] = {
1531         /* Thinkpad often breaks the controller communication when accessing
1532          * to the non-working (or non-existing) modem codec slot.
1533          */
1534         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1535         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1536         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1537         /* broken BIOS */
1538         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1539         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1540         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1541         /* forced codec slots */
1542         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1543         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1544         /* WinFast VP200 H (Teradici) user reported broken communication */
1545         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1546         {}
1547 };
1548
1549 #define AZX_FORCE_CODEC_MASK    0x100
1550
1551 static void check_probe_mask(struct azx *chip, int dev)
1552 {
1553         const struct snd_pci_quirk *q;
1554
1555         chip->codec_probe_mask = probe_mask[dev];
1556         if (chip->codec_probe_mask == -1) {
1557                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1558                 if (q) {
1559                         dev_info(chip->card->dev,
1560                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1561                                  q->value, q->subvendor, q->subdevice);
1562                         chip->codec_probe_mask = q->value;
1563                 }
1564         }
1565
1566         /* check forced option */
1567         if (chip->codec_probe_mask != -1 &&
1568             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1569                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1570                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1571                          (int)azx_bus(chip)->codec_mask);
1572         }
1573 }
1574
1575 /*
1576  * white/black-list for enable_msi
1577  */
1578 static struct snd_pci_quirk msi_black_list[] = {
1579         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1580         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1581         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1582         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1583         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1584         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1585         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1586         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1587         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1588         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1589         {}
1590 };
1591
1592 static void check_msi(struct azx *chip)
1593 {
1594         const struct snd_pci_quirk *q;
1595
1596         if (enable_msi >= 0) {
1597                 chip->msi = !!enable_msi;
1598                 return;
1599         }
1600         chip->msi = 1;  /* enable MSI as default */
1601         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1602         if (q) {
1603                 dev_info(chip->card->dev,
1604                          "msi for device %04x:%04x set to %d\n",
1605                          q->subvendor, q->subdevice, q->value);
1606                 chip->msi = q->value;
1607                 return;
1608         }
1609
1610         /* NVidia chipsets seem to cause troubles with MSI */
1611         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1612                 dev_info(chip->card->dev, "Disabling MSI\n");
1613                 chip->msi = 0;
1614         }
1615 }
1616
1617 /* check the snoop mode availability */
1618 static void azx_check_snoop_available(struct azx *chip)
1619 {
1620         int snoop = hda_snoop;
1621
1622         if (snoop >= 0) {
1623                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1624                          snoop ? "snoop" : "non-snoop");
1625                 chip->snoop = snoop;
1626                 chip->uc_buffer = !snoop;
1627                 return;
1628         }
1629
1630         snoop = true;
1631         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1632             chip->driver_type == AZX_DRIVER_VIA) {
1633                 /* force to non-snoop mode for a new VIA controller
1634                  * when BIOS is set
1635                  */
1636                 u8 val;
1637                 pci_read_config_byte(chip->pci, 0x42, &val);
1638                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1639                                       chip->pci->revision == 0x20))
1640                         snoop = false;
1641         }
1642
1643         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1644                 snoop = false;
1645
1646         chip->snoop = snoop;
1647         if (!snoop) {
1648                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1649                 /* C-Media requires non-cached pages only for CORB/RIRB */
1650                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1651                         chip->uc_buffer = true;
1652         }
1653 }
1654
1655 static void azx_probe_work(struct work_struct *work)
1656 {
1657         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1658         azx_probe_continue(&hda->chip);
1659 }
1660
1661 static int default_bdl_pos_adj(struct azx *chip)
1662 {
1663         /* some exceptions: Atoms seem problematic with value 1 */
1664         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1665                 switch (chip->pci->device) {
1666                 case 0x0f04: /* Baytrail */
1667                 case 0x2284: /* Braswell */
1668                         return 32;
1669                 }
1670         }
1671
1672         switch (chip->driver_type) {
1673         case AZX_DRIVER_ICH:
1674         case AZX_DRIVER_PCH:
1675                 return 1;
1676         default:
1677                 return 32;
1678         }
1679 }
1680
1681 /*
1682  * constructor
1683  */
1684 static const struct hdac_io_ops pci_hda_io_ops;
1685 static const struct hda_controller_ops pci_hda_ops;
1686
1687 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1688                       int dev, unsigned int driver_caps,
1689                       struct azx **rchip)
1690 {
1691         static struct snd_device_ops ops = {
1692                 .dev_disconnect = azx_dev_disconnect,
1693                 .dev_free = azx_dev_free,
1694         };
1695         struct hda_intel *hda;
1696         struct azx *chip;
1697         int err;
1698
1699         *rchip = NULL;
1700
1701         err = pci_enable_device(pci);
1702         if (err < 0)
1703                 return err;
1704
1705         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1706         if (!hda) {
1707                 pci_disable_device(pci);
1708                 return -ENOMEM;
1709         }
1710
1711         chip = &hda->chip;
1712         mutex_init(&chip->open_mutex);
1713         chip->card = card;
1714         chip->pci = pci;
1715         chip->ops = &pci_hda_ops;
1716         chip->driver_caps = driver_caps;
1717         chip->driver_type = driver_caps & 0xff;
1718         check_msi(chip);
1719         chip->dev_index = dev;
1720         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1721                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1722         INIT_LIST_HEAD(&chip->pcm_list);
1723         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1724         INIT_LIST_HEAD(&hda->list);
1725         init_vga_switcheroo(chip);
1726         init_completion(&hda->probe_wait);
1727
1728         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1729
1730         check_probe_mask(chip, dev);
1731
1732         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1733                 chip->fallback_to_single_cmd = 1;
1734         else /* explicitly set to single_cmd or not */
1735                 chip->single_cmd = single_cmd;
1736
1737         azx_check_snoop_available(chip);
1738
1739         if (bdl_pos_adj[dev] < 0)
1740                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1741         else
1742                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1743
1744         /* Workaround for a communication error on CFL (bko#199007) */
1745         if (IS_CFL(pci))
1746                 chip->polling_mode = 1;
1747
1748         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1749         if (err < 0) {
1750                 kfree(hda);
1751                 pci_disable_device(pci);
1752                 return err;
1753         }
1754
1755         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1756                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1757                 chip->bus.needs_damn_long_delay = 1;
1758         }
1759
1760         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1761         if (err < 0) {
1762                 dev_err(card->dev, "Error creating device [card]!\n");
1763                 azx_free(chip);
1764                 return err;
1765         }
1766
1767         /* continue probing in work context as may trigger request module */
1768         INIT_WORK(&hda->probe_work, azx_probe_work);
1769
1770         *rchip = chip;
1771
1772         return 0;
1773 }
1774
1775 static int azx_first_init(struct azx *chip)
1776 {
1777         int dev = chip->dev_index;
1778         struct pci_dev *pci = chip->pci;
1779         struct snd_card *card = chip->card;
1780         struct hdac_bus *bus = azx_bus(chip);
1781         int err;
1782         unsigned short gcap;
1783         unsigned int dma_bits = 64;
1784
1785 #if BITS_PER_LONG != 64
1786         /* Fix up base address on ULI M5461 */
1787         if (chip->driver_type == AZX_DRIVER_ULI) {
1788                 u16 tmp3;
1789                 pci_read_config_word(pci, 0x40, &tmp3);
1790                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1791                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1792         }
1793 #endif
1794
1795         err = pci_request_regions(pci, "ICH HD audio");
1796         if (err < 0)
1797                 return err;
1798         chip->region_requested = 1;
1799
1800         bus->addr = pci_resource_start(pci, 0);
1801         bus->remap_addr = pci_ioremap_bar(pci, 0);
1802         if (bus->remap_addr == NULL) {
1803                 dev_err(card->dev, "ioremap error\n");
1804                 return -ENXIO;
1805         }
1806
1807         if (chip->driver_type == AZX_DRIVER_SKL)
1808                 snd_hdac_bus_parse_capabilities(bus);
1809
1810         /*
1811          * Some Intel CPUs has always running timer (ART) feature and
1812          * controller may have Global time sync reporting capability, so
1813          * check both of these before declaring synchronized time reporting
1814          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1815          */
1816         chip->gts_present = false;
1817
1818 #ifdef CONFIG_X86
1819         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1820                 chip->gts_present = true;
1821 #endif
1822
1823         if (chip->msi) {
1824                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1825                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1826                         pci->no_64bit_msi = true;
1827                 }
1828                 if (pci_enable_msi(pci) < 0)
1829                         chip->msi = 0;
1830         }
1831
1832         if (azx_acquire_irq(chip, 0) < 0)
1833                 return -EBUSY;
1834
1835         pci_set_master(pci);
1836         synchronize_irq(bus->irq);
1837
1838         gcap = azx_readw(chip, GCAP);
1839         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1840
1841         /* AMD devices support 40 or 48bit DMA, take the safe one */
1842         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1843                 dma_bits = 40;
1844
1845         /* disable SB600 64bit support for safety */
1846         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1847                 struct pci_dev *p_smbus;
1848                 dma_bits = 40;
1849                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1850                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1851                                          NULL);
1852                 if (p_smbus) {
1853                         if (p_smbus->revision < 0x30)
1854                                 gcap &= ~AZX_GCAP_64OK;
1855                         pci_dev_put(p_smbus);
1856                 }
1857         }
1858
1859         /* NVidia hardware normally only supports up to 40 bits of DMA */
1860         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1861                 dma_bits = 40;
1862
1863         /* disable 64bit DMA address on some devices */
1864         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1865                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1866                 gcap &= ~AZX_GCAP_64OK;
1867         }
1868
1869         /* disable buffer size rounding to 128-byte multiples if supported */
1870         if (align_buffer_size >= 0)
1871                 chip->align_buffer_size = !!align_buffer_size;
1872         else {
1873                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1874                         chip->align_buffer_size = 0;
1875                 else
1876                         chip->align_buffer_size = 1;
1877         }
1878
1879         /* allow 64bit DMA address if supported by H/W */
1880         if (!(gcap & AZX_GCAP_64OK))
1881                 dma_bits = 32;
1882         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1883                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1884         } else {
1885                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1886                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1887         }
1888
1889         /* read number of streams from GCAP register instead of using
1890          * hardcoded value
1891          */
1892         chip->capture_streams = (gcap >> 8) & 0x0f;
1893         chip->playback_streams = (gcap >> 12) & 0x0f;
1894         if (!chip->playback_streams && !chip->capture_streams) {
1895                 /* gcap didn't give any info, switching to old method */
1896
1897                 switch (chip->driver_type) {
1898                 case AZX_DRIVER_ULI:
1899                         chip->playback_streams = ULI_NUM_PLAYBACK;
1900                         chip->capture_streams = ULI_NUM_CAPTURE;
1901                         break;
1902                 case AZX_DRIVER_ATIHDMI:
1903                 case AZX_DRIVER_ATIHDMI_NS:
1904                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1905                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1906                         break;
1907                 case AZX_DRIVER_GENERIC:
1908                 default:
1909                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1910                         chip->capture_streams = ICH6_NUM_CAPTURE;
1911                         break;
1912                 }
1913         }
1914         chip->capture_index_offset = 0;
1915         chip->playback_index_offset = chip->capture_streams;
1916         chip->num_streams = chip->playback_streams + chip->capture_streams;
1917
1918         /* sanity check for the SDxCTL.STRM field overflow */
1919         if (chip->num_streams > 15 &&
1920             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1921                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1922                          "forcing separate stream tags", chip->num_streams);
1923                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1924         }
1925
1926         /* initialize streams */
1927         err = azx_init_streams(chip);
1928         if (err < 0)
1929                 return err;
1930
1931         err = azx_alloc_stream_pages(chip);
1932         if (err < 0)
1933                 return err;
1934
1935         /* initialize chip */
1936         azx_init_pci(chip);
1937
1938         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1939                 snd_hdac_i915_set_bclk(bus);
1940
1941         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1942
1943         /* codec detection */
1944         if (!azx_bus(chip)->codec_mask) {
1945                 dev_err(card->dev, "no codecs found!\n");
1946                 return -ENODEV;
1947         }
1948
1949         strcpy(card->driver, "HDA-Intel");
1950         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1951                 sizeof(card->shortname));
1952         snprintf(card->longname, sizeof(card->longname),
1953                  "%s at 0x%lx irq %i",
1954                  card->shortname, bus->addr, bus->irq);
1955
1956         return 0;
1957 }
1958
1959 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1960 /* callback from request_firmware_nowait() */
1961 static void azx_firmware_cb(const struct firmware *fw, void *context)
1962 {
1963         struct snd_card *card = context;
1964         struct azx *chip = card->private_data;
1965         struct pci_dev *pci = chip->pci;
1966
1967         if (!fw) {
1968                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1969                 goto error;
1970         }
1971
1972         chip->fw = fw;
1973         if (!chip->disabled) {
1974                 /* continue probing */
1975                 if (azx_probe_continue(chip))
1976                         goto error;
1977         }
1978         return; /* OK */
1979
1980  error:
1981         snd_card_free(card);
1982         pci_set_drvdata(pci, NULL);
1983 }
1984 #endif
1985
1986 /*
1987  * HDA controller ops.
1988  */
1989
1990 /* PCI register access. */
1991 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1992 {
1993         writel(value, addr);
1994 }
1995
1996 static u32 pci_azx_readl(u32 __iomem *addr)
1997 {
1998         return readl(addr);
1999 }
2000
2001 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2002 {
2003         writew(value, addr);
2004 }
2005
2006 static u16 pci_azx_readw(u16 __iomem *addr)
2007 {
2008         return readw(addr);
2009 }
2010
2011 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2012 {
2013         writeb(value, addr);
2014 }
2015
2016 static u8 pci_azx_readb(u8 __iomem *addr)
2017 {
2018         return readb(addr);
2019 }
2020
2021 static int disable_msi_reset_irq(struct azx *chip)
2022 {
2023         struct hdac_bus *bus = azx_bus(chip);
2024         int err;
2025
2026         free_irq(bus->irq, chip);
2027         bus->irq = -1;
2028         pci_disable_msi(chip->pci);
2029         chip->msi = 0;
2030         err = azx_acquire_irq(chip, 1);
2031         if (err < 0)
2032                 return err;
2033
2034         return 0;
2035 }
2036
2037 /* DMA page allocation helpers.  */
2038 static int dma_alloc_pages(struct hdac_bus *bus,
2039                            int type,
2040                            size_t size,
2041                            struct snd_dma_buffer *buf)
2042 {
2043         struct azx *chip = bus_to_azx(bus);
2044
2045         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2046                 type = SNDRV_DMA_TYPE_DEV_UC;
2047         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2048 }
2049
2050 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2051 {
2052         snd_dma_free_pages(buf);
2053 }
2054
2055 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2056                              struct vm_area_struct *area)
2057 {
2058 #ifdef CONFIG_X86
2059         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2060         struct azx *chip = apcm->chip;
2061         if (chip->uc_buffer)
2062                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2063 #endif
2064 }
2065
2066 static const struct hdac_io_ops pci_hda_io_ops = {
2067         .reg_writel = pci_azx_writel,
2068         .reg_readl = pci_azx_readl,
2069         .reg_writew = pci_azx_writew,
2070         .reg_readw = pci_azx_readw,
2071         .reg_writeb = pci_azx_writeb,
2072         .reg_readb = pci_azx_readb,
2073         .dma_alloc_pages = dma_alloc_pages,
2074         .dma_free_pages = dma_free_pages,
2075 };
2076
2077 static const struct hda_controller_ops pci_hda_ops = {
2078         .disable_msi_reset_irq = disable_msi_reset_irq,
2079         .pcm_mmap_prepare = pcm_mmap_prepare,
2080         .position_check = azx_position_check,
2081         .link_power = azx_intel_link_power,
2082 };
2083
2084 static int azx_probe(struct pci_dev *pci,
2085                      const struct pci_device_id *pci_id)
2086 {
2087         static int dev;
2088         struct snd_card *card;
2089         struct hda_intel *hda;
2090         struct azx *chip;
2091         bool schedule_probe;
2092         int err;
2093
2094         if (dev >= SNDRV_CARDS)
2095                 return -ENODEV;
2096         if (!enable[dev]) {
2097                 dev++;
2098                 return -ENOENT;
2099         }
2100
2101         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2102                            0, &card);
2103         if (err < 0) {
2104                 dev_err(&pci->dev, "Error creating card!\n");
2105                 return err;
2106         }
2107
2108         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2109         if (err < 0)
2110                 goto out_free;
2111         card->private_data = chip;
2112         hda = container_of(chip, struct hda_intel, chip);
2113
2114         pci_set_drvdata(pci, card);
2115
2116         err = register_vga_switcheroo(chip);
2117         if (err < 0) {
2118                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2119                 goto out_free;
2120         }
2121
2122         if (check_hdmi_disabled(pci)) {
2123                 dev_info(card->dev, "VGA controller is disabled\n");
2124                 dev_info(card->dev, "Delaying initialization\n");
2125                 chip->disabled = true;
2126         }
2127
2128         schedule_probe = !chip->disabled;
2129
2130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2131         if (patch[dev] && *patch[dev]) {
2132                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2133                          patch[dev]);
2134                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2135                                               &pci->dev, GFP_KERNEL, card,
2136                                               azx_firmware_cb);
2137                 if (err < 0)
2138                         goto out_free;
2139                 schedule_probe = false; /* continued in azx_firmware_cb() */
2140         }
2141 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2142
2143 #ifndef CONFIG_SND_HDA_I915
2144         if (CONTROLLER_IN_GPU(pci))
2145                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2146 #endif
2147
2148         if (schedule_probe)
2149                 schedule_work(&hda->probe_work);
2150
2151         dev++;
2152         if (chip->disabled)
2153                 complete_all(&hda->probe_wait);
2154         return 0;
2155
2156 out_free:
2157         snd_card_free(card);
2158         return err;
2159 }
2160
2161 #ifdef CONFIG_PM
2162 /* On some boards setting power_save to a non 0 value leads to clicking /
2163  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2164  * figure out how to avoid these sounds, but that is not always feasible.
2165  * So we keep a list of devices where we disable powersaving as its known
2166  * to causes problems on these devices.
2167  */
2168 static struct snd_pci_quirk power_save_blacklist[] = {
2169         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2170         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2171         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2172         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2173         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2174         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2175         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2176         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2177         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2178         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2179         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2180         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2181         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2182         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2183         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2184         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2185         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2186         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2187         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2188         {}
2189 };
2190 #endif /* CONFIG_PM */
2191
2192 static void set_default_power_save(struct azx *chip)
2193 {
2194         int val = power_save;
2195
2196 #ifdef CONFIG_PM
2197         if (pm_blacklist) {
2198                 const struct snd_pci_quirk *q;
2199
2200                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2201                 if (q && val) {
2202                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2203                                  q->subvendor, q->subdevice);
2204                         val = 0;
2205                 }
2206         }
2207 #endif /* CONFIG_PM */
2208         snd_hda_set_power_save(&chip->bus, val * 1000);
2209 }
2210
2211 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2212 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2213         [AZX_DRIVER_NVIDIA] = 8,
2214         [AZX_DRIVER_TERA] = 1,
2215 };
2216
2217 static int azx_probe_continue(struct azx *chip)
2218 {
2219         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2220         struct hdac_bus *bus = azx_bus(chip);
2221         struct pci_dev *pci = chip->pci;
2222         int dev = chip->dev_index;
2223         int err;
2224
2225         hda->probe_continued = 1;
2226
2227         /* bind with i915 if needed */
2228         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2229                 err = snd_hdac_i915_init(bus);
2230                 if (err < 0) {
2231                         /* if the controller is bound only with HDMI/DP
2232                          * (for HSW and BDW), we need to abort the probe;
2233                          * for other chips, still continue probing as other
2234                          * codecs can be on the same link.
2235                          */
2236                         if (CONTROLLER_IN_GPU(pci)) {
2237                                 dev_err(chip->card->dev,
2238                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2239                                 goto out_free;
2240                         } else {
2241                                 /* don't bother any longer */
2242                                 chip->driver_caps &=
2243                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2244                         }
2245                 }
2246         }
2247
2248         /* Request display power well for the HDA controller or codec. For
2249          * Haswell/Broadwell, both the display HDA controller and codec need
2250          * this power. For other platforms, like Baytrail/Braswell, only the
2251          * display codec needs the power and it can be released after probe.
2252          */
2253         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2254                 /* HSW/BDW controllers need this power */
2255                 if (CONTROLLER_IN_GPU(pci))
2256                         hda->need_i915_power = 1;
2257
2258                 err = snd_hdac_display_power(bus, true);
2259                 if (err < 0) {
2260                         dev_err(chip->card->dev,
2261                                 "Cannot turn on display power on i915\n");
2262                         goto i915_power_fail;
2263                 }
2264         }
2265
2266         err = azx_first_init(chip);
2267         if (err < 0)
2268                 goto out_free;
2269
2270 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2271         chip->beep_mode = beep_mode[dev];
2272 #endif
2273
2274         /* create codec instances */
2275         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2276         if (err < 0)
2277                 goto out_free;
2278
2279 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2280         if (chip->fw) {
2281                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2282                                          chip->fw->data);
2283                 if (err < 0)
2284                         goto out_free;
2285 #ifndef CONFIG_PM
2286                 release_firmware(chip->fw); /* no longer needed */
2287                 chip->fw = NULL;
2288 #endif
2289         }
2290 #endif
2291         if ((probe_only[dev] & 1) == 0) {
2292                 err = azx_codec_configure(chip);
2293                 if (err < 0)
2294                         goto out_free;
2295         }
2296
2297         err = snd_card_register(chip->card);
2298         if (err < 0)
2299                 goto out_free;
2300
2301         setup_vga_switcheroo_runtime_pm(chip);
2302
2303         chip->running = 1;
2304         azx_add_card_list(chip);
2305
2306         set_default_power_save(chip);
2307
2308         if (azx_has_pm_runtime(chip))
2309                 pm_runtime_put_autosuspend(&pci->dev);
2310
2311 out_free:
2312         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2313                 && !hda->need_i915_power)
2314                 snd_hdac_display_power(bus, false);
2315
2316 i915_power_fail:
2317         if (err < 0)
2318                 hda->init_failed = 1;
2319         complete_all(&hda->probe_wait);
2320         return err;
2321 }
2322
2323 static void azx_remove(struct pci_dev *pci)
2324 {
2325         struct snd_card *card = pci_get_drvdata(pci);
2326         struct azx *chip;
2327         struct hda_intel *hda;
2328
2329         if (card) {
2330                 /* cancel the pending probing work */
2331                 chip = card->private_data;
2332                 hda = container_of(chip, struct hda_intel, chip);
2333                 /* FIXME: below is an ugly workaround.
2334                  * Both device_release_driver() and driver_probe_device()
2335                  * take *both* the device's and its parent's lock before
2336                  * calling the remove() and probe() callbacks.  The codec
2337                  * probe takes the locks of both the codec itself and its
2338                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2339                  * the PCI controller is unbound, it takes its lock, too
2340                  * ==> ouch, a deadlock!
2341                  * As a workaround, we unlock temporarily here the controller
2342                  * device during cancel_work_sync() call.
2343                  */
2344                 device_unlock(&pci->dev);
2345                 cancel_work_sync(&hda->probe_work);
2346                 device_lock(&pci->dev);
2347
2348                 snd_card_free(card);
2349         }
2350 }
2351
2352 static void azx_shutdown(struct pci_dev *pci)
2353 {
2354         struct snd_card *card = pci_get_drvdata(pci);
2355         struct azx *chip;
2356
2357         if (!card)
2358                 return;
2359         chip = card->private_data;
2360         if (chip && chip->running)
2361                 azx_stop_chip(chip);
2362 }
2363
2364 /* PCI IDs */
2365 static const struct pci_device_id azx_ids[] = {
2366         /* CPT */
2367         { PCI_DEVICE(0x8086, 0x1c20),
2368           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2369         /* PBG */
2370         { PCI_DEVICE(0x8086, 0x1d20),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2372         /* Panther Point */
2373         { PCI_DEVICE(0x8086, 0x1e20),
2374           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2375         /* Lynx Point */
2376         { PCI_DEVICE(0x8086, 0x8c20),
2377           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2378         /* 9 Series */
2379         { PCI_DEVICE(0x8086, 0x8ca0),
2380           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2381         /* Wellsburg */
2382         { PCI_DEVICE(0x8086, 0x8d20),
2383           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2384         { PCI_DEVICE(0x8086, 0x8d21),
2385           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2386         /* Lewisburg */
2387         { PCI_DEVICE(0x8086, 0xa1f0),
2388           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2389         { PCI_DEVICE(0x8086, 0xa270),
2390           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2391         /* Lynx Point-LP */
2392         { PCI_DEVICE(0x8086, 0x9c20),
2393           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2394         /* Lynx Point-LP */
2395         { PCI_DEVICE(0x8086, 0x9c21),
2396           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2397         /* Wildcat Point-LP */
2398         { PCI_DEVICE(0x8086, 0x9ca0),
2399           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2400         /* Sunrise Point */
2401         { PCI_DEVICE(0x8086, 0xa170),
2402           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2403         /* Sunrise Point-LP */
2404         { PCI_DEVICE(0x8086, 0x9d70),
2405           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2406         /* Kabylake */
2407         { PCI_DEVICE(0x8086, 0xa171),
2408           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2409         /* Kabylake-LP */
2410         { PCI_DEVICE(0x8086, 0x9d71),
2411           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2412         /* Kabylake-H */
2413         { PCI_DEVICE(0x8086, 0xa2f0),
2414           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2415         /* Coffelake */
2416         { PCI_DEVICE(0x8086, 0xa348),
2417           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2418         /* Cannonlake */
2419         { PCI_DEVICE(0x8086, 0x9dc8),
2420           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2421         /* Icelake */
2422         { PCI_DEVICE(0x8086, 0x34c8),
2423           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2424         /* Broxton-P(Apollolake) */
2425         { PCI_DEVICE(0x8086, 0x5a98),
2426           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2427         /* Broxton-T */
2428         { PCI_DEVICE(0x8086, 0x1a98),
2429           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2430         /* Gemini-Lake */
2431         { PCI_DEVICE(0x8086, 0x3198),
2432           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2433         /* Haswell */
2434         { PCI_DEVICE(0x8086, 0x0a0c),
2435           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2436         { PCI_DEVICE(0x8086, 0x0c0c),
2437           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2438         { PCI_DEVICE(0x8086, 0x0d0c),
2439           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2440         /* Broadwell */
2441         { PCI_DEVICE(0x8086, 0x160c),
2442           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2443         /* 5 Series/3400 */
2444         { PCI_DEVICE(0x8086, 0x3b56),
2445           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2446         /* Poulsbo */
2447         { PCI_DEVICE(0x8086, 0x811b),
2448           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2449         /* Oaktrail */
2450         { PCI_DEVICE(0x8086, 0x080a),
2451           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2452         /* BayTrail */
2453         { PCI_DEVICE(0x8086, 0x0f04),
2454           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2455         /* Braswell */
2456         { PCI_DEVICE(0x8086, 0x2284),
2457           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2458         /* ICH6 */
2459         { PCI_DEVICE(0x8086, 0x2668),
2460           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2461         /* ICH7 */
2462         { PCI_DEVICE(0x8086, 0x27d8),
2463           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2464         /* ESB2 */
2465         { PCI_DEVICE(0x8086, 0x269a),
2466           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2467         /* ICH8 */
2468         { PCI_DEVICE(0x8086, 0x284b),
2469           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2470         /* ICH9 */
2471         { PCI_DEVICE(0x8086, 0x293e),
2472           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2473         /* ICH9 */
2474         { PCI_DEVICE(0x8086, 0x293f),
2475           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2476         /* ICH10 */
2477         { PCI_DEVICE(0x8086, 0x3a3e),
2478           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2479         /* ICH10 */
2480         { PCI_DEVICE(0x8086, 0x3a6e),
2481           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2482         /* Generic Intel */
2483         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2484           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2485           .class_mask = 0xffffff,
2486           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2487         /* ATI SB 450/600/700/800/900 */
2488         { PCI_DEVICE(0x1002, 0x437b),
2489           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2490         { PCI_DEVICE(0x1002, 0x4383),
2491           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2492         /* AMD Hudson */
2493         { PCI_DEVICE(0x1022, 0x780d),
2494           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2495         /* AMD Raven */
2496         { PCI_DEVICE(0x1022, 0x15e3),
2497           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2498                          AZX_DCAPS_PM_RUNTIME },
2499         /* ATI HDMI */
2500         { PCI_DEVICE(0x1002, 0x0002),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x1308),
2503           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2504         { PCI_DEVICE(0x1002, 0x157a),
2505           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2506         { PCI_DEVICE(0x1002, 0x15b3),
2507           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2508         { PCI_DEVICE(0x1002, 0x793b),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x7919),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0x960f),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0x970f),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0x9840),
2517           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2518         { PCI_DEVICE(0x1002, 0xaa00),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa08),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa10),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa18),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa20),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa28),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa30),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa38),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa40),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa48),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa50),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa58),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa60),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa68),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa80),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa88),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0xaa90),
2551           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2552         { PCI_DEVICE(0x1002, 0xaa98),
2553           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2554         { PCI_DEVICE(0x1002, 0x9902),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaaa0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaaa8),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaab0),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaac0),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaac8),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaad8),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         { PCI_DEVICE(0x1002, 0xaae8),
2569           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2570         { PCI_DEVICE(0x1002, 0xaae0),
2571           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2572         { PCI_DEVICE(0x1002, 0xaaf0),
2573           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2574         /* VIA VT8251/VT8237A */
2575         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2576         /* VIA GFX VT7122/VX900 */
2577         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2578         /* VIA GFX VT6122/VX11 */
2579         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2580         /* SIS966 */
2581         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2582         /* ULI M5461 */
2583         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2584         /* NVIDIA MCP */
2585         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2586           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2587           .class_mask = 0xffffff,
2588           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2589         /* Teradici */
2590         { PCI_DEVICE(0x6549, 0x1200),
2591           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2592         { PCI_DEVICE(0x6549, 0x2200),
2593           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2594         /* Creative X-Fi (CA0110-IBG) */
2595         /* CTHDA chips */
2596         { PCI_DEVICE(0x1102, 0x0010),
2597           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2598         { PCI_DEVICE(0x1102, 0x0012),
2599           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2600 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2601         /* the following entry conflicts with snd-ctxfi driver,
2602          * as ctxfi driver mutates from HD-audio to native mode with
2603          * a special command sequence.
2604          */
2605         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2606           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2607           .class_mask = 0xffffff,
2608           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2609           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2610 #else
2611         /* this entry seems still valid -- i.e. without emu20kx chip */
2612         { PCI_DEVICE(0x1102, 0x0009),
2613           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2614           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2615 #endif
2616         /* CM8888 */
2617         { PCI_DEVICE(0x13f6, 0x5011),
2618           .driver_data = AZX_DRIVER_CMEDIA |
2619           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2620         /* Vortex86MX */
2621         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2622         /* VMware HDAudio */
2623         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2624         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2625         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2626           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2627           .class_mask = 0xffffff,
2628           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2629         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2630           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2631           .class_mask = 0xffffff,
2632           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2633         { 0, }
2634 };
2635 MODULE_DEVICE_TABLE(pci, azx_ids);
2636
2637 /* pci_driver definition */
2638 static struct pci_driver azx_driver = {
2639         .name = KBUILD_MODNAME,
2640         .id_table = azx_ids,
2641         .probe = azx_probe,
2642         .remove = azx_remove,
2643         .shutdown = azx_shutdown,
2644         .driver = {
2645                 .pm = AZX_PM_OPS,
2646         },
2647 };
2648
2649 module_pci_driver(azx_driver);