sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 static bool pm_blacklist = true;
 190 module_param(pm_blacklist, bool, 0644);
 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 192
 193 /* reset the HD-audio controller in power save mode.
 194  * this may give more power-saving, but will take longer time to
 195  * wake up.
 196  */
 197 static bool power_save_controller = 1;
 198 module_param(power_save_controller, bool, 0644);
 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 200 #else
 201 #define power_save      0
 202 #endif /* CONFIG_PM */
 203
 204 static int align_buffer_size = -1;
 205 module_param(align_buffer_size, bint, 0644);
 206 MODULE_PARM_DESC(align_buffer_size,
 207                 "Force buffer and period sizes to be multiple of 128 bytes.");
 208
 209 #ifdef CONFIG_X86
 210 static int hda_snoop = -1;
 211 module_param_named(snoop, hda_snoop, bint, 0444);
 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 213 #else
 214 #define hda_snoop               true
 215 #endif
 216
 217
 218 MODULE_LICENSE("GPL");
 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 220                          "{Intel, ICH6M},"
 221                          "{Intel, ICH7},"
 222                          "{Intel, ESB2},"
 223                          "{Intel, ICH8},"
 224                          "{Intel, ICH9},"
 225                          "{Intel, ICH10},"
 226                          "{Intel, PCH},"
 227                          "{Intel, CPT},"
 228                          "{Intel, PPT},"
 229                          "{Intel, LPT},"
 230                          "{Intel, LPT_LP},"
 231                          "{Intel, WPT_LP},"
 232                          "{Intel, SPT},"
 233                          "{Intel, SPT_LP},"
 234                          "{Intel, HPT},"
 235                          "{Intel, PBG},"
 236                          "{Intel, SCH},"
 237                          "{ATI, SB450},"
 238                          "{ATI, SB600},"
 239                          "{ATI, RS600},"
 240                          "{ATI, RS690},"
 241                          "{ATI, RS780},"
 242                          "{ATI, R600},"
 243                          "{ATI, RV630},"
 244                          "{ATI, RV610},"
 245                          "{ATI, RV670},"
 246                          "{ATI, RV635},"
 247                          "{ATI, RV620},"
 248                          "{ATI, RV770},"
 249                          "{VIA, VT8251},"
 250                          "{VIA, VT8237A},"
 251                          "{SiS, SIS966},"
 252                          "{ULI, M5461}}");
 253 MODULE_DESCRIPTION("Intel HDA driver");
 254
 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 257 #define SUPPORT_VGA_SWITCHEROO
 258 #endif
 259 #endif
 260
 261
 262 /*
 263  */
 264
 265 /* driver types */
 266 enum {
 267         AZX_DRIVER_ICH,
 268         AZX_DRIVER_PCH,
 269         AZX_DRIVER_SCH,
 270         AZX_DRIVER_SKL,
 271         AZX_DRIVER_HDMI,
 272         AZX_DRIVER_ATI,
 273         AZX_DRIVER_ATIHDMI,
 274         AZX_DRIVER_ATIHDMI_NS,
 275         AZX_DRIVER_VIA,
 276         AZX_DRIVER_SIS,
 277         AZX_DRIVER_ULI,
 278         AZX_DRIVER_NVIDIA,
 279         AZX_DRIVER_TERA,
 280         AZX_DRIVER_CTX,
 281         AZX_DRIVER_CTHDA,
 282         AZX_DRIVER_CMEDIA,
 283         AZX_DRIVER_GENERIC,
 284         AZX_NUM_DRIVERS, /* keep this as last entry */
 285 };
 286
 287 #define azx_get_snoop_type(chip) \
 288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 290
 291 /* quirks for old Intel chipsets */
 292 #define AZX_DCAPS_INTEL_ICH \
 293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 294
 295 /* quirks for Intel PCH */
 296 #define AZX_DCAPS_INTEL_PCH_BASE \
 297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 301 #define AZX_DCAPS_INTEL_PCH_NOPM \
 302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 303
 304 /* PCH for HSW/BDW; with runtime PM */
 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 306 #define AZX_DCAPS_INTEL_PCH \
 307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 308
 309 /* HSW HDMI */
 310 #define AZX_DCAPS_INTEL_HASWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 316 #define AZX_DCAPS_INTEL_BROADWELL \
 317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 319          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 320
 321 #define AZX_DCAPS_INTEL_BAYTRAIL \
 322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 323          AZX_DCAPS_I915_POWERWELL)
 324
 325 #define AZX_DCAPS_INTEL_BRASWELL \
 326         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 327          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 328
 329 #define AZX_DCAPS_INTEL_SKYLAKE \
 330         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 331          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 332          AZX_DCAPS_I915_POWERWELL)
 333
 334 #define AZX_DCAPS_INTEL_BROXTON \
 335         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 336          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 337          AZX_DCAPS_I915_POWERWELL)
 338
 339 /* quirks for ATI SB / AMD Hudson */
 340 #define AZX_DCAPS_PRESET_ATI_SB \
 341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 342          AZX_DCAPS_SNOOP_TYPE(ATI))
 343
 344 /* quirks for ATI/AMD HDMI */
 345 #define AZX_DCAPS_PRESET_ATI_HDMI \
 346         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 347          AZX_DCAPS_NO_MSI64)
 348
 349 /* quirks for ATI HDMI with snoop off */
 350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 351         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 352
 353 /* quirks for Nvidia */
 354 #define AZX_DCAPS_PRESET_NVIDIA \
 355         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 356          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 357
 358 #define AZX_DCAPS_PRESET_CTHDA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 360          AZX_DCAPS_NO_64BIT |\
 361          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 362
 363 /*
 364  * vga_switcheroo support
 365  */
 366 #ifdef SUPPORT_VGA_SWITCHEROO
 367 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 368 #else
 369 #define use_vga_switcheroo(chip)        0
 370 #endif
 371
 372 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 373                                         ((pci)->device == 0x0c0c) || \
 374                                         ((pci)->device == 0x0d0c) || \
 375                                         ((pci)->device == 0x160c))
 376
 377 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 378 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 379
 380 static char *driver_short_names[] = {
 381         [AZX_DRIVER_ICH] = "HDA Intel",
 382         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 383         [AZX_DRIVER_SCH] = "HDA Intel MID",
 384         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 385         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 386         [AZX_DRIVER_ATI] = "HDA ATI SB",
 387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 388         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 389         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 390         [AZX_DRIVER_SIS] = "HDA SIS966",
 391         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 392         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 393         [AZX_DRIVER_TERA] = "HDA Teradici",
 394         [AZX_DRIVER_CTX] = "HDA Creative",
 395         [AZX_DRIVER_CTHDA] = "HDA Creative",
 396         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 397         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 398 };
 399
 400 #ifdef CONFIG_X86
 401 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 402 {
 403         int pages;
 404
 405         if (azx_snoop(chip))
 406                 return;
 407         if (!dmab || !dmab->area || !dmab->bytes)
 408                 return;
 409
 410 #ifdef CONFIG_SND_DMA_SGBUF
 411         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 412                 struct snd_sg_buf *sgbuf = dmab->private_data;
 413                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 414                         return; /* deal with only CORB/RIRB buffers */
 415                 if (on)
 416                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 417                 else
 418                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 419                 return;
 420         }
 421 #endif
 422
 423         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 424         if (on)
 425                 set_memory_wc((unsigned long)dmab->area, pages);
 426         else
 427                 set_memory_wb((unsigned long)dmab->area, pages);
 428 }
 429
 430 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 431                                  bool on)
 432 {
 433         __mark_pages_wc(chip, buf, on);
 434 }
 435 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 436                                    struct snd_pcm_substream *substream, bool on)
 437 {
 438         if (azx_dev->wc_marked != on) {
 439                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 440                 azx_dev->wc_marked = on;
 441         }
 442 }
 443 #else
 444 /* NOP for other archs */
 445 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 446                                  bool on)
 447 {
 448 }
 449 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 450                                    struct snd_pcm_substream *substream, bool on)
 451 {
 452 }
 453 #endif
 454
 455 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 456
 457 /*
 458  * initialize the PCI registers
 459  */
 460 /* update bits in a PCI register byte */
 461 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 462                             unsigned char mask, unsigned char val)
 463 {
 464         unsigned char data;
 465
 466         pci_read_config_byte(pci, reg, &data);
 467         data &= ~mask;
 468         data |= (val & mask);
 469         pci_write_config_byte(pci, reg, data);
 470 }
 471
 472 static void azx_init_pci(struct azx *chip)
 473 {
 474         int snoop_type = azx_get_snoop_type(chip);
 475
 476         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 477          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 478          * Ensuring these bits are 0 clears playback static on some HD Audio
 479          * codecs.
 480          * The PCI register TCSEL is defined in the Intel manuals.
 481          */
 482         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 483                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 484                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 485         }
 486
 487         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 488          * we need to enable snoop.
 489          */
 490         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 491                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 492                         azx_snoop(chip));
 493                 update_pci_byte(chip->pci,
 494                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 495                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 496         }
 497
 498         /* For NVIDIA HDA, enable snoop */
 499         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 500                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 501                         azx_snoop(chip));
 502                 update_pci_byte(chip->pci,
 503                                 NVIDIA_HDA_TRANSREG_ADDR,
 504                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 505                 update_pci_byte(chip->pci,
 506                                 NVIDIA_HDA_ISTRM_COH,
 507                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 508                 update_pci_byte(chip->pci,
 509                                 NVIDIA_HDA_OSTRM_COH,
 510                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 511         }
 512
 513         /* Enable SCH/PCH snoop if needed */
 514         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 515                 unsigned short snoop;
 516                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 517                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 518                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 519                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 520                         if (!azx_snoop(chip))
 521                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 522                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 523                         pci_read_config_word(chip->pci,
 524                                 INTEL_SCH_HDA_DEVC, &snoop);
 525                 }
 526                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 527                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 528                         "Disabled" : "Enabled");
 529         }
 530 }
 531
 532 /*
 533  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 534  * and makes an audio stream sensitive to system latencies when
 535  * 24/32 bits are playing.
 536  * Adjusting threshold of DMA fifo to force the DMA request
 537  * sooner to improve latency tolerance at the expense of power.
 538  */
 539 static void bxt_reduce_dma_latency(struct azx *chip)
 540 {
 541         u32 val;
 542
 543         val = azx_readl(chip, VS_EM4L);
 544         val &= (0x3 << 20);
 545         azx_writel(chip, VS_EM4L, val);
 546 }
 547
 548 /*
 549  * ML_LCAP bits:
 550  *  bit 0: 6 MHz Supported
 551  *  bit 1: 12 MHz Supported
 552  *  bit 2: 24 MHz Supported
 553  *  bit 3: 48 MHz Supported
 554  *  bit 4: 96 MHz Supported
 555  *  bit 5: 192 MHz Supported
 556  */
 557 static int intel_get_lctl_scf(struct azx *chip)
 558 {
 559         struct hdac_bus *bus = azx_bus(chip);
 560         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 561         u32 val, t;
 562         int i;
 563
 564         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 565
 566         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 567                 t = preferred_bits[i];
 568                 if (val & (1 << t))
 569                         return t;
 570         }
 571
 572         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 573         return 0;
 574 }
 575
 576 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 577 {
 578         struct hdac_bus *bus = azx_bus(chip);
 579         u32 val;
 580         int timeout;
 581
 582         /*
 583          * the codecs are sharing the first link setting by default
 584          * If other links are enabled for stream, they need similar fix
 585          */
 586         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 587         val &= ~AZX_MLCTL_SPA;
 588         val |= state << AZX_MLCTL_SPA_SHIFT;
 589         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 590         /* wait for CPA */
 591         timeout = 50;
 592         while (timeout) {
 593                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 594                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 595                         return 0;
 596                 timeout--;
 597                 udelay(10);
 598         }
 599
 600         return -1;
 601 }
 602
 603 static void intel_init_lctl(struct azx *chip)
 604 {
 605         struct hdac_bus *bus = azx_bus(chip);
 606         u32 val;
 607         int ret;
 608
 609         /* 0. check lctl register value is correct or not */
 610         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 611         /* if SCF is already set, let's use it */
 612         if ((val & ML_LCTL_SCF_MASK) != 0)
 613                 return;
 614
 615         /*
 616          * Before operating on SPA, CPA must match SPA.
 617          * Any deviation may result in undefined behavior.
 618          */
 619         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 620                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 621                 return;
 622
 623         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 624         ret = intel_ml_lctl_set_power(chip, 0);
 625         udelay(100);
 626         if (ret)
 627                 goto set_spa;
 628
 629         /* 2. update SCF to select a properly audio clock*/
 630         val &= ~ML_LCTL_SCF_MASK;
 631         val |= intel_get_lctl_scf(chip);
 632         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 633
 634 set_spa:
 635         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 636         intel_ml_lctl_set_power(chip, 1);
 637         udelay(100);
 638 }
 639
 640 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 641 {
 642         struct hdac_bus *bus = azx_bus(chip);
 643         struct pci_dev *pci = chip->pci;
 644         u32 val;
 645
 646         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 647                 snd_hdac_set_codec_wakeup(bus, true);
 648         if (chip->driver_type == AZX_DRIVER_SKL) {
 649                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 650                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 651                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 652         }
 653         azx_init_chip(chip, full_reset);
 654         if (chip->driver_type == AZX_DRIVER_SKL) {
 655                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 656                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 657                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 658         }
 659         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 660                 snd_hdac_set_codec_wakeup(bus, false);
 661
 662         /* reduce dma latency to avoid noise */
 663         if (IS_BXT(pci))
 664                 bxt_reduce_dma_latency(chip);
 665
 666         if (bus->mlcap != NULL)
 667                 intel_init_lctl(chip);
 668 }
 669
 670 /* calculate runtime delay from LPIB */
 671 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 672                                    unsigned int pos)
 673 {
 674         struct snd_pcm_substream *substream = azx_dev->core.substream;
 675         int stream = substream->stream;
 676         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 677         int delay;
 678
 679         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 680                 delay = pos - lpib_pos;
 681         else
 682                 delay = lpib_pos - pos;
 683         if (delay < 0) {
 684                 if (delay >= azx_dev->core.delay_negative_threshold)
 685                         delay = 0;
 686                 else
 687                         delay += azx_dev->core.bufsize;
 688         }
 689
 690         if (delay >= azx_dev->core.period_bytes) {
 691                 dev_info(chip->card->dev,
 692                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 693                          delay, azx_dev->core.period_bytes);
 694                 delay = 0;
 695                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 696                 chip->get_delay[stream] = NULL;
 697         }
 698
 699         return bytes_to_frames(substream->runtime, delay);
 700 }
 701
 702 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 703
 704 /* called from IRQ */
 705 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 706 {
 707         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 708         int ok;
 709
 710         ok = azx_position_ok(chip, azx_dev);
 711         if (ok == 1) {
 712                 azx_dev->irq_pending = 0;
 713                 return ok;
 714         } else if (ok == 0) {
 715                 /* bogus IRQ, process it later */
 716                 azx_dev->irq_pending = 1;
 717                 schedule_work(&hda->irq_pending_work);
 718         }
 719         return 0;
 720 }
 721
 722 /* Enable/disable i915 display power for the link */
 723 static int azx_intel_link_power(struct azx *chip, bool enable)
 724 {
 725         struct hdac_bus *bus = azx_bus(chip);
 726
 727         return snd_hdac_display_power(bus, enable);
 728 }
 729
 730 /*
 731  * Check whether the current DMA position is acceptable for updating
 732  * periods.  Returns non-zero if it's OK.
 733  *
 734  * Many HD-audio controllers appear pretty inaccurate about
 735  * the update-IRQ timing.  The IRQ is issued before actually the
 736  * data is processed.  So, we need to process it afterwords in a
 737  * workqueue.
 738  */
 739 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 740 {
 741         struct snd_pcm_substream *substream = azx_dev->core.substream;
 742         int stream = substream->stream;
 743         u32 wallclk;
 744         unsigned int pos;
 745
 746         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 747         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 748                 return -1;      /* bogus (too early) interrupt */
 749
 750         if (chip->get_position[stream])
 751                 pos = chip->get_position[stream](chip, azx_dev);
 752         else { /* use the position buffer as default */
 753                 pos = azx_get_pos_posbuf(chip, azx_dev);
 754                 if (!pos || pos == (u32)-1) {
 755                         dev_info(chip->card->dev,
 756                                  "Invalid position buffer, using LPIB read method instead.\n");
 757                         chip->get_position[stream] = azx_get_pos_lpib;
 758                         if (chip->get_position[0] == azx_get_pos_lpib &&
 759                             chip->get_position[1] == azx_get_pos_lpib)
 760                                 azx_bus(chip)->use_posbuf = false;
 761                         pos = azx_get_pos_lpib(chip, azx_dev);
 762                         chip->get_delay[stream] = NULL;
 763                 } else {
 764                         chip->get_position[stream] = azx_get_pos_posbuf;
 765                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 766                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 767                 }
 768         }
 769
 770         if (pos >= azx_dev->core.bufsize)
 771                 pos = 0;
 772
 773         if (WARN_ONCE(!azx_dev->core.period_bytes,
 774                       "hda-intel: zero azx_dev->period_bytes"))
 775                 return -1; /* this shouldn't happen! */
 776         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 777             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 778                 /* NG - it's below the first next period boundary */
 779                 return chip->bdl_pos_adj ? 0 : -1;
 780         azx_dev->core.start_wallclk += wallclk;
 781         return 1; /* OK, it's fine */
 782 }
 783
 784 /*
 785  * The work for pending PCM period updates.
 786  */
 787 static void azx_irq_pending_work(struct work_struct *work)
 788 {
 789         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 790         struct azx *chip = &hda->chip;
 791         struct hdac_bus *bus = azx_bus(chip);
 792         struct hdac_stream *s;
 793         int pending, ok;
 794
 795         if (!hda->irq_pending_warned) {
 796                 dev_info(chip->card->dev,
 797                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 798                          chip->card->number);
 799                 hda->irq_pending_warned = 1;
 800         }
 801
 802         for (;;) {
 803                 pending = 0;
 804                 spin_lock_irq(&bus->reg_lock);
 805                 list_for_each_entry(s, &bus->stream_list, list) {
 806                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 807                         if (!azx_dev->irq_pending ||
 808                             !s->substream ||
 809                             !s->running)
 810                                 continue;
 811                         ok = azx_position_ok(chip, azx_dev);
 812                         if (ok > 0) {
 813                                 azx_dev->irq_pending = 0;
 814                                 spin_unlock(&bus->reg_lock);
 815                                 snd_pcm_period_elapsed(s->substream);
 816                                 spin_lock(&bus->reg_lock);
 817                         } else if (ok < 0) {
 818                                 pending = 0;    /* too early */
 819                         } else
 820                                 pending++;
 821                 }
 822                 spin_unlock_irq(&bus->reg_lock);
 823                 if (!pending)
 824                         return;
 825                 msleep(1);
 826         }
 827 }
 828
 829 /* clear irq_pending flags and assure no on-going workq */
 830 static void azx_clear_irq_pending(struct azx *chip)
 831 {
 832         struct hdac_bus *bus = azx_bus(chip);
 833         struct hdac_stream *s;
 834
 835         spin_lock_irq(&bus->reg_lock);
 836         list_for_each_entry(s, &bus->stream_list, list) {
 837                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 838                 azx_dev->irq_pending = 0;
 839         }
 840         spin_unlock_irq(&bus->reg_lock);
 841 }
 842
 843 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 844 {
 845         struct hdac_bus *bus = azx_bus(chip);
 846
 847         if (request_irq(chip->pci->irq, azx_interrupt,
 848                         chip->msi ? 0 : IRQF_SHARED,
 849                         chip->card->irq_descr, chip)) {
 850                 dev_err(chip->card->dev,
 851                         "unable to grab IRQ %d, disabling device\n",
 852                         chip->pci->irq);
 853                 if (do_disconnect)
 854                         snd_card_disconnect(chip->card);
 855                 return -1;
 856         }
 857         bus->irq = chip->pci->irq;
 858         pci_intx(chip->pci, !chip->msi);
 859         return 0;
 860 }
 861
 862 /* get the current DMA position with correction on VIA chips */
 863 static unsigned int azx_via_get_position(struct azx *chip,
 864                                          struct azx_dev *azx_dev)
 865 {
 866         unsigned int link_pos, mini_pos, bound_pos;
 867         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 868         unsigned int fifo_size;
 869
 870         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 871         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 872                 /* Playback, no problem using link position */
 873                 return link_pos;
 874         }
 875
 876         /* Capture */
 877         /* For new chipset,
 878          * use mod to get the DMA position just like old chipset
 879          */
 880         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 881         mod_dma_pos %= azx_dev->core.period_bytes;
 882
 883         /* azx_dev->fifo_size can't get FIFO size of in stream.
 884          * Get from base address + offset.
 885          */
 886         fifo_size = readw(azx_bus(chip)->remap_addr +
 887                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 888
 889         if (azx_dev->insufficient) {
 890                 /* Link position never gather than FIFO size */
 891                 if (link_pos <= fifo_size)
 892                         return 0;
 893
 894                 azx_dev->insufficient = 0;
 895         }
 896
 897         if (link_pos <= fifo_size)
 898                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 899         else
 900                 mini_pos = link_pos - fifo_size;
 901
 902         /* Find nearest previous boudary */
 903         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 904         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 905         if (mod_link_pos >= fifo_size)
 906                 bound_pos = link_pos - mod_link_pos;
 907         else if (mod_dma_pos >= mod_mini_pos)
 908                 bound_pos = mini_pos - mod_mini_pos;
 909         else {
 910                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 911                 if (bound_pos >= azx_dev->core.bufsize)
 912                         bound_pos = 0;
 913         }
 914
 915         /* Calculate real DMA position we want */
 916         return bound_pos + mod_dma_pos;
 917 }
 918
 919 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 920                                          struct azx_dev *azx_dev)
 921 {
 922         return _snd_hdac_chip_readl(azx_bus(chip),
 923                                     AZX_REG_VS_SDXDPIB_XBASE +
 924                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 925                                      azx_dev->core.index));
 926 }
 927
 928 /* get the current DMA position with correction on SKL+ chips */
 929 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 930 {
 931         /* DPIB register gives a more accurate position for playback */
 932         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 933                 return azx_skl_get_dpib_pos(chip, azx_dev);
 934
 935         /* For capture, we need to read posbuf, but it requires a delay
 936          * for the possible boundary overlap; the read of DPIB fetches the
 937          * actual posbuf
 938          */
 939         udelay(20);
 940         azx_skl_get_dpib_pos(chip, azx_dev);
 941         return azx_get_pos_posbuf(chip, azx_dev);
 942 }
 943
 944 #ifdef CONFIG_PM
 945 static DEFINE_MUTEX(card_list_lock);
 946 static LIST_HEAD(card_list);
 947
 948 static void azx_add_card_list(struct azx *chip)
 949 {
 950         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 951         mutex_lock(&card_list_lock);
 952         list_add(&hda->list, &card_list);
 953         mutex_unlock(&card_list_lock);
 954 }
 955
 956 static void azx_del_card_list(struct azx *chip)
 957 {
 958         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 959         mutex_lock(&card_list_lock);
 960         list_del_init(&hda->list);
 961         mutex_unlock(&card_list_lock);
 962 }
 963
 964 /* trigger power-save check at writing parameter */
 965 static int param_set_xint(const char *val, const struct kernel_param *kp)
 966 {
 967         struct hda_intel *hda;
 968         struct azx *chip;
 969         int prev = power_save;
 970         int ret = param_set_int(val, kp);
 971
 972         if (ret || prev == power_save)
 973                 return ret;
 974
 975         mutex_lock(&card_list_lock);
 976         list_for_each_entry(hda, &card_list, list) {
 977                 chip = &hda->chip;
 978                 if (!hda->probe_continued || chip->disabled)
 979                         continue;
 980                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 981         }
 982         mutex_unlock(&card_list_lock);
 983         return 0;
 984 }
 985 #else
 986 #define azx_add_card_list(chip) /* NOP */
 987 #define azx_del_card_list(chip) /* NOP */
 988 #endif /* CONFIG_PM */
 989
 990 #ifdef CONFIG_PM_SLEEP
 991 /*
 992  * power management
 993  */
 994 static int azx_suspend(struct device *dev)
 995 {
 996         struct snd_card *card = dev_get_drvdata(dev);
 997         struct azx *chip;
 998         struct hda_intel *hda;
 999         struct hdac_bus *bus;
1000
1001         if (!card)
1002                 return 0;
1003
1004         chip = card->private_data;
1005         hda = container_of(chip, struct hda_intel, chip);
1006         if (chip->disabled || hda->init_failed || !chip->running)
1007                 return 0;
1008
1009         bus = azx_bus(chip);
1010         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1011         azx_clear_irq_pending(chip);
1012         azx_stop_chip(chip);
1013         azx_enter_link_reset(chip);
1014         if (bus->irq >= 0) {
1015                 free_irq(bus->irq, chip);
1016                 bus->irq = -1;
1017         }
1018
1019         if (chip->msi)
1020                 pci_disable_msi(chip->pci);
1021         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1022                 && hda->need_i915_power)
1023                 snd_hdac_display_power(bus, false);
1024
1025         trace_azx_suspend(chip);
1026         return 0;
1027 }
1028
1029 static int azx_resume(struct device *dev)
1030 {
1031         struct pci_dev *pci = to_pci_dev(dev);
1032         struct snd_card *card = dev_get_drvdata(dev);
1033         struct azx *chip;
1034         struct hda_intel *hda;
1035         struct hdac_bus *bus;
1036
1037         if (!card)
1038                 return 0;
1039
1040         chip = card->private_data;
1041         hda = container_of(chip, struct hda_intel, chip);
1042         bus = azx_bus(chip);
1043         if (chip->disabled || hda->init_failed || !chip->running)
1044                 return 0;
1045
1046         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1047                 snd_hdac_display_power(bus, true);
1048                 if (hda->need_i915_power)
1049                         snd_hdac_i915_set_bclk(bus);
1050         }
1051
1052         if (chip->msi)
1053                 if (pci_enable_msi(pci) < 0)
1054                         chip->msi = 0;
1055         if (azx_acquire_irq(chip, 1) < 0)
1056                 return -EIO;
1057         azx_init_pci(chip);
1058
1059         hda_intel_init_chip(chip, true);
1060
1061         /* power down again for link-controlled chips */
1062         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1063             !hda->need_i915_power)
1064                 snd_hdac_display_power(bus, false);
1065
1066         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1067
1068         trace_azx_resume(chip);
1069         return 0;
1070 }
1071
1072 /* put codec down to D3 at hibernation for Intel SKL+;
1073  * otherwise BIOS may still access the codec and screw up the driver
1074  */
1075 static int azx_freeze_noirq(struct device *dev)
1076 {
1077         struct snd_card *card = dev_get_drvdata(dev);
1078         struct azx *chip = card->private_data;
1079         struct pci_dev *pci = to_pci_dev(dev);
1080
1081         if (chip->driver_type == AZX_DRIVER_SKL)
1082                 pci_set_power_state(pci, PCI_D3hot);
1083
1084         return 0;
1085 }
1086
1087 static int azx_thaw_noirq(struct device *dev)
1088 {
1089         struct snd_card *card = dev_get_drvdata(dev);
1090         struct azx *chip = card->private_data;
1091         struct pci_dev *pci = to_pci_dev(dev);
1092
1093         if (chip->driver_type == AZX_DRIVER_SKL)
1094                 pci_set_power_state(pci, PCI_D0);
1095
1096         return 0;
1097 }
1098 #endif /* CONFIG_PM_SLEEP */
1099
1100 #ifdef CONFIG_PM
1101 static int azx_runtime_suspend(struct device *dev)
1102 {
1103         struct snd_card *card = dev_get_drvdata(dev);
1104         struct azx *chip;
1105         struct hda_intel *hda;
1106
1107         if (!card)
1108                 return 0;
1109
1110         chip = card->private_data;
1111         hda = container_of(chip, struct hda_intel, chip);
1112         if (chip->disabled || hda->init_failed)
1113                 return 0;
1114
1115         if (!azx_has_pm_runtime(chip))
1116                 return 0;
1117
1118         /* enable controller wake up event */
1119         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1120                   STATESTS_INT_MASK);
1121
1122         azx_stop_chip(chip);
1123         azx_enter_link_reset(chip);
1124         azx_clear_irq_pending(chip);
1125         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1126                 && hda->need_i915_power)
1127                 snd_hdac_display_power(azx_bus(chip), false);
1128
1129         trace_azx_runtime_suspend(chip);
1130         return 0;
1131 }
1132
1133 static int azx_runtime_resume(struct device *dev)
1134 {
1135         struct snd_card *card = dev_get_drvdata(dev);
1136         struct azx *chip;
1137         struct hda_intel *hda;
1138         struct hdac_bus *bus;
1139         struct hda_codec *codec;
1140         int status;
1141
1142         if (!card)
1143                 return 0;
1144
1145         chip = card->private_data;
1146         hda = container_of(chip, struct hda_intel, chip);
1147         bus = azx_bus(chip);
1148         if (chip->disabled || hda->init_failed)
1149                 return 0;
1150
1151         if (!azx_has_pm_runtime(chip))
1152                 return 0;
1153
1154         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1155                 snd_hdac_display_power(bus, true);
1156                 if (hda->need_i915_power)
1157                         snd_hdac_i915_set_bclk(bus);
1158         }
1159
1160         /* Read STATESTS before controller reset */
1161         status = azx_readw(chip, STATESTS);
1162
1163         azx_init_pci(chip);
1164         hda_intel_init_chip(chip, true);
1165
1166         if (status) {
1167                 list_for_each_codec(codec, &chip->bus)
1168                         if (status & (1 << codec->addr))
1169                                 schedule_delayed_work(&codec->jackpoll_work,
1170                                                       codec->jackpoll_interval);
1171         }
1172
1173         /* disable controller Wake Up event*/
1174         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1175                         ~STATESTS_INT_MASK);
1176
1177         /* power down again for link-controlled chips */
1178         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1179             !hda->need_i915_power)
1180                 snd_hdac_display_power(bus, false);
1181
1182         trace_azx_runtime_resume(chip);
1183         return 0;
1184 }
1185
1186 static int azx_runtime_idle(struct device *dev)
1187 {
1188         struct snd_card *card = dev_get_drvdata(dev);
1189         struct azx *chip;
1190         struct hda_intel *hda;
1191
1192         if (!card)
1193                 return 0;
1194
1195         chip = card->private_data;
1196         hda = container_of(chip, struct hda_intel, chip);
1197         if (chip->disabled || hda->init_failed)
1198                 return 0;
1199
1200         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1201             azx_bus(chip)->codec_powered || !chip->running)
1202                 return -EBUSY;
1203
1204         return 0;
1205 }
1206
1207 static const struct dev_pm_ops azx_pm = {
1208         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1209 #ifdef CONFIG_PM_SLEEP
1210         .freeze_noirq = azx_freeze_noirq,
1211         .thaw_noirq = azx_thaw_noirq,
1212 #endif
1213         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1214 };
1215
1216 #define AZX_PM_OPS      &azx_pm
1217 #else
1218 #define AZX_PM_OPS      NULL
1219 #endif /* CONFIG_PM */
1220
1221
1222 static int azx_probe_continue(struct azx *chip);
1223
1224 #ifdef SUPPORT_VGA_SWITCHEROO
1225 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1226
1227 static void azx_vs_set_state(struct pci_dev *pci,
1228                              enum vga_switcheroo_state state)
1229 {
1230         struct snd_card *card = pci_get_drvdata(pci);
1231         struct azx *chip = card->private_data;
1232         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1233         struct hda_codec *codec;
1234         bool disabled;
1235
1236         wait_for_completion(&hda->probe_wait);
1237         if (hda->init_failed)
1238                 return;
1239
1240         disabled = (state == VGA_SWITCHEROO_OFF);
1241         if (chip->disabled == disabled)
1242                 return;
1243
1244         if (!hda->probe_continued) {
1245                 chip->disabled = disabled;
1246                 if (!disabled) {
1247                         dev_info(chip->card->dev,
1248                                  "Start delayed initialization\n");
1249                         if (azx_probe_continue(chip) < 0) {
1250                                 dev_err(chip->card->dev, "initialization error\n");
1251                                 hda->init_failed = true;
1252                         }
1253                 }
1254         } else {
1255                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1256                          disabled ? "Disabling" : "Enabling");
1257                 if (disabled) {
1258                         list_for_each_codec(codec, &chip->bus) {
1259                                 pm_runtime_suspend(hda_codec_dev(codec));
1260                                 pm_runtime_disable(hda_codec_dev(codec));
1261                         }
1262                         pm_runtime_suspend(card->dev);
1263                         pm_runtime_disable(card->dev);
1264                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1265                          * however we have no ACPI handle, so pci/acpi can't put us there,
1266                          * put ourselves there */
1267                         pci->current_state = PCI_D3cold;
1268                         chip->disabled = true;
1269                         if (snd_hda_lock_devices(&chip->bus))
1270                                 dev_warn(chip->card->dev,
1271                                          "Cannot lock devices!\n");
1272                 } else {
1273                         snd_hda_unlock_devices(&chip->bus);
1274                         chip->disabled = false;
1275                         pm_runtime_enable(card->dev);
1276                         list_for_each_codec(codec, &chip->bus) {
1277                                 pm_runtime_enable(hda_codec_dev(codec));
1278                                 pm_runtime_resume(hda_codec_dev(codec));
1279                         }
1280                 }
1281         }
1282 }
1283
1284 static bool azx_vs_can_switch(struct pci_dev *pci)
1285 {
1286         struct snd_card *card = pci_get_drvdata(pci);
1287         struct azx *chip = card->private_data;
1288         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289
1290         wait_for_completion(&hda->probe_wait);
1291         if (hda->init_failed)
1292                 return false;
1293         if (chip->disabled || !hda->probe_continued)
1294                 return true;
1295         if (snd_hda_lock_devices(&chip->bus))
1296                 return false;
1297         snd_hda_unlock_devices(&chip->bus);
1298         return true;
1299 }
1300
1301 static void init_vga_switcheroo(struct azx *chip)
1302 {
1303         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1304         struct pci_dev *p = get_bound_vga(chip->pci);
1305         if (p) {
1306                 dev_info(chip->card->dev,
1307                          "Handle vga_switcheroo audio client\n");
1308                 hda->use_vga_switcheroo = 1;
1309                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1310                 pci_dev_put(p);
1311         }
1312 }
1313
1314 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1315         .set_gpu_state = azx_vs_set_state,
1316         .can_switch = azx_vs_can_switch,
1317 };
1318
1319 static int register_vga_switcheroo(struct azx *chip)
1320 {
1321         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1322         struct pci_dev *p;
1323         int err;
1324
1325         if (!hda->use_vga_switcheroo)
1326                 return 0;
1327
1328         p = get_bound_vga(chip->pci);
1329         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1330         pci_dev_put(p);
1331
1332         if (err < 0)
1333                 return err;
1334         hda->vga_switcheroo_registered = 1;
1335
1336         return 0;
1337 }
1338 #else
1339 #define init_vga_switcheroo(chip)               /* NOP */
1340 #define register_vga_switcheroo(chip)           0
1341 #define check_hdmi_disabled(pci)        false
1342 #endif /* SUPPORT_VGA_SWITCHER */
1343
1344 /*
1345  * destructor
1346  */
1347 static int azx_free(struct azx *chip)
1348 {
1349         struct pci_dev *pci = chip->pci;
1350         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1351         struct hdac_bus *bus = azx_bus(chip);
1352
1353         if (azx_has_pm_runtime(chip) && chip->running)
1354                 pm_runtime_get_noresume(&pci->dev);
1355
1356         azx_del_card_list(chip);
1357
1358         hda->init_failed = 1; /* to be sure */
1359         complete_all(&hda->probe_wait);
1360
1361         if (use_vga_switcheroo(hda)) {
1362                 if (chip->disabled && hda->probe_continued)
1363                         snd_hda_unlock_devices(&chip->bus);
1364                 if (hda->vga_switcheroo_registered)
1365                         vga_switcheroo_unregister_client(chip->pci);
1366         }
1367
1368         if (bus->chip_init) {
1369                 azx_clear_irq_pending(chip);
1370                 azx_stop_all_streams(chip);
1371                 azx_stop_chip(chip);
1372         }
1373
1374         if (bus->irq >= 0)
1375                 free_irq(bus->irq, (void*)chip);
1376         if (chip->msi)
1377                 pci_disable_msi(chip->pci);
1378         iounmap(bus->remap_addr);
1379
1380         azx_free_stream_pages(chip);
1381         azx_free_streams(chip);
1382         snd_hdac_bus_exit(bus);
1383
1384         if (chip->region_requested)
1385                 pci_release_regions(chip->pci);
1386
1387         pci_disable_device(chip->pci);
1388 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1389         release_firmware(chip->fw);
1390 #endif
1391
1392         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1393                 if (hda->need_i915_power)
1394                         snd_hdac_display_power(bus, false);
1395         }
1396         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1397                 snd_hdac_i915_exit(bus);
1398         kfree(hda);
1399
1400         return 0;
1401 }
1402
1403 static int azx_dev_disconnect(struct snd_device *device)
1404 {
1405         struct azx *chip = device->device_data;
1406
1407         chip->bus.shutdown = 1;
1408         return 0;
1409 }
1410
1411 static int azx_dev_free(struct snd_device *device)
1412 {
1413         return azx_free(device->device_data);
1414 }
1415
1416 #ifdef SUPPORT_VGA_SWITCHEROO
1417 /*
1418  * Check of disabled HDMI controller by vga_switcheroo
1419  */
1420 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1421 {
1422         struct pci_dev *p;
1423
1424         /* check only discrete GPU */
1425         switch (pci->vendor) {
1426         case PCI_VENDOR_ID_ATI:
1427         case PCI_VENDOR_ID_AMD:
1428         case PCI_VENDOR_ID_NVIDIA:
1429                 if (pci->devfn == 1) {
1430                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1431                                                         pci->bus->number, 0);
1432                         if (p) {
1433                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1434                                         return p;
1435                                 pci_dev_put(p);
1436                         }
1437                 }
1438                 break;
1439         }
1440         return NULL;
1441 }
1442
1443 static bool check_hdmi_disabled(struct pci_dev *pci)
1444 {
1445         bool vga_inactive = false;
1446         struct pci_dev *p = get_bound_vga(pci);
1447
1448         if (p) {
1449                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1450                         vga_inactive = true;
1451                 pci_dev_put(p);
1452         }
1453         return vga_inactive;
1454 }
1455 #endif /* SUPPORT_VGA_SWITCHEROO */
1456
1457 /*
1458  * white/black-listing for position_fix
1459  */
1460 static struct snd_pci_quirk position_fix_list[] = {
1461         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1462         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1463         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1464         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1465         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1466         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1467         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1468         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1469         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1470         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1471         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1472         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1473         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1474         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1475         {}
1476 };
1477
1478 static int check_position_fix(struct azx *chip, int fix)
1479 {
1480         const struct snd_pci_quirk *q;
1481
1482         switch (fix) {
1483         case POS_FIX_AUTO:
1484         case POS_FIX_LPIB:
1485         case POS_FIX_POSBUF:
1486         case POS_FIX_VIACOMBO:
1487         case POS_FIX_COMBO:
1488         case POS_FIX_SKL:
1489                 return fix;
1490         }
1491
1492         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1493         if (q) {
1494                 dev_info(chip->card->dev,
1495                          "position_fix set to %d for device %04x:%04x\n",
1496                          q->value, q->subvendor, q->subdevice);
1497                 return q->value;
1498         }
1499
1500         /* Check VIA/ATI HD Audio Controller exist */
1501         if (chip->driver_type == AZX_DRIVER_VIA) {
1502                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1503                 return POS_FIX_VIACOMBO;
1504         }
1505         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1506                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1507                 return POS_FIX_LPIB;
1508         }
1509         if (chip->driver_type == AZX_DRIVER_SKL) {
1510                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1511                 return POS_FIX_SKL;
1512         }
1513         return POS_FIX_AUTO;
1514 }
1515
1516 static void assign_position_fix(struct azx *chip, int fix)
1517 {
1518         static azx_get_pos_callback_t callbacks[] = {
1519                 [POS_FIX_AUTO] = NULL,
1520                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1521                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1522                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1523                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1524                 [POS_FIX_SKL] = azx_get_pos_skl,
1525         };
1526
1527         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1528
1529         /* combo mode uses LPIB only for playback */
1530         if (fix == POS_FIX_COMBO)
1531                 chip->get_position[1] = NULL;
1532
1533         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1534             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1535                 chip->get_delay[0] = chip->get_delay[1] =
1536                         azx_get_delay_from_lpib;
1537         }
1538
1539 }
1540
1541 /*
1542  * black-lists for probe_mask
1543  */
1544 static struct snd_pci_quirk probe_mask_list[] = {
1545         /* Thinkpad often breaks the controller communication when accessing
1546          * to the non-working (or non-existing) modem codec slot.
1547          */
1548         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1549         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1550         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1551         /* broken BIOS */
1552         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1553         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1554         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1555         /* forced codec slots */
1556         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1557         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1558         /* WinFast VP200 H (Teradici) user reported broken communication */
1559         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1560         {}
1561 };
1562
1563 #define AZX_FORCE_CODEC_MASK    0x100
1564
1565 static void check_probe_mask(struct azx *chip, int dev)
1566 {
1567         const struct snd_pci_quirk *q;
1568
1569         chip->codec_probe_mask = probe_mask[dev];
1570         if (chip->codec_probe_mask == -1) {
1571                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1572                 if (q) {
1573                         dev_info(chip->card->dev,
1574                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1575                                  q->value, q->subvendor, q->subdevice);
1576                         chip->codec_probe_mask = q->value;
1577                 }
1578         }
1579
1580         /* check forced option */
1581         if (chip->codec_probe_mask != -1 &&
1582             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1583                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1584                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1585                          (int)azx_bus(chip)->codec_mask);
1586         }
1587 }
1588
1589 /*
1590  * white/black-list for enable_msi
1591  */
1592 static struct snd_pci_quirk msi_black_list[] = {
1593         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1594         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1595         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1596         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1597         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1598         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1599         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1600         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1601         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1602         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1603         {}
1604 };
1605
1606 static void check_msi(struct azx *chip)
1607 {
1608         const struct snd_pci_quirk *q;
1609
1610         if (enable_msi >= 0) {
1611                 chip->msi = !!enable_msi;
1612                 return;
1613         }
1614         chip->msi = 1;  /* enable MSI as default */
1615         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1616         if (q) {
1617                 dev_info(chip->card->dev,
1618                          "msi for device %04x:%04x set to %d\n",
1619                          q->subvendor, q->subdevice, q->value);
1620                 chip->msi = q->value;
1621                 return;
1622         }
1623
1624         /* NVidia chipsets seem to cause troubles with MSI */
1625         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1626                 dev_info(chip->card->dev, "Disabling MSI\n");
1627                 chip->msi = 0;
1628         }
1629 }
1630
1631 /* check the snoop mode availability */
1632 static void azx_check_snoop_available(struct azx *chip)
1633 {
1634         int snoop = hda_snoop;
1635
1636         if (snoop >= 0) {
1637                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1638                          snoop ? "snoop" : "non-snoop");
1639                 chip->snoop = snoop;
1640                 return;
1641         }
1642
1643         snoop = true;
1644         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1645             chip->driver_type == AZX_DRIVER_VIA) {
1646                 /* force to non-snoop mode for a new VIA controller
1647                  * when BIOS is set
1648                  */
1649                 u8 val;
1650                 pci_read_config_byte(chip->pci, 0x42, &val);
1651                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1652                                       chip->pci->revision == 0x20))
1653                         snoop = false;
1654         }
1655
1656         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1657                 snoop = false;
1658
1659         chip->snoop = snoop;
1660         if (!snoop)
1661                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1662 }
1663
1664 static void azx_probe_work(struct work_struct *work)
1665 {
1666         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1667         azx_probe_continue(&hda->chip);
1668 }
1669
1670 static int default_bdl_pos_adj(struct azx *chip)
1671 {
1672         /* some exceptions: Atoms seem problematic with value 1 */
1673         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1674                 switch (chip->pci->device) {
1675                 case 0x0f04: /* Baytrail */
1676                 case 0x2284: /* Braswell */
1677                         return 32;
1678                 }
1679         }
1680
1681         switch (chip->driver_type) {
1682         case AZX_DRIVER_ICH:
1683         case AZX_DRIVER_PCH:
1684                 return 1;
1685         default:
1686                 return 32;
1687         }
1688 }
1689
1690 /*
1691  * constructor
1692  */
1693 static const struct hdac_io_ops pci_hda_io_ops;
1694 static const struct hda_controller_ops pci_hda_ops;
1695
1696 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1697                       int dev, unsigned int driver_caps,
1698                       struct azx **rchip)
1699 {
1700         static struct snd_device_ops ops = {
1701                 .dev_disconnect = azx_dev_disconnect,
1702                 .dev_free = azx_dev_free,
1703         };
1704         struct hda_intel *hda;
1705         struct azx *chip;
1706         int err;
1707
1708         *rchip = NULL;
1709
1710         err = pci_enable_device(pci);
1711         if (err < 0)
1712                 return err;
1713
1714         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1715         if (!hda) {
1716                 pci_disable_device(pci);
1717                 return -ENOMEM;
1718         }
1719
1720         chip = &hda->chip;
1721         mutex_init(&chip->open_mutex);
1722         chip->card = card;
1723         chip->pci = pci;
1724         chip->ops = &pci_hda_ops;
1725         chip->driver_caps = driver_caps;
1726         chip->driver_type = driver_caps & 0xff;
1727         check_msi(chip);
1728         chip->dev_index = dev;
1729         chip->jackpoll_ms = jackpoll_ms;
1730         INIT_LIST_HEAD(&chip->pcm_list);
1731         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1732         INIT_LIST_HEAD(&hda->list);
1733         init_vga_switcheroo(chip);
1734         init_completion(&hda->probe_wait);
1735
1736         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1737
1738         check_probe_mask(chip, dev);
1739
1740         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1741                 chip->fallback_to_single_cmd = 1;
1742         else /* explicitly set to single_cmd or not */
1743                 chip->single_cmd = single_cmd;
1744
1745         azx_check_snoop_available(chip);
1746
1747         if (bdl_pos_adj[dev] < 0)
1748                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1749         else
1750                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1751
1752         /* Workaround for a communication error on CFL (bko#199007) */
1753         if (IS_CFL(pci))
1754                 chip->polling_mode = 1;
1755
1756         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1757         if (err < 0) {
1758                 kfree(hda);
1759                 pci_disable_device(pci);
1760                 return err;
1761         }
1762
1763         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1764                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1765                 chip->bus.needs_damn_long_delay = 1;
1766         }
1767
1768         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1769         if (err < 0) {
1770                 dev_err(card->dev, "Error creating device [card]!\n");
1771                 azx_free(chip);
1772                 return err;
1773         }
1774
1775         /* continue probing in work context as may trigger request module */
1776         INIT_WORK(&hda->probe_work, azx_probe_work);
1777
1778         *rchip = chip;
1779
1780         return 0;
1781 }
1782
1783 static int azx_first_init(struct azx *chip)
1784 {
1785         int dev = chip->dev_index;
1786         struct pci_dev *pci = chip->pci;
1787         struct snd_card *card = chip->card;
1788         struct hdac_bus *bus = azx_bus(chip);
1789         int err;
1790         unsigned short gcap;
1791         unsigned int dma_bits = 64;
1792
1793 #if BITS_PER_LONG != 64
1794         /* Fix up base address on ULI M5461 */
1795         if (chip->driver_type == AZX_DRIVER_ULI) {
1796                 u16 tmp3;
1797                 pci_read_config_word(pci, 0x40, &tmp3);
1798                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1799                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1800         }
1801 #endif
1802
1803         err = pci_request_regions(pci, "ICH HD audio");
1804         if (err < 0)
1805                 return err;
1806         chip->region_requested = 1;
1807
1808         bus->addr = pci_resource_start(pci, 0);
1809         bus->remap_addr = pci_ioremap_bar(pci, 0);
1810         if (bus->remap_addr == NULL) {
1811                 dev_err(card->dev, "ioremap error\n");
1812                 return -ENXIO;
1813         }
1814
1815         if (chip->driver_type == AZX_DRIVER_SKL)
1816                 snd_hdac_bus_parse_capabilities(bus);
1817
1818         /*
1819          * Some Intel CPUs has always running timer (ART) feature and
1820          * controller may have Global time sync reporting capability, so
1821          * check both of these before declaring synchronized time reporting
1822          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1823          */
1824         chip->gts_present = false;
1825
1826 #ifdef CONFIG_X86
1827         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1828                 chip->gts_present = true;
1829 #endif
1830
1831         if (chip->msi) {
1832                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1833                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1834                         pci->no_64bit_msi = true;
1835                 }
1836                 if (pci_enable_msi(pci) < 0)
1837                         chip->msi = 0;
1838         }
1839
1840         if (azx_acquire_irq(chip, 0) < 0)
1841                 return -EBUSY;
1842
1843         pci_set_master(pci);
1844         synchronize_irq(bus->irq);
1845
1846         gcap = azx_readw(chip, GCAP);
1847         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1848
1849         /* AMD devices support 40 or 48bit DMA, take the safe one */
1850         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1851                 dma_bits = 40;
1852
1853         /* disable SB600 64bit support for safety */
1854         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1855                 struct pci_dev *p_smbus;
1856                 dma_bits = 40;
1857                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1858                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1859                                          NULL);
1860                 if (p_smbus) {
1861                         if (p_smbus->revision < 0x30)
1862                                 gcap &= ~AZX_GCAP_64OK;
1863                         pci_dev_put(p_smbus);
1864                 }
1865         }
1866
1867         /* NVidia hardware normally only supports up to 40 bits of DMA */
1868         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1869                 dma_bits = 40;
1870
1871         /* disable 64bit DMA address on some devices */
1872         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1873                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1874                 gcap &= ~AZX_GCAP_64OK;
1875         }
1876
1877         /* disable buffer size rounding to 128-byte multiples if supported */
1878         if (align_buffer_size >= 0)
1879                 chip->align_buffer_size = !!align_buffer_size;
1880         else {
1881                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1882                         chip->align_buffer_size = 0;
1883                 else
1884                         chip->align_buffer_size = 1;
1885         }
1886
1887         /* allow 64bit DMA address if supported by H/W */
1888         if (!(gcap & AZX_GCAP_64OK))
1889                 dma_bits = 32;
1890         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1891                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1892         } else {
1893                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1894                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1895         }
1896
1897         /* read number of streams from GCAP register instead of using
1898          * hardcoded value
1899          */
1900         chip->capture_streams = (gcap >> 8) & 0x0f;
1901         chip->playback_streams = (gcap >> 12) & 0x0f;
1902         if (!chip->playback_streams && !chip->capture_streams) {
1903                 /* gcap didn't give any info, switching to old method */
1904
1905                 switch (chip->driver_type) {
1906                 case AZX_DRIVER_ULI:
1907                         chip->playback_streams = ULI_NUM_PLAYBACK;
1908                         chip->capture_streams = ULI_NUM_CAPTURE;
1909                         break;
1910                 case AZX_DRIVER_ATIHDMI:
1911                 case AZX_DRIVER_ATIHDMI_NS:
1912                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1913                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1914                         break;
1915                 case AZX_DRIVER_GENERIC:
1916                 default:
1917                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1918                         chip->capture_streams = ICH6_NUM_CAPTURE;
1919                         break;
1920                 }
1921         }
1922         chip->capture_index_offset = 0;
1923         chip->playback_index_offset = chip->capture_streams;
1924         chip->num_streams = chip->playback_streams + chip->capture_streams;
1925
1926         /* sanity check for the SDxCTL.STRM field overflow */
1927         if (chip->num_streams > 15 &&
1928             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1929                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1930                          "forcing separate stream tags", chip->num_streams);
1931                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1932         }
1933
1934         /* initialize streams */
1935         err = azx_init_streams(chip);
1936         if (err < 0)
1937                 return err;
1938
1939         err = azx_alloc_stream_pages(chip);
1940         if (err < 0)
1941                 return err;
1942
1943         /* initialize chip */
1944         azx_init_pci(chip);
1945
1946         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1947                 snd_hdac_i915_set_bclk(bus);
1948
1949         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1950
1951         /* codec detection */
1952         if (!azx_bus(chip)->codec_mask) {
1953                 dev_err(card->dev, "no codecs found!\n");
1954                 return -ENODEV;
1955         }
1956
1957         strcpy(card->driver, "HDA-Intel");
1958         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1959                 sizeof(card->shortname));
1960         snprintf(card->longname, sizeof(card->longname),
1961                  "%s at 0x%lx irq %i",
1962                  card->shortname, bus->addr, bus->irq);
1963
1964         return 0;
1965 }
1966
1967 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1968 /* callback from request_firmware_nowait() */
1969 static void azx_firmware_cb(const struct firmware *fw, void *context)
1970 {
1971         struct snd_card *card = context;
1972         struct azx *chip = card->private_data;
1973         struct pci_dev *pci = chip->pci;
1974
1975         if (!fw) {
1976                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1977                 goto error;
1978         }
1979
1980         chip->fw = fw;
1981         if (!chip->disabled) {
1982                 /* continue probing */
1983                 if (azx_probe_continue(chip))
1984                         goto error;
1985         }
1986         return; /* OK */
1987
1988  error:
1989         snd_card_free(card);
1990         pci_set_drvdata(pci, NULL);
1991 }
1992 #endif
1993
1994 /*
1995  * HDA controller ops.
1996  */
1997
1998 /* PCI register access. */
1999 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2000 {
2001         writel(value, addr);
2002 }
2003
2004 static u32 pci_azx_readl(u32 __iomem *addr)
2005 {
2006         return readl(addr);
2007 }
2008
2009 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2010 {
2011         writew(value, addr);
2012 }
2013
2014 static u16 pci_azx_readw(u16 __iomem *addr)
2015 {
2016         return readw(addr);
2017 }
2018
2019 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2020 {
2021         writeb(value, addr);
2022 }
2023
2024 static u8 pci_azx_readb(u8 __iomem *addr)
2025 {
2026         return readb(addr);
2027 }
2028
2029 static int disable_msi_reset_irq(struct azx *chip)
2030 {
2031         struct hdac_bus *bus = azx_bus(chip);
2032         int err;
2033
2034         free_irq(bus->irq, chip);
2035         bus->irq = -1;
2036         pci_disable_msi(chip->pci);
2037         chip->msi = 0;
2038         err = azx_acquire_irq(chip, 1);
2039         if (err < 0)
2040                 return err;
2041
2042         return 0;
2043 }
2044
2045 /* DMA page allocation helpers.  */
2046 static int dma_alloc_pages(struct hdac_bus *bus,
2047                            int type,
2048                            size_t size,
2049                            struct snd_dma_buffer *buf)
2050 {
2051         struct azx *chip = bus_to_azx(bus);
2052         int err;
2053
2054         err = snd_dma_alloc_pages(type,
2055                                   bus->dev,
2056                                   size, buf);
2057         if (err < 0)
2058                 return err;
2059         mark_pages_wc(chip, buf, true);
2060         return 0;
2061 }
2062
2063 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2064 {
2065         struct azx *chip = bus_to_azx(bus);
2066
2067         mark_pages_wc(chip, buf, false);
2068         snd_dma_free_pages(buf);
2069 }
2070
2071 static int substream_alloc_pages(struct azx *chip,
2072                                  struct snd_pcm_substream *substream,
2073                                  size_t size)
2074 {
2075         struct azx_dev *azx_dev = get_azx_dev(substream);
2076         int ret;
2077
2078         mark_runtime_wc(chip, azx_dev, substream, false);
2079         ret = snd_pcm_lib_malloc_pages(substream, size);
2080         if (ret < 0)
2081                 return ret;
2082         mark_runtime_wc(chip, azx_dev, substream, true);
2083         return 0;
2084 }
2085
2086 static int substream_free_pages(struct azx *chip,
2087                                 struct snd_pcm_substream *substream)
2088 {
2089         struct azx_dev *azx_dev = get_azx_dev(substream);
2090         mark_runtime_wc(chip, azx_dev, substream, false);
2091         return snd_pcm_lib_free_pages(substream);
2092 }
2093
2094 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2095                              struct vm_area_struct *area)
2096 {
2097 #ifdef CONFIG_X86
2098         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2099         struct azx *chip = apcm->chip;
2100         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
2101                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2102 #endif
2103 }
2104
2105 static const struct hdac_io_ops pci_hda_io_ops = {
2106         .reg_writel = pci_azx_writel,
2107         .reg_readl = pci_azx_readl,
2108         .reg_writew = pci_azx_writew,
2109         .reg_readw = pci_azx_readw,
2110         .reg_writeb = pci_azx_writeb,
2111         .reg_readb = pci_azx_readb,
2112         .dma_alloc_pages = dma_alloc_pages,
2113         .dma_free_pages = dma_free_pages,
2114 };
2115
2116 static const struct hda_controller_ops pci_hda_ops = {
2117         .disable_msi_reset_irq = disable_msi_reset_irq,
2118         .substream_alloc_pages = substream_alloc_pages,
2119         .substream_free_pages = substream_free_pages,
2120         .pcm_mmap_prepare = pcm_mmap_prepare,
2121         .position_check = azx_position_check,
2122         .link_power = azx_intel_link_power,
2123 };
2124
2125 static int azx_probe(struct pci_dev *pci,
2126                      const struct pci_device_id *pci_id)
2127 {
2128         static int dev;
2129         struct snd_card *card;
2130         struct hda_intel *hda;
2131         struct azx *chip;
2132         bool schedule_probe;
2133         int err;
2134
2135         if (dev >= SNDRV_CARDS)
2136                 return -ENODEV;
2137         if (!enable[dev]) {
2138                 dev++;
2139                 return -ENOENT;
2140         }
2141
2142         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2143                            0, &card);
2144         if (err < 0) {
2145                 dev_err(&pci->dev, "Error creating card!\n");
2146                 return err;
2147         }
2148
2149         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2150         if (err < 0)
2151                 goto out_free;
2152         card->private_data = chip;
2153         hda = container_of(chip, struct hda_intel, chip);
2154
2155         pci_set_drvdata(pci, card);
2156
2157         err = register_vga_switcheroo(chip);
2158         if (err < 0) {
2159                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2160                 goto out_free;
2161         }
2162
2163         if (check_hdmi_disabled(pci)) {
2164                 dev_info(card->dev, "VGA controller is disabled\n");
2165                 dev_info(card->dev, "Delaying initialization\n");
2166                 chip->disabled = true;
2167         }
2168
2169         schedule_probe = !chip->disabled;
2170
2171 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2172         if (patch[dev] && *patch[dev]) {
2173                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2174                          patch[dev]);
2175                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2176                                               &pci->dev, GFP_KERNEL, card,
2177                                               azx_firmware_cb);
2178                 if (err < 0)
2179                         goto out_free;
2180                 schedule_probe = false; /* continued in azx_firmware_cb() */
2181         }
2182 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2183
2184 #ifndef CONFIG_SND_HDA_I915
2185         if (CONTROLLER_IN_GPU(pci))
2186                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2187 #endif
2188
2189         if (schedule_probe)
2190                 schedule_work(&hda->probe_work);
2191
2192         dev++;
2193         if (chip->disabled)
2194                 complete_all(&hda->probe_wait);
2195         return 0;
2196
2197 out_free:
2198         snd_card_free(card);
2199         return err;
2200 }
2201
2202 #ifdef CONFIG_PM
2203 /* On some boards setting power_save to a non 0 value leads to clicking /
2204  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2205  * figure out how to avoid these sounds, but that is not always feasible.
2206  * So we keep a list of devices where we disable powersaving as its known
2207  * to causes problems on these devices.
2208  */
2209 static struct snd_pci_quirk power_save_blacklist[] = {
2210         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2211         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2212         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2213         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2214         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2215         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2216         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2217         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2218         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2219         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2220         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2221         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2222         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2223         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2224         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2225         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2226         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2227         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2228         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2229         {}
2230 };
2231 #endif /* CONFIG_PM */
2232
2233 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2234 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2235         [AZX_DRIVER_NVIDIA] = 8,
2236         [AZX_DRIVER_TERA] = 1,
2237 };
2238
2239 static int azx_probe_continue(struct azx *chip)
2240 {
2241         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2242         struct hdac_bus *bus = azx_bus(chip);
2243         struct pci_dev *pci = chip->pci;
2244         struct hda_codec *codec;
2245         int dev = chip->dev_index;
2246         int val;
2247         int err;
2248
2249         hda->probe_continued = 1;
2250
2251         /* bind with i915 if needed */
2252         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2253                 err = snd_hdac_i915_init(bus);
2254                 if (err < 0) {
2255                         /* if the controller is bound only with HDMI/DP
2256                          * (for HSW and BDW), we need to abort the probe;
2257                          * for other chips, still continue probing as other
2258                          * codecs can be on the same link.
2259                          */
2260                         if (CONTROLLER_IN_GPU(pci)) {
2261                                 dev_err(chip->card->dev,
2262                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2263                                 goto out_free;
2264                         } else {
2265                                 /* don't bother any longer */
2266                                 chip->driver_caps &=
2267                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2268                         }
2269                 }
2270         }
2271
2272         /* Request display power well for the HDA controller or codec. For
2273          * Haswell/Broadwell, both the display HDA controller and codec need
2274          * this power. For other platforms, like Baytrail/Braswell, only the
2275          * display codec needs the power and it can be released after probe.
2276          */
2277         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2278                 /* HSW/BDW controllers need this power */
2279                 if (CONTROLLER_IN_GPU(pci))
2280                         hda->need_i915_power = 1;
2281
2282                 err = snd_hdac_display_power(bus, true);
2283                 if (err < 0) {
2284                         dev_err(chip->card->dev,
2285                                 "Cannot turn on display power on i915\n");
2286                         goto i915_power_fail;
2287                 }
2288         }
2289
2290         err = azx_first_init(chip);
2291         if (err < 0)
2292                 goto out_free;
2293
2294 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2295         chip->beep_mode = beep_mode[dev];
2296 #endif
2297
2298         /* create codec instances */
2299         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2300         if (err < 0)
2301                 goto out_free;
2302
2303 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2304         if (chip->fw) {
2305                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2306                                          chip->fw->data);
2307                 if (err < 0)
2308                         goto out_free;
2309 #ifndef CONFIG_PM
2310                 release_firmware(chip->fw); /* no longer needed */
2311                 chip->fw = NULL;
2312 #endif
2313         }
2314 #endif
2315         if ((probe_only[dev] & 1) == 0) {
2316                 err = azx_codec_configure(chip);
2317                 if (err < 0)
2318                         goto out_free;
2319         }
2320
2321         err = snd_card_register(chip->card);
2322         if (err < 0)
2323                 goto out_free;
2324
2325         chip->running = 1;
2326         azx_add_card_list(chip);
2327
2328         val = power_save;
2329 #ifdef CONFIG_PM
2330         if (pm_blacklist) {
2331                 const struct snd_pci_quirk *q;
2332
2333                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2334                 if (q && val) {
2335                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2336                                  q->subvendor, q->subdevice);
2337                         val = 0;
2338                 }
2339         }
2340 #endif /* CONFIG_PM */
2341         /*
2342          * The discrete GPU cannot power down unless the HDA controller runtime
2343          * suspends, so activate runtime PM on codecs even if power_save == 0.
2344          */
2345         if (use_vga_switcheroo(hda))
2346                 list_for_each_codec(codec, &chip->bus)
2347                         codec->auto_runtime_pm = 1;
2348
2349         snd_hda_set_power_save(&chip->bus, val * 1000);
2350         if (azx_has_pm_runtime(chip))
2351                 pm_runtime_put_autosuspend(&pci->dev);
2352
2353 out_free:
2354         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2355                 && !hda->need_i915_power)
2356                 snd_hdac_display_power(bus, false);
2357
2358 i915_power_fail:
2359         if (err < 0)
2360                 hda->init_failed = 1;
2361         complete_all(&hda->probe_wait);
2362         return err;
2363 }
2364
2365 static void azx_remove(struct pci_dev *pci)
2366 {
2367         struct snd_card *card = pci_get_drvdata(pci);
2368         struct azx *chip;
2369         struct hda_intel *hda;
2370
2371         if (card) {
2372                 /* cancel the pending probing work */
2373                 chip = card->private_data;
2374                 hda = container_of(chip, struct hda_intel, chip);
2375                 /* FIXME: below is an ugly workaround.
2376                  * Both device_release_driver() and driver_probe_device()
2377                  * take *both* the device's and its parent's lock before
2378                  * calling the remove() and probe() callbacks.  The codec
2379                  * probe takes the locks of both the codec itself and its
2380                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2381                  * the PCI controller is unbound, it takes its lock, too
2382                  * ==> ouch, a deadlock!
2383                  * As a workaround, we unlock temporarily here the controller
2384                  * device during cancel_work_sync() call.
2385                  */
2386                 device_unlock(&pci->dev);
2387                 cancel_work_sync(&hda->probe_work);
2388                 device_lock(&pci->dev);
2389
2390                 snd_card_free(card);
2391         }
2392 }
2393
2394 static void azx_shutdown(struct pci_dev *pci)
2395 {
2396         struct snd_card *card = pci_get_drvdata(pci);
2397         struct azx *chip;
2398
2399         if (!card)
2400                 return;
2401         chip = card->private_data;
2402         if (chip && chip->running)
2403                 azx_stop_chip(chip);
2404 }
2405
2406 /* PCI IDs */
2407 static const struct pci_device_id azx_ids[] = {
2408         /* CPT */
2409         { PCI_DEVICE(0x8086, 0x1c20),
2410           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2411         /* PBG */
2412         { PCI_DEVICE(0x8086, 0x1d20),
2413           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2414         /* Panther Point */
2415         { PCI_DEVICE(0x8086, 0x1e20),
2416           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2417         /* Lynx Point */
2418         { PCI_DEVICE(0x8086, 0x8c20),
2419           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2420         /* 9 Series */
2421         { PCI_DEVICE(0x8086, 0x8ca0),
2422           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2423         /* Wellsburg */
2424         { PCI_DEVICE(0x8086, 0x8d20),
2425           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2426         { PCI_DEVICE(0x8086, 0x8d21),
2427           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2428         /* Lewisburg */
2429         { PCI_DEVICE(0x8086, 0xa1f0),
2430           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2431         { PCI_DEVICE(0x8086, 0xa270),
2432           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2433         /* Lynx Point-LP */
2434         { PCI_DEVICE(0x8086, 0x9c20),
2435           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2436         /* Lynx Point-LP */
2437         { PCI_DEVICE(0x8086, 0x9c21),
2438           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2439         /* Wildcat Point-LP */
2440         { PCI_DEVICE(0x8086, 0x9ca0),
2441           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2442         /* Sunrise Point */
2443         { PCI_DEVICE(0x8086, 0xa170),
2444           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2445         /* Sunrise Point-LP */
2446         { PCI_DEVICE(0x8086, 0x9d70),
2447           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2448         /* Kabylake */
2449         { PCI_DEVICE(0x8086, 0xa171),
2450           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2451         /* Kabylake-LP */
2452         { PCI_DEVICE(0x8086, 0x9d71),
2453           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2454         /* Kabylake-H */
2455         { PCI_DEVICE(0x8086, 0xa2f0),
2456           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2457         /* Coffelake */
2458         { PCI_DEVICE(0x8086, 0xa348),
2459           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2460         /* Cannonlake */
2461         { PCI_DEVICE(0x8086, 0x9dc8),
2462           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2463         /* Icelake */
2464         { PCI_DEVICE(0x8086, 0x34c8),
2465           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2466         /* Broxton-P(Apollolake) */
2467         { PCI_DEVICE(0x8086, 0x5a98),
2468           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2469         /* Broxton-T */
2470         { PCI_DEVICE(0x8086, 0x1a98),
2471           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2472         /* Gemini-Lake */
2473         { PCI_DEVICE(0x8086, 0x3198),
2474           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2475         /* Haswell */
2476         { PCI_DEVICE(0x8086, 0x0a0c),
2477           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2478         { PCI_DEVICE(0x8086, 0x0c0c),
2479           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2480         { PCI_DEVICE(0x8086, 0x0d0c),
2481           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2482         /* Broadwell */
2483         { PCI_DEVICE(0x8086, 0x160c),
2484           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2485         /* 5 Series/3400 */
2486         { PCI_DEVICE(0x8086, 0x3b56),
2487           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2488         /* Poulsbo */
2489         { PCI_DEVICE(0x8086, 0x811b),
2490           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2491         /* Oaktrail */
2492         { PCI_DEVICE(0x8086, 0x080a),
2493           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2494         /* BayTrail */
2495         { PCI_DEVICE(0x8086, 0x0f04),
2496           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2497         /* Braswell */
2498         { PCI_DEVICE(0x8086, 0x2284),
2499           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2500         /* ICH6 */
2501         { PCI_DEVICE(0x8086, 0x2668),
2502           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2503         /* ICH7 */
2504         { PCI_DEVICE(0x8086, 0x27d8),
2505           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2506         /* ESB2 */
2507         { PCI_DEVICE(0x8086, 0x269a),
2508           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2509         /* ICH8 */
2510         { PCI_DEVICE(0x8086, 0x284b),
2511           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2512         /* ICH9 */
2513         { PCI_DEVICE(0x8086, 0x293e),
2514           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2515         /* ICH9 */
2516         { PCI_DEVICE(0x8086, 0x293f),
2517           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2518         /* ICH10 */
2519         { PCI_DEVICE(0x8086, 0x3a3e),
2520           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2521         /* ICH10 */
2522         { PCI_DEVICE(0x8086, 0x3a6e),
2523           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2524         /* Generic Intel */
2525         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2526           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2527           .class_mask = 0xffffff,
2528           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2529         /* ATI SB 450/600/700/800/900 */
2530         { PCI_DEVICE(0x1002, 0x437b),
2531           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2532         { PCI_DEVICE(0x1002, 0x4383),
2533           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2534         /* AMD Hudson */
2535         { PCI_DEVICE(0x1022, 0x780d),
2536           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2537         /* AMD Raven */
2538         { PCI_DEVICE(0x1022, 0x15e3),
2539           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2540                          AZX_DCAPS_PM_RUNTIME },
2541         /* ATI HDMI */
2542         { PCI_DEVICE(0x1002, 0x0002),
2543           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544         { PCI_DEVICE(0x1002, 0x1308),
2545           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2546         { PCI_DEVICE(0x1002, 0x157a),
2547           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2548         { PCI_DEVICE(0x1002, 0x15b3),
2549           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2550         { PCI_DEVICE(0x1002, 0x793b),
2551           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2552         { PCI_DEVICE(0x1002, 0x7919),
2553           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2554         { PCI_DEVICE(0x1002, 0x960f),
2555           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2556         { PCI_DEVICE(0x1002, 0x970f),
2557           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2558         { PCI_DEVICE(0x1002, 0x9840),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaa00),
2561           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2562         { PCI_DEVICE(0x1002, 0xaa08),
2563           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2564         { PCI_DEVICE(0x1002, 0xaa10),
2565           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2566         { PCI_DEVICE(0x1002, 0xaa18),
2567           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2568         { PCI_DEVICE(0x1002, 0xaa20),
2569           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2570         { PCI_DEVICE(0x1002, 0xaa28),
2571           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2572         { PCI_DEVICE(0x1002, 0xaa30),
2573           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2574         { PCI_DEVICE(0x1002, 0xaa38),
2575           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2576         { PCI_DEVICE(0x1002, 0xaa40),
2577           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578         { PCI_DEVICE(0x1002, 0xaa48),
2579           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580         { PCI_DEVICE(0x1002, 0xaa50),
2581           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2582         { PCI_DEVICE(0x1002, 0xaa58),
2583           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2584         { PCI_DEVICE(0x1002, 0xaa60),
2585           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2586         { PCI_DEVICE(0x1002, 0xaa68),
2587           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2588         { PCI_DEVICE(0x1002, 0xaa80),
2589           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2590         { PCI_DEVICE(0x1002, 0xaa88),
2591           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2592         { PCI_DEVICE(0x1002, 0xaa90),
2593           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2594         { PCI_DEVICE(0x1002, 0xaa98),
2595           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2596         { PCI_DEVICE(0x1002, 0x9902),
2597           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2598         { PCI_DEVICE(0x1002, 0xaaa0),
2599           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2600         { PCI_DEVICE(0x1002, 0xaaa8),
2601           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2602         { PCI_DEVICE(0x1002, 0xaab0),
2603           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2604         { PCI_DEVICE(0x1002, 0xaac0),
2605           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2606         { PCI_DEVICE(0x1002, 0xaac8),
2607           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2608         { PCI_DEVICE(0x1002, 0xaad8),
2609           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2610         { PCI_DEVICE(0x1002, 0xaae8),
2611           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2612         { PCI_DEVICE(0x1002, 0xaae0),
2613           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2614         { PCI_DEVICE(0x1002, 0xaaf0),
2615           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2616         /* VIA VT8251/VT8237A */
2617         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2618         /* VIA GFX VT7122/VX900 */
2619         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2620         /* VIA GFX VT6122/VX11 */
2621         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2622         /* SIS966 */
2623         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2624         /* ULI M5461 */
2625         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2626         /* NVIDIA MCP */
2627         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2628           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2629           .class_mask = 0xffffff,
2630           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2631         /* Teradici */
2632         { PCI_DEVICE(0x6549, 0x1200),
2633           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2634         { PCI_DEVICE(0x6549, 0x2200),
2635           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2636         /* Creative X-Fi (CA0110-IBG) */
2637         /* CTHDA chips */
2638         { PCI_DEVICE(0x1102, 0x0010),
2639           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2640         { PCI_DEVICE(0x1102, 0x0012),
2641           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2642 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2643         /* the following entry conflicts with snd-ctxfi driver,
2644          * as ctxfi driver mutates from HD-audio to native mode with
2645          * a special command sequence.
2646          */
2647         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2648           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2649           .class_mask = 0xffffff,
2650           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2651           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2652 #else
2653         /* this entry seems still valid -- i.e. without emu20kx chip */
2654         { PCI_DEVICE(0x1102, 0x0009),
2655           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2656           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2657 #endif
2658         /* CM8888 */
2659         { PCI_DEVICE(0x13f6, 0x5011),
2660           .driver_data = AZX_DRIVER_CMEDIA |
2661           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2662         /* Vortex86MX */
2663         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2664         /* VMware HDAudio */
2665         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2666         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2667         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2668           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2669           .class_mask = 0xffffff,
2670           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2671         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2672           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2673           .class_mask = 0xffffff,
2674           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2675         { 0, }
2676 };
2677 MODULE_DEVICE_TABLE(pci, azx_ids);
2678
2679 /* pci_driver definition */
2680 static struct pci_driver azx_driver = {
2681         .name = KBUILD_MODNAME,
2682         .id_table = azx_ids,
2683         .probe = azx_probe,
2684         .remove = azx_remove,
2685         .shutdown = azx_shutdown,
2686         .driver = {
2687                 .pm = AZX_PM_OPS,
2688         },
2689 };
2690
2691 module_pci_driver(azx_driver);