sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative CA0132 chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/mutex.h>
  28 #include <linux/module.h>
  29 #include <linux/firmware.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/io.h>
  33 #include <linux/pci.h>
  34 #include <sound/core.h>
  35 #include "hda_codec.h"
  36 #include "hda_local.h"
  37 #include "hda_auto_parser.h"
  38 #include "hda_jack.h"
  39
  40 #include "ca0132_regs.h"
  41
  42 /* Enable this to see controls for tuning purpose. */
  43 /*#define ENABLE_TUNING_CONTROLS*/
  44
  45 #ifdef ENABLE_TUNING_CONTROLS
  46 #include <sound/tlv.h>
  47 #endif
  48
  49 #define FLOAT_ZERO      0x00000000
  50 #define FLOAT_ONE       0x3f800000
  51 #define FLOAT_TWO       0x40000000
  52 #define FLOAT_THREE     0x40400000
  53 #define FLOAT_EIGHT     0x41000000
  54 #define FLOAT_MINUS_5   0xc0a00000
  55
  56 #define UNSOL_TAG_DSP   0x16
  57
  58 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  59 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  60
  61 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  62 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  63 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  64
  65 #define MASTERCONTROL                           0x80
  66 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  67 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  68
  69 #define WIDGET_CHIP_CTRL      0x15
  70 #define WIDGET_DSP_CTRL       0x16
  71
  72 #define MEM_CONNID_MICIN1     3
  73 #define MEM_CONNID_MICIN2     5
  74 #define MEM_CONNID_MICOUT1    12
  75 #define MEM_CONNID_MICOUT2    14
  76 #define MEM_CONNID_WUH        10
  77 #define MEM_CONNID_DSP        16
  78 #define MEM_CONNID_DMIC       100
  79
  80 #define SCP_SET    0
  81 #define SCP_GET    1
  82
  83 #define EFX_FILE   "ctefx.bin"
  84 #define SBZ_EFX_FILE   "ctefx-sbz.bin"
  85 #define R3DI_EFX_FILE  "ctefx-r3di.bin"
  86
  87 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  88 MODULE_FIRMWARE(EFX_FILE);
  89 MODULE_FIRMWARE(SBZ_EFX_FILE);
  90 MODULE_FIRMWARE(R3DI_EFX_FILE);
  91 #endif
  92
  93 static const char *const dirstr[2] = { "Playback", "Capture" };
  94
  95 #define NUM_OF_OUTPUTS 3
  96 enum {
  97         SPEAKER_OUT,
  98         HEADPHONE_OUT,
  99         SURROUND_OUT
 100 };
 101
 102 enum {
 103         DIGITAL_MIC,
 104         LINE_MIC_IN
 105 };
 106
 107 /* Strings for Input Source Enum Control */
 108 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
 109 #define IN_SRC_NUM_OF_INPUTS 3
 110 enum {
 111         REAR_MIC,
 112         REAR_LINE_IN,
 113         FRONT_MIC,
 114 };
 115
 116 enum {
 117 #define VNODE_START_NID    0x80
 118         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 119         VNID_MIC,
 120         VNID_HP_SEL,
 121         VNID_AMIC1_SEL,
 122         VNID_HP_ASEL,
 123         VNID_AMIC1_ASEL,
 124         VNODE_END_NID,
 125 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 126
 127 #define EFFECT_START_NID    0x90
 128 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 129         SURROUND = OUT_EFFECT_START_NID,
 130         CRYSTALIZER,
 131         DIALOG_PLUS,
 132         SMART_VOLUME,
 133         X_BASS,
 134         EQUALIZER,
 135         OUT_EFFECT_END_NID,
 136 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 137
 138 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 139         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 140         VOICE_FOCUS,
 141         MIC_SVM,
 142         NOISE_REDUCTION,
 143         IN_EFFECT_END_NID,
 144 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 145
 146         VOICEFX = IN_EFFECT_END_NID,
 147         PLAY_ENHANCEMENT,
 148         CRYSTAL_VOICE,
 149         EFFECT_END_NID,
 150         OUTPUT_SOURCE_ENUM,
 151         INPUT_SOURCE_ENUM,
 152         XBASS_XOVER,
 153         EQ_PRESET_ENUM,
 154         SMART_VOLUME_ENUM,
 155         MIC_BOOST_ENUM
 156 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 157 };
 158
 159 /* Effects values size*/
 160 #define EFFECT_VALS_MAX_COUNT 12
 161
 162 /*
 163  * Default values for the effect slider controls, they are in order of their
 164  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 165  * X-bass.
 166  */
 167 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 168 /* Amount of effect level sliders for ca0132_alt controls. */
 169 #define EFFECT_LEVEL_SLIDERS 5
 170
 171 /* Latency introduced by DSP blocks in milliseconds. */
 172 #define DSP_CAPTURE_INIT_LATENCY        0
 173 #define DSP_CRYSTAL_VOICE_LATENCY       124
 174 #define DSP_PLAYBACK_INIT_LATENCY       13
 175 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 176 #define DSP_SPEAKER_OUT_LATENCY         7
 177
 178 struct ct_effect {
 179         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 180         hda_nid_t nid;
 181         int mid; /*effect module ID*/
 182         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 183         int direct; /* 0:output; 1:input*/
 184         int params; /* number of default non-on/off params */
 185         /*effect default values, 1st is on/off. */
 186         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 187 };
 188
 189 #define EFX_DIR_OUT 0
 190 #define EFX_DIR_IN  1
 191
 192 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 193         { .name = "Surround",
 194           .nid = SURROUND,
 195           .mid = 0x96,
 196           .reqs = {0, 1},
 197           .direct = EFX_DIR_OUT,
 198           .params = 1,
 199           .def_vals = {0x3F800000, 0x3F2B851F}
 200         },
 201         { .name = "Crystalizer",
 202           .nid = CRYSTALIZER,
 203           .mid = 0x96,
 204           .reqs = {7, 8},
 205           .direct = EFX_DIR_OUT,
 206           .params = 1,
 207           .def_vals = {0x3F800000, 0x3F266666}
 208         },
 209         { .name = "Dialog Plus",
 210           .nid = DIALOG_PLUS,
 211           .mid = 0x96,
 212           .reqs = {2, 3},
 213           .direct = EFX_DIR_OUT,
 214           .params = 1,
 215           .def_vals = {0x00000000, 0x3F000000}
 216         },
 217         { .name = "Smart Volume",
 218           .nid = SMART_VOLUME,
 219           .mid = 0x96,
 220           .reqs = {4, 5, 6},
 221           .direct = EFX_DIR_OUT,
 222           .params = 2,
 223           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 224         },
 225         { .name = "X-Bass",
 226           .nid = X_BASS,
 227           .mid = 0x96,
 228           .reqs = {24, 23, 25},
 229           .direct = EFX_DIR_OUT,
 230           .params = 2,
 231           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 232         },
 233         { .name = "Equalizer",
 234           .nid = EQUALIZER,
 235           .mid = 0x96,
 236           .reqs = {9, 10, 11, 12, 13, 14,
 237                         15, 16, 17, 18, 19, 20},
 238           .direct = EFX_DIR_OUT,
 239           .params = 11,
 240           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 241                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 242                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 243         },
 244         { .name = "Echo Cancellation",
 245           .nid = ECHO_CANCELLATION,
 246           .mid = 0x95,
 247           .reqs = {0, 1, 2, 3},
 248           .direct = EFX_DIR_IN,
 249           .params = 3,
 250           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 251         },
 252         { .name = "Voice Focus",
 253           .nid = VOICE_FOCUS,
 254           .mid = 0x95,
 255           .reqs = {6, 7, 8, 9},
 256           .direct = EFX_DIR_IN,
 257           .params = 3,
 258           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 259         },
 260         { .name = "Mic SVM",
 261           .nid = MIC_SVM,
 262           .mid = 0x95,
 263           .reqs = {44, 45},
 264           .direct = EFX_DIR_IN,
 265           .params = 1,
 266           .def_vals = {0x00000000, 0x3F3D70A4}
 267         },
 268         { .name = "Noise Reduction",
 269           .nid = NOISE_REDUCTION,
 270           .mid = 0x95,
 271           .reqs = {4, 5},
 272           .direct = EFX_DIR_IN,
 273           .params = 1,
 274           .def_vals = {0x3F800000, 0x3F000000}
 275         },
 276         { .name = "VoiceFX",
 277           .nid = VOICEFX,
 278           .mid = 0x95,
 279           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 280           .direct = EFX_DIR_IN,
 281           .params = 8,
 282           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 283                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 284                        0x00000000}
 285         }
 286 };
 287
 288 /* Tuning controls */
 289 #ifdef ENABLE_TUNING_CONTROLS
 290
 291 enum {
 292 #define TUNING_CTL_START_NID  0xC0
 293         WEDGE_ANGLE = TUNING_CTL_START_NID,
 294         SVM_LEVEL,
 295         EQUALIZER_BAND_0,
 296         EQUALIZER_BAND_1,
 297         EQUALIZER_BAND_2,
 298         EQUALIZER_BAND_3,
 299         EQUALIZER_BAND_4,
 300         EQUALIZER_BAND_5,
 301         EQUALIZER_BAND_6,
 302         EQUALIZER_BAND_7,
 303         EQUALIZER_BAND_8,
 304         EQUALIZER_BAND_9,
 305         TUNING_CTL_END_NID
 306 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 307 };
 308
 309 struct ct_tuning_ctl {
 310         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 311         hda_nid_t parent_nid;
 312         hda_nid_t nid;
 313         int mid; /*effect module ID*/
 314         int req; /*effect module request*/
 315         int direct; /* 0:output; 1:input*/
 316         unsigned int def_val;/*effect default values*/
 317 };
 318
 319 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 320         { .name = "Wedge Angle",
 321           .parent_nid = VOICE_FOCUS,
 322           .nid = WEDGE_ANGLE,
 323           .mid = 0x95,
 324           .req = 8,
 325           .direct = EFX_DIR_IN,
 326           .def_val = 0x41F00000
 327         },
 328         { .name = "SVM Level",
 329           .parent_nid = MIC_SVM,
 330           .nid = SVM_LEVEL,
 331           .mid = 0x95,
 332           .req = 45,
 333           .direct = EFX_DIR_IN,
 334           .def_val = 0x3F3D70A4
 335         },
 336         { .name = "EQ Band0",
 337           .parent_nid = EQUALIZER,
 338           .nid = EQUALIZER_BAND_0,
 339           .mid = 0x96,
 340           .req = 11,
 341           .direct = EFX_DIR_OUT,
 342           .def_val = 0x00000000
 343         },
 344         { .name = "EQ Band1",
 345           .parent_nid = EQUALIZER,
 346           .nid = EQUALIZER_BAND_1,
 347           .mid = 0x96,
 348           .req = 12,
 349           .direct = EFX_DIR_OUT,
 350           .def_val = 0x00000000
 351         },
 352         { .name = "EQ Band2",
 353           .parent_nid = EQUALIZER,
 354           .nid = EQUALIZER_BAND_2,
 355           .mid = 0x96,
 356           .req = 13,
 357           .direct = EFX_DIR_OUT,
 358           .def_val = 0x00000000
 359         },
 360         { .name = "EQ Band3",
 361           .parent_nid = EQUALIZER,
 362           .nid = EQUALIZER_BAND_3,
 363           .mid = 0x96,
 364           .req = 14,
 365           .direct = EFX_DIR_OUT,
 366           .def_val = 0x00000000
 367         },
 368         { .name = "EQ Band4",
 369           .parent_nid = EQUALIZER,
 370           .nid = EQUALIZER_BAND_4,
 371           .mid = 0x96,
 372           .req = 15,
 373           .direct = EFX_DIR_OUT,
 374           .def_val = 0x00000000
 375         },
 376         { .name = "EQ Band5",
 377           .parent_nid = EQUALIZER,
 378           .nid = EQUALIZER_BAND_5,
 379           .mid = 0x96,
 380           .req = 16,
 381           .direct = EFX_DIR_OUT,
 382           .def_val = 0x00000000
 383         },
 384         { .name = "EQ Band6",
 385           .parent_nid = EQUALIZER,
 386           .nid = EQUALIZER_BAND_6,
 387           .mid = 0x96,
 388           .req = 17,
 389           .direct = EFX_DIR_OUT,
 390           .def_val = 0x00000000
 391         },
 392         { .name = "EQ Band7",
 393           .parent_nid = EQUALIZER,
 394           .nid = EQUALIZER_BAND_7,
 395           .mid = 0x96,
 396           .req = 18,
 397           .direct = EFX_DIR_OUT,
 398           .def_val = 0x00000000
 399         },
 400         { .name = "EQ Band8",
 401           .parent_nid = EQUALIZER,
 402           .nid = EQUALIZER_BAND_8,
 403           .mid = 0x96,
 404           .req = 19,
 405           .direct = EFX_DIR_OUT,
 406           .def_val = 0x00000000
 407         },
 408         { .name = "EQ Band9",
 409           .parent_nid = EQUALIZER,
 410           .nid = EQUALIZER_BAND_9,
 411           .mid = 0x96,
 412           .req = 20,
 413           .direct = EFX_DIR_OUT,
 414           .def_val = 0x00000000
 415         }
 416 };
 417 #endif
 418
 419 /* Voice FX Presets */
 420 #define VOICEFX_MAX_PARAM_COUNT 9
 421
 422 struct ct_voicefx {
 423         char *name;
 424         hda_nid_t nid;
 425         int mid;
 426         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 427 };
 428
 429 struct ct_voicefx_preset {
 430         char *name; /*preset name*/
 431         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 432 };
 433
 434 static const struct ct_voicefx ca0132_voicefx = {
 435         .name = "VoiceFX Capture Switch",
 436         .nid = VOICEFX,
 437         .mid = 0x95,
 438         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 439 };
 440
 441 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 442         { .name = "Neutral",
 443           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 444                     0x44FA0000, 0x3F800000, 0x3F800000,
 445                     0x3F800000, 0x00000000, 0x00000000 }
 446         },
 447         { .name = "Female2Male",
 448           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 449                     0x44FA0000, 0x3F19999A, 0x3F866666,
 450                     0x3F800000, 0x00000000, 0x00000000 }
 451         },
 452         { .name = "Male2Female",
 453           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 454                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 455                     0x3F800000, 0x00000000, 0x00000000 }
 456         },
 457         { .name = "ScrappyKid",
 458           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 459                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 460                     0x3F800000, 0x00000000, 0x00000000 }
 461         },
 462         { .name = "Elderly",
 463           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 464                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 465                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 466         },
 467         { .name = "Orc",
 468           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 469                     0x45098000, 0x3F266666, 0x3FC00000,
 470                     0x3F800000, 0x00000000, 0x00000000 }
 471         },
 472         { .name = "Elf",
 473           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 474                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 475                     0x3F800000, 0x00000000, 0x00000000 }
 476         },
 477         { .name = "Dwarf",
 478           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 479                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 480                     0x3F800000, 0x00000000, 0x00000000 }
 481         },
 482         { .name = "AlienBrute",
 483           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 484                     0x451F6000, 0x3F266666, 0x3FA7D945,
 485                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 486         },
 487         { .name = "Robot",
 488           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 489                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 490                     0xBC07010E, 0x00000000, 0x00000000 }
 491         },
 492         { .name = "Marine",
 493           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 494                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 495                     0x3F0A3D71, 0x00000000, 0x00000000 }
 496         },
 497         { .name = "Emo",
 498           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 499                     0x44FA0000, 0x3F800000, 0x3F800000,
 500                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 501         },
 502         { .name = "DeepVoice",
 503           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 504                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 505                     0x3F800000, 0x00000000, 0x00000000 }
 506         },
 507         { .name = "Munchkin",
 508           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 509                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 510                     0x3F800000, 0x00000000, 0x00000000 }
 511         }
 512 };
 513
 514 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 515
 516 #define EQ_PRESET_MAX_PARAM_COUNT 11
 517
 518 struct ct_eq {
 519         char *name;
 520         hda_nid_t nid;
 521         int mid;
 522         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 523 };
 524
 525 struct ct_eq_preset {
 526         char *name; /*preset name*/
 527         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 528 };
 529
 530 static const struct ct_eq ca0132_alt_eq_enum = {
 531         .name = "FX: Equalizer Preset Switch",
 532         .nid = EQ_PRESET_ENUM,
 533         .mid = 0x96,
 534         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 535 };
 536
 537
 538 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 539         { .name = "Flat",
 540          .vals = { 0x00000000, 0x00000000, 0x00000000,
 541                    0x00000000, 0x00000000, 0x00000000,
 542                    0x00000000, 0x00000000, 0x00000000,
 543                    0x00000000, 0x00000000            }
 544         },
 545         { .name = "Acoustic",
 546          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 547                    0x40000000, 0x00000000, 0x00000000,
 548                    0x00000000, 0x00000000, 0x40000000,
 549                    0x40000000, 0x40000000            }
 550         },
 551         { .name = "Classical",
 552          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 553                    0x40C00000, 0x40466666, 0x00000000,
 554                    0x00000000, 0x00000000, 0x00000000,
 555                    0x40466666, 0x40466666            }
 556         },
 557         { .name = "Country",
 558          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 559                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 560                    0x00000000, 0x00000000, 0x40000000,
 561                    0x40466666, 0x40800000            }
 562         },
 563         { .name = "Dance",
 564          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 565                    0x40466666, 0x40866666, 0xBF99999A,
 566                    0xBF99999A, 0x00000000, 0x00000000,
 567                    0x40800000, 0x40800000            }
 568         },
 569         { .name = "Jazz",
 570          .vals = { 0x00000000, 0x00000000, 0x00000000,
 571                    0x3F8CCCCD, 0x40800000, 0x40800000,
 572                    0x40800000, 0x00000000, 0x3F8CCCCD,
 573                    0x40466666, 0x40466666            }
 574         },
 575         { .name = "New Age",
 576          .vals = { 0x00000000, 0x00000000, 0x40000000,
 577                    0x40000000, 0x00000000, 0x00000000,
 578                    0x00000000, 0x3F8CCCCD, 0x40000000,
 579                    0x40000000, 0x40000000            }
 580         },
 581         { .name = "Pop",
 582          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 583                    0x40000000, 0x40000000, 0x00000000,
 584                    0xBF99999A, 0xBF99999A, 0x00000000,
 585                    0x40466666, 0x40C00000            }
 586         },
 587         { .name = "Rock",
 588          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 589                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 590                    0xBF99999A, 0x00000000, 0x00000000,
 591                    0x40800000, 0x40800000            }
 592         },
 593         { .name = "Vocal",
 594          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 595                    0xBF99999A, 0x00000000, 0x40466666,
 596                    0x40800000, 0x40466666, 0x00000000,
 597                    0x00000000, 0x3F8CCCCD            }
 598         }
 599 };
 600
 601 /* DSP command sequences for ca0132_alt_select_out */
 602 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
 603 struct ca0132_alt_out_set {
 604         char *name; /*preset name*/
 605         unsigned char commands;
 606         unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
 607         unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
 608         unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
 609 };
 610
 611 static const struct ca0132_alt_out_set alt_out_presets[] = {
 612         { .name = "Line Out",
 613           .commands = 7,
 614           .mids = { 0x96, 0x96, 0x96, 0x8F,
 615                     0x96, 0x96, 0x96 },
 616           .reqs = { 0x19, 0x17, 0x18, 0x01,
 617                     0x1F, 0x15, 0x3A },
 618           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 619                     0x00000000, 0x00000000, 0x00000000,
 620                     0x00000000 }
 621         },
 622         { .name = "Headphone",
 623           .commands = 7,
 624           .mids = { 0x96, 0x96, 0x96, 0x8F,
 625                     0x96, 0x96, 0x96 },
 626           .reqs = { 0x19, 0x17, 0x18, 0x01,
 627                     0x1F, 0x15, 0x3A },
 628           .vals = { 0x3F000000, 0x42A00000, 0x00000000,
 629                     0x00000000, 0x00000000, 0x00000000,
 630                     0x00000000 }
 631         },
 632         { .name = "Surround",
 633           .commands = 8,
 634           .mids = { 0x96, 0x8F, 0x96, 0x96,
 635                     0x96, 0x96, 0x96, 0x96 },
 636           .reqs = { 0x18, 0x01, 0x1F, 0x15,
 637                     0x3A, 0x1A, 0x1B, 0x1C },
 638           .vals = { 0x00000000, 0x00000000, 0x00000000,
 639                     0x00000000, 0x00000000, 0x00000000,
 640                     0x00000000, 0x00000000 }
 641         }
 642 };
 643
 644 /*
 645  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 646  * and I don't know what the third req is, but it's always zero. I assume it's
 647  * some sort of update or set command to tell the DSP there's new volume info.
 648  */
 649 #define DSP_VOL_OUT 0
 650 #define DSP_VOL_IN  1
 651
 652 struct ct_dsp_volume_ctl {
 653         hda_nid_t vnid;
 654         int mid; /* module ID*/
 655         unsigned int reqs[3]; /* scp req ID */
 656 };
 657
 658 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 659         { .vnid = VNID_SPK,
 660           .mid = 0x32,
 661           .reqs = {3, 4, 2}
 662         },
 663         { .vnid = VNID_MIC,
 664           .mid = 0x37,
 665           .reqs = {2, 3, 1}
 666         }
 667 };
 668
 669 enum hda_cmd_vendor_io {
 670         /* for DspIO node */
 671         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 672         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 673
 674         VENDOR_DSPIO_STATUS                  = 0xF01,
 675         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 676         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 677         VENDOR_DSPIO_DSP_INIT                = 0x703,
 678         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 679         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 680
 681         /* for ChipIO node */
 682         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 683         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 684         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 685         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 686         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 687
 688         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 689         VENDOR_CHIPIO_STATUS                 = 0xF01,
 690         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 691         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 692
 693         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 694         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 695
 696         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 697         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 698
 699         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 700         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 701         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 702         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 703         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 704         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 705         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 706         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 707
 708         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 709         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 710         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 711         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 712
 713         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 714         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 715         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 716         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 717
 718         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 719         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 720         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 721         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 722         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 723         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 724
 725         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 726 };
 727
 728 /*
 729  *  Control flag IDs
 730  */
 731 enum control_flag_id {
 732         /* Connection manager stream setup is bypassed/enabled */
 733         CONTROL_FLAG_C_MGR                  = 0,
 734         /* DSP DMA is bypassed/enabled */
 735         CONTROL_FLAG_DMA                    = 1,
 736         /* 8051 'idle' mode is disabled/enabled */
 737         CONTROL_FLAG_IDLE_ENABLE            = 2,
 738         /* Tracker for the SPDIF-in path is bypassed/enabled */
 739         CONTROL_FLAG_TRACKER                = 3,
 740         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 741         CONTROL_FLAG_SPDIF2OUT              = 4,
 742         /* Digital Microphone is disabled/enabled */
 743         CONTROL_FLAG_DMIC                   = 5,
 744         /* ADC_B rate is 48 kHz/96 kHz */
 745         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 746         /* ADC_C rate is 48 kHz/96 kHz */
 747         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 748         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 749         CONTROL_FLAG_DAC_96KHZ              = 8,
 750         /* DSP rate is 48 kHz/96 kHz */
 751         CONTROL_FLAG_DSP_96KHZ              = 9,
 752         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 753         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 754         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 755         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 756         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 757         CONTROL_FLAG_DECODE_LOOP            = 12,
 758         /* De-emphasis filter on DAC-1 disabled/enabled */
 759         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 760         /* De-emphasis filter on DAC-2 disabled/enabled */
 761         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 762         /* De-emphasis filter on DAC-3 disabled/enabled */
 763         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 764         /* High-pass filter on ADC_B disabled/enabled */
 765         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 766         /* High-pass filter on ADC_C disabled/enabled */
 767         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 768         /* Common mode on Port_A disabled/enabled */
 769         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 770         /* Common mode on Port_D disabled/enabled */
 771         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 772         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 773         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 774         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 775         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 776         /* ASI rate is 48kHz/96kHz */
 777         CONTROL_FLAG_ASI_96KHZ              = 22,
 778         /* DAC power settings able to control attached ports no/yes */
 779         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 780         /* Clock Stop OK reporting is disabled/enabled */
 781         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 782         /* Number of control flags */
 783         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 784 };
 785
 786 /*
 787  * Control parameter IDs
 788  */
 789 enum control_param_id {
 790         /* 0: None, 1: Mic1In*/
 791         CONTROL_PARAM_VIP_SOURCE               = 1,
 792         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 793         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 794         /* Port A output stage gain setting to use when 16 Ohm output
 795          * impedance is selected*/
 796         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 797         /* Port D output stage gain setting to use when 16 Ohm output
 798          * impedance is selected*/
 799         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 800
 801         /* Stream Control */
 802
 803         /* Select stream with the given ID */
 804         CONTROL_PARAM_STREAM_ID                = 24,
 805         /* Source connection point for the selected stream */
 806         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 807         /* Destination connection point for the selected stream */
 808         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 809         /* Number of audio channels in the selected stream */
 810         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 811         /*Enable control for the selected stream */
 812         CONTROL_PARAM_STREAM_CONTROL           = 28,
 813
 814         /* Connection Point Control */
 815
 816         /* Select connection point with the given ID */
 817         CONTROL_PARAM_CONN_POINT_ID            = 29,
 818         /* Connection point sample rate */
 819         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 820
 821         /* Node Control */
 822
 823         /* Select HDA node with the given ID */
 824         CONTROL_PARAM_NODE_ID                  = 31
 825 };
 826
 827 /*
 828  *  Dsp Io Status codes
 829  */
 830 enum hda_vendor_status_dspio {
 831         /* Success */
 832         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 833         /* Busy, unable to accept new command, the host must retry */
 834         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 835         /* SCP command queue is full */
 836         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 837         /* SCP response queue is empty */
 838         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 839 };
 840
 841 /*
 842  *  Chip Io Status codes
 843  */
 844 enum hda_vendor_status_chipio {
 845         /* Success */
 846         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 847         /* Busy, unable to accept new command, the host must retry */
 848         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 849 };
 850
 851 /*
 852  *  CA0132 sample rate
 853  */
 854 enum ca0132_sample_rate {
 855         SR_6_000        = 0x00,
 856         SR_8_000        = 0x01,
 857         SR_9_600        = 0x02,
 858         SR_11_025       = 0x03,
 859         SR_16_000       = 0x04,
 860         SR_22_050       = 0x05,
 861         SR_24_000       = 0x06,
 862         SR_32_000       = 0x07,
 863         SR_44_100       = 0x08,
 864         SR_48_000       = 0x09,
 865         SR_88_200       = 0x0A,
 866         SR_96_000       = 0x0B,
 867         SR_144_000      = 0x0C,
 868         SR_176_400      = 0x0D,
 869         SR_192_000      = 0x0E,
 870         SR_384_000      = 0x0F,
 871
 872         SR_COUNT        = 0x10,
 873
 874         SR_RATE_UNKNOWN = 0x1F
 875 };
 876
 877 enum dsp_download_state {
 878         DSP_DOWNLOAD_FAILED = -1,
 879         DSP_DOWNLOAD_INIT   = 0,
 880         DSP_DOWNLOADING     = 1,
 881         DSP_DOWNLOADED      = 2
 882 };
 883
 884 /* retrieve parameters from hda format */
 885 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 886 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 887 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 888 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 889
 890 /*
 891  * CA0132 specific
 892  */
 893
 894 struct ca0132_spec {
 895         const struct snd_kcontrol_new *mixers[5];
 896         unsigned int num_mixers;
 897         const struct hda_verb *base_init_verbs;
 898         const struct hda_verb *base_exit_verbs;
 899         const struct hda_verb *chip_init_verbs;
 900         const struct hda_verb *desktop_init_verbs;
 901         struct hda_verb *spec_init_verbs;
 902         struct auto_pin_cfg autocfg;
 903
 904         /* Nodes configurations */
 905         struct hda_multi_out multiout;
 906         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 907         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 908         unsigned int num_outputs;
 909         hda_nid_t input_pins[AUTO_PIN_LAST];
 910         hda_nid_t adcs[AUTO_PIN_LAST];
 911         hda_nid_t dig_out;
 912         hda_nid_t dig_in;
 913         unsigned int num_inputs;
 914         hda_nid_t shared_mic_nid;
 915         hda_nid_t shared_out_nid;
 916         hda_nid_t unsol_tag_hp;
 917         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
 918         hda_nid_t unsol_tag_amic1;
 919
 920         /* chip access */
 921         struct mutex chipio_mutex; /* chip access mutex */
 922         u32 curr_chip_addx;
 923
 924         /* DSP download related */
 925         enum dsp_download_state dsp_state;
 926         unsigned int dsp_stream_id;
 927         unsigned int wait_scp;
 928         unsigned int wait_scp_header;
 929         unsigned int wait_num_data;
 930         unsigned int scp_resp_header;
 931         unsigned int scp_resp_data[4];
 932         unsigned int scp_resp_count;
 933         bool alt_firmware_present;
 934         bool startup_check_entered;
 935         bool dsp_reload;
 936
 937         /* mixer and effects related */
 938         unsigned char dmic_ctl;
 939         int cur_out_type;
 940         int cur_mic_type;
 941         long vnode_lvol[VNODES_COUNT];
 942         long vnode_rvol[VNODES_COUNT];
 943         long vnode_lswitch[VNODES_COUNT];
 944         long vnode_rswitch[VNODES_COUNT];
 945         long effects_switch[EFFECTS_COUNT];
 946         long voicefx_val;
 947         long cur_mic_boost;
 948         /* ca0132_alt control related values */
 949         unsigned char in_enum_val;
 950         unsigned char out_enum_val;
 951         unsigned char mic_boost_enum_val;
 952         unsigned char smart_volume_setting;
 953         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
 954         long xbass_xover_freq;
 955         long eq_preset_val;
 956         unsigned int tlv[4];
 957         struct hda_vmaster_mute_hook vmaster_mute;
 958
 959
 960         struct hda_codec *codec;
 961         struct delayed_work unsol_hp_work;
 962         int quirk;
 963
 964 #ifdef ENABLE_TUNING_CONTROLS
 965         long cur_ctl_vals[TUNING_CTLS_COUNT];
 966 #endif
 967         /*
 968          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
 969          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
 970          * things.
 971          */
 972         bool use_pci_mmio;
 973         void __iomem *mem_base;
 974
 975         /*
 976          * Whether or not to use the alt functions like alt_select_out,
 977          * alt_select_in, etc. Only used on desktop codecs for now, because of
 978          * surround sound support.
 979          */
 980         bool use_alt_functions;
 981
 982         /*
 983          * Whether or not to use alt controls:  volume effect sliders, EQ
 984          * presets, smart volume presets, and new control names with FX prefix.
 985          * Renames PlayEnhancement and CrystalVoice too.
 986          */
 987         bool use_alt_controls;
 988 };
 989
 990 /*
 991  * CA0132 quirks table
 992  */
 993 enum {
 994         QUIRK_NONE,
 995         QUIRK_ALIENWARE,
 996         QUIRK_ALIENWARE_M17XR4,
 997         QUIRK_SBZ,
 998         QUIRK_R3DI,
 999         QUIRK_R3D,
1000 };
1001
1002 static const struct hda_pintbl alienware_pincfgs[] = {
1003         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1004         { 0x0c, 0x411111f0 }, /* N/A */
1005         { 0x0d, 0x411111f0 }, /* N/A */
1006         { 0x0e, 0x411111f0 }, /* N/A */
1007         { 0x0f, 0x0321101f }, /* HP */
1008         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1009         { 0x11, 0x03a11021 }, /* Mic */
1010         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1011         { 0x13, 0x411111f0 }, /* N/A */
1012         { 0x18, 0x411111f0 }, /* N/A */
1013         {}
1014 };
1015
1016 /* Sound Blaster Z pin configs taken from Windows Driver */
1017 static const struct hda_pintbl sbz_pincfgs[] = {
1018         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1019         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1020         { 0x0d, 0x014510f0 }, /* Digital Out */
1021         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1022         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1023         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1024         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1025         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1026         { 0x13, 0x908700f0 }, /* What U Hear In*/
1027         { 0x18, 0x50d000f0 }, /* N/A */
1028         {}
1029 };
1030
1031 /* Recon3D pin configs taken from Windows Driver */
1032 static const struct hda_pintbl r3d_pincfgs[] = {
1033         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1034         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1035         { 0x0d, 0x014510f0 }, /* Digital Out */
1036         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1037         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1038         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1039         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1040         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1041         { 0x13, 0x908700f0 }, /* What U Hear In*/
1042         { 0x18, 0x50d000f0 }, /* N/A */
1043         {}
1044 };
1045
1046 /* Recon3D integrated pin configs taken from Windows Driver */
1047 static const struct hda_pintbl r3di_pincfgs[] = {
1048         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1049         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1050         { 0x0d, 0x014510f0 }, /* Digital Out */
1051         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1052         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1053         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1054         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1055         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1056         { 0x13, 0x908700f0 }, /* What U Hear In*/
1057         { 0x18, 0x500000f0 }, /* N/A */
1058         {}
1059 };
1060
1061 static const struct snd_pci_quirk ca0132_quirks[] = {
1062         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1063         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1064         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1065         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1066         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1067         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1068         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1069         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1070         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1071         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1072         {}
1073 };
1074
1075 /*
1076  * CA0132 codec access
1077  */
1078 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1079                 unsigned int verb, unsigned int parm, unsigned int *res)
1080 {
1081         unsigned int response;
1082         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1083         *res = response;
1084
1085         return ((response == -1) ? -1 : 0);
1086 }
1087
1088 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1089                 unsigned short converter_format, unsigned int *res)
1090 {
1091         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1092                                 converter_format & 0xffff, res);
1093 }
1094
1095 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1096                                 hda_nid_t nid, unsigned char stream,
1097                                 unsigned char channel, unsigned int *res)
1098 {
1099         unsigned char converter_stream_channel = 0;
1100
1101         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1102         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1103                                 converter_stream_channel, res);
1104 }
1105
1106 /* Chip access helper function */
1107 static int chipio_send(struct hda_codec *codec,
1108                        unsigned int reg,
1109                        unsigned int data)
1110 {
1111         unsigned int res;
1112         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1113
1114         /* send bits of data specified by reg */
1115         do {
1116                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1117                                          reg, data);
1118                 if (res == VENDOR_STATUS_CHIPIO_OK)
1119                         return 0;
1120                 msleep(20);
1121         } while (time_before(jiffies, timeout));
1122
1123         return -EIO;
1124 }
1125
1126 /*
1127  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1128  */
1129 static int chipio_write_address(struct hda_codec *codec,
1130                                 unsigned int chip_addx)
1131 {
1132         struct ca0132_spec *spec = codec->spec;
1133         int res;
1134
1135         if (spec->curr_chip_addx == chip_addx)
1136                         return 0;
1137
1138         /* send low 16 bits of the address */
1139         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1140                           chip_addx & 0xffff);
1141
1142         if (res != -EIO) {
1143                 /* send high 16 bits of the address */
1144                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1145                                   chip_addx >> 16);
1146         }
1147
1148         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1149
1150         return res;
1151 }
1152
1153 /*
1154  * Write data through the vendor widget -- NOT protected by the Mutex!
1155  */
1156 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1157 {
1158         struct ca0132_spec *spec = codec->spec;
1159         int res;
1160
1161         /* send low 16 bits of the data */
1162         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1163
1164         if (res != -EIO) {
1165                 /* send high 16 bits of the data */
1166                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1167                                   data >> 16);
1168         }
1169
1170         /*If no error encountered, automatically increment the address
1171         as per chip behaviour*/
1172         spec->curr_chip_addx = (res != -EIO) ?
1173                                         (spec->curr_chip_addx + 4) : ~0U;
1174         return res;
1175 }
1176
1177 /*
1178  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1179  */
1180 static int chipio_write_data_multiple(struct hda_codec *codec,
1181                                       const u32 *data,
1182                                       unsigned int count)
1183 {
1184         int status = 0;
1185
1186         if (data == NULL) {
1187                 codec_dbg(codec, "chipio_write_data null ptr\n");
1188                 return -EINVAL;
1189         }
1190
1191         while ((count-- != 0) && (status == 0))
1192                 status = chipio_write_data(codec, *data++);
1193
1194         return status;
1195 }
1196
1197
1198 /*
1199  * Read data through the vendor widget -- NOT protected by the Mutex!
1200  */
1201 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1202 {
1203         struct ca0132_spec *spec = codec->spec;
1204         int res;
1205
1206         /* post read */
1207         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1208
1209         if (res != -EIO) {
1210                 /* read status */
1211                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1212         }
1213
1214         if (res != -EIO) {
1215                 /* read data */
1216                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1217                                            VENDOR_CHIPIO_HIC_READ_DATA,
1218                                            0);
1219         }
1220
1221         /*If no error encountered, automatically increment the address
1222         as per chip behaviour*/
1223         spec->curr_chip_addx = (res != -EIO) ?
1224                                         (spec->curr_chip_addx + 4) : ~0U;
1225         return res;
1226 }
1227
1228 /*
1229  * Write given value to the given address through the chip I/O widget.
1230  * protected by the Mutex
1231  */
1232 static int chipio_write(struct hda_codec *codec,
1233                 unsigned int chip_addx, const unsigned int data)
1234 {
1235         struct ca0132_spec *spec = codec->spec;
1236         int err;
1237
1238         mutex_lock(&spec->chipio_mutex);
1239
1240         /* write the address, and if successful proceed to write data */
1241         err = chipio_write_address(codec, chip_addx);
1242         if (err < 0)
1243                 goto exit;
1244
1245         err = chipio_write_data(codec, data);
1246         if (err < 0)
1247                 goto exit;
1248
1249 exit:
1250         mutex_unlock(&spec->chipio_mutex);
1251         return err;
1252 }
1253
1254 /*
1255  * Write given value to the given address through the chip I/O widget.
1256  * not protected by the Mutex
1257  */
1258 static int chipio_write_no_mutex(struct hda_codec *codec,
1259                 unsigned int chip_addx, const unsigned int data)
1260 {
1261         int err;
1262
1263
1264         /* write the address, and if successful proceed to write data */
1265         err = chipio_write_address(codec, chip_addx);
1266         if (err < 0)
1267                 goto exit;
1268
1269         err = chipio_write_data(codec, data);
1270         if (err < 0)
1271                 goto exit;
1272
1273 exit:
1274         return err;
1275 }
1276
1277 /*
1278  * Write multiple values to the given address through the chip I/O widget.
1279  * protected by the Mutex
1280  */
1281 static int chipio_write_multiple(struct hda_codec *codec,
1282                                  u32 chip_addx,
1283                                  const u32 *data,
1284                                  unsigned int count)
1285 {
1286         struct ca0132_spec *spec = codec->spec;
1287         int status;
1288
1289         mutex_lock(&spec->chipio_mutex);
1290         status = chipio_write_address(codec, chip_addx);
1291         if (status < 0)
1292                 goto error;
1293
1294         status = chipio_write_data_multiple(codec, data, count);
1295 error:
1296         mutex_unlock(&spec->chipio_mutex);
1297
1298         return status;
1299 }
1300
1301 /*
1302  * Read the given address through the chip I/O widget
1303  * protected by the Mutex
1304  */
1305 static int chipio_read(struct hda_codec *codec,
1306                 unsigned int chip_addx, unsigned int *data)
1307 {
1308         struct ca0132_spec *spec = codec->spec;
1309         int err;
1310
1311         mutex_lock(&spec->chipio_mutex);
1312
1313         /* write the address, and if successful proceed to write data */
1314         err = chipio_write_address(codec, chip_addx);
1315         if (err < 0)
1316                 goto exit;
1317
1318         err = chipio_read_data(codec, data);
1319         if (err < 0)
1320                 goto exit;
1321
1322 exit:
1323         mutex_unlock(&spec->chipio_mutex);
1324         return err;
1325 }
1326
1327 /*
1328  * Set chip control flags through the chip I/O widget.
1329  */
1330 static void chipio_set_control_flag(struct hda_codec *codec,
1331                                     enum control_flag_id flag_id,
1332                                     bool flag_state)
1333 {
1334         unsigned int val;
1335         unsigned int flag_bit;
1336
1337         flag_bit = (flag_state ? 1 : 0);
1338         val = (flag_bit << 7) | (flag_id);
1339         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1340                             VENDOR_CHIPIO_FLAG_SET, val);
1341 }
1342
1343 /*
1344  * Set chip parameters through the chip I/O widget.
1345  */
1346 static void chipio_set_control_param(struct hda_codec *codec,
1347                 enum control_param_id param_id, int param_val)
1348 {
1349         struct ca0132_spec *spec = codec->spec;
1350         int val;
1351
1352         if ((param_id < 32) && (param_val < 8)) {
1353                 val = (param_val << 5) | (param_id);
1354                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1355                                     VENDOR_CHIPIO_PARAM_SET, val);
1356         } else {
1357                 mutex_lock(&spec->chipio_mutex);
1358                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1359                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1360                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1361                                             param_id);
1362                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1363                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1364                                             param_val);
1365                 }
1366                 mutex_unlock(&spec->chipio_mutex);
1367         }
1368 }
1369
1370 /*
1371  * Set chip parameters through the chip I/O widget. NO MUTEX.
1372  */
1373 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1374                 enum control_param_id param_id, int param_val)
1375 {
1376         int val;
1377
1378         if ((param_id < 32) && (param_val < 8)) {
1379                 val = (param_val << 5) | (param_id);
1380                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1381                                     VENDOR_CHIPIO_PARAM_SET, val);
1382         } else {
1383                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1384                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1385                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1386                                             param_id);
1387                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1388                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1389                                             param_val);
1390                 }
1391         }
1392 }
1393 /*
1394  * Connect stream to a source point, and then connect
1395  * that source point to a destination point.
1396  */
1397 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1398                                 int streamid, int source_point, int dest_point)
1399 {
1400         chipio_set_control_param_no_mutex(codec,
1401                         CONTROL_PARAM_STREAM_ID, streamid);
1402         chipio_set_control_param_no_mutex(codec,
1403                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1404         chipio_set_control_param_no_mutex(codec,
1405                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1406 }
1407
1408 /*
1409  * Set number of channels in the selected stream.
1410  */
1411 static void chipio_set_stream_channels(struct hda_codec *codec,
1412                                 int streamid, unsigned int channels)
1413 {
1414         chipio_set_control_param_no_mutex(codec,
1415                         CONTROL_PARAM_STREAM_ID, streamid);
1416         chipio_set_control_param_no_mutex(codec,
1417                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1418 }
1419
1420 /*
1421  * Enable/Disable audio stream.
1422  */
1423 static void chipio_set_stream_control(struct hda_codec *codec,
1424                                 int streamid, int enable)
1425 {
1426         chipio_set_control_param_no_mutex(codec,
1427                         CONTROL_PARAM_STREAM_ID, streamid);
1428         chipio_set_control_param_no_mutex(codec,
1429                         CONTROL_PARAM_STREAM_CONTROL, enable);
1430 }
1431
1432
1433 /*
1434  * Set sampling rate of the connection point. NO MUTEX.
1435  */
1436 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1437                                 int connid, enum ca0132_sample_rate rate)
1438 {
1439         chipio_set_control_param_no_mutex(codec,
1440                         CONTROL_PARAM_CONN_POINT_ID, connid);
1441         chipio_set_control_param_no_mutex(codec,
1442                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1443 }
1444
1445 /*
1446  * Set sampling rate of the connection point.
1447  */
1448 static void chipio_set_conn_rate(struct hda_codec *codec,
1449                                 int connid, enum ca0132_sample_rate rate)
1450 {
1451         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1452         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1453                                  rate);
1454 }
1455
1456 /*
1457  * Enable clocks.
1458  */
1459 static void chipio_enable_clocks(struct hda_codec *codec)
1460 {
1461         struct ca0132_spec *spec = codec->spec;
1462
1463         mutex_lock(&spec->chipio_mutex);
1464         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1465                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1466         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1468         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1470         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1471                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1472         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1474         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1476         mutex_unlock(&spec->chipio_mutex);
1477 }
1478
1479 /*
1480  * CA0132 DSP IO stuffs
1481  */
1482 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1483                       unsigned int data)
1484 {
1485         int res;
1486         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1487
1488         /* send bits of data specified by reg to dsp */
1489         do {
1490                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1491                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1492                         return res;
1493                 msleep(20);
1494         } while (time_before(jiffies, timeout));
1495
1496         return -EIO;
1497 }
1498
1499 /*
1500  * Wait for DSP to be ready for commands
1501  */
1502 static void dspio_write_wait(struct hda_codec *codec)
1503 {
1504         int status;
1505         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1506
1507         do {
1508                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1509                                                 VENDOR_DSPIO_STATUS, 0);
1510                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1511                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1512                         break;
1513                 msleep(1);
1514         } while (time_before(jiffies, timeout));
1515 }
1516
1517 /*
1518  * Write SCP data to DSP
1519  */
1520 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1521 {
1522         struct ca0132_spec *spec = codec->spec;
1523         int status;
1524
1525         dspio_write_wait(codec);
1526
1527         mutex_lock(&spec->chipio_mutex);
1528         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1529                             scp_data & 0xffff);
1530         if (status < 0)
1531                 goto error;
1532
1533         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1534                                     scp_data >> 16);
1535         if (status < 0)
1536                 goto error;
1537
1538         /* OK, now check if the write itself has executed*/
1539         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1540                                     VENDOR_DSPIO_STATUS, 0);
1541 error:
1542         mutex_unlock(&spec->chipio_mutex);
1543
1544         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1545                         -EIO : 0;
1546 }
1547
1548 /*
1549  * Write multiple SCP data to DSP
1550  */
1551 static int dspio_write_multiple(struct hda_codec *codec,
1552                                 unsigned int *buffer, unsigned int size)
1553 {
1554         int status = 0;
1555         unsigned int count;
1556
1557         if (buffer == NULL)
1558                 return -EINVAL;
1559
1560         count = 0;
1561         while (count < size) {
1562                 status = dspio_write(codec, *buffer++);
1563                 if (status != 0)
1564                         break;
1565                 count++;
1566         }
1567
1568         return status;
1569 }
1570
1571 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1572 {
1573         int status;
1574
1575         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1576         if (status == -EIO)
1577                 return status;
1578
1579         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1580         if (status == -EIO ||
1581             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1582                 return -EIO;
1583
1584         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1585                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1586
1587         return 0;
1588 }
1589
1590 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1591                                unsigned int *buf_size, unsigned int size_count)
1592 {
1593         int status = 0;
1594         unsigned int size = *buf_size;
1595         unsigned int count;
1596         unsigned int skip_count;
1597         unsigned int dummy;
1598
1599         if (buffer == NULL)
1600                 return -1;
1601
1602         count = 0;
1603         while (count < size && count < size_count) {
1604                 status = dspio_read(codec, buffer++);
1605                 if (status != 0)
1606                         break;
1607                 count++;
1608         }
1609
1610         skip_count = count;
1611         if (status == 0) {
1612                 while (skip_count < size) {
1613                         status = dspio_read(codec, &dummy);
1614                         if (status != 0)
1615                                 break;
1616                         skip_count++;
1617                 }
1618         }
1619         *buf_size = count;
1620
1621         return status;
1622 }
1623
1624 /*
1625  * Construct the SCP header using corresponding fields
1626  */
1627 static inline unsigned int
1628 make_scp_header(unsigned int target_id, unsigned int source_id,
1629                 unsigned int get_flag, unsigned int req,
1630                 unsigned int device_flag, unsigned int resp_flag,
1631                 unsigned int error_flag, unsigned int data_size)
1632 {
1633         unsigned int header = 0;
1634
1635         header = (data_size & 0x1f) << 27;
1636         header |= (error_flag & 0x01) << 26;
1637         header |= (resp_flag & 0x01) << 25;
1638         header |= (device_flag & 0x01) << 24;
1639         header |= (req & 0x7f) << 17;
1640         header |= (get_flag & 0x01) << 16;
1641         header |= (source_id & 0xff) << 8;
1642         header |= target_id & 0xff;
1643
1644         return header;
1645 }
1646
1647 /*
1648  * Extract corresponding fields from SCP header
1649  */
1650 static inline void
1651 extract_scp_header(unsigned int header,
1652                    unsigned int *target_id, unsigned int *source_id,
1653                    unsigned int *get_flag, unsigned int *req,
1654                    unsigned int *device_flag, unsigned int *resp_flag,
1655                    unsigned int *error_flag, unsigned int *data_size)
1656 {
1657         if (data_size)
1658                 *data_size = (header >> 27) & 0x1f;
1659         if (error_flag)
1660                 *error_flag = (header >> 26) & 0x01;
1661         if (resp_flag)
1662                 *resp_flag = (header >> 25) & 0x01;
1663         if (device_flag)
1664                 *device_flag = (header >> 24) & 0x01;
1665         if (req)
1666                 *req = (header >> 17) & 0x7f;
1667         if (get_flag)
1668                 *get_flag = (header >> 16) & 0x01;
1669         if (source_id)
1670                 *source_id = (header >> 8) & 0xff;
1671         if (target_id)
1672                 *target_id = header & 0xff;
1673 }
1674
1675 #define SCP_MAX_DATA_WORDS  (16)
1676
1677 /* Structure to contain any SCP message */
1678 struct scp_msg {
1679         unsigned int hdr;
1680         unsigned int data[SCP_MAX_DATA_WORDS];
1681 };
1682
1683 static void dspio_clear_response_queue(struct hda_codec *codec)
1684 {
1685         unsigned int dummy = 0;
1686         int status = -1;
1687
1688         /* clear all from the response queue */
1689         do {
1690                 status = dspio_read(codec, &dummy);
1691         } while (status == 0);
1692 }
1693
1694 static int dspio_get_response_data(struct hda_codec *codec)
1695 {
1696         struct ca0132_spec *spec = codec->spec;
1697         unsigned int data = 0;
1698         unsigned int count;
1699
1700         if (dspio_read(codec, &data) < 0)
1701                 return -EIO;
1702
1703         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1704                 spec->scp_resp_header = data;
1705                 spec->scp_resp_count = data >> 27;
1706                 count = spec->wait_num_data;
1707                 dspio_read_multiple(codec, spec->scp_resp_data,
1708                                     &spec->scp_resp_count, count);
1709                 return 0;
1710         }
1711
1712         return -EIO;
1713 }
1714
1715 /*
1716  * Send SCP message to DSP
1717  */
1718 static int dspio_send_scp_message(struct hda_codec *codec,
1719                                   unsigned char *send_buf,
1720                                   unsigned int send_buf_size,
1721                                   unsigned char *return_buf,
1722                                   unsigned int return_buf_size,
1723                                   unsigned int *bytes_returned)
1724 {
1725         struct ca0132_spec *spec = codec->spec;
1726         int status = -1;
1727         unsigned int scp_send_size = 0;
1728         unsigned int total_size;
1729         bool waiting_for_resp = false;
1730         unsigned int header;
1731         struct scp_msg *ret_msg;
1732         unsigned int resp_src_id, resp_target_id;
1733         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1734
1735         if (bytes_returned)
1736                 *bytes_returned = 0;
1737
1738         /* get scp header from buffer */
1739         header = *((unsigned int *)send_buf);
1740         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1741                            &device_flag, NULL, NULL, &data_size);
1742         scp_send_size = data_size + 1;
1743         total_size = (scp_send_size * 4);
1744
1745         if (send_buf_size < total_size)
1746                 return -EINVAL;
1747
1748         if (get_flag || device_flag) {
1749                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1750                         return -EINVAL;
1751
1752                 spec->wait_scp_header = *((unsigned int *)send_buf);
1753
1754                 /* swap source id with target id */
1755                 resp_target_id = src_id;
1756                 resp_src_id = target_id;
1757                 spec->wait_scp_header &= 0xffff0000;
1758                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1759                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1760                 spec->wait_scp = 1;
1761                 waiting_for_resp = true;
1762         }
1763
1764         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1765                                       scp_send_size);
1766         if (status < 0) {
1767                 spec->wait_scp = 0;
1768                 return status;
1769         }
1770
1771         if (waiting_for_resp) {
1772                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1773                 memset(return_buf, 0, return_buf_size);
1774                 do {
1775                         msleep(20);
1776                 } while (spec->wait_scp && time_before(jiffies, timeout));
1777                 waiting_for_resp = false;
1778                 if (!spec->wait_scp) {
1779                         ret_msg = (struct scp_msg *)return_buf;
1780                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1781                         memcpy(&ret_msg->data, spec->scp_resp_data,
1782                                spec->wait_num_data);
1783                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1784                         status = 0;
1785                 } else {
1786                         status = -EIO;
1787                 }
1788                 spec->wait_scp = 0;
1789         }
1790
1791         return status;
1792 }
1793
1794 /**
1795  * Prepare and send the SCP message to DSP
1796  * @codec: the HDA codec
1797  * @mod_id: ID of the DSP module to send the command
1798  * @req: ID of request to send to the DSP module
1799  * @dir: SET or GET
1800  * @data: pointer to the data to send with the request, request specific
1801  * @len: length of the data, in bytes
1802  * @reply: point to the buffer to hold data returned for a reply
1803  * @reply_len: length of the reply buffer returned from GET
1804  *
1805  * Returns zero or a negative error code.
1806  */
1807 static int dspio_scp(struct hda_codec *codec,
1808                 int mod_id, int src_id, int req, int dir, const void *data,
1809                 unsigned int len, void *reply, unsigned int *reply_len)
1810 {
1811         int status = 0;
1812         struct scp_msg scp_send, scp_reply;
1813         unsigned int ret_bytes, send_size, ret_size;
1814         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1815         unsigned int reply_data_size;
1816
1817         memset(&scp_send, 0, sizeof(scp_send));
1818         memset(&scp_reply, 0, sizeof(scp_reply));
1819
1820         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1821                 return -EINVAL;
1822
1823         if (dir == SCP_GET && reply == NULL) {
1824                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1825                 return -EINVAL;
1826         }
1827
1828         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1829                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1830                 return -EINVAL;
1831         }
1832
1833         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1834                                        0, 0, 0, len/sizeof(unsigned int));
1835         if (data != NULL && len > 0) {
1836                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1837                 memcpy(scp_send.data, data, len);
1838         }
1839
1840         ret_bytes = 0;
1841         send_size = sizeof(unsigned int) + len;
1842         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1843                                         send_size, (unsigned char *)&scp_reply,
1844                                         sizeof(scp_reply), &ret_bytes);
1845
1846         if (status < 0) {
1847                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1848                 return status;
1849         }
1850
1851         /* extract send and reply headers members */
1852         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1853                            NULL, NULL, NULL, NULL, NULL);
1854         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1855                            &reply_resp_flag, &reply_error_flag,
1856                            &reply_data_size);
1857
1858         if (!send_get_flag)
1859                 return 0;
1860
1861         if (reply_resp_flag && !reply_error_flag) {
1862                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1863                                         / sizeof(unsigned int);
1864
1865                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1866                         codec_dbg(codec, "reply too long for buf\n");
1867                         return -EINVAL;
1868                 } else if (ret_size != reply_data_size) {
1869                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1870                         return -EINVAL;
1871                 } else if (!reply) {
1872                         codec_dbg(codec, "NULL reply\n");
1873                         return -EINVAL;
1874                 } else {
1875                         *reply_len = ret_size*sizeof(unsigned int);
1876                         memcpy(reply, scp_reply.data, *reply_len);
1877                 }
1878         } else {
1879                 codec_dbg(codec, "reply ill-formed or errflag set\n");
1880                 return -EIO;
1881         }
1882
1883         return status;
1884 }
1885
1886 /*
1887  * Set DSP parameters
1888  */
1889 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1890                         int src_id, int req, const void *data, unsigned int len)
1891 {
1892         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1893                         NULL);
1894 }
1895
1896 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1897                         int req, const unsigned int data)
1898 {
1899         return dspio_set_param(codec, mod_id, 0x20, req, &data,
1900                         sizeof(unsigned int));
1901 }
1902
1903 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1904                         int req, const unsigned int data)
1905 {
1906         return dspio_set_param(codec, mod_id, 0x00, req, &data,
1907                         sizeof(unsigned int));
1908 }
1909
1910 /*
1911  * Allocate a DSP DMA channel via an SCP message
1912  */
1913 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1914 {
1915         int status = 0;
1916         unsigned int size = sizeof(dma_chan);
1917
1918         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1919         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1920                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1921                         dma_chan, &size);
1922
1923         if (status < 0) {
1924                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1925                 return status;
1926         }
1927
1928         if ((*dma_chan + 1) == 0) {
1929                 codec_dbg(codec, "no free dma channels to allocate\n");
1930                 return -EBUSY;
1931         }
1932
1933         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1934         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1935
1936         return status;
1937 }
1938
1939 /*
1940  * Free a DSP DMA via an SCP message
1941  */
1942 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1943 {
1944         int status = 0;
1945         unsigned int dummy = 0;
1946
1947         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1948         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1949
1950         status = dspio_scp(codec, MASTERCONTROL, 0x20,
1951                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1952                         sizeof(dma_chan), NULL, &dummy);
1953
1954         if (status < 0) {
1955                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1956                 return status;
1957         }
1958
1959         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1960
1961         return status;
1962 }
1963
1964 /*
1965  * (Re)start the DSP
1966  */
1967 static int dsp_set_run_state(struct hda_codec *codec)
1968 {
1969         unsigned int dbg_ctrl_reg;
1970         unsigned int halt_state;
1971         int err;
1972
1973         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1974         if (err < 0)
1975                 return err;
1976
1977         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1978                       DSP_DBGCNTL_STATE_LOBIT;
1979
1980         if (halt_state != 0) {
1981                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1982                                   DSP_DBGCNTL_SS_MASK);
1983                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1984                                    dbg_ctrl_reg);
1985                 if (err < 0)
1986                         return err;
1987
1988                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1989                                 DSP_DBGCNTL_EXEC_MASK;
1990                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1991                                    dbg_ctrl_reg);
1992                 if (err < 0)
1993                         return err;
1994         }
1995
1996         return 0;
1997 }
1998
1999 /*
2000  * Reset the DSP
2001  */
2002 static int dsp_reset(struct hda_codec *codec)
2003 {
2004         unsigned int res;
2005         int retry = 20;
2006
2007         codec_dbg(codec, "dsp_reset\n");
2008         do {
2009                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2010                 retry--;
2011         } while (res == -EIO && retry);
2012
2013         if (!retry) {
2014                 codec_dbg(codec, "dsp_reset timeout\n");
2015                 return -EIO;
2016         }
2017
2018         return 0;
2019 }
2020
2021 /*
2022  * Convert chip address to DSP address
2023  */
2024 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2025                                         bool *code, bool *yram)
2026 {
2027         *code = *yram = false;
2028
2029         if (UC_RANGE(chip_addx, 1)) {
2030                 *code = true;
2031                 return UC_OFF(chip_addx);
2032         } else if (X_RANGE_ALL(chip_addx, 1)) {
2033                 return X_OFF(chip_addx);
2034         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2035                 *yram = true;
2036                 return Y_OFF(chip_addx);
2037         }
2038
2039         return INVALID_CHIP_ADDRESS;
2040 }
2041
2042 /*
2043  * Check if the DSP DMA is active
2044  */
2045 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2046 {
2047         unsigned int dma_chnlstart_reg;
2048
2049         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2050
2051         return ((dma_chnlstart_reg & (1 <<
2052                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2053 }
2054
2055 static int dsp_dma_setup_common(struct hda_codec *codec,
2056                                 unsigned int chip_addx,
2057                                 unsigned int dma_chan,
2058                                 unsigned int port_map_mask,
2059                                 bool ovly)
2060 {
2061         int status = 0;
2062         unsigned int chnl_prop;
2063         unsigned int dsp_addx;
2064         unsigned int active;
2065         bool code, yram;
2066
2067         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2068
2069         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2070                 codec_dbg(codec, "dma chan num invalid\n");
2071                 return -EINVAL;
2072         }
2073
2074         if (dsp_is_dma_active(codec, dma_chan)) {
2075                 codec_dbg(codec, "dma already active\n");
2076                 return -EBUSY;
2077         }
2078
2079         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2080
2081         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2082                 codec_dbg(codec, "invalid chip addr\n");
2083                 return -ENXIO;
2084         }
2085
2086         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2087         active = 0;
2088
2089         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2090
2091         if (ovly) {
2092                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2093                                      &chnl_prop);
2094
2095                 if (status < 0) {
2096                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2097                         return status;
2098                 }
2099                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2100         }
2101
2102         if (!code)
2103                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2104         else
2105                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2106
2107         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2108
2109         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2110         if (status < 0) {
2111                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2112                 return status;
2113         }
2114         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2115
2116         if (ovly) {
2117                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2118                                      &active);
2119
2120                 if (status < 0) {
2121                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2122                         return status;
2123                 }
2124                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2125         }
2126
2127         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2128                 DSPDMAC_ACTIVE_AAR_MASK;
2129
2130         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2131         if (status < 0) {
2132                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2133                 return status;
2134         }
2135
2136         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2137
2138         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2139                               port_map_mask);
2140         if (status < 0) {
2141                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2142                 return status;
2143         }
2144         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2145
2146         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2147                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2148         if (status < 0) {
2149                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2150                 return status;
2151         }
2152         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2153
2154         codec_dbg(codec,
2155                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2156                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2157                    chip_addx, dsp_addx, dma_chan,
2158                    port_map_mask, chnl_prop, active);
2159
2160         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2161
2162         return 0;
2163 }
2164
2165 /*
2166  * Setup the DSP DMA per-transfer-specific registers
2167  */
2168 static int dsp_dma_setup(struct hda_codec *codec,
2169                         unsigned int chip_addx,
2170                         unsigned int count,
2171                         unsigned int dma_chan)
2172 {
2173         int status = 0;
2174         bool code, yram;
2175         unsigned int dsp_addx;
2176         unsigned int addr_field;
2177         unsigned int incr_field;
2178         unsigned int base_cnt;
2179         unsigned int cur_cnt;
2180         unsigned int dma_cfg = 0;
2181         unsigned int adr_ofs = 0;
2182         unsigned int xfr_cnt = 0;
2183         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2184                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2185
2186         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2187
2188         if (count > max_dma_count) {
2189                 codec_dbg(codec, "count too big\n");
2190                 return -EINVAL;
2191         }
2192
2193         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2194         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2195                 codec_dbg(codec, "invalid chip addr\n");
2196                 return -ENXIO;
2197         }
2198
2199         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2200
2201         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2202         incr_field   = 0;
2203
2204         if (!code) {
2205                 addr_field <<= 1;
2206                 if (yram)
2207                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2208
2209                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2210         }
2211
2212         dma_cfg = addr_field + incr_field;
2213         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2214                                 dma_cfg);
2215         if (status < 0) {
2216                 codec_dbg(codec, "write DMACFG Reg fail\n");
2217                 return status;
2218         }
2219         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2220
2221         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2222                                                         (code ? 0 : 1));
2223
2224         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2225                                 adr_ofs);
2226         if (status < 0) {
2227                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2228                 return status;
2229         }
2230         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2231
2232         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2233
2234         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2235
2236         xfr_cnt = base_cnt | cur_cnt;
2237
2238         status = chipio_write(codec,
2239                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2240         if (status < 0) {
2241                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2242                 return status;
2243         }
2244         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2245
2246         codec_dbg(codec,
2247                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2248                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2249                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2250
2251         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2252
2253         return 0;
2254 }
2255
2256 /*
2257  * Start the DSP DMA
2258  */
2259 static int dsp_dma_start(struct hda_codec *codec,
2260                          unsigned int dma_chan, bool ovly)
2261 {
2262         unsigned int reg = 0;
2263         int status = 0;
2264
2265         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2266
2267         if (ovly) {
2268                 status = chipio_read(codec,
2269                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2270
2271                 if (status < 0) {
2272                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2273                         return status;
2274                 }
2275                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2276
2277                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2278                                 DSPDMAC_CHNLSTART_DIS_MASK);
2279         }
2280
2281         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2282                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2283         if (status < 0) {
2284                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2285                 return status;
2286         }
2287         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2288
2289         return status;
2290 }
2291
2292 /*
2293  * Stop the DSP DMA
2294  */
2295 static int dsp_dma_stop(struct hda_codec *codec,
2296                         unsigned int dma_chan, bool ovly)
2297 {
2298         unsigned int reg = 0;
2299         int status = 0;
2300
2301         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2302
2303         if (ovly) {
2304                 status = chipio_read(codec,
2305                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2306
2307                 if (status < 0) {
2308                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2309                         return status;
2310                 }
2311                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2312                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2313                                 DSPDMAC_CHNLSTART_DIS_MASK);
2314         }
2315
2316         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2317                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2318         if (status < 0) {
2319                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2320                 return status;
2321         }
2322         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2323
2324         return status;
2325 }
2326
2327 /**
2328  * Allocate router ports
2329  *
2330  * @codec: the HDA codec
2331  * @num_chans: number of channels in the stream
2332  * @ports_per_channel: number of ports per channel
2333  * @start_device: start device
2334  * @port_map: pointer to the port list to hold the allocated ports
2335  *
2336  * Returns zero or a negative error code.
2337  */
2338 static int dsp_allocate_router_ports(struct hda_codec *codec,
2339                                      unsigned int num_chans,
2340                                      unsigned int ports_per_channel,
2341                                      unsigned int start_device,
2342                                      unsigned int *port_map)
2343 {
2344         int status = 0;
2345         int res;
2346         u8 val;
2347
2348         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2349         if (status < 0)
2350                 return status;
2351
2352         val = start_device << 6;
2353         val |= (ports_per_channel - 1) << 4;
2354         val |= num_chans - 1;
2355
2356         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2357                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2358                             val);
2359
2360         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2361                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2362                             MEM_CONNID_DSP);
2363
2364         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2365         if (status < 0)
2366                 return status;
2367
2368         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2369                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2370
2371         *port_map = res;
2372
2373         return (res < 0) ? res : 0;
2374 }
2375
2376 /*
2377  * Free router ports
2378  */
2379 static int dsp_free_router_ports(struct hda_codec *codec)
2380 {
2381         int status = 0;
2382
2383         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2384         if (status < 0)
2385                 return status;
2386
2387         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2388                             VENDOR_CHIPIO_PORT_FREE_SET,
2389                             MEM_CONNID_DSP);
2390
2391         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2392
2393         return status;
2394 }
2395
2396 /*
2397  * Allocate DSP ports for the download stream
2398  */
2399 static int dsp_allocate_ports(struct hda_codec *codec,
2400                         unsigned int num_chans,
2401                         unsigned int rate_multi, unsigned int *port_map)
2402 {
2403         int status;
2404
2405         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2406
2407         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2408                 codec_dbg(codec, "bad rate multiple\n");
2409                 return -EINVAL;
2410         }
2411
2412         status = dsp_allocate_router_ports(codec, num_chans,
2413                                            rate_multi, 0, port_map);
2414
2415         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2416
2417         return status;
2418 }
2419
2420 static int dsp_allocate_ports_format(struct hda_codec *codec,
2421                         const unsigned short fmt,
2422                         unsigned int *port_map)
2423 {
2424         int status;
2425         unsigned int num_chans;
2426
2427         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2428         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2429         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2430
2431         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2432                 codec_dbg(codec, "bad rate multiple\n");
2433                 return -EINVAL;
2434         }
2435
2436         num_chans = get_hdafmt_chs(fmt) + 1;
2437
2438         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2439
2440         return status;
2441 }
2442
2443 /*
2444  * free DSP ports
2445  */
2446 static int dsp_free_ports(struct hda_codec *codec)
2447 {
2448         int status;
2449
2450         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2451
2452         status = dsp_free_router_ports(codec);
2453         if (status < 0) {
2454                 codec_dbg(codec, "free router ports fail\n");
2455                 return status;
2456         }
2457         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2458
2459         return status;
2460 }
2461
2462 /*
2463  *  HDA DMA engine stuffs for DSP code download
2464  */
2465 struct dma_engine {
2466         struct hda_codec *codec;
2467         unsigned short m_converter_format;
2468         struct snd_dma_buffer *dmab;
2469         unsigned int buf_size;
2470 };
2471
2472
2473 enum dma_state {
2474         DMA_STATE_STOP  = 0,
2475         DMA_STATE_RUN   = 1
2476 };
2477
2478 static int dma_convert_to_hda_format(struct hda_codec *codec,
2479                 unsigned int sample_rate,
2480                 unsigned short channels,
2481                 unsigned short *hda_format)
2482 {
2483         unsigned int format_val;
2484
2485         format_val = snd_hdac_calc_stream_format(sample_rate,
2486                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2487
2488         if (hda_format)
2489                 *hda_format = (unsigned short)format_val;
2490
2491         return 0;
2492 }
2493
2494 /*
2495  *  Reset DMA for DSP download
2496  */
2497 static int dma_reset(struct dma_engine *dma)
2498 {
2499         struct hda_codec *codec = dma->codec;
2500         struct ca0132_spec *spec = codec->spec;
2501         int status;
2502
2503         if (dma->dmab->area)
2504                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2505
2506         status = snd_hda_codec_load_dsp_prepare(codec,
2507                         dma->m_converter_format,
2508                         dma->buf_size,
2509                         dma->dmab);
2510         if (status < 0)
2511                 return status;
2512         spec->dsp_stream_id = status;
2513         return 0;
2514 }
2515
2516 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2517 {
2518         bool cmd;
2519
2520         switch (state) {
2521         case DMA_STATE_STOP:
2522                 cmd = false;
2523                 break;
2524         case DMA_STATE_RUN:
2525                 cmd = true;
2526                 break;
2527         default:
2528                 return 0;
2529         }
2530
2531         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2532         return 0;
2533 }
2534
2535 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2536 {
2537         return dma->dmab->bytes;
2538 }
2539
2540 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2541 {
2542         return dma->dmab->area;
2543 }
2544
2545 static int dma_xfer(struct dma_engine *dma,
2546                 const unsigned int *data,
2547                 unsigned int count)
2548 {
2549         memcpy(dma->dmab->area, data, count);
2550         return 0;
2551 }
2552
2553 static void dma_get_converter_format(
2554                 struct dma_engine *dma,
2555                 unsigned short *format)
2556 {
2557         if (format)
2558                 *format = dma->m_converter_format;
2559 }
2560
2561 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2562 {
2563         struct ca0132_spec *spec = dma->codec->spec;
2564
2565         return spec->dsp_stream_id;
2566 }
2567
2568 struct dsp_image_seg {
2569         u32 magic;
2570         u32 chip_addr;
2571         u32 count;
2572         u32 data[0];
2573 };
2574
2575 static const u32 g_magic_value = 0x4c46584d;
2576 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2577
2578 static bool is_valid(const struct dsp_image_seg *p)
2579 {
2580         return p->magic == g_magic_value;
2581 }
2582
2583 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2584 {
2585         return g_chip_addr_magic_value == p->chip_addr;
2586 }
2587
2588 static bool is_last(const struct dsp_image_seg *p)
2589 {
2590         return p->count == 0;
2591 }
2592
2593 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2594 {
2595         return sizeof(*p) + p->count*sizeof(u32);
2596 }
2597
2598 static const struct dsp_image_seg *get_next_seg_ptr(
2599                                 const struct dsp_image_seg *p)
2600 {
2601         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2602 }
2603
2604 /*
2605  * CA0132 chip DSP transfer stuffs.  For DSP download.
2606  */
2607 #define INVALID_DMA_CHANNEL (~0U)
2608
2609 /*
2610  * Program a list of address/data pairs via the ChipIO widget.
2611  * The segment data is in the format of successive pairs of words.
2612  * These are repeated as indicated by the segment's count field.
2613  */
2614 static int dspxfr_hci_write(struct hda_codec *codec,
2615                         const struct dsp_image_seg *fls)
2616 {
2617         int status;
2618         const u32 *data;
2619         unsigned int count;
2620
2621         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2622                 codec_dbg(codec, "hci_write invalid params\n");
2623                 return -EINVAL;
2624         }
2625
2626         count = fls->count;
2627         data = (u32 *)(fls->data);
2628         while (count >= 2) {
2629                 status = chipio_write(codec, data[0], data[1]);
2630                 if (status < 0) {
2631                         codec_dbg(codec, "hci_write chipio failed\n");
2632                         return status;
2633                 }
2634                 count -= 2;
2635                 data  += 2;
2636         }
2637         return 0;
2638 }
2639
2640 /**
2641  * Write a block of data into DSP code or data RAM using pre-allocated
2642  * DMA engine.
2643  *
2644  * @codec: the HDA codec
2645  * @fls: pointer to a fast load image
2646  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2647  *         no relocation
2648  * @dma_engine: pointer to DMA engine to be used for DSP download
2649  * @dma_chan: The number of DMA channels used for DSP download
2650  * @port_map_mask: port mapping
2651  * @ovly: TRUE if overlay format is required
2652  *
2653  * Returns zero or a negative error code.
2654  */
2655 static int dspxfr_one_seg(struct hda_codec *codec,
2656                         const struct dsp_image_seg *fls,
2657                         unsigned int reloc,
2658                         struct dma_engine *dma_engine,
2659                         unsigned int dma_chan,
2660                         unsigned int port_map_mask,
2661                         bool ovly)
2662 {
2663         int status = 0;
2664         bool comm_dma_setup_done = false;
2665         const unsigned int *data;
2666         unsigned int chip_addx;
2667         unsigned int words_to_write;
2668         unsigned int buffer_size_words;
2669         unsigned char *buffer_addx;
2670         unsigned short hda_format;
2671         unsigned int sample_rate_div;
2672         unsigned int sample_rate_mul;
2673         unsigned int num_chans;
2674         unsigned int hda_frame_size_words;
2675         unsigned int remainder_words;
2676         const u32 *data_remainder;
2677         u32 chip_addx_remainder;
2678         unsigned int run_size_words;
2679         const struct dsp_image_seg *hci_write = NULL;
2680         unsigned long timeout;
2681         bool dma_active;
2682
2683         if (fls == NULL)
2684                 return -EINVAL;
2685         if (is_hci_prog_list_seg(fls)) {
2686                 hci_write = fls;
2687                 fls = get_next_seg_ptr(fls);
2688         }
2689
2690         if (hci_write && (!fls || is_last(fls))) {
2691                 codec_dbg(codec, "hci_write\n");
2692                 return dspxfr_hci_write(codec, hci_write);
2693         }
2694
2695         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2696                 codec_dbg(codec, "Invalid Params\n");
2697                 return -EINVAL;
2698         }
2699
2700         data = fls->data;
2701         chip_addx = fls->chip_addr,
2702         words_to_write = fls->count;
2703
2704         if (!words_to_write)
2705                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2706         if (reloc)
2707                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2708
2709         if (!UC_RANGE(chip_addx, words_to_write) &&
2710             !X_RANGE_ALL(chip_addx, words_to_write) &&
2711             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2712                 codec_dbg(codec, "Invalid chip_addx Params\n");
2713                 return -EINVAL;
2714         }
2715
2716         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2717                                         sizeof(u32);
2718
2719         buffer_addx = dma_get_buffer_addr(dma_engine);
2720
2721         if (buffer_addx == NULL) {
2722                 codec_dbg(codec, "dma_engine buffer NULL\n");
2723                 return -EINVAL;
2724         }
2725
2726         dma_get_converter_format(dma_engine, &hda_format);
2727         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2728         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2729         num_chans = get_hdafmt_chs(hda_format) + 1;
2730
2731         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2732                         (num_chans * sample_rate_mul / sample_rate_div));
2733
2734         if (hda_frame_size_words == 0) {
2735                 codec_dbg(codec, "frmsz zero\n");
2736                 return -EINVAL;
2737         }
2738
2739         buffer_size_words = min(buffer_size_words,
2740                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2741                                 65536 : 32768));
2742         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2743         codec_dbg(codec,
2744                    "chpadr=0x%08x frmsz=%u nchan=%u "
2745                    "rate_mul=%u div=%u bufsz=%u\n",
2746                    chip_addx, hda_frame_size_words, num_chans,
2747                    sample_rate_mul, sample_rate_div, buffer_size_words);
2748
2749         if (buffer_size_words < hda_frame_size_words) {
2750                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2751                 return -EINVAL;
2752         }
2753
2754         remainder_words = words_to_write % hda_frame_size_words;
2755         data_remainder = data;
2756         chip_addx_remainder = chip_addx;
2757
2758         data += remainder_words;
2759         chip_addx += remainder_words*sizeof(u32);
2760         words_to_write -= remainder_words;
2761
2762         while (words_to_write != 0) {
2763                 run_size_words = min(buffer_size_words, words_to_write);
2764                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2765                             words_to_write, run_size_words, remainder_words);
2766                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2767                 if (!comm_dma_setup_done) {
2768                         status = dsp_dma_stop(codec, dma_chan, ovly);
2769                         if (status < 0)
2770                                 return status;
2771                         status = dsp_dma_setup_common(codec, chip_addx,
2772                                                 dma_chan, port_map_mask, ovly);
2773                         if (status < 0)
2774                                 return status;
2775                         comm_dma_setup_done = true;
2776                 }
2777
2778                 status = dsp_dma_setup(codec, chip_addx,
2779                                                 run_size_words, dma_chan);
2780                 if (status < 0)
2781                         return status;
2782                 status = dsp_dma_start(codec, dma_chan, ovly);
2783                 if (status < 0)
2784                         return status;
2785                 if (!dsp_is_dma_active(codec, dma_chan)) {
2786                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2787                         return -EIO;
2788                 }
2789                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2790                 if (status < 0)
2791                         return status;
2792                 if (remainder_words != 0) {
2793                         status = chipio_write_multiple(codec,
2794                                                 chip_addx_remainder,
2795                                                 data_remainder,
2796                                                 remainder_words);
2797                         if (status < 0)
2798                                 return status;
2799                         remainder_words = 0;
2800                 }
2801                 if (hci_write) {
2802                         status = dspxfr_hci_write(codec, hci_write);
2803                         if (status < 0)
2804                                 return status;
2805                         hci_write = NULL;
2806                 }
2807
2808                 timeout = jiffies + msecs_to_jiffies(2000);
2809                 do {
2810                         dma_active = dsp_is_dma_active(codec, dma_chan);
2811                         if (!dma_active)
2812                                 break;
2813                         msleep(20);
2814                 } while (time_before(jiffies, timeout));
2815                 if (dma_active)
2816                         break;
2817
2818                 codec_dbg(codec, "+++++ DMA complete\n");
2819                 dma_set_state(dma_engine, DMA_STATE_STOP);
2820                 status = dma_reset(dma_engine);
2821
2822                 if (status < 0)
2823                         return status;
2824
2825                 data += run_size_words;
2826                 chip_addx += run_size_words*sizeof(u32);
2827                 words_to_write -= run_size_words;
2828         }
2829
2830         if (remainder_words != 0) {
2831                 status = chipio_write_multiple(codec, chip_addx_remainder,
2832                                         data_remainder, remainder_words);
2833         }
2834
2835         return status;
2836 }
2837
2838 /**
2839  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2840  *
2841  * @codec: the HDA codec
2842  * @fls_data: pointer to a fast load image
2843  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2844  *         no relocation
2845  * @sample_rate: sampling rate of the stream used for DSP download
2846  * @channels: channels of the stream used for DSP download
2847  * @ovly: TRUE if overlay format is required
2848  *
2849  * Returns zero or a negative error code.
2850  */
2851 static int dspxfr_image(struct hda_codec *codec,
2852                         const struct dsp_image_seg *fls_data,
2853                         unsigned int reloc,
2854                         unsigned int sample_rate,
2855                         unsigned short channels,
2856                         bool ovly)
2857 {
2858         struct ca0132_spec *spec = codec->spec;
2859         int status;
2860         unsigned short hda_format = 0;
2861         unsigned int response;
2862         unsigned char stream_id = 0;
2863         struct dma_engine *dma_engine;
2864         unsigned int dma_chan;
2865         unsigned int port_map_mask;
2866
2867         if (fls_data == NULL)
2868                 return -EINVAL;
2869
2870         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2871         if (!dma_engine)
2872                 return -ENOMEM;
2873
2874         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2875         if (!dma_engine->dmab) {
2876                 kfree(dma_engine);
2877                 return -ENOMEM;
2878         }
2879
2880         dma_engine->codec = codec;
2881         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2882         dma_engine->m_converter_format = hda_format;
2883         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2884                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2885
2886         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2887
2888         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2889                                         hda_format, &response);
2890
2891         if (status < 0) {
2892                 codec_dbg(codec, "set converter format fail\n");
2893                 goto exit;
2894         }
2895
2896         status = snd_hda_codec_load_dsp_prepare(codec,
2897                                 dma_engine->m_converter_format,
2898                                 dma_engine->buf_size,
2899                                 dma_engine->dmab);
2900         if (status < 0)
2901                 goto exit;
2902         spec->dsp_stream_id = status;
2903
2904         if (ovly) {
2905                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2906                 if (status < 0) {
2907                         codec_dbg(codec, "alloc dmachan fail\n");
2908                         dma_chan = INVALID_DMA_CHANNEL;
2909                         goto exit;
2910                 }
2911         }
2912
2913         port_map_mask = 0;
2914         status = dsp_allocate_ports_format(codec, hda_format,
2915                                         &port_map_mask);
2916         if (status < 0) {
2917                 codec_dbg(codec, "alloc ports fail\n");
2918                 goto exit;
2919         }
2920
2921         stream_id = dma_get_stream_id(dma_engine);
2922         status = codec_set_converter_stream_channel(codec,
2923                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2924         if (status < 0) {
2925                 codec_dbg(codec, "set stream chan fail\n");
2926                 goto exit;
2927         }
2928
2929         while ((fls_data != NULL) && !is_last(fls_data)) {
2930                 if (!is_valid(fls_data)) {
2931                         codec_dbg(codec, "FLS check fail\n");
2932                         status = -EINVAL;
2933                         goto exit;
2934                 }
2935                 status = dspxfr_one_seg(codec, fls_data, reloc,
2936                                         dma_engine, dma_chan,
2937                                         port_map_mask, ovly);
2938                 if (status < 0)
2939                         break;
2940
2941                 if (is_hci_prog_list_seg(fls_data))
2942                         fls_data = get_next_seg_ptr(fls_data);
2943
2944                 if ((fls_data != NULL) && !is_last(fls_data))
2945                         fls_data = get_next_seg_ptr(fls_data);
2946         }
2947
2948         if (port_map_mask != 0)
2949                 status = dsp_free_ports(codec);
2950
2951         if (status < 0)
2952                 goto exit;
2953
2954         status = codec_set_converter_stream_channel(codec,
2955                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2956
2957 exit:
2958         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2959                 dspio_free_dma_chan(codec, dma_chan);
2960
2961         if (dma_engine->dmab->area)
2962                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2963         kfree(dma_engine->dmab);
2964         kfree(dma_engine);
2965
2966         return status;
2967 }
2968
2969 /*
2970  * CA0132 DSP download stuffs.
2971  */
2972 static void dspload_post_setup(struct hda_codec *codec)
2973 {
2974         struct ca0132_spec *spec = codec->spec;
2975         codec_dbg(codec, "---- dspload_post_setup ------\n");
2976         if (!spec->use_alt_functions) {
2977                 /*set DSP speaker to 2.0 configuration*/
2978                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2979                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2980
2981                 /*update write pointer*/
2982                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2983         }
2984 }
2985
2986 /**
2987  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2988  *
2989  * @codec: the HDA codec
2990  * @fls: pointer to a fast load image
2991  * @ovly: TRUE if overlay format is required
2992  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2993  *         no relocation
2994  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2995  * @router_chans: number of audio router channels to be allocated (0 means use
2996  *                internal defaults; max is 32)
2997  *
2998  * Download DSP from a DSP Image Fast Load structure. This structure is a
2999  * linear, non-constant sized element array of structures, each of which
3000  * contain the count of the data to be loaded, the data itself, and the
3001  * corresponding starting chip address of the starting data location.
3002  * Returns zero or a negative error code.
3003  */
3004 static int dspload_image(struct hda_codec *codec,
3005                         const struct dsp_image_seg *fls,
3006                         bool ovly,
3007                         unsigned int reloc,
3008                         bool autostart,
3009                         int router_chans)
3010 {
3011         int status = 0;
3012         unsigned int sample_rate;
3013         unsigned short channels;
3014
3015         codec_dbg(codec, "---- dspload_image begin ------\n");
3016         if (router_chans == 0) {
3017                 if (!ovly)
3018                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3019                 else
3020                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3021         }
3022
3023         sample_rate = 48000;
3024         channels = (unsigned short)router_chans;
3025
3026         while (channels > 16) {
3027                 sample_rate *= 2;
3028                 channels /= 2;
3029         }
3030
3031         do {
3032                 codec_dbg(codec, "Ready to program DMA\n");
3033                 if (!ovly)
3034                         status = dsp_reset(codec);
3035
3036                 if (status < 0)
3037                         break;
3038
3039                 codec_dbg(codec, "dsp_reset() complete\n");
3040                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3041                                       ovly);
3042
3043                 if (status < 0)
3044                         break;
3045
3046                 codec_dbg(codec, "dspxfr_image() complete\n");
3047                 if (autostart && !ovly) {
3048                         dspload_post_setup(codec);
3049                         status = dsp_set_run_state(codec);
3050                 }
3051
3052                 codec_dbg(codec, "LOAD FINISHED\n");
3053         } while (0);
3054
3055         return status;
3056 }
3057
3058 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3059 static bool dspload_is_loaded(struct hda_codec *codec)
3060 {
3061         unsigned int data = 0;
3062         int status = 0;
3063
3064         status = chipio_read(codec, 0x40004, &data);
3065         if ((status < 0) || (data != 1))
3066                 return false;
3067
3068         return true;
3069 }
3070 #else
3071 #define dspload_is_loaded(codec)        false
3072 #endif
3073
3074 static bool dspload_wait_loaded(struct hda_codec *codec)
3075 {
3076         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3077
3078         do {
3079                 if (dspload_is_loaded(codec)) {
3080                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3081                         return true;
3082                 }
3083                 msleep(20);
3084         } while (time_before(jiffies, timeout));
3085
3086         codec_err(codec, "ca0132 failed to download DSP\n");
3087         return false;
3088 }
3089
3090 /*
3091  * Setup GPIO for the other variants of Core3D.
3092  */
3093
3094 /*
3095  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3096  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3097  * The first eight bits are just the number of the pin. So far, I've only seen
3098  * this number go to 7.
3099  */
3100 static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3101                 bool enable)
3102 {
3103         struct ca0132_spec *spec = codec->spec;
3104         unsigned short gpio_data;
3105
3106         gpio_data = gpio_pin & 0xF;
3107         gpio_data |= ((enable << 8) & 0x100);
3108
3109         writew(gpio_data, spec->mem_base + 0x320);
3110 }
3111
3112 /*
3113  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3114  * the card shows as having no GPIO pins.
3115  */
3116 static void ca0132_gpio_init(struct hda_codec *codec)
3117 {
3118         struct ca0132_spec *spec = codec->spec;
3119
3120         switch (spec->quirk) {
3121         case QUIRK_SBZ:
3122                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3123                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3124                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3125                 break;
3126         case QUIRK_R3DI:
3127                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3128                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3129                 break;
3130         }
3131
3132 }
3133
3134 /* Sets the GPIO for audio output. */
3135 static void ca0132_gpio_setup(struct hda_codec *codec)
3136 {
3137         struct ca0132_spec *spec = codec->spec;
3138
3139         switch (spec->quirk) {
3140         case QUIRK_SBZ:
3141                 snd_hda_codec_write(codec, 0x01, 0,
3142                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3143                 snd_hda_codec_write(codec, 0x01, 0,
3144                                 AC_VERB_SET_GPIO_MASK, 0x07);
3145                 snd_hda_codec_write(codec, 0x01, 0,
3146                                 AC_VERB_SET_GPIO_DATA, 0x04);
3147                 snd_hda_codec_write(codec, 0x01, 0,
3148                                 AC_VERB_SET_GPIO_DATA, 0x06);
3149                 break;
3150         case QUIRK_R3DI:
3151                 snd_hda_codec_write(codec, 0x01, 0,
3152                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3153                 snd_hda_codec_write(codec, 0x01, 0,
3154                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3155                 snd_hda_codec_write(codec, 0x01, 0,
3156                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3157                 break;
3158         }
3159 }
3160
3161 /*
3162  * GPIO control functions for the Recon3D integrated.
3163  */
3164
3165 enum r3di_gpio_bit {
3166         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3167         R3DI_MIC_SELECT_BIT = 1,
3168         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3169         R3DI_OUT_SELECT_BIT = 2,
3170         /*
3171          * I dunno what this actually does, but it stays on until the dsp
3172          * is downloaded.
3173          */
3174         R3DI_GPIO_DSP_DOWNLOADING = 3,
3175         /*
3176          * Same as above, no clue what it does, but it comes on after the dsp
3177          * is downloaded.
3178          */
3179         R3DI_GPIO_DSP_DOWNLOADED = 4
3180 };
3181
3182 enum r3di_mic_select {
3183         /* Set GPIO bit 1 to 0 for rear mic */
3184         R3DI_REAR_MIC = 0,
3185         /* Set GPIO bit 1 to 1 for front microphone*/
3186         R3DI_FRONT_MIC = 1
3187 };
3188
3189 enum r3di_out_select {
3190         /* Set GPIO bit 2 to 0 for headphone */
3191         R3DI_HEADPHONE_OUT = 0,
3192         /* Set GPIO bit 2 to 1 for speaker */
3193         R3DI_LINE_OUT = 1
3194 };
3195 enum r3di_dsp_status {
3196         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3197         R3DI_DSP_DOWNLOADING = 0,
3198         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3199         R3DI_DSP_DOWNLOADED = 1
3200 };
3201
3202
3203 static void r3di_gpio_mic_set(struct hda_codec *codec,
3204                 enum r3di_mic_select cur_mic)
3205 {
3206         unsigned int cur_gpio;
3207
3208         /* Get the current GPIO Data setup */
3209         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3210
3211         switch (cur_mic) {
3212         case R3DI_REAR_MIC:
3213                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3214                 break;
3215         case R3DI_FRONT_MIC:
3216                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3217                 break;
3218         }
3219         snd_hda_codec_write(codec, codec->core.afg, 0,
3220                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3221 }
3222
3223 static void r3di_gpio_out_set(struct hda_codec *codec,
3224                 enum r3di_out_select cur_out)
3225 {
3226         unsigned int cur_gpio;
3227
3228         /* Get the current GPIO Data setup */
3229         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3230
3231         switch (cur_out) {
3232         case R3DI_HEADPHONE_OUT:
3233                 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3234                 break;
3235         case R3DI_LINE_OUT:
3236                 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3237                 break;
3238         }
3239         snd_hda_codec_write(codec, codec->core.afg, 0,
3240                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3241 }
3242
3243 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3244                 enum r3di_dsp_status dsp_status)
3245 {
3246         unsigned int cur_gpio;
3247
3248         /* Get the current GPIO Data setup */
3249         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3250
3251         switch (dsp_status) {
3252         case R3DI_DSP_DOWNLOADING:
3253                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3254                 snd_hda_codec_write(codec, codec->core.afg, 0,
3255                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3256                 break;
3257         case R3DI_DSP_DOWNLOADED:
3258                 /* Set DOWNLOADING bit to 0. */
3259                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3260
3261                 snd_hda_codec_write(codec, codec->core.afg, 0,
3262                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3263
3264                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3265                 break;
3266         }
3267
3268         snd_hda_codec_write(codec, codec->core.afg, 0,
3269                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3270 }
3271
3272 /*
3273  * PCM callbacks
3274  */
3275 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3276                         struct hda_codec *codec,
3277                         unsigned int stream_tag,
3278                         unsigned int format,
3279                         struct snd_pcm_substream *substream)
3280 {
3281         struct ca0132_spec *spec = codec->spec;
3282
3283         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3284
3285         return 0;
3286 }
3287
3288 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3289                         struct hda_codec *codec,
3290                         struct snd_pcm_substream *substream)
3291 {
3292         struct ca0132_spec *spec = codec->spec;
3293
3294         if (spec->dsp_state == DSP_DOWNLOADING)
3295                 return 0;
3296
3297         /*If Playback effects are on, allow stream some time to flush
3298          *effects tail*/
3299         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3300                 msleep(50);
3301
3302         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3303
3304         return 0;
3305 }
3306
3307 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3308                         struct hda_codec *codec,
3309                         struct snd_pcm_substream *substream)
3310 {
3311         struct ca0132_spec *spec = codec->spec;
3312         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3313         struct snd_pcm_runtime *runtime = substream->runtime;
3314
3315         if (spec->dsp_state != DSP_DOWNLOADED)
3316                 return 0;
3317
3318         /* Add latency if playback enhancement and either effect is enabled. */
3319         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3320                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3321                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3322                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3323         }
3324
3325         /* Applying Speaker EQ adds latency as well. */
3326         if (spec->cur_out_type == SPEAKER_OUT)
3327                 latency += DSP_SPEAKER_OUT_LATENCY;
3328
3329         return (latency * runtime->rate) / 1000;
3330 }
3331
3332 /*
3333  * Digital out
3334  */
3335 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3336                                         struct hda_codec *codec,
3337                                         struct snd_pcm_substream *substream)
3338 {
3339         struct ca0132_spec *spec = codec->spec;
3340         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3341 }
3342
3343 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3344                         struct hda_codec *codec,
3345                         unsigned int stream_tag,
3346                         unsigned int format,
3347                         struct snd_pcm_substream *substream)
3348 {
3349         struct ca0132_spec *spec = codec->spec;
3350         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3351                                              stream_tag, format, substream);
3352 }
3353
3354 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3355                         struct hda_codec *codec,
3356                         struct snd_pcm_substream *substream)
3357 {
3358         struct ca0132_spec *spec = codec->spec;
3359         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3360 }
3361
3362 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3363                                          struct hda_codec *codec,
3364                                          struct snd_pcm_substream *substream)
3365 {
3366         struct ca0132_spec *spec = codec->spec;
3367         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3368 }
3369
3370 /*
3371  * Analog capture
3372  */
3373 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3374                                         struct hda_codec *codec,
3375                                         unsigned int stream_tag,
3376                                         unsigned int format,
3377                                         struct snd_pcm_substream *substream)
3378 {
3379         snd_hda_codec_setup_stream(codec, hinfo->nid,
3380                                    stream_tag, 0, format);
3381
3382         return 0;
3383 }
3384
3385 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3386                         struct hda_codec *codec,
3387                         struct snd_pcm_substream *substream)
3388 {
3389         struct ca0132_spec *spec = codec->spec;
3390
3391         if (spec->dsp_state == DSP_DOWNLOADING)
3392                 return 0;
3393
3394         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3395         return 0;
3396 }
3397
3398 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3399                         struct hda_codec *codec,
3400                         struct snd_pcm_substream *substream)
3401 {
3402         struct ca0132_spec *spec = codec->spec;
3403         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3404         struct snd_pcm_runtime *runtime = substream->runtime;
3405
3406         if (spec->dsp_state != DSP_DOWNLOADED)
3407                 return 0;
3408
3409         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3410                 latency += DSP_CRYSTAL_VOICE_LATENCY;
3411
3412         return (latency * runtime->rate) / 1000;
3413 }
3414
3415 /*
3416  * Controls stuffs.
3417  */
3418
3419 /*
3420  * Mixer controls helpers.
3421  */
3422 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3423         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3424           .name = xname, \
3425           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3426           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3427                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3428                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3429           .info = ca0132_volume_info, \
3430           .get = ca0132_volume_get, \
3431           .put = ca0132_volume_put, \
3432           .tlv = { .c = ca0132_volume_tlv }, \
3433           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3434
3435 /*
3436  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3437  * volume put, which is used for setting the DSP volume. This was done because
3438  * the ca0132 functions were taking too much time and causing lag.
3439  */
3440 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3441         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3442           .name = xname, \
3443           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3444           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3445                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3446                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3447           .info = snd_hda_mixer_amp_volume_info, \
3448           .get = snd_hda_mixer_amp_volume_get, \
3449           .put = ca0132_alt_volume_put, \
3450           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3451           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3452
3453 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3454         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3455           .name = xname, \
3456           .subdevice = HDA_SUBDEV_AMP_FLAG, \
3457           .info = snd_hda_mixer_amp_switch_info, \
3458           .get = ca0132_switch_get, \
3459           .put = ca0132_switch_put, \
3460           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3461
3462 /* stereo */
3463 #define CA0132_CODEC_VOL(xname, nid, dir) \
3464         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3465 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3466         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3467 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3468         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3469
3470 /* lookup tables */
3471 /*
3472  * Lookup table with decibel values for the DSP. When volume is changed in
3473  * Windows, the DSP is also sent the dB value in floating point. In Windows,
3474  * these values have decimal points, probably because the Windows driver
3475  * actually uses floating point. We can't here, so I made a lookup table of
3476  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3477  * DAC's, and 9 is the maximum.
3478  */
3479 static const unsigned int float_vol_db_lookup[] = {
3480 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3481 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3482 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3483 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3484 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3485 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3486 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3487 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3488 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3489 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3490 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3491 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3492 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3493 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3494 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3495 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3496 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3497 };
3498
3499 /*
3500  * This table counts from float 0 to 1 in increments of .01, which is
3501  * useful for a few different sliders.
3502  */
3503 static const unsigned int float_zero_to_one_lookup[] = {
3504 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3505 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3506 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3507 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3508 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3509 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3510 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3511 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3512 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3513 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3514 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3515 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3516 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3517 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3518 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3519 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3520 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3521 };
3522
3523 /*
3524  * This table counts from float 10 to 1000, which is the range of the x-bass
3525  * crossover slider in Windows.
3526  */
3527 static const unsigned int float_xbass_xover_lookup[] = {
3528 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3529 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3530 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3531 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3532 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3533 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3534 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3535 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3536 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3537 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3538 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3539 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3540 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3541 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3542 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3543 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3544 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3545 };
3546
3547 /* The following are for tuning of products */
3548 #ifdef ENABLE_TUNING_CONTROLS
3549
3550 static unsigned int voice_focus_vals_lookup[] = {
3551 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3552 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3553 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3554 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3555 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3556 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3557 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3558 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3559 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3560 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3561 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3562 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3563 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3564 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3565 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3566 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3567 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3568 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3569 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3570 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3571 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3572 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3573 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3574 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3575 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3576 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3577 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3578 };
3579
3580 static unsigned int mic_svm_vals_lookup[] = {
3581 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3582 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3583 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3584 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3585 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3586 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3587 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3588 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3589 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3590 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3591 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3592 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3593 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3594 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3595 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3596 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3597 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3598 };
3599
3600 static unsigned int equalizer_vals_lookup[] = {
3601 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3602 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3603 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3604 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3605 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3606 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3607 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3608 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3609 0x41C00000
3610 };
3611
3612 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3613                           unsigned int *lookup, int idx)
3614 {
3615         int i = 0;
3616
3617         for (i = 0; i < TUNING_CTLS_COUNT; i++)
3618                 if (nid == ca0132_tuning_ctls[i].nid)
3619                         break;
3620
3621         snd_hda_power_up(codec);
3622         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3623                         ca0132_tuning_ctls[i].req,
3624                         &(lookup[idx]), sizeof(unsigned int));
3625         snd_hda_power_down(codec);
3626
3627         return 1;
3628 }
3629
3630 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3631                           struct snd_ctl_elem_value *ucontrol)
3632 {
3633         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3634         struct ca0132_spec *spec = codec->spec;
3635         hda_nid_t nid = get_amp_nid(kcontrol);
3636         long *valp = ucontrol->value.integer.value;
3637         int idx = nid - TUNING_CTL_START_NID;
3638
3639         *valp = spec->cur_ctl_vals[idx];
3640         return 0;
3641 }
3642
3643 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3644                               struct snd_ctl_elem_info *uinfo)
3645 {
3646         int chs = get_amp_channels(kcontrol);
3647         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3648         uinfo->count = chs == 3 ? 2 : 1;
3649         uinfo->value.integer.min = 20;
3650         uinfo->value.integer.max = 180;
3651         uinfo->value.integer.step = 1;
3652
3653         return 0;
3654 }
3655
3656 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3657                                 struct snd_ctl_elem_value *ucontrol)
3658 {
3659         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3660         struct ca0132_spec *spec = codec->spec;
3661         hda_nid_t nid = get_amp_nid(kcontrol);
3662         long *valp = ucontrol->value.integer.value;
3663         int idx;
3664
3665         idx = nid - TUNING_CTL_START_NID;
3666         /* any change? */
3667         if (spec->cur_ctl_vals[idx] == *valp)
3668                 return 0;
3669
3670         spec->cur_ctl_vals[idx] = *valp;
3671
3672         idx = *valp - 20;
3673         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3674
3675         return 1;
3676 }
3677
3678 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3679                               struct snd_ctl_elem_info *uinfo)
3680 {
3681         int chs = get_amp_channels(kcontrol);
3682         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3683         uinfo->count = chs == 3 ? 2 : 1;
3684         uinfo->value.integer.min = 0;
3685         uinfo->value.integer.max = 100;
3686         uinfo->value.integer.step = 1;
3687
3688         return 0;
3689 }
3690
3691 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3692                                 struct snd_ctl_elem_value *ucontrol)
3693 {
3694         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3695         struct ca0132_spec *spec = codec->spec;
3696         hda_nid_t nid = get_amp_nid(kcontrol);
3697         long *valp = ucontrol->value.integer.value;
3698         int idx;
3699
3700         idx = nid - TUNING_CTL_START_NID;
3701         /* any change? */
3702         if (spec->cur_ctl_vals[idx] == *valp)
3703                 return 0;
3704
3705         spec->cur_ctl_vals[idx] = *valp;
3706
3707         idx = *valp;
3708         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3709
3710         return 0;
3711 }
3712
3713 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3714                               struct snd_ctl_elem_info *uinfo)
3715 {
3716         int chs = get_amp_channels(kcontrol);
3717         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3718         uinfo->count = chs == 3 ? 2 : 1;
3719         uinfo->value.integer.min = 0;
3720         uinfo->value.integer.max = 48;
3721         uinfo->value.integer.step = 1;
3722
3723         return 0;
3724 }
3725
3726 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3727                                 struct snd_ctl_elem_value *ucontrol)
3728 {
3729         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3730         struct ca0132_spec *spec = codec->spec;
3731         hda_nid_t nid = get_amp_nid(kcontrol);
3732         long *valp = ucontrol->value.integer.value;
3733         int idx;
3734
3735         idx = nid - TUNING_CTL_START_NID;
3736         /* any change? */
3737         if (spec->cur_ctl_vals[idx] == *valp)
3738                 return 0;
3739
3740         spec->cur_ctl_vals[idx] = *valp;
3741
3742         idx = *valp;
3743         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3744
3745         return 1;
3746 }
3747
3748 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3749 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3750
3751 static int add_tuning_control(struct hda_codec *codec,
3752                                 hda_nid_t pnid, hda_nid_t nid,
3753                                 const char *name, int dir)
3754 {
3755         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3756         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3757         struct snd_kcontrol_new knew =
3758                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3759
3760         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3761                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3762         knew.tlv.c = 0;
3763         knew.tlv.p = 0;
3764         switch (pnid) {
3765         case VOICE_FOCUS:
3766                 knew.info = voice_focus_ctl_info;
3767                 knew.get = tuning_ctl_get;
3768                 knew.put = voice_focus_ctl_put;
3769                 knew.tlv.p = voice_focus_db_scale;
3770                 break;
3771         case MIC_SVM:
3772                 knew.info = mic_svm_ctl_info;
3773                 knew.get = tuning_ctl_get;
3774                 knew.put = mic_svm_ctl_put;
3775                 break;
3776         case EQUALIZER:
3777                 knew.info = equalizer_ctl_info;
3778                 knew.get = tuning_ctl_get;
3779                 knew.put = equalizer_ctl_put;
3780                 knew.tlv.p = eq_db_scale;
3781                 break;
3782         default:
3783                 return 0;
3784         }
3785         knew.private_value =
3786                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3787         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3788         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3789 }
3790
3791 static int add_tuning_ctls(struct hda_codec *codec)
3792 {
3793         int i;
3794         int err;
3795
3796         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3797                 err = add_tuning_control(codec,
3798                                         ca0132_tuning_ctls[i].parent_nid,
3799                                         ca0132_tuning_ctls[i].nid,
3800                                         ca0132_tuning_ctls[i].name,
3801                                         ca0132_tuning_ctls[i].direct);
3802                 if (err < 0)
3803                         return err;
3804         }
3805
3806         return 0;
3807 }
3808
3809 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3810 {
3811         struct ca0132_spec *spec = codec->spec;
3812         int i;
3813
3814         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3815         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3816         /* SVM level defaults to 0.74. */
3817         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3818
3819         /* EQ defaults to 0dB. */
3820         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3821                 spec->cur_ctl_vals[i] = 24;
3822 }
3823 #endif /*ENABLE_TUNING_CONTROLS*/
3824
3825 /*
3826  * Select the active output.
3827  * If autodetect is enabled, output will be selected based on jack detection.
3828  * If jack inserted, headphone will be selected, else built-in speakers
3829  * If autodetect is disabled, output will be selected based on selection.
3830  */
3831 static int ca0132_select_out(struct hda_codec *codec)
3832 {
3833         struct ca0132_spec *spec = codec->spec;
3834         unsigned int pin_ctl;
3835         int jack_present;
3836         int auto_jack;
3837         unsigned int tmp;
3838         int err;
3839
3840         codec_dbg(codec, "ca0132_select_out\n");
3841
3842         snd_hda_power_up_pm(codec);
3843
3844         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3845
3846         if (auto_jack)
3847                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3848         else
3849                 jack_present =
3850                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3851
3852         if (jack_present)
3853                 spec->cur_out_type = HEADPHONE_OUT;
3854         else
3855                 spec->cur_out_type = SPEAKER_OUT;
3856
3857         if (spec->cur_out_type == SPEAKER_OUT) {
3858                 codec_dbg(codec, "ca0132_select_out speaker\n");
3859                 /*speaker out config*/
3860                 tmp = FLOAT_ONE;
3861                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3862                 if (err < 0)
3863                         goto exit;
3864                 /*enable speaker EQ*/
3865                 tmp = FLOAT_ONE;
3866                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3867                 if (err < 0)
3868                         goto exit;
3869
3870                 /* Setup EAPD */
3871                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3872                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3873                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3874                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3875                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3876                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3877                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3878                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3879
3880                 /* disable headphone node */
3881                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3882                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3883                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3884                                     pin_ctl & ~PIN_HP);
3885                 /* enable speaker node */
3886                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3887                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3888                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3889                                     pin_ctl | PIN_OUT);
3890         } else {
3891                 codec_dbg(codec, "ca0132_select_out hp\n");
3892                 /*headphone out config*/
3893                 tmp = FLOAT_ZERO;
3894                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3895                 if (err < 0)
3896                         goto exit;
3897                 /*disable speaker EQ*/
3898                 tmp = FLOAT_ZERO;
3899                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3900                 if (err < 0)
3901                         goto exit;
3902
3903                 /* Setup EAPD */
3904                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3905                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3906                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3907                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3908                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3909                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3910                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3911                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3912
3913                 /* disable speaker*/
3914                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3915                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3916                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3917                                     pin_ctl & ~PIN_HP);
3918                 /* enable headphone*/
3919                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3920                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3921                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3922                                     pin_ctl | PIN_HP);
3923         }
3924
3925 exit:
3926         snd_hda_power_down_pm(codec);
3927
3928         return err < 0 ? err : 0;
3929 }
3930
3931 /*
3932  * This function behaves similarly to the ca0132_select_out funciton above,
3933  * except with a few differences. It adds the ability to select the current
3934  * output with an enumerated control "output source" if the auto detect
3935  * mute switch is set to off. If the auto detect mute switch is enabled, it
3936  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3937  * It also adds the ability to auto-detect the front headphone port. The only
3938  * way to select surround is to disable auto detect, and set Surround with the
3939  * enumerated control.
3940  */
3941 static int ca0132_alt_select_out(struct hda_codec *codec)
3942 {
3943         struct ca0132_spec *spec = codec->spec;
3944         unsigned int pin_ctl;
3945         int jack_present;
3946         int auto_jack;
3947         unsigned int i;
3948         unsigned int tmp;
3949         int err;
3950         /* Default Headphone is rear headphone */
3951         hda_nid_t headphone_nid = spec->out_pins[1];
3952
3953         codec_dbg(codec, "%s\n", __func__);
3954
3955         snd_hda_power_up_pm(codec);
3956
3957         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3958
3959         /*
3960          * If headphone rear or front is plugged in, set to headphone.
3961          * If neither is plugged in, set to rear line out. Only if
3962          * hp/speaker auto detect is enabled.
3963          */
3964         if (auto_jack) {
3965                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3966                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3967
3968                 if (jack_present)
3969                         spec->cur_out_type = HEADPHONE_OUT;
3970                 else
3971                         spec->cur_out_type = SPEAKER_OUT;
3972         } else
3973                 spec->cur_out_type = spec->out_enum_val;
3974
3975         /* Begin DSP output switch */
3976         tmp = FLOAT_ONE;
3977         err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3978         if (err < 0)
3979                 goto exit;
3980
3981         switch (spec->cur_out_type) {
3982         case SPEAKER_OUT:
3983                 codec_dbg(codec, "%s speaker\n", __func__);
3984                 /*speaker out config*/
3985                 switch (spec->quirk) {
3986                 case QUIRK_SBZ:
3987                         ca0132_mmio_gpio_set(codec, 7, false);
3988                         ca0132_mmio_gpio_set(codec, 4, true);
3989                         ca0132_mmio_gpio_set(codec, 1, true);
3990                         chipio_set_control_param(codec, 0x0D, 0x18);
3991                         break;
3992                 case QUIRK_R3DI:
3993                         chipio_set_control_param(codec, 0x0D, 0x24);
3994                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3995                         break;
3996                 case QUIRK_R3D:
3997                         chipio_set_control_param(codec, 0x0D, 0x24);
3998                         ca0132_mmio_gpio_set(codec, 1, true);
3999                         break;
4000                 }
4001
4002                 /* disable headphone node */
4003                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4004                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4005                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4006                                     pin_ctl & ~PIN_HP);
4007                 /* enable line-out node */
4008                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4009                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4010                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4011                                     pin_ctl | PIN_OUT);
4012                 /* Enable EAPD */
4013                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4014                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4015
4016                 /* If PlayEnhancement is enabled, set different source */
4017                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4018                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4019                 else
4020                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4021                 break;
4022         case HEADPHONE_OUT:
4023                 codec_dbg(codec, "%s hp\n", __func__);
4024                 /* Headphone out config*/
4025                 switch (spec->quirk) {
4026                 case QUIRK_SBZ:
4027                         ca0132_mmio_gpio_set(codec, 7, true);
4028                         ca0132_mmio_gpio_set(codec, 4, true);
4029                         ca0132_mmio_gpio_set(codec, 1, false);
4030                         chipio_set_control_param(codec, 0x0D, 0x12);
4031                         break;
4032                 case QUIRK_R3DI:
4033                         chipio_set_control_param(codec, 0x0D, 0x21);
4034                         r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4035                         break;
4036                 case QUIRK_R3D:
4037                         chipio_set_control_param(codec, 0x0D, 0x21);
4038                         ca0132_mmio_gpio_set(codec, 0x1, false);
4039                         break;
4040                 }
4041
4042                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4043                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4044
4045                 /* disable speaker*/
4046                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4047                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4048                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4049                                 pin_ctl & ~PIN_HP);
4050
4051                 /* enable headphone, either front or rear */
4052
4053                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4054                         headphone_nid = spec->out_pins[2];
4055                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4056                         headphone_nid = spec->out_pins[1];
4057
4058                 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4059                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4060                 snd_hda_set_pin_ctl(codec, headphone_nid,
4061                                     pin_ctl | PIN_HP);
4062
4063                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4064                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4065                 else
4066                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4067                 break;
4068         case SURROUND_OUT:
4069                 codec_dbg(codec, "%s surround\n", __func__);
4070                 /* Surround out config*/
4071                 switch (spec->quirk) {
4072                 case QUIRK_SBZ:
4073                         ca0132_mmio_gpio_set(codec, 7, false);
4074                         ca0132_mmio_gpio_set(codec, 4, true);
4075                         ca0132_mmio_gpio_set(codec, 1, true);
4076                         chipio_set_control_param(codec, 0x0D, 0x18);
4077                         break;
4078                 case QUIRK_R3DI:
4079                         chipio_set_control_param(codec, 0x0D, 0x24);
4080                         r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4081                         break;
4082                 case QUIRK_R3D:
4083                         ca0132_mmio_gpio_set(codec, 1, true);
4084                         chipio_set_control_param(codec, 0x0D, 0x24);
4085                         break;
4086                 }
4087                 /* enable line out node */
4088                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4089                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4090                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4091                                                 pin_ctl | PIN_OUT);
4092                 /* Disable headphone out */
4093                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4094                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4095                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4096                                     pin_ctl & ~PIN_HP);
4097                 /* Enable EAPD on line out */
4098                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4099                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4100                 /* enable center/lfe out node */
4101                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4102                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4103                 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4104                                     pin_ctl | PIN_OUT);
4105                 /* Now set rear surround node as out. */
4106                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4107                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4108                 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4109                                     pin_ctl | PIN_OUT);
4110
4111                 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4112                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4113                 else
4114                         dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4115                 break;
4116         }
4117
4118         /* run through the output dsp commands for line-out */
4119         for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4120                 err = dspio_set_uint_param(codec,
4121                 alt_out_presets[spec->cur_out_type].mids[i],
4122                 alt_out_presets[spec->cur_out_type].reqs[i],
4123                 alt_out_presets[spec->cur_out_type].vals[i]);
4124
4125                 if (err < 0)
4126                         goto exit;
4127         }
4128
4129 exit:
4130         snd_hda_power_down_pm(codec);
4131
4132         return err < 0 ? err : 0;
4133 }
4134
4135 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4136 {
4137         struct ca0132_spec *spec = container_of(
4138                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4139         struct hda_jack_tbl *jack;
4140
4141         if (spec->use_alt_functions)
4142                 ca0132_alt_select_out(spec->codec);
4143         else
4144                 ca0132_select_out(spec->codec);
4145
4146         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4147         if (jack) {
4148                 jack->block_report = 0;
4149                 snd_hda_jack_report_sync(spec->codec);
4150         }
4151 }
4152
4153 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4154 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4155 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4156 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4157 static int stop_mic1(struct hda_codec *codec);
4158 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4159 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4160
4161 /*
4162  * Select the active VIP source
4163  */
4164 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4165 {
4166         struct ca0132_spec *spec = codec->spec;
4167         unsigned int tmp;
4168
4169         if (spec->dsp_state != DSP_DOWNLOADED)
4170                 return 0;
4171
4172         /* if CrystalVoice if off, vipsource should be 0 */
4173         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4174             (val == 0)) {
4175                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4176                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4177                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4178                 if (spec->cur_mic_type == DIGITAL_MIC)
4179                         tmp = FLOAT_TWO;
4180                 else
4181                         tmp = FLOAT_ONE;
4182                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4183                 tmp = FLOAT_ZERO;
4184                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4185         } else {
4186                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4187                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4188                 if (spec->cur_mic_type == DIGITAL_MIC)
4189                         tmp = FLOAT_TWO;
4190                 else
4191                         tmp = FLOAT_ONE;
4192                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4193                 tmp = FLOAT_ONE;
4194                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4195                 msleep(20);
4196                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4197         }
4198
4199         return 1;
4200 }
4201
4202 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4203 {
4204         struct ca0132_spec *spec = codec->spec;
4205         unsigned int tmp;
4206
4207         if (spec->dsp_state != DSP_DOWNLOADED)
4208                 return 0;
4209
4210         codec_dbg(codec, "%s\n", __func__);
4211
4212         chipio_set_stream_control(codec, 0x03, 0);
4213         chipio_set_stream_control(codec, 0x04, 0);
4214
4215         /* if CrystalVoice is off, vipsource should be 0 */
4216         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4217             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4218                 codec_dbg(codec, "%s: off.", __func__);
4219                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4220
4221                 tmp = FLOAT_ZERO;
4222                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4223
4224                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4225                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4226                 if (spec->quirk == QUIRK_R3DI)
4227                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4228
4229
4230                 if (spec->in_enum_val == REAR_LINE_IN)
4231                         tmp = FLOAT_ZERO;
4232                 else {
4233                         if (spec->quirk == QUIRK_SBZ)
4234                                 tmp = FLOAT_THREE;
4235                         else
4236                                 tmp = FLOAT_ONE;
4237                 }
4238
4239                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4240
4241         } else {
4242                 codec_dbg(codec, "%s: on.", __func__);
4243                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4244                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4245                 if (spec->quirk == QUIRK_R3DI)
4246                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4247
4248                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4249                         tmp = FLOAT_TWO;
4250                 else
4251                         tmp = FLOAT_ONE;
4252                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4253
4254                 tmp = FLOAT_ONE;
4255                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4256
4257                 msleep(20);
4258                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4259         }
4260
4261         chipio_set_stream_control(codec, 0x03, 1);
4262         chipio_set_stream_control(codec, 0x04, 1);
4263
4264         return 1;
4265 }
4266
4267 /*
4268  * Select the active microphone.
4269  * If autodetect is enabled, mic will be selected based on jack detection.
4270  * If jack inserted, ext.mic will be selected, else built-in mic
4271  * If autodetect is disabled, mic will be selected based on selection.
4272  */
4273 static int ca0132_select_mic(struct hda_codec *codec)
4274 {
4275         struct ca0132_spec *spec = codec->spec;
4276         int jack_present;
4277         int auto_jack;
4278
4279         codec_dbg(codec, "ca0132_select_mic\n");
4280
4281         snd_hda_power_up_pm(codec);
4282
4283         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4284
4285         if (auto_jack)
4286                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4287         else
4288                 jack_present =
4289                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4290
4291         if (jack_present)
4292                 spec->cur_mic_type = LINE_MIC_IN;
4293         else
4294                 spec->cur_mic_type = DIGITAL_MIC;
4295
4296         if (spec->cur_mic_type == DIGITAL_MIC) {
4297                 /* enable digital Mic */
4298                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4299                 ca0132_set_dmic(codec, 1);
4300                 ca0132_mic_boost_set(codec, 0);
4301                 /* set voice focus */
4302                 ca0132_effects_set(codec, VOICE_FOCUS,
4303                                    spec->effects_switch
4304                                    [VOICE_FOCUS - EFFECT_START_NID]);
4305         } else {
4306                 /* disable digital Mic */
4307                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4308                 ca0132_set_dmic(codec, 0);
4309                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4310                 /* disable voice focus */
4311                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4312         }
4313
4314         snd_hda_power_down_pm(codec);
4315
4316         return 0;
4317 }
4318
4319 /*
4320  * Select the active input.
4321  * Mic detection isn't used, because it's kind of pointless on the SBZ.
4322  * The front mic has no jack-detection, so the only way to switch to it
4323  * is to do it manually in alsamixer.
4324  */
4325 static int ca0132_alt_select_in(struct hda_codec *codec)
4326 {
4327         struct ca0132_spec *spec = codec->spec;
4328         unsigned int tmp;
4329
4330         codec_dbg(codec, "%s\n", __func__);
4331
4332         snd_hda_power_up_pm(codec);
4333
4334         chipio_set_stream_control(codec, 0x03, 0);
4335         chipio_set_stream_control(codec, 0x04, 0);
4336
4337         spec->cur_mic_type = spec->in_enum_val;
4338
4339         switch (spec->cur_mic_type) {
4340         case REAR_MIC:
4341                 switch (spec->quirk) {
4342                 case QUIRK_SBZ:
4343                 case QUIRK_R3D:
4344                         ca0132_mmio_gpio_set(codec, 0, false);
4345                         tmp = FLOAT_THREE;
4346                         break;
4347                 case QUIRK_R3DI:
4348                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4349                         tmp = FLOAT_ONE;
4350                         break;
4351                 default:
4352                         tmp = FLOAT_ONE;
4353                         break;
4354                 }
4355
4356                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4357                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4358                 if (spec->quirk == QUIRK_R3DI)
4359                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4360
4361                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4362
4363                 chipio_set_stream_control(codec, 0x03, 1);
4364                 chipio_set_stream_control(codec, 0x04, 1);
4365
4366                 if (spec->quirk == QUIRK_SBZ) {
4367                         chipio_write(codec, 0x18B098, 0x0000000C);
4368                         chipio_write(codec, 0x18B09C, 0x0000000C);
4369                 }
4370                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4371                 break;
4372         case REAR_LINE_IN:
4373                 ca0132_mic_boost_set(codec, 0);
4374                 switch (spec->quirk) {
4375                 case QUIRK_SBZ:
4376                 case QUIRK_R3D:
4377                         ca0132_mmio_gpio_set(codec, 0, false);
4378                         break;
4379                 case QUIRK_R3DI:
4380                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4381                         break;
4382                 }
4383
4384                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4385                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4386                 if (spec->quirk == QUIRK_R3DI)
4387                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4388
4389                 tmp = FLOAT_ZERO;
4390                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4391
4392                 if (spec->quirk == QUIRK_SBZ) {
4393                         chipio_write(codec, 0x18B098, 0x00000000);
4394                         chipio_write(codec, 0x18B09C, 0x00000000);
4395                 }
4396
4397                 chipio_set_stream_control(codec, 0x03, 1);
4398                 chipio_set_stream_control(codec, 0x04, 1);
4399                 break;
4400         case FRONT_MIC:
4401                 switch (spec->quirk) {
4402                 case QUIRK_SBZ:
4403                 case QUIRK_R3D:
4404                         ca0132_mmio_gpio_set(codec, 0, true);
4405                         ca0132_mmio_gpio_set(codec, 5, false);
4406                         tmp = FLOAT_THREE;
4407                         break;
4408                 case QUIRK_R3DI:
4409                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4410                         tmp = FLOAT_ONE;
4411                         break;
4412                 default:
4413                         tmp = FLOAT_ONE;
4414                         break;
4415                 }
4416
4417                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4418                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4419                 if (spec->quirk == QUIRK_R3DI)
4420                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4421
4422                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4423
4424                 chipio_set_stream_control(codec, 0x03, 1);
4425                 chipio_set_stream_control(codec, 0x04, 1);
4426
4427                 if (spec->quirk == QUIRK_SBZ) {
4428                         chipio_write(codec, 0x18B098, 0x0000000C);
4429                         chipio_write(codec, 0x18B09C, 0x000000CC);
4430                 }
4431                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4432                 break;
4433         }
4434         ca0132_cvoice_switch_set(codec);
4435
4436         snd_hda_power_down_pm(codec);
4437         return 0;
4438
4439 }
4440
4441 /*
4442  * Check if VNODE settings take effect immediately.
4443  */
4444 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4445                                      hda_nid_t vnid,
4446                                      hda_nid_t *shared_nid)
4447 {
4448         struct ca0132_spec *spec = codec->spec;
4449         hda_nid_t nid;
4450
4451         switch (vnid) {
4452         case VNID_SPK:
4453                 nid = spec->shared_out_nid;
4454                 break;
4455         case VNID_MIC:
4456                 nid = spec->shared_mic_nid;
4457                 break;
4458         default:
4459                 return false;
4460         }
4461
4462         if (shared_nid)
4463                 *shared_nid = nid;
4464
4465         return true;
4466 }
4467
4468 /*
4469 * The following functions are control change helpers.
4470 * They return 0 if no changed.  Return 1 if changed.
4471 */
4472 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4473 {
4474         struct ca0132_spec *spec = codec->spec;
4475         unsigned int tmp;
4476
4477         /* based on CrystalVoice state to enable VoiceFX. */
4478         if (enable) {
4479                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4480                         FLOAT_ONE : FLOAT_ZERO;
4481         } else {
4482                 tmp = FLOAT_ZERO;
4483         }
4484
4485         dspio_set_uint_param(codec, ca0132_voicefx.mid,
4486                              ca0132_voicefx.reqs[0], tmp);
4487
4488         return 1;
4489 }
4490
4491 /*
4492  * Set the effects parameters
4493  */
4494 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4495 {
4496         struct ca0132_spec *spec = codec->spec;
4497         unsigned int on, tmp;
4498         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4499         int err = 0;
4500         int idx = nid - EFFECT_START_NID;
4501
4502         if ((idx < 0) || (idx >= num_fx))
4503                 return 0; /* no changed */
4504
4505         /* for out effect, qualify with PE */
4506         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4507                 /* if PE if off, turn off out effects. */
4508                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4509                         val = 0;
4510         }
4511
4512         /* for in effect, qualify with CrystalVoice */
4513         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4514                 /* if CrystalVoice if off, turn off in effects. */
4515                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4516                         val = 0;
4517
4518                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4519                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4520                         val = 0;
4521
4522                 /* If Voice Focus on SBZ, set to two channel. */
4523                 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4524                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4525                         if (spec->effects_switch[CRYSTAL_VOICE -
4526                                                  EFFECT_START_NID]) {
4527
4528                                 if (spec->effects_switch[VOICE_FOCUS -
4529                                                          EFFECT_START_NID]) {
4530                                         tmp = FLOAT_TWO;
4531                                         val = 1;
4532                                 } else
4533                                         tmp = FLOAT_ONE;
4534
4535                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4536                         }
4537                 }
4538                 /*
4539                  * For SBZ noise reduction, there's an extra command
4540                  * to module ID 0x47. No clue why.
4541                  */
4542                 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4543                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
4544                         if (spec->effects_switch[CRYSTAL_VOICE -
4545                                                  EFFECT_START_NID]) {
4546                                 if (spec->effects_switch[NOISE_REDUCTION -
4547                                                          EFFECT_START_NID])
4548                                         tmp = FLOAT_ONE;
4549                                 else
4550                                         tmp = FLOAT_ZERO;
4551                         } else
4552                                 tmp = FLOAT_ZERO;
4553
4554                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4555                 }
4556
4557                 /* If rear line in disable effects. */
4558                 if (spec->use_alt_functions &&
4559                                 spec->in_enum_val == REAR_LINE_IN)
4560                         val = 0;
4561         }
4562
4563         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4564                     nid, val);
4565
4566         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4567         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4568                                    ca0132_effects[idx].reqs[0], on);
4569
4570         if (err < 0)
4571                 return 0; /* no changed */
4572
4573         return 1;
4574 }
4575
4576 /*
4577  * Turn on/off Playback Enhancements
4578  */
4579 static int ca0132_pe_switch_set(struct hda_codec *codec)
4580 {
4581         struct ca0132_spec *spec = codec->spec;
4582         hda_nid_t nid;
4583         int i, ret = 0;
4584
4585         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4586                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4587
4588         if (spec->use_alt_functions)
4589                 ca0132_alt_select_out(codec);
4590
4591         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4592         nid = OUT_EFFECT_START_NID;
4593         /* PE affects all out effects */
4594         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4595                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4596
4597         return ret;
4598 }
4599
4600 /* Check if Mic1 is streaming, if so, stop streaming */
4601 static int stop_mic1(struct hda_codec *codec)
4602 {
4603         struct ca0132_spec *spec = codec->spec;
4604         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4605                                                  AC_VERB_GET_CONV, 0);
4606         if (oldval != 0)
4607                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4608                                     AC_VERB_SET_CHANNEL_STREAMID,
4609                                     0);
4610         return oldval;
4611 }
4612
4613 /* Resume Mic1 streaming if it was stopped. */
4614 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4615 {
4616         struct ca0132_spec *spec = codec->spec;
4617         /* Restore the previous stream and channel */
4618         if (oldval != 0)
4619                 snd_hda_codec_write(codec, spec->adcs[0], 0,
4620                                     AC_VERB_SET_CHANNEL_STREAMID,
4621                                     oldval);
4622 }
4623
4624 /*
4625  * Turn on/off CrystalVoice
4626  */
4627 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4628 {
4629         struct ca0132_spec *spec = codec->spec;
4630         hda_nid_t nid;
4631         int i, ret = 0;
4632         unsigned int oldval;
4633
4634         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4635                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4636
4637         i = IN_EFFECT_START_NID - EFFECT_START_NID;
4638         nid = IN_EFFECT_START_NID;
4639         /* CrystalVoice affects all in effects */
4640         for (; nid < IN_EFFECT_END_NID; nid++, i++)
4641                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4642
4643         /* including VoiceFX */
4644         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4645
4646         /* set correct vipsource */
4647         oldval = stop_mic1(codec);
4648         if (spec->use_alt_functions)
4649                 ret |= ca0132_alt_set_vipsource(codec, 1);
4650         else
4651                 ret |= ca0132_set_vipsource(codec, 1);
4652         resume_mic1(codec, oldval);
4653         return ret;
4654 }
4655
4656 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4657 {
4658         struct ca0132_spec *spec = codec->spec;
4659         int ret = 0;
4660
4661         if (val) /* on */
4662                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4663                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4664         else /* off */
4665                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4666                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4667
4668         return ret;
4669 }
4670
4671 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4672 {
4673         struct ca0132_spec *spec = codec->spec;
4674         int ret = 0;
4675
4676         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4677                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4678         return ret;
4679 }
4680
4681 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4682                                 struct snd_ctl_elem_value *ucontrol)
4683 {
4684         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4685         hda_nid_t nid = get_amp_nid(kcontrol);
4686         hda_nid_t shared_nid = 0;
4687         bool effective;
4688         int ret = 0;
4689         struct ca0132_spec *spec = codec->spec;
4690         int auto_jack;
4691
4692         if (nid == VNID_HP_SEL) {
4693                 auto_jack =
4694                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4695                 if (!auto_jack) {
4696                         if (spec->use_alt_functions)
4697                                 ca0132_alt_select_out(codec);
4698                         else
4699                                 ca0132_select_out(codec);
4700                 }
4701                 return 1;
4702         }
4703
4704         if (nid == VNID_AMIC1_SEL) {
4705                 auto_jack =
4706                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4707                 if (!auto_jack)
4708                         ca0132_select_mic(codec);
4709                 return 1;
4710         }
4711
4712         if (nid == VNID_HP_ASEL) {
4713                 if (spec->use_alt_functions)
4714                         ca0132_alt_select_out(codec);
4715                 else
4716                         ca0132_select_out(codec);
4717                 return 1;
4718         }
4719
4720         if (nid == VNID_AMIC1_ASEL) {
4721                 ca0132_select_mic(codec);
4722                 return 1;
4723         }
4724
4725         /* if effective conditions, then update hw immediately. */
4726         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4727         if (effective) {
4728                 int dir = get_amp_direction(kcontrol);
4729                 int ch = get_amp_channels(kcontrol);
4730                 unsigned long pval;
4731
4732                 mutex_lock(&codec->control_mutex);
4733                 pval = kcontrol->private_value;
4734                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4735                                                                 0, dir);
4736                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4737                 kcontrol->private_value = pval;
4738                 mutex_unlock(&codec->control_mutex);
4739         }
4740
4741         return ret;
4742 }
4743 /* End of control change helpers. */
4744 /*
4745  * Below I've added controls to mess with the effect levels, I've only enabled
4746  * them on the Sound Blaster Z, but they would probably also work on the
4747  * Chromebook. I figured they were probably tuned specifically for it, and left
4748  * out for a reason.
4749  */
4750
4751 /* Sets DSP effect level from the sliders above the controls */
4752 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4753                           const unsigned int *lookup, int idx)
4754 {
4755         int i = 0;
4756         unsigned int y;
4757         /*
4758          * For X_BASS, req 2 is actually crossover freq instead of
4759          * effect level
4760          */
4761         if (nid == X_BASS)
4762                 y = 2;
4763         else
4764                 y = 1;
4765
4766         snd_hda_power_up(codec);
4767         if (nid == XBASS_XOVER) {
4768                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4769                         if (ca0132_effects[i].nid == X_BASS)
4770                                 break;
4771
4772                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4773                                 ca0132_effects[i].reqs[1],
4774                                 &(lookup[idx - 1]), sizeof(unsigned int));
4775         } else {
4776                 /* Find the actual effect structure */
4777                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4778                         if (nid == ca0132_effects[i].nid)
4779                                 break;
4780
4781                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4782                                 ca0132_effects[i].reqs[y],
4783                                 &(lookup[idx]), sizeof(unsigned int));
4784         }
4785
4786         snd_hda_power_down(codec);
4787
4788         return 0;
4789 }
4790
4791 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4792                           struct snd_ctl_elem_value *ucontrol)
4793 {
4794         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4795         struct ca0132_spec *spec = codec->spec;
4796         long *valp = ucontrol->value.integer.value;
4797
4798         *valp = spec->xbass_xover_freq;
4799         return 0;
4800 }
4801
4802 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4803                           struct snd_ctl_elem_value *ucontrol)
4804 {
4805         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4806         struct ca0132_spec *spec = codec->spec;
4807         hda_nid_t nid = get_amp_nid(kcontrol);
4808         long *valp = ucontrol->value.integer.value;
4809         int idx = nid - OUT_EFFECT_START_NID;
4810
4811         *valp = spec->fx_ctl_val[idx];
4812         return 0;
4813 }
4814
4815 /*
4816  * The X-bass crossover starts at 10hz, so the min is 1. The
4817  * frequency is set in multiples of 10.
4818  */
4819 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4820                 struct snd_ctl_elem_info *uinfo)
4821 {
4822         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4823         uinfo->count = 1;
4824         uinfo->value.integer.min = 1;
4825         uinfo->value.integer.max = 100;
4826         uinfo->value.integer.step = 1;
4827
4828         return 0;
4829 }
4830
4831 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4832                 struct snd_ctl_elem_info *uinfo)
4833 {
4834         int chs = get_amp_channels(kcontrol);
4835
4836         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4837         uinfo->count = chs == 3 ? 2 : 1;
4838         uinfo->value.integer.min = 0;
4839         uinfo->value.integer.max = 100;
4840         uinfo->value.integer.step = 1;
4841
4842         return 0;
4843 }
4844
4845 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4846                                 struct snd_ctl_elem_value *ucontrol)
4847 {
4848         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4849         struct ca0132_spec *spec = codec->spec;
4850         hda_nid_t nid = get_amp_nid(kcontrol);
4851         long *valp = ucontrol->value.integer.value;
4852         int idx;
4853
4854         /* any change? */
4855         if (spec->xbass_xover_freq == *valp)
4856                 return 0;
4857
4858         spec->xbass_xover_freq = *valp;
4859
4860         idx = *valp;
4861         ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4862
4863         return 0;
4864 }
4865
4866 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4867                                 struct snd_ctl_elem_value *ucontrol)
4868 {
4869         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4870         struct ca0132_spec *spec = codec->spec;
4871         hda_nid_t nid = get_amp_nid(kcontrol);
4872         long *valp = ucontrol->value.integer.value;
4873         int idx;
4874
4875         idx = nid - EFFECT_START_NID;
4876         /* any change? */
4877         if (spec->fx_ctl_val[idx] == *valp)
4878                 return 0;
4879
4880         spec->fx_ctl_val[idx] = *valp;
4881
4882         idx = *valp;
4883         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4884
4885         return 0;
4886 }
4887
4888
4889 /*
4890  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4891  * only has off or full 30 dB, and didn't like making a volume slider that has
4892  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4893  */
4894 #define MIC_BOOST_NUM_OF_STEPS 4
4895 #define MIC_BOOST_ENUM_MAX_STRLEN 10
4896
4897 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4898                                  struct snd_ctl_elem_info *uinfo)
4899 {
4900         char *sfx = "dB";
4901         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4902
4903         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4904         uinfo->count = 1;
4905         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4906         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4907                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4908         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4909         strcpy(uinfo->value.enumerated.name, namestr);
4910         return 0;
4911 }
4912
4913 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4914                                 struct snd_ctl_elem_value *ucontrol)
4915 {
4916         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4917         struct ca0132_spec *spec = codec->spec;
4918
4919         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4920         return 0;
4921 }
4922
4923 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4924                                 struct snd_ctl_elem_value *ucontrol)
4925 {
4926         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4927         struct ca0132_spec *spec = codec->spec;
4928         int sel = ucontrol->value.enumerated.item[0];
4929         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4930
4931         if (sel >= items)
4932                 return 0;
4933
4934         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4935                     sel);
4936
4937         spec->mic_boost_enum_val = sel;
4938
4939         if (spec->in_enum_val != REAR_LINE_IN)
4940                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4941
4942         return 1;
4943 }
4944
4945
4946 /*
4947  * Input Select Control for alternative ca0132 codecs. This exists because
4948  * front microphone has no auto-detect, and we need a way to set the rear
4949  * as line-in
4950  */
4951 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4952                                  struct snd_ctl_elem_info *uinfo)
4953 {
4954         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4955         uinfo->count = 1;
4956         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4957         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4958                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4959         strcpy(uinfo->value.enumerated.name,
4960                         in_src_str[uinfo->value.enumerated.item]);
4961         return 0;
4962 }
4963
4964 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4965                                 struct snd_ctl_elem_value *ucontrol)
4966 {
4967         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4968         struct ca0132_spec *spec = codec->spec;
4969
4970         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4971         return 0;
4972 }
4973
4974 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4975                                 struct snd_ctl_elem_value *ucontrol)
4976 {
4977         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4978         struct ca0132_spec *spec = codec->spec;
4979         int sel = ucontrol->value.enumerated.item[0];
4980         unsigned int items = IN_SRC_NUM_OF_INPUTS;
4981
4982         if (sel >= items)
4983                 return 0;
4984
4985         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4986                     sel, in_src_str[sel]);
4987
4988         spec->in_enum_val = sel;
4989
4990         ca0132_alt_select_in(codec);
4991
4992         return 1;
4993 }
4994
4995 /* Sound Blaster Z Output Select Control */
4996 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4997                                  struct snd_ctl_elem_info *uinfo)
4998 {
4999         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5000         uinfo->count = 1;
5001         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5002         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5003                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5004         strcpy(uinfo->value.enumerated.name,
5005                         alt_out_presets[uinfo->value.enumerated.item].name);
5006         return 0;
5007 }
5008
5009 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5010                                 struct snd_ctl_elem_value *ucontrol)
5011 {
5012         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5013         struct ca0132_spec *spec = codec->spec;
5014
5015         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5016         return 0;
5017 }
5018
5019 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5020                                 struct snd_ctl_elem_value *ucontrol)
5021 {
5022         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5023         struct ca0132_spec *spec = codec->spec;
5024         int sel = ucontrol->value.enumerated.item[0];
5025         unsigned int items = NUM_OF_OUTPUTS;
5026         unsigned int auto_jack;
5027
5028         if (sel >= items)
5029                 return 0;
5030
5031         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5032                     sel, alt_out_presets[sel].name);
5033
5034         spec->out_enum_val = sel;
5035
5036         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5037
5038         if (!auto_jack)
5039                 ca0132_alt_select_out(codec);
5040
5041         return 1;
5042 }
5043
5044 /*
5045  * Smart Volume output setting control. Three different settings, Normal,
5046  * which takes the value from the smart volume slider. The two others, loud
5047  * and night, disregard the slider value and have uneditable values.
5048  */
5049 #define NUM_OF_SVM_SETTINGS 3
5050 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5051
5052 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5053                                  struct snd_ctl_elem_info *uinfo)
5054 {
5055         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5056         uinfo->count = 1;
5057         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5058         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5059                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5060         strcpy(uinfo->value.enumerated.name,
5061                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
5062         return 0;
5063 }
5064
5065 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5066                                 struct snd_ctl_elem_value *ucontrol)
5067 {
5068         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5069         struct ca0132_spec *spec = codec->spec;
5070
5071         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5072         return 0;
5073 }
5074
5075 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5076                                 struct snd_ctl_elem_value *ucontrol)
5077 {
5078         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5079         struct ca0132_spec *spec = codec->spec;
5080         int sel = ucontrol->value.enumerated.item[0];
5081         unsigned int items = NUM_OF_SVM_SETTINGS;
5082         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5083         unsigned int tmp;
5084
5085         if (sel >= items)
5086                 return 0;
5087
5088         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5089                     sel, out_svm_set_enum_str[sel]);
5090
5091         spec->smart_volume_setting = sel;
5092
5093         switch (sel) {
5094         case 0:
5095                 tmp = FLOAT_ZERO;
5096                 break;
5097         case 1:
5098                 tmp = FLOAT_ONE;
5099                 break;
5100         case 2:
5101                 tmp = FLOAT_TWO;
5102                 break;
5103         default:
5104                 tmp = FLOAT_ZERO;
5105                 break;
5106         }
5107         /* Req 2 is the Smart Volume Setting req. */
5108         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5109                         ca0132_effects[idx].reqs[2], tmp);
5110         return 1;
5111 }
5112
5113 /* Sound Blaster Z EQ preset controls */
5114 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5115                                  struct snd_ctl_elem_info *uinfo)
5116 {
5117         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5118
5119         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5120         uinfo->count = 1;
5121         uinfo->value.enumerated.items = items;
5122         if (uinfo->value.enumerated.item >= items)
5123                 uinfo->value.enumerated.item = items - 1;
5124         strcpy(uinfo->value.enumerated.name,
5125                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5126         return 0;
5127 }
5128
5129 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5130                                 struct snd_ctl_elem_value *ucontrol)
5131 {
5132         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5133         struct ca0132_spec *spec = codec->spec;
5134
5135         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5136         return 0;
5137 }
5138
5139 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5140                                 struct snd_ctl_elem_value *ucontrol)
5141 {
5142         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5143         struct ca0132_spec *spec = codec->spec;
5144         int i, err = 0;
5145         int sel = ucontrol->value.enumerated.item[0];
5146         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5147
5148         if (sel >= items)
5149                 return 0;
5150
5151         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5152                         ca0132_alt_eq_presets[sel].name);
5153         /*
5154          * Idx 0 is default.
5155          * Default needs to qualify with CrystalVoice state.
5156          */
5157         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5158                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5159                                 ca0132_alt_eq_enum.reqs[i],
5160                                 ca0132_alt_eq_presets[sel].vals[i]);
5161                 if (err < 0)
5162                         break;
5163         }
5164
5165         if (err >= 0)
5166                 spec->eq_preset_val = sel;
5167
5168         return 1;
5169 }
5170
5171 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5172                                  struct snd_ctl_elem_info *uinfo)
5173 {
5174         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5175
5176         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5177         uinfo->count = 1;
5178         uinfo->value.enumerated.items = items;
5179         if (uinfo->value.enumerated.item >= items)
5180                 uinfo->value.enumerated.item = items - 1;
5181         strcpy(uinfo->value.enumerated.name,
5182                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5183         return 0;
5184 }
5185
5186 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5187                                 struct snd_ctl_elem_value *ucontrol)
5188 {
5189         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5190         struct ca0132_spec *spec = codec->spec;
5191
5192         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5193         return 0;
5194 }
5195
5196 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5197                                 struct snd_ctl_elem_value *ucontrol)
5198 {
5199         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5200         struct ca0132_spec *spec = codec->spec;
5201         int i, err = 0;
5202         int sel = ucontrol->value.enumerated.item[0];
5203
5204         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5205                 return 0;
5206
5207         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5208                     sel, ca0132_voicefx_presets[sel].name);
5209
5210         /*
5211          * Idx 0 is default.
5212          * Default needs to qualify with CrystalVoice state.
5213          */
5214         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5215                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5216                                 ca0132_voicefx.reqs[i],
5217                                 ca0132_voicefx_presets[sel].vals[i]);
5218                 if (err < 0)
5219                         break;
5220         }
5221
5222         if (err >= 0) {
5223                 spec->voicefx_val = sel;
5224                 /* enable voice fx */
5225                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5226         }
5227
5228         return 1;
5229 }
5230
5231 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5232                                 struct snd_ctl_elem_value *ucontrol)
5233 {
5234         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5235         struct ca0132_spec *spec = codec->spec;
5236         hda_nid_t nid = get_amp_nid(kcontrol);
5237         int ch = get_amp_channels(kcontrol);
5238         long *valp = ucontrol->value.integer.value;
5239
5240         /* vnode */
5241         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5242                 if (ch & 1) {
5243                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5244                         valp++;
5245                 }
5246                 if (ch & 2) {
5247                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5248                         valp++;
5249                 }
5250                 return 0;
5251         }
5252
5253         /* effects, include PE and CrystalVoice */
5254         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5255                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5256                 return 0;
5257         }
5258
5259         /* mic boost */
5260         if (nid == spec->input_pins[0]) {
5261                 *valp = spec->cur_mic_boost;
5262                 return 0;
5263         }
5264
5265         return 0;
5266 }
5267
5268 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5269                              struct snd_ctl_elem_value *ucontrol)
5270 {
5271         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5272         struct ca0132_spec *spec = codec->spec;
5273         hda_nid_t nid = get_amp_nid(kcontrol);
5274         int ch = get_amp_channels(kcontrol);
5275         long *valp = ucontrol->value.integer.value;
5276         int changed = 1;
5277
5278         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5279                     nid, *valp);
5280
5281         snd_hda_power_up(codec);
5282         /* vnode */
5283         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5284                 if (ch & 1) {
5285                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5286                         valp++;
5287                 }
5288                 if (ch & 2) {
5289                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5290                         valp++;
5291                 }
5292                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5293                 goto exit;
5294         }
5295
5296         /* PE */
5297         if (nid == PLAY_ENHANCEMENT) {
5298                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5299                 changed = ca0132_pe_switch_set(codec);
5300                 goto exit;
5301         }
5302
5303         /* CrystalVoice */
5304         if (nid == CRYSTAL_VOICE) {
5305                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5306                 changed = ca0132_cvoice_switch_set(codec);
5307                 goto exit;
5308         }
5309
5310         /* out and in effects */
5311         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5312             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5313                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5314                 changed = ca0132_effects_set(codec, nid, *valp);
5315                 goto exit;
5316         }
5317
5318         /* mic boost */
5319         if (nid == spec->input_pins[0]) {
5320                 spec->cur_mic_boost = *valp;
5321                 if (spec->use_alt_functions) {
5322                         if (spec->in_enum_val != REAR_LINE_IN)
5323                                 changed = ca0132_mic_boost_set(codec, *valp);
5324                 } else {
5325                         /* Mic boost does not apply to Digital Mic */
5326                         if (spec->cur_mic_type != DIGITAL_MIC)
5327                                 changed = ca0132_mic_boost_set(codec, *valp);
5328                 }
5329
5330                 goto exit;
5331         }
5332
5333 exit:
5334         snd_hda_power_down(codec);
5335         return changed;
5336 }
5337
5338 /*
5339  * Volume related
5340  */
5341 /*
5342  * Sets the internal DSP decibel level to match the DAC for output, and the
5343  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5344  * all alternative codecs set DSP playback volume.
5345  */
5346 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5347 {
5348         struct ca0132_spec *spec = codec->spec;
5349         unsigned int dsp_dir;
5350         unsigned int lookup_val;
5351
5352         if (nid == VNID_SPK)
5353                 dsp_dir = DSP_VOL_OUT;
5354         else
5355                 dsp_dir = DSP_VOL_IN;
5356
5357         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5358
5359         dspio_set_uint_param(codec,
5360                 ca0132_alt_vol_ctls[dsp_dir].mid,
5361                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5362                 float_vol_db_lookup[lookup_val]);
5363
5364         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5365
5366         dspio_set_uint_param(codec,
5367                 ca0132_alt_vol_ctls[dsp_dir].mid,
5368                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5369                 float_vol_db_lookup[lookup_val]);
5370
5371         dspio_set_uint_param(codec,
5372                 ca0132_alt_vol_ctls[dsp_dir].mid,
5373                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5374 }
5375
5376 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5377                               struct snd_ctl_elem_info *uinfo)
5378 {
5379         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5380         struct ca0132_spec *spec = codec->spec;
5381         hda_nid_t nid = get_amp_nid(kcontrol);
5382         int ch = get_amp_channels(kcontrol);
5383         int dir = get_amp_direction(kcontrol);
5384         unsigned long pval;
5385         int err;
5386
5387         switch (nid) {
5388         case VNID_SPK:
5389                 /* follow shared_out info */
5390                 nid = spec->shared_out_nid;
5391                 mutex_lock(&codec->control_mutex);
5392                 pval = kcontrol->private_value;
5393                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5394                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5395                 kcontrol->private_value = pval;
5396                 mutex_unlock(&codec->control_mutex);
5397                 break;
5398         case VNID_MIC:
5399                 /* follow shared_mic info */
5400                 nid = spec->shared_mic_nid;
5401                 mutex_lock(&codec->control_mutex);
5402                 pval = kcontrol->private_value;
5403                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5404                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5405                 kcontrol->private_value = pval;
5406                 mutex_unlock(&codec->control_mutex);
5407                 break;
5408         default:
5409                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5410         }
5411         return err;
5412 }
5413
5414 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5415                                 struct snd_ctl_elem_value *ucontrol)
5416 {
5417         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5418         struct ca0132_spec *spec = codec->spec;
5419         hda_nid_t nid = get_amp_nid(kcontrol);
5420         int ch = get_amp_channels(kcontrol);
5421         long *valp = ucontrol->value.integer.value;
5422
5423         /* store the left and right volume */
5424         if (ch & 1) {
5425                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5426                 valp++;
5427         }
5428         if (ch & 2) {
5429                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5430                 valp++;
5431         }
5432         return 0;
5433 }
5434
5435 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5436                                 struct snd_ctl_elem_value *ucontrol)
5437 {
5438         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5439         struct ca0132_spec *spec = codec->spec;
5440         hda_nid_t nid = get_amp_nid(kcontrol);
5441         int ch = get_amp_channels(kcontrol);
5442         long *valp = ucontrol->value.integer.value;
5443         hda_nid_t shared_nid = 0;
5444         bool effective;
5445         int changed = 1;
5446
5447         /* store the left and right volume */
5448         if (ch & 1) {
5449                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5450                 valp++;
5451         }
5452         if (ch & 2) {
5453                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5454                 valp++;
5455         }
5456
5457         /* if effective conditions, then update hw immediately. */
5458         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5459         if (effective) {
5460                 int dir = get_amp_direction(kcontrol);
5461                 unsigned long pval;
5462
5463                 snd_hda_power_up(codec);
5464                 mutex_lock(&codec->control_mutex);
5465                 pval = kcontrol->private_value;
5466                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5467                                                                 0, dir);
5468                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5469                 kcontrol->private_value = pval;
5470                 mutex_unlock(&codec->control_mutex);
5471                 snd_hda_power_down(codec);
5472         }
5473
5474         return changed;
5475 }
5476
5477 /*
5478  * This function is the same as the one above, because using an if statement
5479  * inside of the above volume control for the DSP volume would cause too much
5480  * lag. This is a lot more smooth.
5481  */
5482 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5483                                 struct snd_ctl_elem_value *ucontrol)
5484 {
5485         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5486         struct ca0132_spec *spec = codec->spec;
5487         hda_nid_t nid = get_amp_nid(kcontrol);
5488         int ch = get_amp_channels(kcontrol);
5489         long *valp = ucontrol->value.integer.value;
5490         hda_nid_t vnid = 0;
5491         int changed = 1;
5492
5493         switch (nid) {
5494         case 0x02:
5495                 vnid = VNID_SPK;
5496                 break;
5497         case 0x07:
5498                 vnid = VNID_MIC;
5499                 break;
5500         }
5501
5502         /* store the left and right volume */
5503         if (ch & 1) {
5504                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5505                 valp++;
5506         }
5507         if (ch & 2) {
5508                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5509                 valp++;
5510         }
5511
5512         snd_hda_power_up(codec);
5513         ca0132_alt_dsp_volume_put(codec, vnid);
5514         mutex_lock(&codec->control_mutex);
5515         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5516         mutex_unlock(&codec->control_mutex);
5517         snd_hda_power_down(codec);
5518
5519         return changed;
5520 }
5521
5522 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5523                              unsigned int size, unsigned int __user *tlv)
5524 {
5525         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5526         struct ca0132_spec *spec = codec->spec;
5527         hda_nid_t nid = get_amp_nid(kcontrol);
5528         int ch = get_amp_channels(kcontrol);
5529         int dir = get_amp_direction(kcontrol);
5530         unsigned long pval;
5531         int err;
5532
5533         switch (nid) {
5534         case VNID_SPK:
5535                 /* follow shared_out tlv */
5536                 nid = spec->shared_out_nid;
5537                 mutex_lock(&codec->control_mutex);
5538                 pval = kcontrol->private_value;
5539                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5540                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5541                 kcontrol->private_value = pval;
5542                 mutex_unlock(&codec->control_mutex);
5543                 break;
5544         case VNID_MIC:
5545                 /* follow shared_mic tlv */
5546                 nid = spec->shared_mic_nid;
5547                 mutex_lock(&codec->control_mutex);
5548                 pval = kcontrol->private_value;
5549                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5550                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5551                 kcontrol->private_value = pval;
5552                 mutex_unlock(&codec->control_mutex);
5553                 break;
5554         default:
5555                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5556         }
5557         return err;
5558 }
5559
5560 /* Add volume slider control for effect level */
5561 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5562                                         const char *pfx, int dir)
5563 {
5564         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5565         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5566         struct snd_kcontrol_new knew =
5567                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5568
5569         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5570
5571         knew.tlv.c = NULL;
5572
5573         switch (nid) {
5574         case XBASS_XOVER:
5575                 knew.info = ca0132_alt_xbass_xover_slider_info;
5576                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5577                 knew.put = ca0132_alt_xbass_xover_slider_put;
5578                 break;
5579         default:
5580                 knew.info = ca0132_alt_effect_slider_info;
5581                 knew.get = ca0132_alt_slider_ctl_get;
5582                 knew.put = ca0132_alt_effect_slider_put;
5583                 knew.private_value =
5584                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5585                 break;
5586         }
5587
5588         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5589 }
5590
5591 /*
5592  * Added FX: prefix for the alternative codecs, because otherwise the surround
5593  * effect would conflict with the Surround sound volume control. Also seems more
5594  * clear as to what the switches do. Left alone for others.
5595  */
5596 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5597                          const char *pfx, int dir)
5598 {
5599         struct ca0132_spec *spec = codec->spec;
5600         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5601         int type = dir ? HDA_INPUT : HDA_OUTPUT;
5602         struct snd_kcontrol_new knew =
5603                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5604         /* If using alt_controls, add FX: prefix. But, don't add FX:
5605          * prefix to OutFX or InFX enable controls.
5606          */
5607         if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5608                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5609         else
5610                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5611
5612         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5613 }
5614
5615 static int add_voicefx(struct hda_codec *codec)
5616 {
5617         struct snd_kcontrol_new knew =
5618                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5619                                     VOICEFX, 1, 0, HDA_INPUT);
5620         knew.info = ca0132_voicefx_info;
5621         knew.get = ca0132_voicefx_get;
5622         knew.put = ca0132_voicefx_put;
5623         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5624 }
5625
5626 /* Create the EQ Preset control */
5627 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5628 {
5629         struct snd_kcontrol_new knew =
5630                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5631                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5632         knew.info = ca0132_alt_eq_preset_info;
5633         knew.get = ca0132_alt_eq_preset_get;
5634         knew.put = ca0132_alt_eq_preset_put;
5635         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5636                                 snd_ctl_new1(&knew, codec));
5637 }
5638
5639 /*
5640  * Add enumerated control for the three different settings of the smart volume
5641  * output effect. Normal just uses the slider value, and loud and night are
5642  * their own things that ignore that value.
5643  */
5644 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5645 {
5646         struct snd_kcontrol_new knew =
5647                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5648                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5649         knew.info = ca0132_alt_svm_setting_info;
5650         knew.get = ca0132_alt_svm_setting_get;
5651         knew.put = ca0132_alt_svm_setting_put;
5652         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5653                                 snd_ctl_new1(&knew, codec));
5654
5655 }
5656
5657 /*
5658  * Create an Output Select enumerated control for codecs with surround
5659  * out capabilities.
5660  */
5661 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5662 {
5663         struct snd_kcontrol_new knew =
5664                 HDA_CODEC_MUTE_MONO("Output Select",
5665                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5666         knew.info = ca0132_alt_output_select_get_info;
5667         knew.get = ca0132_alt_output_select_get;
5668         knew.put = ca0132_alt_output_select_put;
5669         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5670                                 snd_ctl_new1(&knew, codec));
5671 }
5672
5673 /*
5674  * Create an Input Source enumerated control for the alternate ca0132 codecs
5675  * because the front microphone has no auto-detect, and Line-in has to be set
5676  * somehow.
5677  */
5678 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5679 {
5680         struct snd_kcontrol_new knew =
5681                 HDA_CODEC_MUTE_MONO("Input Source",
5682                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5683         knew.info = ca0132_alt_input_source_info;
5684         knew.get = ca0132_alt_input_source_get;
5685         knew.put = ca0132_alt_input_source_put;
5686         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5687                                 snd_ctl_new1(&knew, codec));
5688 }
5689
5690 /*
5691  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5692  * more control than the original mic boost, which is either full 30dB or off.
5693  */
5694 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5695 {
5696         struct snd_kcontrol_new knew =
5697                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5698                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5699         knew.info = ca0132_alt_mic_boost_info;
5700         knew.get = ca0132_alt_mic_boost_get;
5701         knew.put = ca0132_alt_mic_boost_put;
5702         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5703                                 snd_ctl_new1(&knew, codec));
5704
5705 }
5706
5707 /*
5708  * Need to create slave controls for the alternate codecs that have surround
5709  * capabilities.
5710  */
5711 static const char * const ca0132_alt_slave_pfxs[] = {
5712         "Front", "Surround", "Center", "LFE", NULL,
5713 };
5714
5715 /*
5716  * Also need special channel map, because the default one is incorrect.
5717  * I think this has to do with the pin for rear surround being 0x11,
5718  * and the center/lfe being 0x10. Usually the pin order is the opposite.
5719  */
5720 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5721         { .channels = 2,
5722           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5723         { .channels = 4,
5724           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5725                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5726         { .channels = 6,
5727           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5728                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5729                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5730         { }
5731 };
5732
5733 /* Add the correct chmap for streams with 6 channels. */
5734 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5735 {
5736         int err = 0;
5737         struct hda_pcm *pcm;
5738
5739         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5740                 struct hda_pcm_stream *hinfo =
5741                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5742                 struct snd_pcm_chmap *chmap;
5743                 const struct snd_pcm_chmap_elem *elem;
5744
5745                 elem = ca0132_alt_chmaps;
5746                 if (hinfo->channels_max == 6) {
5747                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
5748                                         SNDRV_PCM_STREAM_PLAYBACK,
5749                                         elem, hinfo->channels_max, 0, &chmap);
5750                         if (err < 0)
5751                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5752                 }
5753         }
5754 }
5755
5756 /*
5757  * When changing Node IDs for Mixer Controls below, make sure to update
5758  * Node IDs in ca0132_config() as well.
5759  */
5760 static const struct snd_kcontrol_new ca0132_mixer[] = {
5761         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5762         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5763         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5764         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5765         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5766         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5767         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5768         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5769         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5770                                0x12, 1, HDA_INPUT),
5771         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5772                                VNID_HP_SEL, 1, HDA_OUTPUT),
5773         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5774                                VNID_AMIC1_SEL, 1, HDA_INPUT),
5775         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5776                                VNID_HP_ASEL, 1, HDA_OUTPUT),
5777         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5778                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
5779         { } /* end */
5780 };
5781
5782 /*
5783  * Desktop specific control mixer. Removes auto-detect for mic, and adds
5784  * surround controls. Also sets both the Front Playback and Capture Volume
5785  * controls to alt so they set the DSP's decibel level.
5786  */
5787 static const struct snd_kcontrol_new desktop_mixer[] = {
5788         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5789         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5790         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5791         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5792         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5793         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5794         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5795         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5796         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5797         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5798         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5799         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5800         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5801                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5802         { } /* end */
5803 };
5804
5805 /*
5806  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5807  * because it doesn't set decibel levels for the DSP for capture.
5808  */
5809 static const struct snd_kcontrol_new r3di_mixer[] = {
5810         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5811         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5812         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5813         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5814         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5815         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5816         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5817         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5818         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5819         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5820         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5821         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5822         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5823                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
5824         { } /* end */
5825 };
5826
5827 static int ca0132_build_controls(struct hda_codec *codec)
5828 {
5829         struct ca0132_spec *spec = codec->spec;
5830         int i, num_fx, num_sliders;
5831         int err = 0;
5832
5833         /* Add Mixer controls */
5834         for (i = 0; i < spec->num_mixers; i++) {
5835                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5836                 if (err < 0)
5837                         return err;
5838         }
5839         /* Setup vmaster with surround slaves for desktop ca0132 devices */
5840         if (spec->use_alt_functions) {
5841                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5842                                         spec->tlv);
5843                 snd_hda_add_vmaster(codec, "Master Playback Volume",
5844                                         spec->tlv, ca0132_alt_slave_pfxs,
5845                                         "Playback Volume");
5846                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5847                                             NULL, ca0132_alt_slave_pfxs,
5848                                             "Playback Switch",
5849                                             true, &spec->vmaster_mute.sw_kctl);
5850
5851         }
5852
5853         /* Add in and out effects controls.
5854          * VoiceFX, PE and CrystalVoice are added separately.
5855          */
5856         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5857         for (i = 0; i < num_fx; i++) {
5858                 /* SBZ and R3D break if Echo Cancellation is used. */
5859                 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
5860                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5861                                                 OUT_EFFECTS_COUNT))
5862                                 continue;
5863                 }
5864
5865                 err = add_fx_switch(codec, ca0132_effects[i].nid,
5866                                     ca0132_effects[i].name,
5867                                     ca0132_effects[i].direct);
5868                 if (err < 0)
5869                         return err;
5870         }
5871         /*
5872          * If codec has use_alt_controls set to true, add effect level sliders,
5873          * EQ presets, and Smart Volume presets. Also, change names to add FX
5874          * prefix, and change PlayEnhancement and CrystalVoice to match.
5875          */
5876         if (spec->use_alt_controls) {
5877                 ca0132_alt_add_svm_enum(codec);
5878                 add_ca0132_alt_eq_presets(codec);
5879                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5880                                         "Enable OutFX", 0);
5881                 if (err < 0)
5882                         return err;
5883
5884                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5885                                         "Enable InFX", 1);
5886                 if (err < 0)
5887                         return err;
5888
5889                 num_sliders = OUT_EFFECTS_COUNT - 1;
5890                 for (i = 0; i < num_sliders; i++) {
5891                         err = ca0132_alt_add_effect_slider(codec,
5892                                             ca0132_effects[i].nid,
5893                                             ca0132_effects[i].name,
5894                                             ca0132_effects[i].direct);
5895                         if (err < 0)
5896                                 return err;
5897                 }
5898
5899                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5900                                         "X-Bass Crossover", EFX_DIR_OUT);
5901
5902                 if (err < 0)
5903                         return err;
5904         } else {
5905                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5906                                         "PlayEnhancement", 0);
5907                 if (err < 0)
5908                         return err;
5909
5910                 err = add_fx_switch(codec, CRYSTAL_VOICE,
5911                                         "CrystalVoice", 1);
5912                 if (err < 0)
5913                         return err;
5914         }
5915         add_voicefx(codec);
5916
5917         /*
5918          * If the codec uses alt_functions, you need the enumerated controls
5919          * to select the new outputs and inputs, plus add the new mic boost
5920          * setting control.
5921          */
5922         if (spec->use_alt_functions) {
5923                 ca0132_alt_add_output_enum(codec);
5924                 ca0132_alt_add_input_enum(codec);
5925                 ca0132_alt_add_mic_boost_enum(codec);
5926         }
5927 #ifdef ENABLE_TUNING_CONTROLS
5928         add_tuning_ctls(codec);
5929 #endif
5930
5931         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5932         if (err < 0)
5933                 return err;
5934
5935         if (spec->dig_out) {
5936                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5937                                                     spec->dig_out);
5938                 if (err < 0)
5939                         return err;
5940                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5941                 if (err < 0)
5942                         return err;
5943                 /* spec->multiout.share_spdif = 1; */
5944         }
5945
5946         if (spec->dig_in) {
5947                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5948                 if (err < 0)
5949                         return err;
5950         }
5951
5952         if (spec->use_alt_functions)
5953                 ca0132_alt_add_chmap_ctls(codec);
5954
5955         return 0;
5956 }
5957
5958 /*
5959  * PCM
5960  */
5961 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5962         .substreams = 1,
5963         .channels_min = 2,
5964         .channels_max = 6,
5965         .ops = {
5966                 .prepare = ca0132_playback_pcm_prepare,
5967                 .cleanup = ca0132_playback_pcm_cleanup,
5968                 .get_delay = ca0132_playback_pcm_delay,
5969         },
5970 };
5971
5972 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5973         .substreams = 1,
5974         .channels_min = 2,
5975         .channels_max = 2,
5976         .ops = {
5977                 .prepare = ca0132_capture_pcm_prepare,
5978                 .cleanup = ca0132_capture_pcm_cleanup,
5979                 .get_delay = ca0132_capture_pcm_delay,
5980         },
5981 };
5982
5983 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5984         .substreams = 1,
5985         .channels_min = 2,
5986         .channels_max = 2,
5987         .ops = {
5988                 .open = ca0132_dig_playback_pcm_open,
5989                 .close = ca0132_dig_playback_pcm_close,
5990                 .prepare = ca0132_dig_playback_pcm_prepare,
5991                 .cleanup = ca0132_dig_playback_pcm_cleanup
5992         },
5993 };
5994
5995 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
5996         .substreams = 1,
5997         .channels_min = 2,
5998         .channels_max = 2,
5999 };
6000
6001 static int ca0132_build_pcms(struct hda_codec *codec)
6002 {
6003         struct ca0132_spec *spec = codec->spec;
6004         struct hda_pcm *info;
6005
6006         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6007         if (!info)
6008                 return -ENOMEM;
6009         if (spec->use_alt_functions) {
6010                 info->own_chmap = true;
6011                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6012                         = ca0132_alt_chmaps;
6013         }
6014         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6015         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6016         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6017                 spec->multiout.max_channels;
6018         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6019         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6020         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6021
6022         /* With the DSP enabled, desktops don't use this ADC. */
6023         if (!spec->use_alt_functions) {
6024                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6025                 if (!info)
6026                         return -ENOMEM;
6027                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6028                         ca0132_pcm_analog_capture;
6029                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6030                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6031         }
6032
6033         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6034         if (!info)
6035                 return -ENOMEM;
6036         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6037         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6038         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6039
6040         if (!spec->dig_out && !spec->dig_in)
6041                 return 0;
6042
6043         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6044         if (!info)
6045                 return -ENOMEM;
6046         info->pcm_type = HDA_PCM_TYPE_SPDIF;
6047         if (spec->dig_out) {
6048                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6049                         ca0132_pcm_digital_playback;
6050                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6051         }
6052         if (spec->dig_in) {
6053                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6054                         ca0132_pcm_digital_capture;
6055                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6056         }
6057
6058         return 0;
6059 }
6060
6061 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6062 {
6063         if (pin) {
6064                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6065                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6066                         snd_hda_codec_write(codec, pin, 0,
6067                                             AC_VERB_SET_AMP_GAIN_MUTE,
6068                                             AMP_OUT_UNMUTE);
6069         }
6070         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6071                 snd_hda_codec_write(codec, dac, 0,
6072                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6073 }
6074
6075 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6076 {
6077         if (pin) {
6078                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6079                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6080                         snd_hda_codec_write(codec, pin, 0,
6081                                             AC_VERB_SET_AMP_GAIN_MUTE,
6082                                             AMP_IN_UNMUTE(0));
6083         }
6084         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6085                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6086                                     AMP_IN_UNMUTE(0));
6087
6088                 /* init to 0 dB and unmute. */
6089                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6090                                          HDA_AMP_VOLMASK, 0x5a);
6091                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6092                                          HDA_AMP_MUTE, 0);
6093         }
6094 }
6095
6096 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6097 {
6098         unsigned int caps;
6099
6100         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6101                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6102         snd_hda_override_amp_caps(codec, nid, dir, caps);
6103 }
6104
6105 /*
6106  * Switch between Digital built-in mic and analog mic.
6107  */
6108 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6109 {
6110         struct ca0132_spec *spec = codec->spec;
6111         unsigned int tmp;
6112         u8 val;
6113         unsigned int oldval;
6114
6115         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6116
6117         oldval = stop_mic1(codec);
6118         ca0132_set_vipsource(codec, 0);
6119         if (enable) {
6120                 /* set DMic input as 2-ch */
6121                 tmp = FLOAT_TWO;
6122                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6123
6124                 val = spec->dmic_ctl;
6125                 val |= 0x80;
6126                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6127                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6128
6129                 if (!(spec->dmic_ctl & 0x20))
6130                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6131         } else {
6132                 /* set AMic input as mono */
6133                 tmp = FLOAT_ONE;
6134                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6135
6136                 val = spec->dmic_ctl;
6137                 /* clear bit7 and bit5 to disable dmic */
6138                 val &= 0x5f;
6139                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6140                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
6141
6142                 if (!(spec->dmic_ctl & 0x20))
6143                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6144         }
6145         ca0132_set_vipsource(codec, 1);
6146         resume_mic1(codec, oldval);
6147 }
6148
6149 /*
6150  * Initialization for Digital Mic.
6151  */
6152 static void ca0132_init_dmic(struct hda_codec *codec)
6153 {
6154         struct ca0132_spec *spec = codec->spec;
6155         u8 val;
6156
6157         /* Setup Digital Mic here, but don't enable.
6158          * Enable based on jack detect.
6159          */
6160
6161         /* MCLK uses MPIO1, set to enable.
6162          * Bit 2-0: MPIO select
6163          * Bit   3: set to disable
6164          * Bit 7-4: reserved
6165          */
6166         val = 0x01;
6167         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6168                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6169
6170         /* Data1 uses MPIO3. Data2 not use
6171          * Bit 2-0: Data1 MPIO select
6172          * Bit   3: set disable Data1
6173          * Bit 6-4: Data2 MPIO select
6174          * Bit   7: set disable Data2
6175          */
6176         val = 0x83;
6177         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6178                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
6179
6180         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6181          * Bit 3-0: Channel mask
6182          * Bit   4: set for 48KHz, clear for 32KHz
6183          * Bit   5: mode
6184          * Bit   6: set to select Data2, clear for Data1
6185          * Bit   7: set to enable DMic, clear for AMic
6186          */
6187         if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6188                 val = 0x33;
6189         else
6190                 val = 0x23;
6191         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6192         spec->dmic_ctl = val;
6193         snd_hda_codec_write(codec, spec->input_pins[0], 0,
6194                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
6195 }
6196
6197 /*
6198  * Initialization for Analog Mic 2
6199  */
6200 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6201 {
6202         struct ca0132_spec *spec = codec->spec;
6203
6204         mutex_lock(&spec->chipio_mutex);
6205         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6206                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6207         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6208                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6209         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6210                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6211         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6212                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6213         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6214                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6215         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6216                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6217         mutex_unlock(&spec->chipio_mutex);
6218 }
6219
6220 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6221 {
6222         struct ca0132_spec *spec = codec->spec;
6223         int i;
6224
6225         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6226         snd_hda_codec_update_widgets(codec);
6227
6228         for (i = 0; i < spec->multiout.num_dacs; i++)
6229                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6230
6231         for (i = 0; i < spec->num_outputs; i++)
6232                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6233
6234         for (i = 0; i < spec->num_inputs; i++) {
6235                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6236                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6237         }
6238 }
6239
6240 /*
6241  * Recon3D r3d_setup_defaults sub functions.
6242  */
6243
6244 static void r3d_dsp_scp_startup(struct hda_codec *codec)
6245 {
6246         unsigned int tmp;
6247
6248         tmp = 0x00000000;
6249         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6250
6251         tmp = 0x00000001;
6252         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6253
6254         tmp = 0x00000004;
6255         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6256
6257         tmp = 0x00000005;
6258         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6259
6260         tmp = 0x00000000;
6261         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6262
6263 }
6264
6265 static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6266 {
6267         unsigned int tmp;
6268
6269         /* Mic 1 Setup */
6270         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6271         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6272         /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6273         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6274         tmp = FLOAT_ONE;
6275         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6276
6277         /* Mic 2 Setup, even though it isn't connected on SBZ */
6278         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6279         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6280         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6281         tmp = FLOAT_ZERO;
6282         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6283 }
6284
6285 /*
6286  * Initialize Sound Blaster Z analog microphones.
6287  */
6288 static void sbz_init_analog_mics(struct hda_codec *codec)
6289 {
6290         unsigned int tmp;
6291
6292         /* Mic 1 Setup */
6293         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6294         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6295         tmp = FLOAT_THREE;
6296         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6297
6298         /* Mic 2 Setup, even though it isn't connected on SBZ */
6299         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6300         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6301         tmp = FLOAT_ZERO;
6302         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6303
6304 }
6305
6306 /*
6307  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6308  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6309  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6310  * having an updated DAC, which changes the destination to that DAC.
6311  */
6312 static void sbz_connect_streams(struct hda_codec *codec)
6313 {
6314         struct ca0132_spec *spec = codec->spec;
6315
6316         mutex_lock(&spec->chipio_mutex);
6317
6318         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6319
6320         chipio_set_stream_channels(codec, 0x0C, 6);
6321         chipio_set_stream_control(codec, 0x0C, 1);
6322
6323         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6324         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6325
6326         /* Setup stream 0x14 with it's source and destination points */
6327         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6328         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6329         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6330         chipio_set_stream_channels(codec, 0x14, 2);
6331         chipio_set_stream_control(codec, 0x14, 1);
6332
6333         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6334
6335         mutex_unlock(&spec->chipio_mutex);
6336
6337 }
6338
6339 /*
6340  * Write data through ChipIO to setup proper stream destinations.
6341  * Not sure how it exactly works, but it seems to direct data
6342  * to different destinations. Example is f8 to c0, e0 to c0.
6343  * All I know is, if you don't set these, you get no sound.
6344  */
6345 static void sbz_chipio_startup_data(struct hda_codec *codec)
6346 {
6347         struct ca0132_spec *spec = codec->spec;
6348
6349         mutex_lock(&spec->chipio_mutex);
6350         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6351
6352         /* These control audio output */
6353         chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6354         chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6355         chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6356         chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6357         /* Signal to update I think */
6358         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6359
6360         chipio_set_stream_channels(codec, 0x0C, 6);
6361         chipio_set_stream_control(codec, 0x0C, 1);
6362         /* No clue what these control */
6363         chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6364         chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6365         chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6366         chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6367         chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6368         chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6369         chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6370         chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6371         chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6372         chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6373         chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6374         chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6375
6376         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6377
6378         codec_dbg(codec, "Startup Data exited, mutex released.\n");
6379         mutex_unlock(&spec->chipio_mutex);
6380 }
6381
6382 /*
6383  * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6384  * without a 0x20 source like normal.
6385  */
6386 static void sbz_dsp_scp_startup(struct hda_codec *codec)
6387 {
6388         unsigned int tmp;
6389
6390         tmp = 0x00000003;
6391         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6392
6393         tmp = 0x00000000;
6394         dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6395
6396         tmp = 0x00000001;
6397         dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6398
6399         tmp = 0x00000004;
6400         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6401
6402         tmp = 0x00000005;
6403         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6404
6405         tmp = 0x00000000;
6406         dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6407
6408 }
6409
6410 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6411 {
6412         unsigned int tmp;
6413
6414         chipio_set_stream_control(codec, 0x03, 0);
6415         chipio_set_stream_control(codec, 0x04, 0);
6416
6417         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6418         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6419
6420         tmp = FLOAT_THREE;
6421         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6422
6423         chipio_set_stream_control(codec, 0x03, 1);
6424         chipio_set_stream_control(codec, 0x04, 1);
6425
6426         chipio_write(codec, 0x18b098, 0x0000000c);
6427         chipio_write(codec, 0x18b09C, 0x0000000c);
6428 }
6429
6430 /*
6431  * Setup default parameters for DSP
6432  */
6433 static void ca0132_setup_defaults(struct hda_codec *codec)
6434 {
6435         struct ca0132_spec *spec = codec->spec;
6436         unsigned int tmp;
6437         int num_fx;
6438         int idx, i;
6439
6440         if (spec->dsp_state != DSP_DOWNLOADED)
6441                 return;
6442
6443         /* out, in effects + voicefx */
6444         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6445         for (idx = 0; idx < num_fx; idx++) {
6446                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6447                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6448                                              ca0132_effects[idx].reqs[i],
6449                                              ca0132_effects[idx].def_vals[i]);
6450                 }
6451         }
6452
6453         /*remove DSP headroom*/
6454         tmp = FLOAT_ZERO;
6455         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6456
6457         /*set speaker EQ bypass attenuation*/
6458         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6459
6460         /* set AMic1 and AMic2 as mono mic */
6461         tmp = FLOAT_ONE;
6462         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6463         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6464
6465         /* set AMic1 as CrystalVoice input */
6466         tmp = FLOAT_ONE;
6467         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6468
6469         /* set WUH source */
6470         tmp = FLOAT_TWO;
6471         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6472 }
6473
6474 /*
6475  * Setup default parameters for Recon3D/Recon3Di DSP.
6476  */
6477
6478 static void r3d_setup_defaults(struct hda_codec *codec)
6479 {
6480         struct ca0132_spec *spec = codec->spec;
6481         unsigned int tmp;
6482         int num_fx;
6483         int idx, i;
6484
6485         if (spec->dsp_state != DSP_DOWNLOADED)
6486                 return;
6487
6488         r3d_dsp_scp_startup(codec);
6489
6490         r3d_dsp_initial_mic_setup(codec);
6491
6492         /*remove DSP headroom*/
6493         tmp = FLOAT_ZERO;
6494         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6495
6496         /* set WUH source */
6497         tmp = FLOAT_TWO;
6498         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6499         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6500
6501         /* Set speaker source? */
6502         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6503
6504         if (spec->quirk == QUIRK_R3DI)
6505                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6506
6507         /* Setup effect defaults */
6508         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6509         for (idx = 0; idx < num_fx; idx++) {
6510                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6511                         dspio_set_uint_param(codec,
6512                                         ca0132_effects[idx].mid,
6513                                         ca0132_effects[idx].reqs[i],
6514                                         ca0132_effects[idx].def_vals[i]);
6515                 }
6516         }
6517 }
6518
6519 /*
6520  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6521  * than the Chromebook setup.
6522  */
6523 static void sbz_setup_defaults(struct hda_codec *codec)
6524 {
6525         struct ca0132_spec *spec = codec->spec;
6526         unsigned int tmp, stream_format;
6527         int num_fx;
6528         int idx, i;
6529
6530         if (spec->dsp_state != DSP_DOWNLOADED)
6531                 return;
6532
6533         sbz_dsp_scp_startup(codec);
6534
6535         sbz_init_analog_mics(codec);
6536
6537         sbz_connect_streams(codec);
6538
6539         sbz_chipio_startup_data(codec);
6540
6541         chipio_set_stream_control(codec, 0x03, 1);
6542         chipio_set_stream_control(codec, 0x04, 1);
6543
6544         /*
6545          * Sets internal input loopback to off, used to have a switch to
6546          * enable input loopback, but turned out to be way too buggy.
6547          */
6548         tmp = FLOAT_ONE;
6549         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6550         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6551
6552         /*remove DSP headroom*/
6553         tmp = FLOAT_ZERO;
6554         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6555
6556         /* set WUH source */
6557         tmp = FLOAT_TWO;
6558         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6559         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6560
6561         /* Set speaker source? */
6562         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6563
6564         sbz_dsp_initial_mic_setup(codec);
6565
6566
6567         /* out, in effects + voicefx */
6568         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6569         for (idx = 0; idx < num_fx; idx++) {
6570                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6571                         dspio_set_uint_param(codec,
6572                                         ca0132_effects[idx].mid,
6573                                         ca0132_effects[idx].reqs[i],
6574                                         ca0132_effects[idx].def_vals[i]);
6575                 }
6576         }
6577
6578         /*
6579          * Have to make a stream to bind the sound output to, otherwise
6580          * you'll get dead audio. Before I did this, it would bind to an
6581          * audio input, and would never work
6582          */
6583         stream_format = snd_hdac_calc_stream_format(48000, 2,
6584                         SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6585
6586         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6587                                         0, stream_format);
6588
6589         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6590
6591         snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6592                                         0, stream_format);
6593
6594         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6595 }
6596
6597 /*
6598  * Initialization of flags in chip
6599  */
6600 static void ca0132_init_flags(struct hda_codec *codec)
6601 {
6602         struct ca0132_spec *spec = codec->spec;
6603
6604         if (spec->use_alt_functions) {
6605                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6606                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6607                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6608                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6609                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6610                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6611                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6612                 chipio_set_control_flag(codec,
6613                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6614                 chipio_set_control_flag(codec,
6615                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6616         } else {
6617                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6618                 chipio_set_control_flag(codec,
6619                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6620                 chipio_set_control_flag(codec,
6621                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6622                 chipio_set_control_flag(codec,
6623                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6624                 chipio_set_control_flag(codec,
6625                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6626                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6627         }
6628 }
6629
6630 /*
6631  * Initialization of parameters in chip
6632  */
6633 static void ca0132_init_params(struct hda_codec *codec)
6634 {
6635         struct ca0132_spec *spec = codec->spec;
6636
6637         if (spec->use_alt_functions) {
6638                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6639                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6640                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6641                 chipio_set_control_param(codec, 0, 0);
6642                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6643         }
6644
6645         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6646         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6647 }
6648
6649 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6650 {
6651         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6652         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6653         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6654         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6655         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6656         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6657
6658         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6659         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6660         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6661 }
6662
6663 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6664 {
6665         bool dsp_loaded = false;
6666         struct ca0132_spec *spec = codec->spec;
6667         const struct dsp_image_seg *dsp_os_image;
6668         const struct firmware *fw_entry;
6669         /*
6670          * Alternate firmwares for different variants. The Recon3Di apparently
6671          * can use the default firmware, but I'll leave the option in case
6672          * it needs it again.
6673          */
6674         switch (spec->quirk) {
6675         case QUIRK_SBZ:
6676                 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6677                                         codec->card->dev) != 0) {
6678                         codec_dbg(codec, "SBZ alt firmware not detected. ");
6679                         spec->alt_firmware_present = false;
6680                 } else {
6681                         codec_dbg(codec, "Sound Blaster Z firmware selected.");
6682                         spec->alt_firmware_present = true;
6683                 }
6684                 break;
6685         case QUIRK_R3DI:
6686                 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6687                                         codec->card->dev) != 0) {
6688                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
6689                         spec->alt_firmware_present = false;
6690                 } else {
6691                         codec_dbg(codec, "Recon3Di firmware selected.");
6692                         spec->alt_firmware_present = true;
6693                 }
6694                 break;
6695         default:
6696                 spec->alt_firmware_present = false;
6697                 break;
6698         }
6699         /*
6700          * Use default ctefx.bin if no alt firmware is detected, or if none
6701          * exists for your particular codec.
6702          */
6703         if (!spec->alt_firmware_present) {
6704                 codec_dbg(codec, "Default firmware selected.");
6705                 if (request_firmware(&fw_entry, EFX_FILE,
6706                                         codec->card->dev) != 0)
6707                         return false;
6708         }
6709
6710         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6711         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6712                 codec_err(codec, "ca0132 DSP load image failed\n");
6713                 goto exit_download;
6714         }
6715
6716         dsp_loaded = dspload_wait_loaded(codec);
6717
6718 exit_download:
6719         release_firmware(fw_entry);
6720
6721         return dsp_loaded;
6722 }
6723
6724 static void ca0132_download_dsp(struct hda_codec *codec)
6725 {
6726         struct ca0132_spec *spec = codec->spec;
6727
6728 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6729         return; /* NOP */
6730 #endif
6731
6732         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6733                 return; /* don't retry failures */
6734
6735         chipio_enable_clocks(codec);
6736         if (spec->dsp_state != DSP_DOWNLOADED) {
6737                 spec->dsp_state = DSP_DOWNLOADING;
6738
6739                 if (!ca0132_download_dsp_images(codec))
6740                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
6741                 else
6742                         spec->dsp_state = DSP_DOWNLOADED;
6743         }
6744
6745         /* For codecs using alt functions, this is already done earlier */
6746         if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6747                 ca0132_set_dsp_msr(codec, true);
6748 }
6749
6750 static void ca0132_process_dsp_response(struct hda_codec *codec,
6751                                         struct hda_jack_callback *callback)
6752 {
6753         struct ca0132_spec *spec = codec->spec;
6754
6755         codec_dbg(codec, "ca0132_process_dsp_response\n");
6756         if (spec->wait_scp) {
6757                 if (dspio_get_response_data(codec) >= 0)
6758                         spec->wait_scp = 0;
6759         }
6760
6761         dspio_clear_response_queue(codec);
6762 }
6763
6764 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6765 {
6766         struct ca0132_spec *spec = codec->spec;
6767         struct hda_jack_tbl *tbl;
6768
6769         /* Delay enabling the HP amp, to let the mic-detection
6770          * state machine run.
6771          */
6772         cancel_delayed_work_sync(&spec->unsol_hp_work);
6773         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6774         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6775         if (tbl)
6776                 tbl->block_report = 1;
6777 }
6778
6779 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6780 {
6781         struct ca0132_spec *spec = codec->spec;
6782
6783         if (spec->use_alt_functions)
6784                 ca0132_alt_select_in(codec);
6785         else
6786                 ca0132_select_mic(codec);
6787 }
6788
6789 static void ca0132_init_unsol(struct hda_codec *codec)
6790 {
6791         struct ca0132_spec *spec = codec->spec;
6792         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6793         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6794                                             amic_callback);
6795         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6796                                             ca0132_process_dsp_response);
6797         /* Front headphone jack detection */
6798         if (spec->use_alt_functions)
6799                 snd_hda_jack_detect_enable_callback(codec,
6800                         spec->unsol_tag_front_hp, hp_callback);
6801 }
6802
6803 /*
6804  * Verbs tables.
6805  */
6806
6807 /* Sends before DSP download. */
6808 static struct hda_verb ca0132_base_init_verbs[] = {
6809         /*enable ct extension*/
6810         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6811         {}
6812 };
6813
6814 /* Send at exit. */
6815 static struct hda_verb ca0132_base_exit_verbs[] = {
6816         /*set afg to D3*/
6817         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6818         /*disable ct extension*/
6819         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6820         {}
6821 };
6822
6823 /* Other verbs tables. Sends after DSP download. */
6824
6825 static struct hda_verb ca0132_init_verbs0[] = {
6826         /* chip init verbs */
6827         {0x15, 0x70D, 0xF0},
6828         {0x15, 0x70E, 0xFE},
6829         {0x15, 0x707, 0x75},
6830         {0x15, 0x707, 0xD3},
6831         {0x15, 0x707, 0x09},
6832         {0x15, 0x707, 0x53},
6833         {0x15, 0x707, 0xD4},
6834         {0x15, 0x707, 0xEF},
6835         {0x15, 0x707, 0x75},
6836         {0x15, 0x707, 0xD3},
6837         {0x15, 0x707, 0x09},
6838         {0x15, 0x707, 0x02},
6839         {0x15, 0x707, 0x37},
6840         {0x15, 0x707, 0x78},
6841         {0x15, 0x53C, 0xCE},
6842         {0x15, 0x575, 0xC9},
6843         {0x15, 0x53D, 0xCE},
6844         {0x15, 0x5B7, 0xC9},
6845         {0x15, 0x70D, 0xE8},
6846         {0x15, 0x70E, 0xFE},
6847         {0x15, 0x707, 0x02},
6848         {0x15, 0x707, 0x68},
6849         {0x15, 0x707, 0x62},
6850         {0x15, 0x53A, 0xCE},
6851         {0x15, 0x546, 0xC9},
6852         {0x15, 0x53B, 0xCE},
6853         {0x15, 0x5E8, 0xC9},
6854         {}
6855 };
6856
6857 /* Extra init verbs for desktop cards. */
6858 static struct hda_verb ca0132_init_verbs1[] = {
6859         {0x15, 0x70D, 0x20},
6860         {0x15, 0x70E, 0x19},
6861         {0x15, 0x707, 0x00},
6862         {0x15, 0x539, 0xCE},
6863         {0x15, 0x546, 0xC9},
6864         {0x15, 0x70D, 0xB7},
6865         {0x15, 0x70E, 0x09},
6866         {0x15, 0x707, 0x10},
6867         {0x15, 0x70D, 0xAF},
6868         {0x15, 0x70E, 0x09},
6869         {0x15, 0x707, 0x01},
6870         {0x15, 0x707, 0x05},
6871         {0x15, 0x70D, 0x73},
6872         {0x15, 0x70E, 0x09},
6873         {0x15, 0x707, 0x14},
6874         {0x15, 0x6FF, 0xC4},
6875         {}
6876 };
6877
6878 static void ca0132_init_chip(struct hda_codec *codec)
6879 {
6880         struct ca0132_spec *spec = codec->spec;
6881         int num_fx;
6882         int i;
6883         unsigned int on;
6884
6885         mutex_init(&spec->chipio_mutex);
6886
6887         spec->cur_out_type = SPEAKER_OUT;
6888         if (!spec->use_alt_functions)
6889                 spec->cur_mic_type = DIGITAL_MIC;
6890         else
6891                 spec->cur_mic_type = REAR_MIC;
6892
6893         spec->cur_mic_boost = 0;
6894
6895         for (i = 0; i < VNODES_COUNT; i++) {
6896                 spec->vnode_lvol[i] = 0x5a;
6897                 spec->vnode_rvol[i] = 0x5a;
6898                 spec->vnode_lswitch[i] = 0;
6899                 spec->vnode_rswitch[i] = 0;
6900         }
6901
6902         /*
6903          * Default states for effects are in ca0132_effects[].
6904          */
6905         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6906         for (i = 0; i < num_fx; i++) {
6907                 on = (unsigned int)ca0132_effects[i].reqs[0];
6908                 spec->effects_switch[i] = on ? 1 : 0;
6909         }
6910         /*
6911          * Sets defaults for the effect slider controls, only for alternative
6912          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6913          */
6914         if (spec->use_alt_controls) {
6915                 spec->xbass_xover_freq = 8;
6916                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6917                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
6918         }
6919
6920         spec->voicefx_val = 0;
6921         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6922         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6923
6924 #ifdef ENABLE_TUNING_CONTROLS
6925         ca0132_init_tuning_defaults(codec);
6926 #endif
6927 }
6928
6929 /*
6930  * Recon3Di exit specific commands.
6931  */
6932 /* prevents popping noise on shutdown */
6933 static void r3di_gpio_shutdown(struct hda_codec *codec)
6934 {
6935         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6936 }
6937
6938 /*
6939  * Sound Blaster Z exit specific commands.
6940  */
6941 static void sbz_region2_exit(struct hda_codec *codec)
6942 {
6943         struct ca0132_spec *spec = codec->spec;
6944         unsigned int i;
6945
6946         for (i = 0; i < 4; i++)
6947                 writeb(0x0, spec->mem_base + 0x100);
6948         for (i = 0; i < 8; i++)
6949                 writeb(0xb3, spec->mem_base + 0x304);
6950
6951         ca0132_mmio_gpio_set(codec, 0, false);
6952         ca0132_mmio_gpio_set(codec, 1, false);
6953         ca0132_mmio_gpio_set(codec, 4, true);
6954         ca0132_mmio_gpio_set(codec, 5, false);
6955         ca0132_mmio_gpio_set(codec, 7, false);
6956 }
6957
6958 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6959 {
6960         hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6961         unsigned int i;
6962
6963         snd_hda_codec_write(codec, 0x11, 0,
6964                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6965
6966         for (i = 0; i < 5; i++)
6967                 snd_hda_codec_write(codec, pins[i], 0,
6968                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6969 }
6970
6971 static void ca0132_clear_unsolicited(struct hda_codec *codec)
6972 {
6973         hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6974         unsigned int i;
6975
6976         for (i = 0; i < 7; i++) {
6977                 snd_hda_codec_write(codec, pins[i], 0,
6978                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6979         }
6980 }
6981
6982 /* On shutdown, sends commands in sets of three */
6983 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6984                                                         int mask, int data)
6985 {
6986         if (dir >= 0)
6987                 snd_hda_codec_write(codec, 0x01, 0,
6988                                 AC_VERB_SET_GPIO_DIRECTION, dir);
6989         if (mask >= 0)
6990                 snd_hda_codec_write(codec, 0x01, 0,
6991                                 AC_VERB_SET_GPIO_MASK, mask);
6992
6993         if (data >= 0)
6994                 snd_hda_codec_write(codec, 0x01, 0,
6995                                 AC_VERB_SET_GPIO_DATA, data);
6996 }
6997
6998 static void sbz_exit_chip(struct hda_codec *codec)
6999 {
7000         chipio_set_stream_control(codec, 0x03, 0);
7001         chipio_set_stream_control(codec, 0x04, 0);
7002
7003         /* Mess with GPIO */
7004         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7005         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7006         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7007
7008         chipio_set_stream_control(codec, 0x14, 0);
7009         chipio_set_stream_control(codec, 0x0C, 0);
7010
7011         chipio_set_conn_rate(codec, 0x41, SR_192_000);
7012         chipio_set_conn_rate(codec, 0x91, SR_192_000);
7013
7014         chipio_write(codec, 0x18a020, 0x00000083);
7015
7016         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7017         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7018         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7019
7020         chipio_set_stream_control(codec, 0x0C, 0);
7021
7022         chipio_set_control_param(codec, 0x0D, 0x24);
7023
7024         ca0132_clear_unsolicited(codec);
7025         sbz_set_pin_ctl_default(codec);
7026
7027         snd_hda_codec_write(codec, 0x0B, 0,
7028                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7029
7030         sbz_region2_exit(codec);
7031 }
7032
7033 static void r3d_exit_chip(struct hda_codec *codec)
7034 {
7035         ca0132_clear_unsolicited(codec);
7036         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7037         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7038 }
7039
7040 static void ca0132_exit_chip(struct hda_codec *codec)
7041 {
7042         /* put any chip cleanup stuffs here. */
7043
7044         if (dspload_is_loaded(codec))
7045                 dsp_reset(codec);
7046 }
7047
7048 /*
7049  * This fixes a problem that was hard to reproduce. Very rarely, I would
7050  * boot up, and there would be no sound, but the DSP indicated it had loaded
7051  * properly. I did a few memory dumps to see if anything was different, and
7052  * there were a few areas of memory uninitialized with a1a2a3a4. This function
7053  * checks if those areas are uninitialized, and if they are, it'll attempt to
7054  * reload the card 3 times. Usually it fixes by the second.
7055  */
7056 static void sbz_dsp_startup_check(struct hda_codec *codec)
7057 {
7058         struct ca0132_spec *spec = codec->spec;
7059         unsigned int dsp_data_check[4];
7060         unsigned int cur_address = 0x390;
7061         unsigned int i;
7062         unsigned int failure = 0;
7063         unsigned int reload = 3;
7064
7065         if (spec->startup_check_entered)
7066                 return;
7067
7068         spec->startup_check_entered = true;
7069
7070         for (i = 0; i < 4; i++) {
7071                 chipio_read(codec, cur_address, &dsp_data_check[i]);
7072                 cur_address += 0x4;
7073         }
7074         for (i = 0; i < 4; i++) {
7075                 if (dsp_data_check[i] == 0xa1a2a3a4)
7076                         failure = 1;
7077         }
7078
7079         codec_dbg(codec, "Startup Check: %d ", failure);
7080         if (failure)
7081                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7082         /*
7083          * While the failure condition is true, and we haven't reached our
7084          * three reload limit, continue trying to reload the driver and
7085          * fix the issue.
7086          */
7087         while (failure && (reload != 0)) {
7088                 codec_info(codec, "Reloading... Tries left: %d", reload);
7089                 sbz_exit_chip(codec);
7090                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7091                 codec->patch_ops.init(codec);
7092                 failure = 0;
7093                 for (i = 0; i < 4; i++) {
7094                         chipio_read(codec, cur_address, &dsp_data_check[i]);
7095                         cur_address += 0x4;
7096                 }
7097                 for (i = 0; i < 4; i++) {
7098                         if (dsp_data_check[i] == 0xa1a2a3a4)
7099                                 failure = 1;
7100                 }
7101                 reload--;
7102         }
7103
7104         if (!failure && reload < 3)
7105                 codec_info(codec, "DSP fixed.");
7106
7107         if (!failure)
7108                 return;
7109
7110         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7111 }
7112
7113 /*
7114  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7115  * extra precision for decibel values. If you had the dB value in floating point
7116  * you would take the value after the decimal point, multiply by 64, and divide
7117  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7118  * implement fixed point or floating point dB volumes. For now, I'll set them
7119  * to 0 just incase a value has lingered from a boot into Windows.
7120  */
7121 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7122 {
7123         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7124         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7125         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7126         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7127         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7128         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7129         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7130         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7131 }
7132
7133 /*
7134  * Extra commands that don't really fit anywhere else.
7135  */
7136 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7137 {
7138         struct ca0132_spec *spec = codec->spec;
7139
7140         writel(0x00820680, spec->mem_base + 0x01C);
7141         writel(0x00820680, spec->mem_base + 0x01C);
7142
7143         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7144         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7145         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7146         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7147
7148         chipio_write(codec, 0x18b0a4, 0x000000c2);
7149
7150         snd_hda_codec_write(codec, 0x11, 0,
7151                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7152 }
7153
7154 static void r3d_pre_dsp_setup(struct hda_codec *codec)
7155 {
7156
7157         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7158         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7159         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7160         snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7161
7162         chipio_write(codec, 0x18b0a4, 0x000000c2);
7163
7164         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7165                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7166         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7167                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7168         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7169                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7170
7171         snd_hda_codec_write(codec, 0x11, 0,
7172                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7173 }
7174
7175 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7176 {
7177         chipio_write(codec, 0x18b0a4, 0x000000c2);
7178
7179         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7180                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7181         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7182                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7183         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7184                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7185
7186         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7187                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7188         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7189                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7190         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7191                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7192         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7193                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7194
7195         snd_hda_codec_write(codec, 0x11, 0,
7196                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7197 }
7198
7199 /*
7200  * These are sent before the DSP is downloaded. Not sure
7201  * what they do, or if they're necessary. Could possibly
7202  * be removed. Figure they're better to leave in.
7203  */
7204 static void ca0132_mmio_init(struct hda_codec *codec)
7205 {
7206         struct ca0132_spec *spec = codec->spec;
7207
7208         writel(0x00000000, spec->mem_base + 0x400);
7209         writel(0x00000000, spec->mem_base + 0x408);
7210         writel(0x00000000, spec->mem_base + 0x40C);
7211         writel(0x00880680, spec->mem_base + 0x01C);
7212         writel(0x00000083, spec->mem_base + 0xC0C);
7213         writel(0x00000030, spec->mem_base + 0xC00);
7214         writel(0x00000000, spec->mem_base + 0xC04);
7215         writel(0x00000003, spec->mem_base + 0xC0C);
7216         writel(0x00000003, spec->mem_base + 0xC0C);
7217         writel(0x00000003, spec->mem_base + 0xC0C);
7218         writel(0x00000003, spec->mem_base + 0xC0C);
7219         writel(0x000000C1, spec->mem_base + 0xC08);
7220         writel(0x000000F1, spec->mem_base + 0xC08);
7221         writel(0x00000001, spec->mem_base + 0xC08);
7222         writel(0x000000C7, spec->mem_base + 0xC08);
7223         writel(0x000000C1, spec->mem_base + 0xC08);
7224         writel(0x00000080, spec->mem_base + 0xC04);
7225 }
7226
7227 /*
7228  * Extra init functions for alternative ca0132 codecs. Done
7229  * here so they don't clutter up the main ca0132_init function
7230  * anymore than they have to.
7231  */
7232 static void ca0132_alt_init(struct hda_codec *codec)
7233 {
7234         struct ca0132_spec *spec = codec->spec;
7235
7236         ca0132_alt_vol_setup(codec);
7237
7238         switch (spec->quirk) {
7239         case QUIRK_SBZ:
7240                 codec_dbg(codec, "SBZ alt_init");
7241                 ca0132_gpio_init(codec);
7242                 sbz_pre_dsp_setup(codec);
7243                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7244                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7245                 break;
7246         case QUIRK_R3DI:
7247                 codec_dbg(codec, "R3DI alt_init");
7248                 ca0132_gpio_init(codec);
7249                 ca0132_gpio_setup(codec);
7250                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7251                 r3di_pre_dsp_setup(codec);
7252                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7253                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7254                 break;
7255         case QUIRK_R3D:
7256                 r3d_pre_dsp_setup(codec);
7257                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7258                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7259                 break;
7260         }
7261 }
7262
7263 static int ca0132_init(struct hda_codec *codec)
7264 {
7265         struct ca0132_spec *spec = codec->spec;
7266         struct auto_pin_cfg *cfg = &spec->autocfg;
7267         int i;
7268         bool dsp_loaded;
7269
7270         /*
7271          * If the DSP is already downloaded, and init has been entered again,
7272          * there's only two reasons for it. One, the codec has awaken from a
7273          * suspended state, and in that case dspload_is_loaded will return
7274          * false, and the init will be ran again. The other reason it gets
7275          * re entered is on startup for some reason it triggers a suspend and
7276          * resume state. In this case, it will check if the DSP is downloaded,
7277          * and not run the init function again. For codecs using alt_functions,
7278          * it will check if the DSP is loaded properly.
7279          */
7280         if (spec->dsp_state == DSP_DOWNLOADED) {
7281                 dsp_loaded = dspload_is_loaded(codec);
7282                 if (!dsp_loaded) {
7283                         spec->dsp_reload = true;
7284                         spec->dsp_state = DSP_DOWNLOAD_INIT;
7285                 } else {
7286                         if (spec->quirk == QUIRK_SBZ)
7287                                 sbz_dsp_startup_check(codec);
7288                         return 0;
7289                 }
7290         }
7291
7292         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7293                 spec->dsp_state = DSP_DOWNLOAD_INIT;
7294         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7295
7296         if (spec->use_pci_mmio)
7297                 ca0132_mmio_init(codec);
7298
7299         snd_hda_power_up_pm(codec);
7300
7301         ca0132_init_unsol(codec);
7302         ca0132_init_params(codec);
7303         ca0132_init_flags(codec);
7304
7305         snd_hda_sequence_write(codec, spec->base_init_verbs);
7306
7307         if (spec->use_alt_functions)
7308                 ca0132_alt_init(codec);
7309
7310         ca0132_download_dsp(codec);
7311
7312         ca0132_refresh_widget_caps(codec);
7313
7314         switch (spec->quirk) {
7315         case QUIRK_R3DI:
7316         case QUIRK_R3D:
7317                 r3d_setup_defaults(codec);
7318                 break;
7319         case QUIRK_SBZ:
7320                 sbz_setup_defaults(codec);
7321                 break;
7322         default:
7323                 ca0132_setup_defaults(codec);
7324                 ca0132_init_analog_mic2(codec);
7325                 ca0132_init_dmic(codec);
7326                 break;
7327         }
7328
7329         for (i = 0; i < spec->num_outputs; i++)
7330                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7331
7332         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7333
7334         for (i = 0; i < spec->num_inputs; i++)
7335                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7336
7337         init_input(codec, cfg->dig_in_pin, spec->dig_in);
7338
7339         if (!spec->use_alt_functions) {
7340                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7341                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7342                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7343                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7344                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7345         }
7346
7347         if (spec->quirk == QUIRK_SBZ)
7348                 ca0132_gpio_setup(codec);
7349
7350         snd_hda_sequence_write(codec, spec->spec_init_verbs);
7351         if (spec->use_alt_functions) {
7352                 ca0132_alt_select_out(codec);
7353                 ca0132_alt_select_in(codec);
7354         } else {
7355                 ca0132_select_out(codec);
7356                 ca0132_select_mic(codec);
7357         }
7358
7359         snd_hda_jack_report_sync(codec);
7360
7361         /*
7362          * Re set the PlayEnhancement switch on a resume event, because the
7363          * controls will not be reloaded.
7364          */
7365         if (spec->dsp_reload) {
7366                 spec->dsp_reload = false;
7367                 ca0132_pe_switch_set(codec);
7368         }
7369
7370         snd_hda_power_down_pm(codec);
7371
7372         return 0;
7373 }
7374
7375 static void ca0132_free(struct hda_codec *codec)
7376 {
7377         struct ca0132_spec *spec = codec->spec;
7378
7379         cancel_delayed_work_sync(&spec->unsol_hp_work);
7380         snd_hda_power_up(codec);
7381         switch (spec->quirk) {
7382         case QUIRK_SBZ:
7383                 sbz_exit_chip(codec);
7384                 break;
7385         case QUIRK_R3D:
7386                 r3d_exit_chip(codec);
7387                 break;
7388         case QUIRK_R3DI:
7389                 r3di_gpio_shutdown(codec);
7390                 break;
7391         }
7392
7393         snd_hda_sequence_write(codec, spec->base_exit_verbs);
7394         ca0132_exit_chip(codec);
7395
7396         snd_hda_power_down(codec);
7397         if (spec->mem_base)
7398                 iounmap(spec->mem_base);
7399         kfree(spec->spec_init_verbs);
7400         kfree(codec->spec);
7401 }
7402
7403 static void ca0132_reboot_notify(struct hda_codec *codec)
7404 {
7405         codec->patch_ops.free(codec);
7406 }
7407
7408 static const struct hda_codec_ops ca0132_patch_ops = {
7409         .build_controls = ca0132_build_controls,
7410         .build_pcms = ca0132_build_pcms,
7411         .init = ca0132_init,
7412         .free = ca0132_free,
7413         .unsol_event = snd_hda_jack_unsol_event,
7414         .reboot_notify = ca0132_reboot_notify,
7415 };
7416
7417 static void ca0132_config(struct hda_codec *codec)
7418 {
7419         struct ca0132_spec *spec = codec->spec;
7420
7421         spec->dacs[0] = 0x2;
7422         spec->dacs[1] = 0x3;
7423         spec->dacs[2] = 0x4;
7424
7425         spec->multiout.dac_nids = spec->dacs;
7426         spec->multiout.num_dacs = 3;
7427
7428         if (!spec->use_alt_functions)
7429                 spec->multiout.max_channels = 2;
7430         else
7431                 spec->multiout.max_channels = 6;
7432
7433         switch (spec->quirk) {
7434         case QUIRK_ALIENWARE:
7435                 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7436                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7437
7438                 spec->num_outputs = 2;
7439                 spec->out_pins[0] = 0x0b; /* speaker out */
7440                 spec->out_pins[1] = 0x0f;
7441                 spec->shared_out_nid = 0x2;
7442                 spec->unsol_tag_hp = 0x0f;
7443
7444                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7445                 spec->adcs[1] = 0x8; /* analog mic2 */
7446                 spec->adcs[2] = 0xa; /* what u hear */
7447
7448                 spec->num_inputs = 3;
7449                 spec->input_pins[0] = 0x12;
7450                 spec->input_pins[1] = 0x11;
7451                 spec->input_pins[2] = 0x13;
7452                 spec->shared_mic_nid = 0x7;
7453                 spec->unsol_tag_amic1 = 0x11;
7454                 break;
7455         case QUIRK_SBZ:
7456         case QUIRK_R3D:
7457                 if (spec->quirk == QUIRK_SBZ) {
7458                         codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7459                         snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7460                 }
7461                 if (spec->quirk == QUIRK_R3D) {
7462                         codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7463                         snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7464                 }
7465
7466                 spec->num_outputs = 2;
7467                 spec->out_pins[0] = 0x0B; /* Line out */
7468                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7469                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7470                 spec->out_pins[3] = 0x11; /* Rear surround */
7471                 spec->shared_out_nid = 0x2;
7472                 spec->unsol_tag_hp = spec->out_pins[1];
7473                 spec->unsol_tag_front_hp = spec->out_pins[2];
7474
7475                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7476                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7477                 spec->adcs[2] = 0xa; /* what u hear */
7478
7479                 spec->num_inputs = 2;
7480                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7481                 spec->input_pins[1] = 0x13; /* What U Hear */
7482                 spec->shared_mic_nid = 0x7;
7483                 spec->unsol_tag_amic1 = spec->input_pins[0];
7484
7485                 /* SPDIF I/O */
7486                 spec->dig_out = 0x05;
7487                 spec->multiout.dig_out_nid = spec->dig_out;
7488                 spec->dig_in = 0x09;
7489                 break;
7490         case QUIRK_R3DI:
7491                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7492                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7493
7494                 spec->num_outputs = 2;
7495                 spec->out_pins[0] = 0x0B; /* Line out */
7496                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7497                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7498                 spec->out_pins[3] = 0x11; /* Rear surround */
7499                 spec->shared_out_nid = 0x2;
7500                 spec->unsol_tag_hp = spec->out_pins[1];
7501                 spec->unsol_tag_front_hp = spec->out_pins[2];
7502
7503                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7504                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7505                 spec->adcs[2] = 0x0a; /* what u hear */
7506
7507                 spec->num_inputs = 2;
7508                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7509                 spec->input_pins[1] = 0x13; /* What U Hear */
7510                 spec->shared_mic_nid = 0x7;
7511                 spec->unsol_tag_amic1 = spec->input_pins[0];
7512
7513                 /* SPDIF I/O */
7514                 spec->dig_out = 0x05;
7515                 spec->multiout.dig_out_nid = spec->dig_out;
7516                 break;
7517         default:
7518                 spec->num_outputs = 2;
7519                 spec->out_pins[0] = 0x0b; /* speaker out */
7520                 spec->out_pins[1] = 0x10; /* headphone out */
7521                 spec->shared_out_nid = 0x2;
7522                 spec->unsol_tag_hp = spec->out_pins[1];
7523
7524                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7525                 spec->adcs[1] = 0x8; /* analog mic2 */
7526                 spec->adcs[2] = 0xa; /* what u hear */
7527
7528                 spec->num_inputs = 3;
7529                 spec->input_pins[0] = 0x12;
7530                 spec->input_pins[1] = 0x11;
7531                 spec->input_pins[2] = 0x13;
7532                 spec->shared_mic_nid = 0x7;
7533                 spec->unsol_tag_amic1 = spec->input_pins[0];
7534
7535                 /* SPDIF I/O */
7536                 spec->dig_out = 0x05;
7537                 spec->multiout.dig_out_nid = spec->dig_out;
7538                 spec->dig_in = 0x09;
7539                 break;
7540         }
7541 }
7542
7543 static int ca0132_prepare_verbs(struct hda_codec *codec)
7544 {
7545 /* Verbs + terminator (an empty element) */
7546 #define NUM_SPEC_VERBS 2
7547         struct ca0132_spec *spec = codec->spec;
7548
7549         spec->chip_init_verbs = ca0132_init_verbs0;
7550         if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
7551                 spec->desktop_init_verbs = ca0132_init_verbs1;
7552         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7553                                         sizeof(struct hda_verb),
7554                                         GFP_KERNEL);
7555         if (!spec->spec_init_verbs)
7556                 return -ENOMEM;
7557
7558         /* config EAPD */
7559         spec->spec_init_verbs[0].nid = 0x0b;
7560         spec->spec_init_verbs[0].param = 0x78D;
7561         spec->spec_init_verbs[0].verb = 0x00;
7562
7563         /* Previously commented configuration */
7564         /*
7565         spec->spec_init_verbs[2].nid = 0x0b;
7566         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7567         spec->spec_init_verbs[2].verb = 0x02;
7568
7569         spec->spec_init_verbs[3].nid = 0x10;
7570         spec->spec_init_verbs[3].param = 0x78D;
7571         spec->spec_init_verbs[3].verb = 0x02;
7572
7573         spec->spec_init_verbs[4].nid = 0x10;
7574         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7575         spec->spec_init_verbs[4].verb = 0x02;
7576         */
7577
7578         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7579         return 0;
7580 }
7581
7582 static int patch_ca0132(struct hda_codec *codec)
7583 {
7584         struct ca0132_spec *spec;
7585         int err;
7586         const struct snd_pci_quirk *quirk;
7587
7588         codec_dbg(codec, "patch_ca0132\n");
7589
7590         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7591         if (!spec)
7592                 return -ENOMEM;
7593         codec->spec = spec;
7594         spec->codec = codec;
7595
7596         codec->patch_ops = ca0132_patch_ops;
7597         codec->pcm_format_first = 1;
7598         codec->no_sticky_stream = 1;
7599
7600         /* Detect codec quirk */
7601         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7602         if (quirk)
7603                 spec->quirk = quirk->value;
7604         else
7605                 spec->quirk = QUIRK_NONE;
7606
7607         spec->dsp_state = DSP_DOWNLOAD_INIT;
7608         spec->num_mixers = 1;
7609
7610         /* Set which mixers each quirk uses. */
7611         switch (spec->quirk) {
7612         case QUIRK_SBZ:
7613                 spec->mixers[0] = desktop_mixer;
7614                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7615                 break;
7616         case QUIRK_R3D:
7617                 spec->mixers[0] = desktop_mixer;
7618                 snd_hda_codec_set_name(codec, "Recon3D");
7619                 break;
7620         case QUIRK_R3DI:
7621                 spec->mixers[0] = r3di_mixer;
7622                 snd_hda_codec_set_name(codec, "Recon3Di");
7623                 break;
7624         default:
7625                 spec->mixers[0] = ca0132_mixer;
7626                 break;
7627         }
7628
7629         /* Setup whether or not to use alt functions/controls/pci_mmio */
7630         switch (spec->quirk) {
7631         case QUIRK_SBZ:
7632         case QUIRK_R3D:
7633                 spec->use_alt_controls = true;
7634                 spec->use_alt_functions = true;
7635                 spec->use_pci_mmio = true;
7636                 break;
7637         case QUIRK_R3DI:
7638                 spec->use_alt_controls = true;
7639                 spec->use_alt_functions = true;
7640                 spec->use_pci_mmio = false;
7641                 break;
7642         default:
7643                 spec->use_alt_controls = false;
7644                 spec->use_alt_functions = false;
7645                 spec->use_pci_mmio = false;
7646                 break;
7647         }
7648
7649         if (spec->use_pci_mmio) {
7650                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7651                 if (spec->mem_base == NULL) {
7652                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7653                         spec->quirk = QUIRK_NONE;
7654                 }
7655         }
7656
7657         spec->base_init_verbs = ca0132_base_init_verbs;
7658         spec->base_exit_verbs = ca0132_base_exit_verbs;
7659
7660         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7661
7662         ca0132_init_chip(codec);
7663
7664         ca0132_config(codec);
7665
7666         err = ca0132_prepare_verbs(codec);
7667         if (err < 0)
7668                 goto error;
7669
7670         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7671         if (err < 0)
7672                 goto error;
7673
7674         return 0;
7675
7676  error:
7677         ca0132_free(codec);
7678         return err;
7679 }
7680
7681 /*
7682  * patch entries
7683  */
7684 static struct hda_device_id snd_hda_id_ca0132[] = {
7685         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7686         {} /* terminator */
7687 };
7688 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7689
7690 MODULE_LICENSE("GPL");
7691 MODULE_DESCRIPTION("Creative Sound Core3D codec");
7692
7693 static struct hda_codec_driver ca0132_driver = {
7694         .id = snd_hda_id_ca0132,
7695 };
7696
7697 module_hda_codec_driver(ca0132_driver);