1 /** Filename: Tfa98xx_TfaFieldnames.h
2 * This file was generated automatically on 09/01/15 at 09:40:28.
3 * Source file: TFA9888_N1C_I2C_regmap_V1.xlsx
6 typedef enum nxpTfa2BfEnumList {
7 TFA2_BF_PWDN = 0x0000, /*!< Powerdown selection */
8 TFA2_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
9 TFA2_BF_CFE = 0x0020, /*!< Enable CoolFlux */
10 TFA2_BF_AMPE = 0x0030, /*!< Activate Amplifier */
11 TFA2_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
12 TFA2_BF_SBSL = 0x0050, /*!< Coolflux configured */
13 TFA2_BF_AMPC = 0x0060, /*!< CoolFlux controls amplifier */
14 TFA2_BF_INTP = 0x0071, /*!< Interrupt config */
15 TFA2_BF_FSSSEL = 0x0091, /*!< Audio sample reference */
16 TFA2_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
17 TFA2_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
18 TFA2_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
19 TFA2_BF_MANSCONF = 0x0120, /*!< I2C configured */
20 TFA2_BF_MANCOLD = 0x0130, /*!< Execute cold start */
21 TFA2_BF_MANAOOSC = 0x0140, /*!< Internal osc off at PWDN */
22 TFA2_BF_MANROBOD = 0x0150, /*!< Reaction on BOD */
23 TFA2_BF_BODE = 0x0160, /*!< BOD Enable */
24 TFA2_BF_BODHYS = 0x0170, /*!< BOD Hysteresis */
25 TFA2_BF_BODFILT = 0x0181, /*!< BOD filter */
26 TFA2_BF_BODTHLVL = 0x01a1, /*!< BOD threshold */
27 TFA2_BF_MUTETO = 0x01d0, /*!< Time out SB mute sequence */
28 TFA2_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
29 TFA2_BF_MANWDE = 0x01f0, /*!< Watchdog manager reaction */
30 TFA2_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
31 TFA2_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
32 TFA2_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
33 TFA2_BF_BYPHVBF = 0x02b0, /*!< Bypass HVBAT filter */
34 TFA2_BF_LDOBYP = 0x02c0, /*!< Receiver LDO bypass */
35 TFA2_BF_REV = 0x030f, /*!< Revision info */
36 TFA2_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
37 TFA2_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
38 TFA2_BF_SSLEFTE = 0x0500, /*!< Enable left channel */
39 TFA2_BF_SSRIGHTE = 0x0510, /*!< Enable right channel */
40 TFA2_BF_VSLEFTE = 0x0520, /*!< Voltage sense left */
41 TFA2_BF_VSRIGHTE = 0x0530, /*!< Voltage sense right */
42 TFA2_BF_CSLEFTE = 0x0540, /*!< Current sense left */
43 TFA2_BF_CSRIGHTE = 0x0550, /*!< Current sense right */
44 TFA2_BF_SSPDME = 0x0560, /*!< Sub-system PDM */
45 TFA2_BF_STGAIN = 0x0d18, /*!< Side tone gain */
46 TFA2_BF_PDMSMUTE = 0x0da0, /*!< Side tone soft mute */
47 TFA2_BF_SWVSTEP = 0x0e06, /*!< Register for the host SW to record the current active vstep */
48 TFA2_BF_VDDS = 0x1000, /*!< POR */
49 TFA2_BF_PLLS = 0x1010, /*!< PLL lock */
50 TFA2_BF_OTDS = 0x1020, /*!< OTP alarm */
51 TFA2_BF_OVDS = 0x1030, /*!< OVP alarm */
52 TFA2_BF_UVDS = 0x1040, /*!< UVP alarm */
53 TFA2_BF_CLKS = 0x1050, /*!< Clocks stable */
54 TFA2_BF_MTPB = 0x1060, /*!< MTP busy */
55 TFA2_BF_NOCLK = 0x1070, /*!< Lost clock */
56 TFA2_BF_SPKS = 0x1080, /*!< Speaker error */
57 TFA2_BF_ACS = 0x1090, /*!< Cold Start */
58 TFA2_BF_SWS = 0x10a0, /*!< Amplifier engage */
59 TFA2_BF_WDS = 0x10b0, /*!< Watchdog */
60 TFA2_BF_AMPS = 0x10c0, /*!< Amplifier enable */
61 TFA2_BF_AREFS = 0x10d0, /*!< References enable */
62 TFA2_BF_ADCCR = 0x10e0, /*!< Control ADC */
63 TFA2_BF_BODNOK = 0x10f0, /*!< BOD */
64 TFA2_BF_DCIL = 0x1100, /*!< DCDC current limiting */
65 TFA2_BF_DCDCA = 0x1110, /*!< DCDC active */
66 TFA2_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos */
67 TFA2_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
68 TFA2_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
69 TFA2_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
70 TFA2_BF_STMUTEB = 0x1170, /*!< side tone (un)mute busy */
71 TFA2_BF_STMUTE = 0x1180, /*!< side tone mute state */
72 TFA2_BF_TDMLUTER = 0x1190, /*!< TDM LUT error */
73 TFA2_BF_TDMSTAT = 0x11a2, /*!< TDM status bits */
74 TFA2_BF_TDMERR = 0x11d0, /*!< TDM error */
75 TFA2_BF_HAPTIC = 0x11e0, /*!< Status haptic driver */
76 TFA2_BF_OCPOAPL = 0x1200, /*!< OCPOK pmos A left */
77 TFA2_BF_OCPOANL = 0x1210, /*!< OCPOK nmos A left */
78 TFA2_BF_OCPOBPL = 0x1220, /*!< OCPOK pmos B left */
79 TFA2_BF_OCPOBNL = 0x1230, /*!< OCPOK nmos B left */
80 TFA2_BF_CLIPAHL = 0x1240, /*!< Clipping A left to Vddp */
81 TFA2_BF_CLIPALL = 0x1250, /*!< Clipping A left to gnd */
82 TFA2_BF_CLIPBHL = 0x1260, /*!< Clipping B left to Vddp */
83 TFA2_BF_CLIPBLL = 0x1270, /*!< Clipping B left to gnd */
84 TFA2_BF_OCPOAPRC = 0x1280, /*!< OCPOK pmos A RCV */
85 TFA2_BF_OCPOANRC = 0x1290, /*!< OCPOK nmos A RCV */
86 TFA2_BF_OCPOBPRC = 0x12a0, /*!< OCPOK pmos B RCV */
87 TFA2_BF_OCPOBNRC = 0x12b0, /*!< OCPOK nmos B RCV */
88 TFA2_BF_RCVLDOR = 0x12c0, /*!< RCV LDO regulates */
89 TFA2_BF_RCVLDOBR = 0x12d0, /*!< Receiver LDO ready */
90 TFA2_BF_OCDSL = 0x12e0, /*!< OCP left amplifier */
91 TFA2_BF_CLIPSL = 0x12f0, /*!< Amplifier left clipping */
92 TFA2_BF_OCPOAPR = 0x1300, /*!< OCPOK pmos A right */
93 TFA2_BF_OCPOANR = 0x1310, /*!< OCPOK nmos A right */
94 TFA2_BF_OCPOBPR = 0x1320, /*!< OCPOK pmos B right */
95 TFA2_BF_OCPOBNR = 0x1330, /*!< OCPOK nmos B right */
96 TFA2_BF_CLIPAHR = 0x1340, /*!< Clipping A right to Vddp */
97 TFA2_BF_CLIPALR = 0x1350, /*!< Clipping A right to gnd */
98 TFA2_BF_CLIPBHR = 0x1360, /*!< Clipping B left to Vddp */
99 TFA2_BF_CLIPBLR = 0x1370, /*!< Clipping B right to gnd */
100 TFA2_BF_OCDSR = 0x1380, /*!< OCP right amplifier */
101 TFA2_BF_CLIPSR = 0x1390, /*!< Amplifier right clipping */
102 TFA2_BF_OCPOKMC = 0x13a0, /*!< OCPOK MICVDD */
103 TFA2_BF_MANALARM = 0x13b0, /*!< Alarm state */
104 TFA2_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
105 TFA2_BF_MANWAIT2 = 0x13d0, /*!< Wait CF config */
106 TFA2_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
107 TFA2_BF_MANOPER = 0x13f0, /*!< Operating state */
108 TFA2_BF_SPKSL = 0x1400, /*!< Left speaker status */
109 TFA2_BF_SPKSR = 0x1410, /*!< Right speaker status */
110 TFA2_BF_CLKOOR = 0x1420, /*!< External clock status */
111 TFA2_BF_MANSTATE = 0x1433, /*!< Device manager status */
112 TFA2_BF_BATS = 0x1509, /*!< Battery voltage (V) */
113 TFA2_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
114 TFA2_BF_TDMUC = 0x2003, /*!< Usecase setting */
115 TFA2_BF_TDME = 0x2040, /*!< Enable interface */
116 TFA2_BF_TDMMODE = 0x2050, /*!< Slave/master */
117 TFA2_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
118 TFA2_BF_TDMFSLN = 0x2073, /*!< FS length (master mode only) */
119 TFA2_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
120 TFA2_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
121 TFA2_BF_TDMSLOTS = 0x2103, /*!< N-slots in Frame */
122 TFA2_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
123 TFA2_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
124 TFA2_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
125 TFA2_BF_TDMADJ = 0x21f0, /*!< data adjustment */
126 TFA2_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
127 TFA2_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
128 TFA2_BF_TDMTXDFO = 0x2271, /*!< Format unused bits */
129 TFA2_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots GAINIO */
130 TFA2_BF_TDMTXUS1 = 0x22b1, /*!< Format unused slots DIO1 */
131 TFA2_BF_TDMTXUS2 = 0x22d1, /*!< Format unused slots DIO2 */
132 TFA2_BF_TDMLE = 0x2310, /*!< Control audio left */
133 TFA2_BF_TDMRE = 0x2320, /*!< Control audio right */
134 TFA2_BF_TDMVSRE = 0x2340, /*!< Control voltage sense right */
135 TFA2_BF_TDMCSRE = 0x2350, /*!< Control current sense right */
136 TFA2_BF_TDMVSLE = 0x2360, /*!< Voltage sense left control */
137 TFA2_BF_TDMCSLE = 0x2370, /*!< Current sense left control */
138 TFA2_BF_TDMCFRE = 0x2380, /*!< DSP out right control */
139 TFA2_BF_TDMCFLE = 0x2390, /*!< DSP out left control */
140 TFA2_BF_TDMCF3E = 0x23a0, /*!< AEC ref left control */
141 TFA2_BF_TDMCF4E = 0x23b0, /*!< AEC ref right control */
142 TFA2_BF_TDMPD1E = 0x23c0, /*!< PDM 1 control */
143 TFA2_BF_TDMPD2E = 0x23d0, /*!< PDM 2 control */
144 TFA2_BF_TDMLIO = 0x2421, /*!< IO audio left */
145 TFA2_BF_TDMRIO = 0x2441, /*!< IO audio right */
146 TFA2_BF_TDMVSRIO = 0x2481, /*!< IO voltage sense right */
147 TFA2_BF_TDMCSRIO = 0x24a1, /*!< IO current sense right */
148 TFA2_BF_TDMVSLIO = 0x24c1, /*!< IO voltage sense left */
149 TFA2_BF_TDMCSLIO = 0x24e1, /*!< IO current sense left */
150 TFA2_BF_TDMCFRIO = 0x2501, /*!< IO dspout right */
151 TFA2_BF_TDMCFLIO = 0x2521, /*!< IO dspout left */
152 TFA2_BF_TDMCF3IO = 0x2541, /*!< IO AEC ref left control */
153 TFA2_BF_TDMCF4IO = 0x2561, /*!< IO AEC ref right control */
154 TFA2_BF_TDMPD1IO = 0x2581, /*!< IO pdm1 */
155 TFA2_BF_TDMPD2IO = 0x25a1, /*!< IO pdm2 */
156 TFA2_BF_TDMLS = 0x2643, /*!< Position audio left */
157 TFA2_BF_TDMRS = 0x2683, /*!< Position audio right */
158 TFA2_BF_TDMVSRS = 0x2703, /*!< Position voltage sense right */
159 TFA2_BF_TDMCSRS = 0x2743, /*!< Position current sense right */
160 TFA2_BF_TDMVSLS = 0x2783, /*!< Position voltage sense left */
161 TFA2_BF_TDMCSLS = 0x27c3, /*!< Position current sense left */
162 TFA2_BF_TDMCFRS = 0x2803, /*!< Position dspout right */
163 TFA2_BF_TDMCFLS = 0x2843, /*!< Position dspout left */
164 TFA2_BF_TDMCF3S = 0x2883, /*!< Position AEC ref left control */
165 TFA2_BF_TDMCF4S = 0x28c3, /*!< Position AEC ref right control */
166 TFA2_BF_TDMPD1S = 0x2903, /*!< Position pdm1 */
167 TFA2_BF_TDMPD2S = 0x2943, /*!< Position pdm2 */
168 TFA2_BF_PDMSM = 0x3100, /*!< PDM control */
169 TFA2_BF_PDMSTSEL = 0x3111, /*!< Side tone input */
170 TFA2_BF_PDMLSEL = 0x3130, /*!< PDM data selection for left channel during PDM direct mode */
171 TFA2_BF_PDMRSEL = 0x3140, /*!< PDM data selection for right channel during PDM direct mode */
172 TFA2_BF_MICVDDE = 0x3150, /*!< Enable MICVDD */
173 TFA2_BF_PDMCLRAT = 0x3201, /*!< PDM BCK/Fs ratio */
174 TFA2_BF_PDMGAIN = 0x3223, /*!< PDM gain */
175 TFA2_BF_PDMOSEL = 0x3263, /*!< PDM output selection - RE/FE data combination */
176 TFA2_BF_SELCFHAPD = 0x32a0, /*!< Select the source for haptic data output (not for customer) */
177 TFA2_BF_HAPTIME = 0x3307, /*!< Duration (ms) */
178 TFA2_BF_HAPLEVEL = 0x3387, /*!< DC value (FFS) */
179 TFA2_BF_GPIODIN = 0x3403, /*!< Receiving value */
180 TFA2_BF_GPIOCTRL = 0x3500, /*!< GPIO master control over GPIO1/2 ports (not for customer) */
181 TFA2_BF_GPIOCONF = 0x3513, /*!< Configuration */
182 TFA2_BF_GPIODOUT = 0x3553, /*!< Transmitting value */
183 TFA2_BF_ISTVDDS = 0x4000, /*!< Status POR */
184 TFA2_BF_ISTPLLS = 0x4010, /*!< Status PLL lock */
185 TFA2_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
186 TFA2_BF_ISTOVDS = 0x4030, /*!< Status OVP alarm */
187 TFA2_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
188 TFA2_BF_ISTCLKS = 0x4050, /*!< Status clocks stable */
189 TFA2_BF_ISTMTPB = 0x4060, /*!< Status MTP busy */
190 TFA2_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
191 TFA2_BF_ISTSPKS = 0x4080, /*!< Status speaker error */
192 TFA2_BF_ISTACS = 0x4090, /*!< Status cold start */
193 TFA2_BF_ISTSWS = 0x40a0, /*!< Status amplifier engage */
194 TFA2_BF_ISTWDS = 0x40b0, /*!< Status watchdog */
195 TFA2_BF_ISTAMPS = 0x40c0, /*!< Status amplifier enable */
196 TFA2_BF_ISTAREFS = 0x40d0, /*!< Status Ref enable */
197 TFA2_BF_ISTADCCR = 0x40e0, /*!< Status Control ADC */
198 TFA2_BF_ISTBODNOK = 0x40f0, /*!< Status BOD */
199 TFA2_BF_ISTBSTCU = 0x4100, /*!< Status DCDC current limiting */
200 TFA2_BF_ISTBSTHI = 0x4110, /*!< Status DCDC active */
201 TFA2_BF_ISTBSTOC = 0x4120, /*!< Status DCDC OCP */
202 TFA2_BF_ISTBSTPKCUR = 0x4130, /*!< Status bst peakcur */
203 TFA2_BF_ISTBSTVC = 0x4140, /*!< Status DCDC level 1x */
204 TFA2_BF_ISTBST86 = 0x4150, /*!< Status DCDC level 1.14x */
205 TFA2_BF_ISTBST93 = 0x4160, /*!< Status DCDC level 1.07x */
206 TFA2_BF_ISTRCVLD = 0x4170, /*!< Status rcvldop ready */
207 TFA2_BF_ISTOCPL = 0x4180, /*!< Status ocp alarm left */
208 TFA2_BF_ISTOCPR = 0x4190, /*!< Status ocp alarm right */
209 TFA2_BF_ISTMWSRC = 0x41a0, /*!< Status Waits HW I2C settings */
210 TFA2_BF_ISTMWCFC = 0x41b0, /*!< Status waits CF config */
211 TFA2_BF_ISTMWSMU = 0x41c0, /*!< Status Audio mute sequence */
212 TFA2_BF_ISTCFMER = 0x41d0, /*!< Status cfma error */
213 TFA2_BF_ISTCFMAC = 0x41e0, /*!< Status cfma ack */
214 TFA2_BF_ISTCLKOOR = 0x41f0, /*!< Status flag_clk_out_of_range */
215 TFA2_BF_ISTTDMER = 0x4200, /*!< Status tdm error */
216 TFA2_BF_ISTCLPL = 0x4210, /*!< Status clip left */
217 TFA2_BF_ISTCLPR = 0x4220, /*!< Status clip right */
218 TFA2_BF_ISTOCPM = 0x4230, /*!< Status mic ocpok */
219 TFA2_BF_ICLVDDS = 0x4400, /*!< Clear POR */
220 TFA2_BF_ICLPLLS = 0x4410, /*!< Clear PLL lock */
221 TFA2_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
222 TFA2_BF_ICLOVDS = 0x4430, /*!< Clear OVP alarm */
223 TFA2_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
224 TFA2_BF_ICLCLKS = 0x4450, /*!< Clear clocks stable */
225 TFA2_BF_ICLMTPB = 0x4460, /*!< Clear mtp busy */
226 TFA2_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
227 TFA2_BF_ICLSPKS = 0x4480, /*!< Clear speaker error */
228 TFA2_BF_ICLACS = 0x4490, /*!< Clear cold started */
229 TFA2_BF_ICLSWS = 0x44a0, /*!< Clear amplifier engage */
230 TFA2_BF_ICLWDS = 0x44b0, /*!< Clear watchdog */
231 TFA2_BF_ICLAMPS = 0x44c0, /*!< Clear enbl amp */
232 TFA2_BF_ICLAREFS = 0x44d0, /*!< Clear ref enable */
233 TFA2_BF_ICLADCCR = 0x44e0, /*!< Clear control ADC */
234 TFA2_BF_ICLBODNOK = 0x44f0, /*!< Clear BOD */
235 TFA2_BF_ICLBSTCU = 0x4500, /*!< Clear DCDC current limiting */
236 TFA2_BF_ICLBSTHI = 0x4510, /*!< Clear DCDC active */
237 TFA2_BF_ICLBSTOC = 0x4520, /*!< Clear DCDC OCP */
238 TFA2_BF_ICLBSTPC = 0x4530, /*!< Clear bst peakcur */
239 TFA2_BF_ICLBSTVC = 0x4540, /*!< Clear DCDC level 1x */
240 TFA2_BF_ICLBST86 = 0x4550, /*!< Clear DCDC level 1.14x */
241 TFA2_BF_ICLBST93 = 0x4560, /*!< Clear DCDC level 1.07x */
242 TFA2_BF_ICLRCVLD = 0x4570, /*!< Clear rcvldop ready */
243 TFA2_BF_ICLOCPL = 0x4580, /*!< Clear ocp alarm left */
244 TFA2_BF_ICLOCPR = 0x4590, /*!< Clear ocp alarm right */
245 TFA2_BF_ICLMWSRC = 0x45a0, /*!< Clear wait HW I2C settings */
246 TFA2_BF_ICLMWCFC = 0x45b0, /*!< Clear wait cf config */
247 TFA2_BF_ICLMWSMU = 0x45c0, /*!< Clear audio mute sequence */
248 TFA2_BF_ICLCFMER = 0x45d0, /*!< Clear cfma err */
249 TFA2_BF_ICLCFMAC = 0x45e0, /*!< Clear cfma ack */
250 TFA2_BF_ICLCLKOOR = 0x45f0, /*!< Clear flag_clk_out_of_range */
251 TFA2_BF_ICLTDMER = 0x4600, /*!< Clear tdm error */
252 TFA2_BF_ICLCLPL = 0x4610, /*!< Clear clip left */
253 TFA2_BF_ICLCLPR = 0x4620, /*!< Clear clip right */
254 TFA2_BF_ICLOCPM = 0x4630, /*!< Clear mic ocpok */
255 TFA2_BF_IEVDDS = 0x4800, /*!< Enable por */
256 TFA2_BF_IEPLLS = 0x4810, /*!< Enable pll lock */
257 TFA2_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
258 TFA2_BF_IEOVDS = 0x4830, /*!< Enable OVP alarm */
259 TFA2_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
260 TFA2_BF_IECLKS = 0x4850, /*!< Enable clocks stable */
261 TFA2_BF_IEMTPB = 0x4860, /*!< Enable mtp busy */
262 TFA2_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
263 TFA2_BF_IESPKS = 0x4880, /*!< Enable speaker error */
264 TFA2_BF_IEACS = 0x4890, /*!< Enable cold started */
265 TFA2_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
266 TFA2_BF_IEWDS = 0x48b0, /*!< Enable watchdog */
267 TFA2_BF_IEAMPS = 0x48c0, /*!< Enable enbl amp */
268 TFA2_BF_IEAREFS = 0x48d0, /*!< Enable ref enable */
269 TFA2_BF_IEADCCR = 0x48e0, /*!< Enable Control ADC */
270 TFA2_BF_IEBODNOK = 0x48f0, /*!< Enable BOD */
271 TFA2_BF_IEBSTCU = 0x4900, /*!< Enable DCDC current limiting */
272 TFA2_BF_IEBSTHI = 0x4910, /*!< Enable DCDC active */
273 TFA2_BF_IEBSTOC = 0x4920, /*!< Enable DCDC OCP */
274 TFA2_BF_IEBSTPC = 0x4930, /*!< Enable bst peakcur */
275 TFA2_BF_IEBSTVC = 0x4940, /*!< Enable DCDC level 1x */
276 TFA2_BF_IEBST86 = 0x4950, /*!< Enable DCDC level 1.14x */
277 TFA2_BF_IEBST93 = 0x4960, /*!< Enable DCDC level 1.07x */
278 TFA2_BF_IERCVLD = 0x4970, /*!< Enable rcvldop ready */
279 TFA2_BF_IEOCPL = 0x4980, /*!< Enable ocp alarm left */
280 TFA2_BF_IEOCPR = 0x4990, /*!< Enable ocp alarm right */
281 TFA2_BF_IEMWSRC = 0x49a0, /*!< Enable waits HW I2C settings */
282 TFA2_BF_IEMWCFC = 0x49b0, /*!< Enable man wait cf config */
283 TFA2_BF_IEMWSMU = 0x49c0, /*!< Enable man Audio mute sequence */
284 TFA2_BF_IECFMER = 0x49d0, /*!< Enable cfma err */
285 TFA2_BF_IECFMAC = 0x49e0, /*!< Enable cfma ack */
286 TFA2_BF_IECLKOOR = 0x49f0, /*!< Enable flag_clk_out_of_range */
287 TFA2_BF_IETDMER = 0x4a00, /*!< Enable tdm error */
288 TFA2_BF_IECLPL = 0x4a10, /*!< Enable clip left */
289 TFA2_BF_IECLPR = 0x4a20, /*!< Enable clip right */
290 TFA2_BF_IEOCPM1 = 0x4a30, /*!< Enable mic ocpok */
291 TFA2_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
292 TFA2_BF_IPOPLLS = 0x4c10, /*!< Polarity pll lock */
293 TFA2_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
294 TFA2_BF_IPOOVDS = 0x4c30, /*!< Polarity OVP alarm */
295 TFA2_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
296 TFA2_BF_IPOCLKS = 0x4c50, /*!< Polarity clocks stable */
297 TFA2_BF_IPOMTPB = 0x4c60, /*!< Polarity mtp busy */
298 TFA2_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
299 TFA2_BF_IPOSPKS = 0x4c80, /*!< Polarity speaker error */
300 TFA2_BF_IPOACS = 0x4c90, /*!< Polarity cold started */
301 TFA2_BF_IPOSWS = 0x4ca0, /*!< Polarity amplifier engage */
302 TFA2_BF_IPOWDS = 0x4cb0, /*!< Polarity watchdog */
303 TFA2_BF_IPOAMPS = 0x4cc0, /*!< Polarity enbl amp */
304 TFA2_BF_IPOAREFS = 0x4cd0, /*!< Polarity ref enable */
305 TFA2_BF_IPOADCCR = 0x4ce0, /*!< Polarity Control ADC */
306 TFA2_BF_IPOBODNOK = 0x4cf0, /*!< Polarity BOD */
307 TFA2_BF_IPOBSTCU = 0x4d00, /*!< Polarity DCDC current limiting */
308 TFA2_BF_IPOBSTHI = 0x4d10, /*!< Polarity DCDC active */
309 TFA2_BF_IPOBSTOC = 0x4d20, /*!< Polarity DCDC OCP */
310 TFA2_BF_IPOBSTPC = 0x4d30, /*!< Polarity bst peakcur */
311 TFA2_BF_IPOBSTVC = 0x4d40, /*!< Polarity DCDC level 1x */
312 TFA2_BF_IPOBST86 = 0x4d50, /*!< Polarity DCDC level 1.14x */
313 TFA2_BF_IPOBST93 = 0x4d60, /*!< Polarity DCDC level 1.07x */
314 TFA2_BF_IPORCVLD = 0x4d70, /*!< Polarity rcvldop ready */
315 TFA2_BF_IPOOCPL = 0x4d80, /*!< Polarity ocp alarm left */
316 TFA2_BF_IPOOCPR = 0x4d90, /*!< Polarity ocp alarm right */
317 TFA2_BF_IPOMWSRC = 0x4da0, /*!< Polarity waits HW I2C settings */
318 TFA2_BF_IPOMWCFC = 0x4db0, /*!< Polarity man wait cf config */
319 TFA2_BF_IPOMWSMU = 0x4dc0, /*!< Polarity man audio mute sequence */
320 TFA2_BF_IPOCFMER = 0x4dd0, /*!< Polarity cfma err */
321 TFA2_BF_IPOCFMAC = 0x4de0, /*!< Polarity cfma ack */
322 TFA2_BF_IPCLKOOR = 0x4df0, /*!< Polarity flag_clk_out_of_range */
323 TFA2_BF_IPOTDMER = 0x4e00, /*!< Polarity tdm error */
324 TFA2_BF_IPOCLPL = 0x4e10, /*!< Polarity clip left */
325 TFA2_BF_IPOCLPR = 0x4e20, /*!< Polarity clip right */
326 TFA2_BF_IPOOCPM = 0x4e30, /*!< Polarity mic ocpok */
327 TFA2_BF_BSSCR = 0x5001, /*!< Battery protection attack Time */
328 TFA2_BF_BSST = 0x5023, /*!< Battery protection threshold voltage level */
329 TFA2_BF_BSSRL = 0x5061, /*!< Battery protection maximum reduction */
330 TFA2_BF_BSSRR = 0x5082, /*!< Battery protection release time */
331 TFA2_BF_BSSHY = 0x50b1, /*!< Battery protection hysteresis */
332 TFA2_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
333 TFA2_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
334 TFA2_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
335 TFA2_BF_INTSMUTE = 0x5110, /*!< Soft mute HW */
336 TFA2_BF_CFSML = 0x5120, /*!< Soft mute FW left */
337 TFA2_BF_CFSMR = 0x5130, /*!< Soft mute FW right */
338 TFA2_BF_HPFBYPL = 0x5140, /*!< Bypass HPF left */
339 TFA2_BF_HPFBYPR = 0x5150, /*!< Bypass HPF right */
340 TFA2_BF_DPSAL = 0x5160, /*!< Enable DPSA left */
341 TFA2_BF_DPSAR = 0x5170, /*!< Enable DPSA right */
342 TFA2_BF_VOL = 0x5187, /*!< FW volume control for primary audio channel */
343 TFA2_BF_HNDSFRCV = 0x5200, /*!< Selection receiver */
344 TFA2_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
345 TFA2_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
346 TFA2_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
347 TFA2_BF_SLOPESET = 0x52e1, /*!< Set slope */
348 TFA2_BF_VOLSEC = 0x5a07, /*!< FW volume control for secondary audio channel */
349 TFA2_BF_SWPROFIL = 0x5a87, /*!< Software profile data */
350 TFA2_BF_DCVO = 0x7002, /*!< Boost voltage */
351 TFA2_BF_DCMCC = 0x7033, /*!< Max coil current */
352 TFA2_BF_DCCV = 0x7071, /*!< Coil Value */
353 TFA2_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
354 TFA2_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
355 TFA2_BF_DCSYNCP = 0x70b2, /*!< DCDC synchronization off + 7 positions */
356 TFA2_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
357 TFA2_BF_RST = 0x9000, /*!< Reset */
358 TFA2_BF_DMEM = 0x9011, /*!< Target memory */
359 TFA2_BF_AIF = 0x9030, /*!< Auto increment */
360 TFA2_BF_CFINT = 0x9040, /*!< Interrupt - auto clear */
361 TFA2_BF_CFCGATE = 0x9050, /*!< Coolflux clock gating disabling control */
362 TFA2_BF_REQ = 0x9087, /*!< request for access (8 channels) */
363 TFA2_BF_REQCMD = 0x9080, /*!< Firmware event request rpc command */
364 TFA2_BF_REQRST = 0x9090, /*!< Firmware event request reset restart */
365 TFA2_BF_REQMIPS = 0x90a0, /*!< Firmware event request short on mips */
366 TFA2_BF_REQMUTED = 0x90b0, /*!< Firmware event request mute sequence ready */
367 TFA2_BF_REQVOL = 0x90c0, /*!< Firmware event request volume ready */
368 TFA2_BF_REQDMG = 0x90d0, /*!< Firmware event request speaker damage detected */
369 TFA2_BF_REQCAL = 0x90e0, /*!< Firmware event request calibration completed */
370 TFA2_BF_REQRSV = 0x90f0, /*!< Firmware event request reserved */
371 TFA2_BF_MADD = 0x910f, /*!< Memory address */
372 TFA2_BF_MEMA = 0x920f, /*!< Activate memory access */
373 TFA2_BF_ERR = 0x9307, /*!< Error flags */
374 TFA2_BF_ACK = 0x9387, /*!< Acknowledge of requests */
375 TFA2_BF_ACKCMD = 0x9380, /*!< Firmware event acknowledge rpc command */
376 TFA2_BF_ACKRST = 0x9390, /*!< Firmware event acknowledge reset restart */
377 TFA2_BF_ACKMIPS = 0x93a0, /*!< Firmware event acknowledge short on mips */
378 TFA2_BF_ACKMUTED = 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
379 TFA2_BF_ACKVOL = 0x93c0, /*!< Firmware event acknowledge volume ready */
380 TFA2_BF_ACKDMG = 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
381 TFA2_BF_ACKCAL = 0x93e0, /*!< Firmware event acknowledge calibration completed */
382 TFA2_BF_ACKRSV = 0x93f0, /*!< Firmware event acknowledge reserved */
383 TFA2_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
384 TFA2_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
385 TFA2_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
386 TFA2_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
387 TFA2_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
388 TFA2_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
389 TFA2_BF_EXTTS = 0xb108, /*!< External temperature (C) */
390 TFA2_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
391 TFA2_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
392 TFA2_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
393 TFA2_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
394 TFA2_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
395 TFA2_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
396 TFA2_BF_R25CL = 0xf40f, /*!< Ron resistance of left channel speaker coil */
397 TFA2_BF_R25CR = 0xf50f, /*!< Ron resistance of right channel speaker coil */
398 } nxpTfa2BfEnumList_t;
399 #define TFA2_NAMETABLE static tfaBfName_t Tfa2DatasheetNames[] = {\
400 { 0x0, "PWDN"}, /* Powerdown selection , */\
401 { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
402 { 0x20, "CFE"}, /* Enable CoolFlux , */\
403 { 0x30, "AMPE"}, /* Activate Amplifier , */\
404 { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
405 { 0x50, "SBSL"}, /* Coolflux configured , */\
406 { 0x60, "AMPC"}, /* CoolFlux controls amplifier , */\
407 { 0x71, "INTP"}, /* Interrupt config , */\
408 { 0x91, "FSSSEL"}, /* Audio sample reference , */\
409 { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
410 { 0xc0, "TSTOCP"}, /* OCP testing control , */\
411 { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
412 { 0x120, "MANSCONF"}, /* I2C configured , */\
413 { 0x130, "MANCOLD"}, /* Execute cold start , */\
414 { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
415 { 0x150, "MANROBOD"}, /* Reaction on BOD , */\
416 { 0x160, "BODE"}, /* BOD Enable , */\
417 { 0x170, "BODHYS"}, /* BOD Hysteresis , */\
418 { 0x181, "BODFILT"}, /* BOD filter , */\
419 { 0x1a1, "BODTHLVL"}, /* BOD threshold , */\
420 { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
421 { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
422 { 0x1f0, "MANWDE"}, /* Watchdog manager reaction , */\
423 { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
424 { 0x240, "INPLEV"}, /* TDM output attenuation , */\
425 { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
426 { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
427 { 0x2c0, "LDOBYP"}, /* Receiver LDO bypass , */\
428 { 0x30f, "REV"}, /* Revision info , */\
429 { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
430 { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
431 { 0x500, "SSLEFTE"}, /* Enable left channel , */\
432 { 0x510, "SSRIGHTE"}, /* Enable right channel , */\
433 { 0x520, "VSLEFTE"}, /* Voltage sense left , */\
434 { 0x530, "VSRIGHTE"}, /* Voltage sense right , */\
435 { 0x540, "CSLEFTE"}, /* Current sense left , */\
436 { 0x550, "CSRIGHTE"}, /* Current sense right , */\
437 { 0x560, "SSPDME"}, /* Sub-system PDM , */\
438 { 0xd18, "STGAIN"}, /* Side tone gain , */\
439 { 0xda0, "PDMSMUTE"}, /* Side tone soft mute , */\
440 { 0xe06, "SWVSTEP"}, /* Register for the host SW to record the current active vstep, */\
441 { 0x1000, "VDDS"}, /* POR , */\
442 { 0x1010, "PLLS"}, /* PLL lock , */\
443 { 0x1020, "OTDS"}, /* OTP alarm , */\
444 { 0x1030, "OVDS"}, /* OVP alarm , */\
445 { 0x1040, "UVDS"}, /* UVP alarm , */\
446 { 0x1050, "CLKS"}, /* Clocks stable , */\
447 { 0x1060, "MTPB"}, /* MTP busy , */\
448 { 0x1070, "NOCLK"}, /* Lost clock , */\
449 { 0x1080, "SPKS"}, /* Speaker error , */\
450 { 0x1090, "ACS"}, /* Cold Start , */\
451 { 0x10a0, "SWS"}, /* Amplifier engage , */\
452 { 0x10b0, "WDS"}, /* Watchdog , */\
453 { 0x10c0, "AMPS"}, /* Amplifier enable , */\
454 { 0x10d0, "AREFS"}, /* References enable , */\
455 { 0x10e0, "ADCCR"}, /* Control ADC , */\
456 { 0x10f0, "BODNOK"}, /* BOD , */\
457 { 0x1100, "DCIL"}, /* DCDC current limiting , */\
458 { 0x1110, "DCDCA"}, /* DCDC active , */\
459 { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
460 { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
461 { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
462 { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
463 { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
464 { 0x1180, "STMUTE"}, /* side tone mute state , */\
465 { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
466 { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
467 { 0x11d0, "TDMERR"}, /* TDM error , */\
468 { 0x11e0, "HAPTIC"}, /* Status haptic driver , */\
469 { 0x1200, "OCPOAPL"}, /* OCPOK pmos A left , */\
470 { 0x1210, "OCPOANL"}, /* OCPOK nmos A left , */\
471 { 0x1220, "OCPOBPL"}, /* OCPOK pmos B left , */\
472 { 0x1230, "OCPOBNL"}, /* OCPOK nmos B left , */\
473 { 0x1240, "CLIPAHL"}, /* Clipping A left to Vddp , */\
474 { 0x1250, "CLIPALL"}, /* Clipping A left to gnd , */\
475 { 0x1260, "CLIPBHL"}, /* Clipping B left to Vddp , */\
476 { 0x1270, "CLIPBLL"}, /* Clipping B left to gnd , */\
477 { 0x1280, "OCPOAPRC"}, /* OCPOK pmos A RCV , */\
478 { 0x1290, "OCPOANRC"}, /* OCPOK nmos A RCV , */\
479 { 0x12a0, "OCPOBPRC"}, /* OCPOK pmos B RCV , */\
480 { 0x12b0, "OCPOBNRC"}, /* OCPOK nmos B RCV , */\
481 { 0x12c0, "RCVLDOR"}, /* RCV LDO regulates , */\
482 { 0x12d0, "RCVLDOBR"}, /* Receiver LDO ready , */\
483 { 0x12e0, "OCDSL"}, /* OCP left amplifier , */\
484 { 0x12f0, "CLIPSL"}, /* Amplifier left clipping , */\
485 { 0x1300, "OCPOAPR"}, /* OCPOK pmos A right , */\
486 { 0x1310, "OCPOANR"}, /* OCPOK nmos A right , */\
487 { 0x1320, "OCPOBPR"}, /* OCPOK pmos B right , */\
488 { 0x1330, "OCPOBNR"}, /* OCPOK nmos B right , */\
489 { 0x1340, "CLIPAHR"}, /* Clipping A right to Vddp , */\
490 { 0x1350, "CLIPALR"}, /* Clipping A right to gnd , */\
491 { 0x1360, "CLIPBHR"}, /* Clipping B left to Vddp , */\
492 { 0x1370, "CLIPBLR"}, /* Clipping B right to gnd , */\
493 { 0x1380, "OCDSR"}, /* OCP right amplifier , */\
494 { 0x1390, "CLIPSR"}, /* Amplifier right clipping , */\
495 { 0x13a0, "OCPOKMC"}, /* OCPOK MICVDD , */\
496 { 0x13b0, "MANALARM"}, /* Alarm state , */\
497 { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
498 { 0x13d0, "MANWAIT2"}, /* Wait CF config , */\
499 { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
500 { 0x13f0, "MANOPER"}, /* Operating state , */\
501 { 0x1400, "SPKSL"}, /* Left speaker status , */\
502 { 0x1410, "SPKSR"}, /* Right speaker status , */\
503 { 0x1420, "CLKOOR"}, /* External clock status , */\
504 { 0x1433, "MANSTATE"}, /* Device manager status , */\
505 { 0x1509, "BATS"}, /* Battery voltage (V) , */\
506 { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
507 { 0x2003, "TDMUC"}, /* Usecase setting , */\
508 { 0x2040, "TDME"}, /* Enable interface , */\
509 { 0x2050, "TDMMODE"}, /* Slave/master , */\
510 { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
511 { 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
512 { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
513 { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
514 { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
515 { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
516 { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
517 { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
518 { 0x21f0, "TDMADJ"}, /* data adjustment , */\
519 { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
520 { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
521 { 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
522 { 0x2291, "TDMTXUS0"}, /* Format unused slots GAINIO , */\
523 { 0x22b1, "TDMTXUS1"}, /* Format unused slots DIO1 , */\
524 { 0x22d1, "TDMTXUS2"}, /* Format unused slots DIO2 , */\
525 { 0x2310, "TDMLE"}, /* Control audio left , */\
526 { 0x2320, "TDMRE"}, /* Control audio right , */\
527 { 0x2340, "TDMVSRE"}, /* Control voltage sense right , */\
528 { 0x2350, "TDMCSRE"}, /* Control current sense right , */\
529 { 0x2360, "TDMVSLE"}, /* Voltage sense left control , */\
530 { 0x2370, "TDMCSLE"}, /* Current sense left control , */\
531 { 0x2380, "TDMCFRE"}, /* DSP out right control , */\
532 { 0x2390, "TDMCFLE"}, /* DSP out left control , */\
533 { 0x23a0, "TDMCF3E"}, /* AEC ref left control , */\
534 { 0x23b0, "TDMCF4E"}, /* AEC ref right control , */\
535 { 0x23c0, "TDMPD1E"}, /* PDM 1 control , */\
536 { 0x23d0, "TDMPD2E"}, /* PDM 2 control , */\
537 { 0x2421, "TDMLIO"}, /* IO audio left , */\
538 { 0x2441, "TDMRIO"}, /* IO audio right , */\
539 { 0x2481, "TDMVSRIO"}, /* IO voltage sense right , */\
540 { 0x24a1, "TDMCSRIO"}, /* IO current sense right , */\
541 { 0x24c1, "TDMVSLIO"}, /* IO voltage sense left , */\
542 { 0x24e1, "TDMCSLIO"}, /* IO current sense left , */\
543 { 0x2501, "TDMCFRIO"}, /* IO dspout right , */\
544 { 0x2521, "TDMCFLIO"}, /* IO dspout left , */\
545 { 0x2541, "TDMCF3IO"}, /* IO AEC ref left control , */\
546 { 0x2561, "TDMCF4IO"}, /* IO AEC ref right control , */\
547 { 0x2581, "TDMPD1IO"}, /* IO pdm1 , */\
548 { 0x25a1, "TDMPD2IO"}, /* IO pdm2 , */\
549 { 0x2643, "TDMLS"}, /* Position audio left , */\
550 { 0x2683, "TDMRS"}, /* Position audio right , */\
551 { 0x2703, "TDMVSRS"}, /* Position voltage sense right , */\
552 { 0x2743, "TDMCSRS"}, /* Position current sense right , */\
553 { 0x2783, "TDMVSLS"}, /* Position voltage sense left , */\
554 { 0x27c3, "TDMCSLS"}, /* Position current sense left , */\
555 { 0x2803, "TDMCFRS"}, /* Position dspout right , */\
556 { 0x2843, "TDMCFLS"}, /* Position dspout left , */\
557 { 0x2883, "TDMCF3S"}, /* Position AEC ref left control , */\
558 { 0x28c3, "TDMCF4S"}, /* Position AEC ref right control , */\
559 { 0x2903, "TDMPD1S"}, /* Position pdm1 , */\
560 { 0x2943, "TDMPD2S"}, /* Position pdm2 , */\
561 { 0x3100, "PDMSM"}, /* PDM control , */\
562 { 0x3111, "PDMSTSEL"}, /* Side tone input , */\
563 { 0x3130, "PDMLSEL"}, /* PDM data selection for left channel during PDM direct mode, */\
564 { 0x3140, "PDMRSEL"}, /* PDM data selection for right channel during PDM direct mode, */\
565 { 0x3150, "MICVDDE"}, /* Enable MICVDD , */\
566 { 0x3201, "PDMCLRAT"}, /* PDM BCK/Fs ratio , */\
567 { 0x3223, "PDMGAIN"}, /* PDM gain , */\
568 { 0x3263, "PDMOSEL"}, /* PDM output selection - RE/FE data combination , */\
569 { 0x32a0, "SELCFHAPD"}, /* Select the source for haptic data output (not for customer), */\
570 { 0x3307, "HAPTIME"}, /* Duration (ms) , */\
571 { 0x3387, "HAPLEVEL"}, /* DC value (FFS) , */\
572 { 0x3403, "GPIODIN"}, /* Receiving value , */\
573 { 0x3500, "GPIOCTRL"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
574 { 0x3513, "GPIOCONF"}, /* Configuration , */\
575 { 0x3553, "GPIODOUT"}, /* Transmitting value , */\
576 { 0x4000, "ISTVDDS"}, /* Status POR , */\
577 { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
578 { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
579 { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
580 { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
581 { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
582 { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
583 { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
584 { 0x4080, "ISTSPKS"}, /* Status speaker error , */\
585 { 0x4090, "ISTACS"}, /* Status cold start , */\
586 { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
587 { 0x40b0, "ISTWDS"}, /* Status watchdog , */\
588 { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
589 { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
590 { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
591 { 0x40f0, "ISTBODNOK"}, /* Status BOD , */\
592 { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
593 { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
594 { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
595 { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
596 { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
597 { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
598 { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
599 { 0x4170, "ISTRCVLD"}, /* Status rcvldop ready , */\
600 { 0x4180, "ISTOCPL"}, /* Status ocp alarm left , */\
601 { 0x4190, "ISTOCPR"}, /* Status ocp alarm right , */\
602 { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
603 { 0x41b0, "ISTMWCFC"}, /* Status waits CF config , */\
604 { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
605 { 0x41d0, "ISTCFMER"}, /* Status cfma error , */\
606 { 0x41e0, "ISTCFMAC"}, /* Status cfma ack , */\
607 { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
608 { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
609 { 0x4210, "ISTCLPL"}, /* Status clip left , */\
610 { 0x4220, "ISTCLPR"}, /* Status clip right , */\
611 { 0x4230, "ISTOCPM"}, /* Status mic ocpok , */\
612 { 0x4400, "ICLVDDS"}, /* Clear POR , */\
613 { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
614 { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
615 { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
616 { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
617 { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
618 { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
619 { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
620 { 0x4480, "ICLSPKS"}, /* Clear speaker error , */\
621 { 0x4490, "ICLACS"}, /* Clear cold started , */\
622 { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
623 { 0x44b0, "ICLWDS"}, /* Clear watchdog , */\
624 { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
625 { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
626 { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
627 { 0x44f0, "ICLBODNOK"}, /* Clear BOD , */\
628 { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
629 { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
630 { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
631 { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
632 { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
633 { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
634 { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
635 { 0x4570, "ICLRCVLD"}, /* Clear rcvldop ready , */\
636 { 0x4580, "ICLOCPL"}, /* Clear ocp alarm left , */\
637 { 0x4590, "ICLOCPR"}, /* Clear ocp alarm right , */\
638 { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
639 { 0x45b0, "ICLMWCFC"}, /* Clear wait cf config , */\
640 { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
641 { 0x45d0, "ICLCFMER"}, /* Clear cfma err , */\
642 { 0x45e0, "ICLCFMAC"}, /* Clear cfma ack , */\
643 { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
644 { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
645 { 0x4610, "ICLCLPL"}, /* Clear clip left , */\
646 { 0x4620, "ICLCLPR"}, /* Clear clip right , */\
647 { 0x4630, "ICLOCPM"}, /* Clear mic ocpok , */\
648 { 0x4800, "IEVDDS"}, /* Enable por , */\
649 { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
650 { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
651 { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
652 { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
653 { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
654 { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
655 { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
656 { 0x4880, "IESPKS"}, /* Enable speaker error , */\
657 { 0x4890, "IEACS"}, /* Enable cold started , */\
658 { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
659 { 0x48b0, "IEWDS"}, /* Enable watchdog , */\
660 { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
661 { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
662 { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
663 { 0x48f0, "IEBODNOK"}, /* Enable BOD , */\
664 { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
665 { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
666 { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
667 { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
668 { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
669 { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
670 { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
671 { 0x4970, "IERCVLD"}, /* Enable rcvldop ready , */\
672 { 0x4980, "IEOCPL"}, /* Enable ocp alarm left , */\
673 { 0x4990, "IEOCPR"}, /* Enable ocp alarm right , */\
674 { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
675 { 0x49b0, "IEMWCFC"}, /* Enable man wait cf config , */\
676 { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
677 { 0x49d0, "IECFMER"}, /* Enable cfma err , */\
678 { 0x49e0, "IECFMAC"}, /* Enable cfma ack , */\
679 { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
680 { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
681 { 0x4a10, "IECLPL"}, /* Enable clip left , */\
682 { 0x4a20, "IECLPR"}, /* Enable clip right , */\
683 { 0x4a30, "IEOCPM1"}, /* Enable mic ocpok , */\
684 { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
685 { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
686 { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
687 { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
688 { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
689 { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
690 { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
691 { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
692 { 0x4c80, "IPOSPKS"}, /* Polarity speaker error , */\
693 { 0x4c90, "IPOACS"}, /* Polarity cold started , */\
694 { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
695 { 0x4cb0, "IPOWDS"}, /* Polarity watchdog , */\
696 { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
697 { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
698 { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
699 { 0x4cf0, "IPOBODNOK"}, /* Polarity BOD , */\
700 { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
701 { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
702 { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
703 { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
704 { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
705 { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
706 { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
707 { 0x4d70, "IPORCVLD"}, /* Polarity rcvldop ready , */\
708 { 0x4d80, "IPOOCPL"}, /* Polarity ocp alarm left , */\
709 { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm right , */\
710 { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
711 { 0x4db0, "IPOMWCFC"}, /* Polarity man wait cf config , */\
712 { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
713 { 0x4dd0, "IPOCFMER"}, /* Polarity cfma err , */\
714 { 0x4de0, "IPOCFMAC"}, /* Polarity cfma ack , */\
715 { 0x4df0, "IPCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
716 { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
717 { 0x4e10, "IPOCLPL"}, /* Polarity clip left , */\
718 { 0x4e20, "IPOCLPR"}, /* Polarity clip right , */\
719 { 0x4e30, "IPOOCPM"}, /* Polarity mic ocpok , */\
720 { 0x5001, "BSSCR"}, /* Battery protection attack Time , */\
721 { 0x5023, "BSST"}, /* Battery protection threshold voltage level , */\
722 { 0x5061, "BSSRL"}, /* Battery protection maximum reduction , */\
723 { 0x5082, "BSSRR"}, /* Battery protection release time , */\
724 { 0x50b1, "BSSHY"}, /* Battery protection hysteresis , */\
725 { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
726 { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
727 { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
728 { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
729 { 0x5120, "CFSML"}, /* Soft mute FW left , */\
730 { 0x5130, "CFSMR"}, /* Soft mute FW right , */\
731 { 0x5140, "HPFBYPL"}, /* Bypass HPF left , */\
732 { 0x5150, "HPFBYPR"}, /* Bypass HPF right , */\
733 { 0x5160, "DPSAL"}, /* Enable DPSA left , */\
734 { 0x5170, "DPSAR"}, /* Enable DPSA right , */\
735 { 0x5187, "VOL"}, /* FW volume control for primary audio channel , */\
736 { 0x5200, "HNDSFRCV"}, /* Selection receiver , */\
737 { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
738 { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
739 { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
740 { 0x52e1, "SLOPESET"}, /* Set slope , */\
741 { 0x5a07, "VOLSEC"}, /* FW volume control for secondary audio channel , */\
742 { 0x5a87, "SWPROFIL"}, /* Software profile data , */\
743 { 0x7002, "DCVO"}, /* Boost voltage , */\
744 { 0x7033, "DCMCC"}, /* Max coil current , */\
745 { 0x7071, "DCCV"}, /* Coil Value , */\
746 { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
747 { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
748 { 0x70b2, "DCSYNCP"}, /* DCDC synchronization off + 7 positions , */\
749 { 0x70e0, "DCDIS"}, /* DCDC on/off , */\
750 { 0x9000, "RST"}, /* Reset , */\
751 { 0x9011, "DMEM"}, /* Target memory , */\
752 { 0x9030, "AIF"}, /* Auto increment , */\
753 { 0x9040, "CFINT"}, /* Interrupt - auto clear , */\
754 { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
755 { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
756 { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
757 { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
758 { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
759 { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
760 { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
761 { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
762 { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
763 { 0x910f, "MADD"}, /* Memory address , */\
764 { 0x920f, "MEMA"}, /* Activate memory access , */\
765 { 0x9307, "ERR"}, /* Error flags , */\
766 { 0x9387, "ACK"}, /* Acknowledge of requests , */\
767 { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
768 { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
769 { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
770 { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
771 { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
772 { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
773 { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
774 { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
775 { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
776 { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
777 { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
778 { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
779 { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
780 { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
781 { 0xb108, "EXTTS"}, /* External temperature (C) , */\
782 { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
783 { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
784 { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
785 { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
786 { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
787 { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
788 { 0xf40f, "R25CL"}, /* Ron resistance of left channel speaker coil , */\
789 { 0xf50f, "R25CR"}, /* Ron resistance of right channel speaker coil , */\
790 { 0xffff, "Unknown bitfield enum" } /* not found */\
793 #define TFA2_BITNAMETABLE static tfaBfName_t Tfa2BitNames[] = {\
794 { 0x0, "powerdown"}, /* Powerdown selection , */\
795 { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
796 { 0x20, "enbl_coolflux"}, /* Enable CoolFlux , */\
797 { 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
798 { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
799 { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
800 { 0x60, "sel_enbl_amplifier"}, /* CoolFlux controls amplifier , */\
801 { 0x71, "int_pad_io"}, /* Interrupt config , */\
802 { 0x91, "fs_pulse_sel"}, /* Audio sample reference , */\
803 { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
804 { 0xc0, "test_ocp"}, /* OCP testing control , */\
805 { 0x101, "vamp_sel"}, /* Amplifier input selection , */\
806 { 0x120, "src_set_configured"}, /* I2C configured , */\
807 { 0x130, "execute_cold_start"}, /* Execute cold start , */\
808 { 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
809 { 0x150, "man_enbl_brown_out"}, /* Reaction on BOD , */\
810 { 0x160, "enbl_bod"}, /* BOD Enable , */\
811 { 0x170, "enbl_bod_hyst"}, /* BOD Hysteresis , */\
812 { 0x181, "bod_delay"}, /* BOD filter , */\
813 { 0x1a1, "bod_lvlsel"}, /* BOD threshold , */\
814 { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
815 { 0x1e0, "pwm_sel_rcv_ns"}, /* Noise shaper selection , */\
816 { 0x1f0, "man_enbl_watchdog"}, /* Watchdog manager reaction , */\
817 { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
818 { 0x240, "input_level"}, /* TDM output attenuation , */\
819 { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
820 { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
821 { 0x2c0, "ctrl_rcvldop_bypass"}, /* Receiver LDO bypass , */\
822 { 0x30f, "device_rev"}, /* Revision info , */\
823 { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
824 { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
825 { 0x500, "enbl_spkr_ss_left"}, /* Enable left channel , */\
826 { 0x510, "enbl_spkr_ss_right"}, /* Enable right channel , */\
827 { 0x520, "enbl_volsense_left"}, /* Voltage sense left , */\
828 { 0x530, "enbl_volsense_right"}, /* Voltage sense right , */\
829 { 0x540, "enbl_cursense_left"}, /* Current sense left , */\
830 { 0x550, "enbl_cursense_right"}, /* Current sense right , */\
831 { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
832 { 0xd00, "side_tone_gain_sel"}, /* PDM side tone gain selector , */\
833 { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
834 { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
835 { 0xe06, "ctrl_digtoana"}, /* Register for the host SW to record the current active vstep, */\
836 { 0xe70, "enbl_cmfb_left"}, /* Current sense common mode feedback control for left channel, */\
837 { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
838 { 0x1000, "flag_por"}, /* POR , */\
839 { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
840 { 0x1020, "flag_otpok"}, /* OTP alarm , */\
841 { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
842 { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
843 { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
844 { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
845 { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
846 { 0x1080, "flag_cf_speakererror"}, /* Speaker error , */\
847 { 0x1090, "flag_cold_started"}, /* Cold Start , */\
848 { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
849 { 0x10b0, "flag_watchdog_reset"}, /* Watchdog , */\
850 { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
851 { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
852 { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
853 { 0x10f0, "flag_bod_vddd_nok"}, /* BOD , */\
854 { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
855 { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
856 { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
857 { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
858 { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
859 { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
860 { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
861 { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
862 { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
863 { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
864 { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
865 { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
866 { 0x11e0, "flag_haptic_busy"}, /* Status haptic driver , */\
867 { 0x1200, "flag_ocpokap_left"}, /* OCPOK pmos A left , */\
868 { 0x1210, "flag_ocpokan_left"}, /* OCPOK nmos A left , */\
869 { 0x1220, "flag_ocpokbp_left"}, /* OCPOK pmos B left , */\
870 { 0x1230, "flag_ocpokbn_left"}, /* OCPOK nmos B left , */\
871 { 0x1240, "flag_clipa_high_left"}, /* Clipping A left to Vddp , */\
872 { 0x1250, "flag_clipa_low_left"}, /* Clipping A left to gnd , */\
873 { 0x1260, "flag_clipb_high_left"}, /* Clipping B left to Vddp , */\
874 { 0x1270, "flag_clipb_low_left"}, /* Clipping B left to gnd , */\
875 { 0x1280, "flag_ocpokap_rcv"}, /* OCPOK pmos A RCV , */\
876 { 0x1290, "flag_ocpokan_rcv"}, /* OCPOK nmos A RCV , */\
877 { 0x12a0, "flag_ocpokbp_rcv"}, /* OCPOK pmos B RCV , */\
878 { 0x12b0, "flag_ocpokbn_rcv"}, /* OCPOK nmos B RCV , */\
879 { 0x12c0, "flag_rcvldop_ready"}, /* RCV LDO regulates , */\
880 { 0x12d0, "flag_rcvldop_bypassready"}, /* Receiver LDO ready , */\
881 { 0x12e0, "flag_ocp_alarm_left"}, /* OCP left amplifier , */\
882 { 0x12f0, "flag_clip_left"}, /* Amplifier left clipping , */\
883 { 0x1300, "flag_ocpokap_right"}, /* OCPOK pmos A right , */\
884 { 0x1310, "flag_ocpokan_right"}, /* OCPOK nmos A right , */\
885 { 0x1320, "flag_ocpokbp_right"}, /* OCPOK pmos B right , */\
886 { 0x1330, "flag_ocpokbn_right"}, /* OCPOK nmos B right , */\
887 { 0x1340, "flag_clipa_high_right"}, /* Clipping A right to Vddp , */\
888 { 0x1350, "flag_clipa_low_right"}, /* Clipping A right to gnd , */\
889 { 0x1360, "flag_clipb_high_right"}, /* Clipping B left to Vddp , */\
890 { 0x1370, "flag_clipb_low_right"}, /* Clipping B right to gnd , */\
891 { 0x1380, "flag_ocp_alarm_right"}, /* OCP right amplifier , */\
892 { 0x1390, "flag_clip_right"}, /* Amplifier right clipping , */\
893 { 0x13a0, "flag_mic_ocpok"}, /* OCPOK MICVDD , */\
894 { 0x13b0, "flag_man_alarm_state"}, /* Alarm state , */\
895 { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
896 { 0x13d0, "flag_man_wait_cf_config"}, /* Wait CF config , */\
897 { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
898 { 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
899 { 0x1400, "flag_cf_speakererror_left"}, /* Left speaker status , */\
900 { 0x1410, "flag_cf_speakererror_right"}, /* Right speaker status , */\
901 { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
902 { 0x1433, "man_state"}, /* Device manager status , */\
903 { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
904 { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
905 { 0x2003, "tdm_usecase"}, /* Usecase setting , */\
906 { 0x2040, "tdm_enable"}, /* Enable interface , */\
907 { 0x2050, "tdm_mode"}, /* Slave/master , */\
908 { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
909 { 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
910 { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
911 { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
912 { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
913 { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
914 { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
915 { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
916 { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
917 { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
918 { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
919 { 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
920 { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots GAINIO , */\
921 { 0x22b1, "tdm_txdata_format_unused_slot_sd1"}, /* Format unused slots DIO1 , */\
922 { 0x22d1, "tdm_txdata_format_unused_slot_sd2"}, /* Format unused slots DIO2 , */\
923 { 0x2300, "tdm_sink0_enable"}, /* Control gainin (not used in DSP) , */\
924 { 0x2310, "tdm_sink1_enable"}, /* Control audio left , */\
925 { 0x2320, "tdm_sink2_enable"}, /* Control audio right , */\
926 { 0x2330, "tdm_source0_enable"}, /* Control gainout (not used in DSP) , */\
927 { 0x2340, "tdm_source1_enable"}, /* Control voltage sense right , */\
928 { 0x2350, "tdm_source2_enable"}, /* Control current sense right , */\
929 { 0x2360, "tdm_source3_enable"}, /* Voltage sense left control , */\
930 { 0x2370, "tdm_source4_enable"}, /* Current sense left control , */\
931 { 0x2380, "tdm_source5_enable"}, /* DSP out right control , */\
932 { 0x2390, "tdm_source6_enable"}, /* DSP out left control , */\
933 { 0x23a0, "tdm_source7_enable"}, /* AEC ref left control , */\
934 { 0x23b0, "tdm_source8_enable"}, /* AEC ref right control , */\
935 { 0x23c0, "tdm_source9_enable"}, /* PDM 1 control , */\
936 { 0x23d0, "tdm_source10_enable"}, /* PDM 2 control , */\
937 { 0x2401, "tdm_sink0_io"}, /* IO gainin (not used in DSP) , */\
938 { 0x2421, "tdm_sink1_io"}, /* IO audio left , */\
939 { 0x2441, "tdm_sink2_io"}, /* IO audio right , */\
940 { 0x2461, "tdm_source0_io"}, /* IO gainout (not used in DSP) , */\
941 { 0x2481, "tdm_source1_io"}, /* IO voltage sense right , */\
942 { 0x24a1, "tdm_source2_io"}, /* IO current sense right , */\
943 { 0x24c1, "tdm_source3_io"}, /* IO voltage sense left , */\
944 { 0x24e1, "tdm_source4_io"}, /* IO current sense left , */\
945 { 0x2501, "tdm_source5_io"}, /* IO dspout right , */\
946 { 0x2521, "tdm_source6_io"}, /* IO dspout left , */\
947 { 0x2541, "tdm_source7_io"}, /* IO AEC ref left control , */\
948 { 0x2561, "tdm_source8_io"}, /* IO AEC ref right control , */\
949 { 0x2581, "tdm_source9_io"}, /* IO pdm1 , */\
950 { 0x25a1, "tdm_source10_io"}, /* IO pdm2 , */\
951 { 0x2603, "tdm_sink0_slot"}, /* Position gainin (not used in DSP) , */\
952 { 0x2643, "tdm_sink1_slot"}, /* Position audio left , */\
953 { 0x2683, "tdm_sink2_slot"}, /* Position audio right , */\
954 { 0x26c3, "tdm_source0_slot"}, /* Position gainout (not used in DSP) , */\
955 { 0x2703, "tdm_source1_slot"}, /* Position voltage sense right , */\
956 { 0x2743, "tdm_source2_slot"}, /* Position current sense right , */\
957 { 0x2783, "tdm_source3_slot"}, /* Position voltage sense left , */\
958 { 0x27c3, "tdm_source4_slot"}, /* Position current sense left , */\
959 { 0x2803, "tdm_source5_slot"}, /* Position dspout right , */\
960 { 0x2843, "tdm_source6_slot"}, /* Position dspout left , */\
961 { 0x2883, "tdm_source7_slot"}, /* Position AEC ref left control , */\
962 { 0x28c3, "tdm_source8_slot"}, /* Position AEC ref right control , */\
963 { 0x2903, "tdm_source9_slot"}, /* Position pdm1 , */\
964 { 0x2943, "tdm_source10_slot"}, /* Position pdm2 , */\
965 { 0x3100, "pdm_mode"}, /* PDM control , */\
966 { 0x3111, "pdm_side_tone_sel"}, /* Side tone input , */\
967 { 0x3130, "pdm_left_sel"}, /* PDM data selection for left channel during PDM direct mode, */\
968 { 0x3140, "pdm_right_sel"}, /* PDM data selection for right channel during PDM direct mode, */\
969 { 0x3150, "enbl_micvdd"}, /* Enable MICVDD , */\
970 { 0x3160, "bypass_micvdd_ocp"}, /* Bypass control for the MICVDD OCP flag processing , */\
971 { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
972 { 0x3223, "pdm_gain"}, /* PDM gain , */\
973 { 0x3263, "sel_pdm_out_data"}, /* PDM output selection - RE/FE data combination , */\
974 { 0x32a0, "sel_cf_haptic_data"}, /* Select the source for haptic data output (not for customer), */\
975 { 0x3307, "haptic_duration"}, /* Duration (ms) , */\
976 { 0x3387, "haptic_data"}, /* DC value (FFS) , */\
977 { 0x3403, "gpio_datain"}, /* Receiving value , */\
978 { 0x3500, "gpio_ctrl"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
979 { 0x3513, "gpio_dir"}, /* Configuration , */\
980 { 0x3553, "gpio_dataout"}, /* Transmitting value , */\
981 { 0x4000, "int_out_flag_por"}, /* Status POR , */\
982 { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
983 { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
984 { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
985 { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
986 { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
987 { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
988 { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
989 { 0x4080, "int_out_flag_cf_speakererror"}, /* Status speaker error , */\
990 { 0x4090, "int_out_flag_cold_started"}, /* Status cold start , */\
991 { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
992 { 0x40b0, "int_out_flag_watchdog_reset"}, /* Status watchdog , */\
993 { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
994 { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
995 { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
996 { 0x40f0, "int_out_flag_bod_vddd_nok"}, /* Status BOD , */\
997 { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
998 { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
999 { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
1000 { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
1001 { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
1002 { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
1003 { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
1004 { 0x4170, "int_out_flag_rcvldop_ready"}, /* Status rcvldop ready , */\
1005 { 0x4180, "int_out_flag_ocp_alarm_left"}, /* Status ocp alarm left , */\
1006 { 0x4190, "int_out_flag_ocp_alarm_right"}, /* Status ocp alarm right , */\
1007 { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
1008 { 0x41b0, "int_out_flag_man_wait_cf_config"}, /* Status waits CF config , */\
1009 { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
1010 { 0x41d0, "int_out_flag_cfma_err"}, /* Status cfma error , */\
1011 { 0x41e0, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
1012 { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
1013 { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
1014 { 0x4210, "int_out_flag_clip_left"}, /* Status clip left , */\
1015 { 0x4220, "int_out_flag_clip_right"}, /* Status clip right , */\
1016 { 0x4230, "int_out_flag_mic_ocpok"}, /* Status mic ocpok , */\
1017 { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
1018 { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
1019 { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
1020 { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
1021 { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
1022 { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
1023 { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
1024 { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
1025 { 0x4480, "int_in_flag_cf_speakererror"}, /* Clear speaker error , */\
1026 { 0x4490, "int_in_flag_cold_started"}, /* Clear cold started , */\
1027 { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
1028 { 0x44b0, "int_in_flag_watchdog_reset"}, /* Clear watchdog , */\
1029 { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
1030 { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
1031 { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
1032 { 0x44f0, "int_in_flag_bod_vddd_nok"}, /* Clear BOD , */\
1033 { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
1034 { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
1035 { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
1036 { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
1037 { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
1038 { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
1039 { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
1040 { 0x4570, "int_in_flag_rcvldop_ready"}, /* Clear rcvldop ready , */\
1041 { 0x4580, "int_in_flag_ocp_alarm_left"}, /* Clear ocp alarm left , */\
1042 { 0x4590, "int_in_flag_ocp_alarm_right"}, /* Clear ocp alarm right , */\
1043 { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
1044 { 0x45b0, "int_in_flag_man_wait_cf_config"}, /* Clear wait cf config , */\
1045 { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
1046 { 0x45d0, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
1047 { 0x45e0, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
1048 { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
1049 { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
1050 { 0x4610, "int_in_flag_clip_left"}, /* Clear clip left , */\
1051 { 0x4620, "int_in_flag_clip_right"}, /* Clear clip right , */\
1052 { 0x4630, "int_in_flag_mic_ocpok"}, /* Clear mic ocpok , */\
1053 { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
1054 { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
1055 { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
1056 { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
1057 { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
1058 { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
1059 { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
1060 { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
1061 { 0x4880, "int_enable_flag_cf_speakererror"}, /* Enable speaker error , */\
1062 { 0x4890, "int_enable_flag_cold_started"}, /* Enable cold started , */\
1063 { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
1064 { 0x48b0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog , */\
1065 { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
1066 { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
1067 { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
1068 { 0x48f0, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD , */\
1069 { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
1070 { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
1071 { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
1072 { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
1073 { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
1074 { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
1075 { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
1076 { 0x4970, "int_enable_flag_rcvldop_ready"}, /* Enable rcvldop ready , */\
1077 { 0x4980, "int_enable_flag_ocp_alarm_left"}, /* Enable ocp alarm left , */\
1078 { 0x4990, "int_enable_flag_ocp_alarm_right"}, /* Enable ocp alarm right , */\
1079 { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
1080 { 0x49b0, "int_enable_flag_man_wait_cf_config"}, /* Enable man wait cf config , */\
1081 { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
1082 { 0x49d0, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
1083 { 0x49e0, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
1084 { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
1085 { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
1086 { 0x4a10, "int_enable_flag_clip_left"}, /* Enable clip left , */\
1087 { 0x4a20, "int_enable_flag_clip_right"}, /* Enable clip right , */\
1088 { 0x4a30, "int_enable_flag_mic_ocpok"}, /* Enable mic ocpok , */\
1089 { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
1090 { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
1091 { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
1092 { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
1093 { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
1094 { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
1095 { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
1096 { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
1097 { 0x4c80, "int_polarity_flag_cf_speakererror"}, /* Polarity speaker error , */\
1098 { 0x4c90, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
1099 { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
1100 { 0x4cb0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog , */\
1101 { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
1102 { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
1103 { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
1104 { 0x4cf0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD , */\
1105 { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
1106 { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
1107 { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
1108 { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
1109 { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
1110 { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
1111 { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
1112 { 0x4d70, "int_polarity_flag_rcvldop_ready"}, /* Polarity rcvldop ready , */\
1113 { 0x4d80, "int_polarity_flag_ocp_alarm_left"}, /* Polarity ocp alarm left , */\
1114 { 0x4d90, "int_polarity_flag_ocp_alarm_right"}, /* Polarity ocp alarm right , */\
1115 { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
1116 { 0x4db0, "int_polarity_flag_man_wait_cf_config"}, /* Polarity man wait cf config , */\
1117 { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
1118 { 0x4dd0, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
1119 { 0x4de0, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
1120 { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
1121 { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
1122 { 0x4e10, "int_polarity_flag_clip_left"}, /* Polarity clip left , */\
1123 { 0x4e20, "int_polarity_flag_clip_right"}, /* Polarity clip right , */\
1124 { 0x4e30, "int_polarity_flag_mic_ocpok"}, /* Polarity mic ocpok , */\
1125 { 0x5001, "vbat_prot_attack_time"}, /* Battery protection attack Time , */\
1126 { 0x5023, "vbat_prot_thlevel"}, /* Battery protection threshold voltage level , */\
1127 { 0x5061, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
1128 { 0x5082, "vbat_prot_release_time"}, /* Battery protection release time , */\
1129 { 0x50b1, "vbat_prot_hysterese"}, /* Battery protection hysteresis , */\
1130 { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
1131 { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
1132 { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
1133 { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
1134 { 0x5110, "soft_mute"}, /* Soft mute HW , */\
1135 { 0x5120, "cf_mute_left"}, /* Soft mute FW left , */\
1136 { 0x5130, "cf_mute_right"}, /* Soft mute FW right , */\
1137 { 0x5140, "bypass_hp_left"}, /* Bypass HPF left , */\
1138 { 0x5150, "bypass_hp_right"}, /* Bypass HPF right , */\
1139 { 0x5160, "enbl_dpsa_left"}, /* Enable DPSA left , */\
1140 { 0x5170, "enbl_dpsa_right"}, /* Enable DPSA right , */\
1141 { 0x5187, "cf_volume"}, /* FW volume control for primary audio channel , */\
1142 { 0x5200, "ctrl_rcv"}, /* Selection receiver , */\
1143 { 0x5210, "ctrl_rcv_fb_100k"}, /* Selection of feedback resistor for receiver mode (not for customer), */\
1144 { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
1145 { 0x5257, "gain"}, /* Amplifier gain , */\
1146 { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
1147 { 0x52e1, "ctrl_slope"}, /* Set slope , */\
1148 { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
1149 { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
1150 { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery protection, */\
1151 { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
1152 { 0x5360, "enbl_low_latency"}, /* CF low latency outputs for add module , */\
1153 { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
1154 { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
1155 { 0x5420, "fb_hz"}, /* Feedback resistor set to high ohmic , */\
1156 { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
1157 { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
1158 { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
1159 { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
1160 { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
1161 { 0x5581, "dpsa_drive"}, /* Control of the number of power stage sections, total of 4 sections. Each section is 1/4 of the total power stages., */\
1162 { 0x560a, "enbl_amp_left"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Left channel, */\
1163 { 0x56b0, "enbl_engage_left"}, /* Enables/engage power stage and control loop - left channel, */\
1164 { 0x570a, "enbl_amp_right"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Right channel, */\
1165 { 0x57b0, "enbl_engage_right"}, /* Enables/engage power stage and control loop - right channel, */\
1166 { 0x5800, "hard_mute_left"}, /* Hard mute - PWM module left , */\
1167 { 0x5810, "hard_mute_right"}, /* Hard mute - PWM module right , */\
1168 { 0x5820, "pwm_shape"}, /* PWM shape , */\
1169 { 0x5830, "pwm_bitlength"}, /* PWM bit length in noise shaper , */\
1170 { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
1171 { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
1172 { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
1173 { 0x58b0, "enbl_pwm_phase_shift_left"}, /* Control for pwm phase shift, inverted function - left channel, */\
1174 { 0x58c0, "enbl_pwm_phase_shift_right"}, /* Control for pwm phase shift - right channel , */\
1175 { 0x5900, "ctrl_rcvldop_pulldown"}, /* Pulldown of LDO (2.7V) , */\
1176 { 0x5910, "ctrl_rcvldop_test_comp"}, /* Enable testing of LDO comparator , */\
1177 { 0x5920, "ctrl_rcvldop_test_loadedldo"}, /* Load connected to rcvldo , */\
1178 { 0x5930, "enbl_rcvldop"}, /* Enables the LDO (2.7) , */\
1179 { 0x5a07, "cf_volume_sec"}, /* FW volume control for secondary audio channel , */\
1180 { 0x5a87, "sw_profile"}, /* Software profile data , */\
1181 { 0x7002, "boost_volt"}, /* Boost voltage , */\
1182 { 0x7033, "boost_cur"}, /* Max coil current , */\
1183 { 0x7071, "bst_coil_value"}, /* Coil Value , */\
1184 { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
1185 { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
1186 { 0x70b2, "dcdc_synchronisation"}, /* DCDC synchronization off + 7 positions , */\
1187 { 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
1188 { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
1189 { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
1190 { 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
1191 { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
1192 { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
1193 { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
1194 { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
1195 { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
1196 { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
1197 { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
1198 { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
1199 { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
1200 { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
1201 { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
1202 { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
1203 { 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
1204 { 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
1205 { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
1206 { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
1207 { 0x7332, "bst_freq"}, /* DCDC bost frequency control , */\
1208 { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
1209 { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
1210 { 0x8040, "cs_dc_offset"}, /* Current sense decimator offset control , */\
1211 { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
1212 { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
1213 { 0x8087, "cs_gain"}, /* Current sense gain , */\
1214 { 0x8110, "invertpwm_left"}, /* Current sense common mode feedback pwm invert control for left channel, */\
1215 { 0x8122, "cmfb_gain_left"}, /* Current sense common mode feedback control gain for left channel, */\
1216 { 0x8154, "cmfb_offset_left"}, /* Current sense common mode feedback control offset for left channel, */\
1217 { 0x8200, "enbl_cmfb_right"}, /* Current sense common mode feedback control for right channel, */\
1218 { 0x8210, "invertpwm_right"}, /* Current sense common mode feedback pwm invert control for right channel, */\
1219 { 0x8222, "cmfb_gain_right"}, /* Current sense common mode feedback control gain for right channel, */\
1220 { 0x8254, "cmfb_offset_right"}, /* Current sense common mode feedback control offset for right channel, */\
1221 { 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
1222 { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
1223 { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
1224 { 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
1225 { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
1226 { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
1227 { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
1228 { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
1229 { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
1230 { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
1231 { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
1232 { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
1233 { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
1234 { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
1235 { 0x8600, "enbl_cs_adc_left"}, /* Enable current sense ADC , */\
1236 { 0x8610, "enbl_cs_inn1_left"}, /* Enable connection of current sense negative1 , */\
1237 { 0x8630, "enbl_cs_inp1_left"}, /* Enable connection of current sense positive1 , */\
1238 { 0x8650, "enbl_cs_ldo_left"}, /* Enable current sense LDO , */\
1239 { 0x8660, "enbl_cs_nofloating_n_left"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
1240 { 0x8670, "enbl_cs_nofloating_p_left"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
1241 { 0x8680, "enbl_cs_vbatldo_left"}, /* Enable of current sense LDO , */\
1242 { 0x8700, "enbl_cs_adc_right"}, /* Enable current sense ADC , */\
1243 { 0x8710, "enbl_cs_inn1_right"}, /* Enable connection of current sense negative1 , */\
1244 { 0x8730, "enbl_cs_inp1_right"}, /* Enable connection of current sense positive1 , */\
1245 { 0x8750, "enbl_cs_ldo_right"}, /* Enable current sense LDO , */\
1246 { 0x8760, "enbl_cs_nofloating_n_right"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
1247 { 0x8770, "enbl_cs_nofloating_p_right"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
1248 { 0x8780, "enbl_cs_vbatldo_right"}, /* Enable of current sense LDO , */\
1249 { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
1250 { 0x8810, "volsense_dc_offset"}, /* Voltage sense decimator offset control , */\
1251 { 0x9000, "cf_rst_dsp"}, /* Reset , */\
1252 { 0x9011, "cf_dmem"}, /* Target memory , */\
1253 { 0x9030, "cf_aif"}, /* Auto increment , */\
1254 { 0x9040, "cf_int"}, /* Interrupt - auto clear , */\
1255 { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
1256 { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
1257 { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
1258 { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
1259 { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
1260 { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
1261 { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
1262 { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
1263 { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
1264 { 0x910f, "cf_madd"}, /* Memory address , */\
1265 { 0x920f, "cf_mema"}, /* Activate memory access , */\
1266 { 0x9307, "cf_err"}, /* Error flags , */\
1267 { 0x9387, "cf_ack"}, /* Acknowledge of requests , */\
1268 { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
1269 { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
1270 { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
1271 { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
1272 { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
1273 { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
1274 { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
1275 { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
1276 { 0x980f, "ivt_addr0_msb"}, /* Coolflux interrupt vector table address0 MSB , */\
1277 { 0x990f, "ivt_addr0_lsb"}, /* Coolflux interrupt vector table address0 LSB , */\
1278 { 0x9a0f, "ivt_addr1_msb"}, /* Coolflux interrupt vector table address1 MSB , */\
1279 { 0x9b0f, "ivt_addr1_lsb"}, /* Coolflux interrupt vector table address1 LSB , */\
1280 { 0x9c0f, "ivt_addr2_msb"}, /* Coolflux interrupt vector table address2 MSB , */\
1281 { 0x9d0f, "ivt_addr2_lsb"}, /* Coolflux interrupt vector table address2 LSB , */\
1282 { 0x9e0f, "ivt_addr3_msb"}, /* Coolflux interrupt vector table address3 MSB , */\
1283 { 0x9f0f, "ivt_addr3_lsb"}, /* Coolflux interrupt vector table address3 LSB , */\
1284 { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
1285 { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
1286 { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
1287 { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
1288 { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
1289 { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
1290 { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
1291 { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
1292 { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
1293 { 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
1294 { 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
1295 { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
1296 { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
1297 { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
1298 { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
1299 { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
1300 { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
1301 { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
1302 { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
1303 { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
1304 { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
1305 { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
1306 { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
1307 { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
1308 { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
1309 { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
1310 { 0xb108, "ext_temp"}, /* External temperature (C) , */\
1311 { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
1312 { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
1313 { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
1314 { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
1315 { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
1316 { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
1317 { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
1318 { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
1319 { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
1320 { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
1321 { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
1322 { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
1323 { 0xc300, "bypasslatch"}, /* Bypass latch , */\
1324 { 0xc311, "sourcea"}, /* Set OUTA to , */\
1325 { 0xc331, "sourceb"}, /* Set OUTB to , */\
1326 { 0xc350, "inverta"}, /* Invert pwma test signal , */\
1327 { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
1328 { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
1329 { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
1330 { 0xc3d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
1331 { 0xc3e0, "test_pwr_switch"}, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */\
1332 { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
1333 { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
1334 { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
1335 { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
1336 { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
1337 { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
1338 { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
1339 { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
1340 { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
1341 { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
1342 { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
1343 { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
1344 { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
1345 { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
1346 { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
1347 { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
1348 { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
1349 { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
1350 { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
1351 { 0xc660, "bypass_diosw_ovp"}, /* Bypass ovp for memory switch diosw , */\
1352 { 0xc670, "enbl_powerswitch"}, /* Vddd core power switch control - overrules the manager control, */\
1353 { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to GPIO1 (see Digimux list for details), */\
1354 { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to GPIO2 (see Digimux list for details), */\
1355 { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to GPIO3 (see Digimux list for details), */\
1356 { 0xc887, "digimuxd_sel"}, /* DigimuxD input selection control routed to GPIO4 (see Digimux list for details), */\
1357 { 0xc901, "dio1_ehs"}, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1358 { 0xc921, "dio2_ehs"}, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1359 { 0xc941, "gainio_ehs"}, /* Speed/load setting for GAINIO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1360 { 0xc961, "pdmo_ehs"}, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1361 { 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1362 { 0xc9a1, "tdo_ehs"}, /* Speed/load setting for TDO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
1363 { 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
1364 { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
1365 { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
1366 { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
1367 { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
1368 { 0xca40, "enbl_anamux5"}, /* Enable anamux5 , */\
1369 { 0xca50, "enbl_anamux6"}, /* Enable anamux6 , */\
1370 { 0xca60, "enbl_anamux7"}, /* Enable anamux7 , */\
1371 { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
1372 { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
1373 { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
1374 { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
1375 { 0xcc04, "anamux5"}, /* Anamux selection control - anamux on TEST5 , */\
1376 { 0xcc54, "anamux6"}, /* Anamux selection control - anamux on TEST6 , */\
1377 { 0xcca4, "anamux7"}, /* Anamux selection control - anamux on TEST7 , */\
1378 { 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
1379 { 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
1380 { 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
1381 { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
1382 { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
1383 { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
1384 { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
1385 { 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
1386 { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
1387 { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
1388 { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
1389 { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
1390 { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
1391 { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
1392 { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
1393 { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
1394 { 0xd243, "tsig_gain_left"}, /* Test signal gain for left channel , */\
1395 { 0xd283, "tsig_gain_right"}, /* Test signal gain for right channel , */\
1396 { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
1397 { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
1398 { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
1399 { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
1400 { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
1401 { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
1402 { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
1403 { 0xd506, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
1404 { 0xd570, "enbl_clk_out_of_range"}, /* Clock out of range , */\
1405 { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
1406 { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
1407 { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
1408 { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
1409 { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
1410 { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
1411 { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
1412 { 0xf163, "calibr_gain_left"}, /* HW gain module - left channel (2's complement) , */\
1413 { 0xf1a5, "calibr_offset_left"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
1414 { 0xf203, "calibr_gain_right"}, /* HW gain module - right channel (2's complement) , */\
1415 { 0xf245, "calibr_offset_right"}, /* Offset for amplifier, HW gain module - right channel (2's complement), */\
1416 { 0xf2a3, "calibr_rcvldop_trim"}, /* Trimming of LDO (2.7V) , */\
1417 { 0xf307, "calibr_gain_cs_left"}, /* Current sense gain - left channel (signed two's complement format), */\
1418 { 0xf387, "calibr_gain_cs_right"}, /* Current sense gain - right channel (signed two's complement format), */\
1419 { 0xf40f, "calibr_R25C_L"}, /* Ron resistance of left channel speaker coil , */\
1420 { 0xf50f, "calibr_R25C_R"}, /* Ron resistance of right channel speaker coil , */\
1421 { 0xf606, "ctrl_offset_a_left"}, /* Offset of left amplifier level shifter A , */\
1422 { 0xf686, "ctrl_offset_b_left"}, /* Offset of left amplifier level shifter B , */\
1423 { 0xf706, "ctrl_offset_a_right"}, /* Offset of right amplifier level shifter A , */\
1424 { 0xf786, "ctrl_offset_b_right"}, /* Offset of right amplifier level shifter B , */\
1425 { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
1426 { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
1427 { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
1428 { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
1429 { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
1430 { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable function enbl_coolflux , */\
1431 { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
1432 { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
1433 { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
1434 { 0xf987, "type_bits_fw"}, /* MTP-control FW - See Firmware I2C API document for details, */\
1435 { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
1436 { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
1437 { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
1438 { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
1439 { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
1440 { 0xff05, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
1441 { 0xffff, "Unknown bitfield enum" } /* not found */\
1445 tfa2_irq_stvdds = 0,
1446 tfa2_irq_stplls = 1,
1447 tfa2_irq_stotds = 2,
1448 tfa2_irq_stovds = 3,
1449 tfa2_irq_stuvds = 4,
1450 tfa2_irq_stclks = 5,
1451 tfa2_irq_stmtpb = 6,
1452 tfa2_irq_stnoclk = 7,
1453 tfa2_irq_stspks = 8,
1455 tfa2_irq_stsws = 10,
1456 tfa2_irq_stwds = 11,
1457 tfa2_irq_stamps = 12,
1458 tfa2_irq_starefs = 13,
1459 tfa2_irq_stadccr = 14,
1460 tfa2_irq_stbodnok = 15,
1461 tfa2_irq_stbstcu = 16,
1462 tfa2_irq_stbsthi = 17,
1463 tfa2_irq_stbstoc = 18,
1464 tfa2_irq_stbstpkcur = 19,
1465 tfa2_irq_stbstvc = 20,
1466 tfa2_irq_stbst86 = 21,
1467 tfa2_irq_stbst93 = 22,
1468 tfa2_irq_strcvld = 23,
1469 tfa2_irq_stocpl = 24,
1470 tfa2_irq_stocpr = 25,
1471 tfa2_irq_stmwsrc = 26,
1472 tfa2_irq_stmwcfc = 27,
1473 tfa2_irq_stmwsmu = 28,
1474 tfa2_irq_stcfmer = 29,
1475 tfa2_irq_stcfmac = 30,
1476 tfa2_irq_stclkoor = 31,
1477 tfa2_irq_sttdmer = 32,
1478 tfa2_irq_stclpl = 33,
1479 tfa2_irq_stclpr = 34,
1480 tfa2_irq_stocpm = 35,
1482 tfa2_irq_all = -1 /* all irqs */};
1484 #define TFA2_IRQ_NAMETABLE static tfaIrqName_t Tfa2IrqNames[] = {\
1504 { 19, "STBSTPKCUR"},\
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