sound/soc/codecs/wcd9335.c

   1 /*
   2  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/firmware.h>
  16 #include <linux/slab.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/device.h>
  19 #include <linux/printk.h>
  20 #include <linux/ratelimit.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/wait.h>
  23 #include <linux/bitops.h>
  24 #include <linux/regmap.h>
  25 #include <linux/mfd/wcd9xxx/core.h>
  26 #include <linux/mfd/wcd9xxx/wcd9xxx-irq.h>
  27 #include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
  28 #include <linux/mfd/wcd9335/registers.h>
  29 #include <linux/mfd/wcd9xxx/pdata.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/clk.h>
  32 #include <linux/delay.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/kernel.h>
  35 #include <linux/gpio.h>
  36 #include <linux/soundwire/swr-wcd.h>
  37 #include <sound/pcm.h>
  38 #include <sound/pcm_params.h>
  39 #include <sound/soc.h>
  40 #include <sound/soc-dapm.h>
  41 #include <sound/tlv.h>
  42 #include <sound/info.h>
  43 #include "wcd9335.h"
  44 #include "wcd-mbhc-v2.h"
  45 #include "wcd9xxx-common-v2.h"
  46 #include "wcd9xxx-resmgr-v2.h"
  47 #include "wcd_cpe_core.h"
  48 #include "wcdcal-hwdep.h"
  49
  50 #define TASHA_RX_PORT_START_NUMBER  16
  51
  52 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  53                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  54                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  55 /* Fractional Rates */
  56 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
  57
  58 #define WCD9335_MIX_RATES_MASK (SNDRV_PCM_RATE_48000 |\
  59                                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  60
  61 #define TASHA_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  62                                   SNDRV_PCM_FMTBIT_S24_LE | \
  63                                   SNDRV_PCM_FMTBIT_S24_3LE)
  64
  65 #define TASHA_FORMATS_S16_S24_S32_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  66                                   SNDRV_PCM_FMTBIT_S24_LE | \
  67                                   SNDRV_PCM_FMTBIT_S24_3LE | \
  68                                   SNDRV_PCM_FMTBIT_S32_LE)
  69
  70 #define TASHA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
  71
  72 /*
  73  * Timeout in milli seconds and it is the wait time for
  74  * slim channel removal interrupt to receive.
  75  */
  76 #define TASHA_SLIM_CLOSE_TIMEOUT 1000
  77 #define TASHA_SLIM_IRQ_OVERFLOW (1 << 0)
  78 #define TASHA_SLIM_IRQ_UNDERFLOW (1 << 1)
  79 #define TASHA_SLIM_IRQ_PORT_CLOSED (1 << 2)
  80 #define TASHA_MCLK_CLK_12P288MHZ 12288000
  81 #define TASHA_MCLK_CLK_9P6MHZ 9600000
  82
  83 #define TASHA_SLIM_PGD_PORT_INT_TX_EN0 (TASHA_SLIM_PGD_PORT_INT_EN0 + 2)
  84
  85 #define TASHA_NUM_INTERPOLATORS 9
  86 #define TASHA_NUM_DECIMATORS 9
  87
  88 #define BYTE_BIT_MASK(nr) (1 << ((nr) % BITS_PER_BYTE))
  89 #define TASHA_MAD_AUDIO_FIRMWARE_PATH "wcd9335/wcd9335_mad_audio.bin"
  90 #define TASHA_CPE_SS_ERR_STATUS_MEM_ACCESS (1 << 0)
  91 #define TASHA_CPE_SS_ERR_STATUS_WDOG_BITE (1 << 1)
  92
  93 #define TASHA_CPE_FATAL_IRQS \
  94         (TASHA_CPE_SS_ERR_STATUS_WDOG_BITE | \
  95          TASHA_CPE_SS_ERR_STATUS_MEM_ACCESS)
  96
  97 #define SLIM_BW_CLK_GEAR_9 6200000
  98 #define SLIM_BW_UNVOTE 0
  99
 100 #define CPE_FLL_CLK_75MHZ 75000000
 101 #define CPE_FLL_CLK_150MHZ 150000000
 102 #define WCD9335_REG_BITS 8
 103
 104 #define WCD9335_MAX_VALID_ADC_MUX  13
 105 #define WCD9335_INVALID_ADC_MUX 9
 106
 107 #define TASHA_DIG_CORE_REG_MIN  WCD9335_CDC_ANC0_CLK_RESET_CTL
 108 #define TASHA_DIG_CORE_REG_MAX  0xDFF
 109
 110 /* Convert from vout ctl to micbias voltage in mV */
 111 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
 112
 113 #define TASHA_ZDET_NUM_MEASUREMENTS 150
 114 #define TASHA_MBHC_GET_C1(c)  ((c & 0xC000) >> 14)
 115 #define TASHA_MBHC_GET_X1(x)  (x & 0x3FFF)
 116 /* z value compared in milliOhm */
 117 #define TASHA_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
 118 #define TASHA_MBHC_ZDET_CONST  (86 * 16384)
 119 #define TASHA_MBHC_MOISTURE_VREF  V_45_MV
 120 #define TASHA_MBHC_MOISTURE_IREF  I_3P0_UA
 121
 122 #define TASHA_VERSION_ENTRY_SIZE 17
 123
 124 #define WCD9335_AMIC_PWR_LEVEL_LP 0
 125 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
 126 #define WCD9335_AMIC_PWR_LEVEL_HP 2
 127 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
 128 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
 129
 130 #define WCD9335_DEC_PWR_LVL_MASK 0x06
 131 #define WCD9335_DEC_PWR_LVL_LP 0x02
 132 #define WCD9335_DEC_PWR_LVL_HP 0x04
 133 #define WCD9335_DEC_PWR_LVL_DF 0x00
 134 #define WCD9335_STRING_LEN 100
 135
 136 #define CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
 137
 138 static int cpe_debug_mode;
 139
 140 #define TASHA_MAX_MICBIAS 4
 141 #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
 142 #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
 143 #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
 144 #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
 145
 146 #define DAPM_LDO_H_STANDALONE "LDO_H"
 147 module_param(cpe_debug_mode, int,
 148              S_IRUGO | S_IWUSR | S_IWGRP);
 149 MODULE_PARM_DESC(cpe_debug_mode, "boot cpe in debug mode");
 150
 151 #define TASHA_DIG_CORE_COLLAPSE_TIMER_MS  (5 * 1000)
 152
 153 #define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH    64
 154
 155 static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = {
 156         "cdc-vdd-mic-bias",
 157 };
 158
 159 enum {
 160         POWER_COLLAPSE,
 161         POWER_RESUME,
 162 };
 163
 164 enum tasha_sido_voltage {
 165         SIDO_VOLTAGE_SVS_MV = 950,
 166         SIDO_VOLTAGE_NOMINAL_MV = 1100,
 167 };
 168
 169 static enum codec_variant codec_ver;
 170
 171 static int dig_core_collapse_enable = 1;
 172 module_param(dig_core_collapse_enable, int,
 173                 S_IRUGO | S_IWUSR | S_IWGRP);
 174 MODULE_PARM_DESC(dig_core_collapse_enable, "enable/disable power gating");
 175
 176 /* dig_core_collapse timer in seconds */
 177 static int dig_core_collapse_timer = (TASHA_DIG_CORE_COLLAPSE_TIMER_MS/1000);
 178 module_param(dig_core_collapse_timer, int,
 179                 S_IRUGO | S_IWUSR | S_IWGRP);
 180 MODULE_PARM_DESC(dig_core_collapse_timer, "timer for power gating");
 181
 182 /* SVS Scaling enable/disable */
 183 static int svs_scaling_enabled = 1;
 184 module_param(svs_scaling_enabled, int,
 185                 S_IRUGO | S_IWUSR | S_IWGRP);
 186 MODULE_PARM_DESC(svs_scaling_enabled, "enable/disable svs scaling");
 187
 188 /* SVS buck setting */
 189 static int sido_buck_svs_voltage = SIDO_VOLTAGE_SVS_MV;
 190 module_param(sido_buck_svs_voltage, int,
 191                 S_IRUGO | S_IWUSR | S_IWGRP);
 192 MODULE_PARM_DESC(sido_buck_svs_voltage,
 193                         "setting for SVS voltage for SIDO BUCK");
 194
 195 #define TASHA_TX_UNMUTE_DELAY_MS        40
 196
 197 static int tx_unmute_delay = TASHA_TX_UNMUTE_DELAY_MS;
 198 module_param(tx_unmute_delay, int,
 199                 S_IRUGO | S_IWUSR | S_IWGRP);
 200 MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path");
 201
 202 static struct afe_param_slimbus_slave_port_cfg tasha_slimbus_slave_port_cfg = {
 203         .minor_version = 1,
 204         .slimbus_dev_id = AFE_SLIMBUS_DEVICE_1,
 205         .slave_dev_pgd_la = 0,
 206         .slave_dev_intfdev_la = 0,
 207         .bit_width = 16,
 208         .data_format = 0,
 209         .num_channels = 1
 210 };
 211
 212 struct tasha_mbhc_zdet_param {
 213         u16 ldo_ctl;
 214         u16 noff;
 215         u16 nshift;
 216         u16 btn5;
 217         u16 btn6;
 218         u16 btn7;
 219 };
 220
 221 static struct afe_param_cdc_reg_page_cfg tasha_cdc_reg_page_cfg = {
 222         .minor_version = AFE_API_VERSION_CDC_REG_PAGE_CFG,
 223         .enable = 1,
 224         .proc_id = AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_1,
 225 };
 226
 227 static struct afe_param_cdc_reg_cfg audio_reg_cfg[] = {
 228         {
 229                 1,
 230                 (TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_MAIN_CTL_1),
 231                 HW_MAD_AUDIO_ENABLE, 0x1, WCD9335_REG_BITS, 0
 232         },
 233         {
 234                 1,
 235                 (TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_AUDIO_CTL_3),
 236                 HW_MAD_AUDIO_SLEEP_TIME, 0xF, WCD9335_REG_BITS, 0
 237         },
 238         {
 239                 1,
 240                 (TASHA_REGISTER_START_OFFSET + WCD9335_SOC_MAD_AUDIO_CTL_4),
 241                 HW_MAD_TX_AUDIO_SWITCH_OFF, 0x1, WCD9335_REG_BITS, 0
 242         },
 243         {
 244                 1,
 245                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_CFG),
 246                 MAD_AUDIO_INT_DEST_SELECT_REG, 0x2, WCD9335_REG_BITS, 0
 247         },
 248         {
 249                 1,
 250                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_MASK3),
 251                 MAD_AUDIO_INT_MASK_REG, 0x1, WCD9335_REG_BITS, 0
 252         },
 253         {
 254                 1,
 255                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_STATUS3),
 256                 MAD_AUDIO_INT_STATUS_REG, 0x1, WCD9335_REG_BITS, 0
 257         },
 258         {
 259                 1,
 260                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_CLEAR3),
 261                 MAD_AUDIO_INT_CLEAR_REG, 0x1, WCD9335_REG_BITS, 0
 262         },
 263         {
 264                 1,
 265                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_CFG),
 266                 VBAT_INT_DEST_SELECT_REG, 0x2, WCD9335_REG_BITS, 0
 267         },
 268         {
 269                 1,
 270                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_MASK3),
 271                 VBAT_INT_MASK_REG, 0x08, WCD9335_REG_BITS, 0
 272         },
 273         {
 274                 1,
 275                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_STATUS3),
 276                 VBAT_INT_STATUS_REG, 0x08, WCD9335_REG_BITS, 0
 277         },
 278         {
 279                 1,
 280                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_CLEAR3),
 281                 VBAT_INT_CLEAR_REG, 0x08, WCD9335_REG_BITS, 0
 282         },
 283         {
 284                 1,
 285                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_CFG),
 286                 VBAT_RELEASE_INT_DEST_SELECT_REG, 0x2, WCD9335_REG_BITS, 0
 287         },
 288         {
 289                 1,
 290                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_MASK3),
 291                 VBAT_RELEASE_INT_MASK_REG, 0x10, WCD9335_REG_BITS, 0
 292         },
 293         {
 294                 1,
 295                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_STATUS3),
 296                 VBAT_RELEASE_INT_STATUS_REG, 0x10, WCD9335_REG_BITS, 0
 297         },
 298         {
 299                 1,
 300                 (TASHA_REGISTER_START_OFFSET + WCD9335_INTR_PIN2_CLEAR3),
 301                 VBAT_RELEASE_INT_CLEAR_REG, 0x10, WCD9335_REG_BITS, 0
 302         },
 303         {
 304                 1,
 305                 (TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_TX_BASE),
 306                 SB_PGD_PORT_TX_WATERMARK_N, 0x1E, WCD9335_REG_BITS, 0x1
 307         },
 308         {
 309                 1,
 310                 (TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_TX_BASE),
 311                 SB_PGD_PORT_TX_ENABLE_N, 0x1, WCD9335_REG_BITS, 0x1
 312         },
 313         {
 314                 1,
 315                 (TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_RX_BASE),
 316                 SB_PGD_PORT_RX_WATERMARK_N, 0x1E, WCD9335_REG_BITS, 0x1
 317         },
 318         {
 319                 1,
 320                 (TASHA_REGISTER_START_OFFSET + TASHA_SB_PGD_PORT_RX_BASE),
 321                 SB_PGD_PORT_RX_ENABLE_N, 0x1, WCD9335_REG_BITS, 0x1
 322         },
 323         {       1,
 324                 (TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_IIR_ADAPT_CTL),
 325                 AANC_FF_GAIN_ADAPTIVE, 0x4, WCD9335_REG_BITS, 0
 326         },
 327         {       1,
 328                 (TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_IIR_ADAPT_CTL),
 329                 AANC_FFGAIN_ADAPTIVE_EN, 0x8, WCD9335_REG_BITS, 0
 330         },
 331         {
 332                 1,
 333                 (TASHA_REGISTER_START_OFFSET + WCD9335_CDC_ANC0_FF_A_GAIN_CTL),
 334                 AANC_GAIN_CONTROL, 0xFF, WCD9335_REG_BITS, 0
 335         },
 336 };
 337
 338 static struct afe_param_cdc_reg_cfg_data tasha_audio_reg_cfg = {
 339         .num_registers = ARRAY_SIZE(audio_reg_cfg),
 340         .reg_data = audio_reg_cfg,
 341 };
 342
 343 static struct afe_param_id_cdc_aanc_version tasha_cdc_aanc_version = {
 344         .cdc_aanc_minor_version = AFE_API_VERSION_CDC_AANC_VERSION,
 345         .aanc_hw_version        = AANC_HW_BLOCK_VERSION_2,
 346 };
 347
 348 enum {
 349         VI_SENSE_1,
 350         VI_SENSE_2,
 351         AIF4_SWITCH_VALUE,
 352         AUDIO_NOMINAL,
 353         CPE_NOMINAL,
 354         HPH_PA_DELAY,
 355         ANC_MIC_AMIC1,
 356         ANC_MIC_AMIC2,
 357         ANC_MIC_AMIC3,
 358         ANC_MIC_AMIC4,
 359         ANC_MIC_AMIC5,
 360         ANC_MIC_AMIC6,
 361         CLASSH_CONFIG,
 362 };
 363
 364 enum {
 365         AIF1_PB = 0,
 366         AIF1_CAP,
 367         AIF2_PB,
 368         AIF2_CAP,
 369         AIF3_PB,
 370         AIF3_CAP,
 371         AIF4_PB,
 372         AIF_MIX1_PB,
 373         AIF4_MAD_TX,
 374         AIF4_VIFEED,
 375         AIF5_CPE_TX,
 376         NUM_CODEC_DAIS,
 377 };
 378
 379 enum {
 380         INTn_1_MIX_INP_SEL_ZERO = 0,
 381         INTn_1_MIX_INP_SEL_DEC0,
 382         INTn_1_MIX_INP_SEL_DEC1,
 383         INTn_1_MIX_INP_SEL_IIR0,
 384         INTn_1_MIX_INP_SEL_IIR1,
 385         INTn_1_MIX_INP_SEL_RX0,
 386         INTn_1_MIX_INP_SEL_RX1,
 387         INTn_1_MIX_INP_SEL_RX2,
 388         INTn_1_MIX_INP_SEL_RX3,
 389         INTn_1_MIX_INP_SEL_RX4,
 390         INTn_1_MIX_INP_SEL_RX5,
 391         INTn_1_MIX_INP_SEL_RX6,
 392         INTn_1_MIX_INP_SEL_RX7,
 393
 394 };
 395
 396 #define IS_VALID_NATIVE_FIFO_PORT(inp) \
 397         ((inp >= INTn_1_MIX_INP_SEL_RX0) && \
 398          (inp <= INTn_1_MIX_INP_SEL_RX3))
 399
 400 enum {
 401         INTn_2_INP_SEL_ZERO = 0,
 402         INTn_2_INP_SEL_RX0,
 403         INTn_2_INP_SEL_RX1,
 404         INTn_2_INP_SEL_RX2,
 405         INTn_2_INP_SEL_RX3,
 406         INTn_2_INP_SEL_RX4,
 407         INTn_2_INP_SEL_RX5,
 408         INTn_2_INP_SEL_RX6,
 409         INTn_2_INP_SEL_RX7,
 410         INTn_2_INP_SEL_PROXIMITY,
 411 };
 412
 413 enum {
 414         INTERP_EAR = 0,
 415         INTERP_HPHL,
 416         INTERP_HPHR,
 417         INTERP_LO1,
 418         INTERP_LO2,
 419         INTERP_LO3,
 420         INTERP_LO4,
 421         INTERP_SPKR1,
 422         INTERP_SPKR2,
 423 };
 424
 425 struct interp_sample_rate {
 426         int sample_rate;
 427         int rate_val;
 428 };
 429
 430 static struct interp_sample_rate int_prim_sample_rate_val[] = {
 431         {8000, 0x0},    /* 8K */
 432         {16000, 0x1},   /* 16K */
 433         {24000, -EINVAL},/* 24K */
 434         {32000, 0x3},   /* 32K */
 435         {48000, 0x4},   /* 48K */
 436         {96000, 0x5},   /* 96K */
 437         {192000, 0x6},  /* 192K */
 438         {384000, 0x7},  /* 384K */
 439         {44100, 0x8}, /* 44.1K */
 440 };
 441
 442 static struct interp_sample_rate int_mix_sample_rate_val[] = {
 443         {48000, 0x4},   /* 48K */
 444         {96000, 0x5},   /* 96K */
 445         {192000, 0x6},  /* 192K */
 446 };
 447
 448 static const struct wcd9xxx_ch tasha_rx_chs[TASHA_RX_MAX] = {
 449         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER, 0),
 450         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 1, 1),
 451         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 2, 2),
 452         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 3, 3),
 453         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 4, 4),
 454         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 5, 5),
 455         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 6, 6),
 456         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 7, 7),
 457         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 8, 8),
 458         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 9, 9),
 459         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 10, 10),
 460         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 11, 11),
 461         WCD9XXX_CH(TASHA_RX_PORT_START_NUMBER + 12, 12),
 462 };
 463
 464 static const struct wcd9xxx_ch tasha_tx_chs[TASHA_TX_MAX] = {
 465         WCD9XXX_CH(0, 0),
 466         WCD9XXX_CH(1, 1),
 467         WCD9XXX_CH(2, 2),
 468         WCD9XXX_CH(3, 3),
 469         WCD9XXX_CH(4, 4),
 470         WCD9XXX_CH(5, 5),
 471         WCD9XXX_CH(6, 6),
 472         WCD9XXX_CH(7, 7),
 473         WCD9XXX_CH(8, 8),
 474         WCD9XXX_CH(9, 9),
 475         WCD9XXX_CH(10, 10),
 476         WCD9XXX_CH(11, 11),
 477         WCD9XXX_CH(12, 12),
 478         WCD9XXX_CH(13, 13),
 479         WCD9XXX_CH(14, 14),
 480         WCD9XXX_CH(15, 15),
 481 };
 482
 483 static const u32 vport_slim_check_table[NUM_CODEC_DAIS] = {
 484         /* Needs to define in the same order of DAI enum definitions */
 485         0,
 486         BIT(AIF2_CAP) | BIT(AIF3_CAP) | BIT(AIF4_MAD_TX) | BIT(AIF5_CPE_TX),
 487         0,
 488         BIT(AIF1_CAP) | BIT(AIF3_CAP) | BIT(AIF4_MAD_TX) | BIT(AIF5_CPE_TX),
 489         0,
 490         BIT(AIF1_CAP) | BIT(AIF2_CAP) | BIT(AIF4_MAD_TX) | BIT(AIF5_CPE_TX),
 491         0,
 492         0,
 493         BIT(AIF1_CAP) | BIT(AIF2_CAP) | BIT(AIF3_CAP) | BIT(AIF5_CPE_TX),
 494         0,
 495         BIT(AIF1_CAP) | BIT(AIF2_CAP) | BIT(AIF3_CAP) | BIT(AIF4_MAD_TX),
 496 };
 497
 498 static const u32 vport_i2s_check_table[NUM_CODEC_DAIS] = {
 499         0,                      /* AIF1_PB */
 500         BIT(AIF2_CAP),          /* AIF1_CAP */
 501         0,                      /* AIF2_PB */
 502         BIT(AIF1_CAP),          /* AIF2_CAP */
 503 };
 504
 505 /* Codec supports 2 IIR filters */
 506 enum {
 507         IIR0 = 0,
 508         IIR1,
 509         IIR_MAX,
 510 };
 511
 512 /* Each IIR has 5 Filter Stages */
 513 enum {
 514         BAND1 = 0,
 515         BAND2,
 516         BAND3,
 517         BAND4,
 518         BAND5,
 519         BAND_MAX,
 520 };
 521
 522 enum {
 523         COMPANDER_1, /* HPH_L */
 524         COMPANDER_2, /* HPH_R */
 525         COMPANDER_3, /* LO1_DIFF */
 526         COMPANDER_4, /* LO2_DIFF */
 527         COMPANDER_5, /* LO3_SE */
 528         COMPANDER_6, /* LO4_SE */
 529         COMPANDER_7, /* SWR SPK CH1 */
 530         COMPANDER_8, /* SWR SPK CH2 */
 531         COMPANDER_MAX,
 532 };
 533
 534 enum {
 535         SRC_IN_HPHL,
 536         SRC_IN_LO1,
 537         SRC_IN_HPHR,
 538         SRC_IN_LO2,
 539         SRC_IN_SPKRL,
 540         SRC_IN_LO3,
 541         SRC_IN_SPKRR,
 542         SRC_IN_LO4,
 543 };
 544
 545 enum {
 546         SPLINE_SRC0,
 547         SPLINE_SRC1,
 548         SPLINE_SRC2,
 549         SPLINE_SRC3,
 550         SPLINE_SRC_MAX,
 551 };
 552
 553 /* wcd9335 interrupt table  */
 554 static const struct intr_data wcd9335_intr_table[] = {
 555         {WCD9XXX_IRQ_SLIMBUS, false},
 556         {WCD9335_IRQ_MBHC_SW_DET, true},
 557         {WCD9335_IRQ_MBHC_BUTTON_PRESS_DET, true},
 558         {WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET, true},
 559         {WCD9335_IRQ_MBHC_ELECT_INS_REM_DET, true},
 560         {WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET, true},
 561         {WCD9335_IRQ_FLL_LOCK_LOSS, false},
 562         {WCD9335_IRQ_HPH_PA_CNPL_COMPLETE, false},
 563         {WCD9335_IRQ_HPH_PA_CNPR_COMPLETE, false},
 564         {WCD9335_IRQ_EAR_PA_CNP_COMPLETE, false},
 565         {WCD9335_IRQ_LINE_PA1_CNP_COMPLETE, false},
 566         {WCD9335_IRQ_LINE_PA2_CNP_COMPLETE, false},
 567         {WCD9335_IRQ_LINE_PA3_CNP_COMPLETE, false},
 568         {WCD9335_IRQ_LINE_PA4_CNP_COMPLETE, false},
 569         {WCD9335_IRQ_HPH_PA_OCPL_FAULT, false},
 570         {WCD9335_IRQ_HPH_PA_OCPR_FAULT, false},
 571         {WCD9335_IRQ_EAR_PA_OCP_FAULT, false},
 572         {WCD9335_IRQ_SOUNDWIRE, false},
 573         {WCD9335_IRQ_VDD_DIG_RAMP_COMPLETE, false},
 574         {WCD9335_IRQ_RCO_ERROR, false},
 575         {WCD9335_IRQ_SVA_ERROR, false},
 576         {WCD9335_IRQ_MAD_AUDIO, false},
 577         {WCD9335_IRQ_MAD_BEACON, false},
 578         {WCD9335_IRQ_SVA_OUTBOX1, true},
 579         {WCD9335_IRQ_SVA_OUTBOX2, true},
 580         {WCD9335_IRQ_MAD_ULTRASOUND, false},
 581         {WCD9335_IRQ_VBAT_ATTACK, false},
 582         {WCD9335_IRQ_VBAT_RESTORE, false},
 583 };
 584
 585 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
 586 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 587 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 588
 589 static struct snd_soc_dai_driver tasha_dai[];
 590 static int wcd9335_get_micb_vout_ctl_val(u32 micb_mv);
 591
 592 static int tasha_config_compander(struct snd_soc_codec *, int, int);
 593 static void tasha_codec_set_tx_hold(struct snd_soc_codec *, u16, bool);
 594 static int tasha_codec_internal_rco_ctrl(struct snd_soc_codec *codec,
 595                                   bool enable);
 596
 597 /* Hold instance to soundwire platform device */
 598 struct tasha_swr_ctrl_data {
 599         struct platform_device *swr_pdev;
 600         struct ida swr_ida;
 601 };
 602
 603 struct wcd_swr_ctrl_platform_data {
 604         void *handle; /* holds codec private data */
 605         int (*read)(void *handle, int reg);
 606         int (*write)(void *handle, int reg, int val);
 607         int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
 608         int (*clk)(void *handle, bool enable);
 609         int (*handle_irq)(void *handle,
 610                           irqreturn_t (*swrm_irq_handler)(int irq,
 611                                                           void *data),
 612                           void *swrm_handle,
 613                           int action);
 614 };
 615
 616 static struct wcd_mbhc_register
 617         wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = {
 618         WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN",
 619                           WCD9335_ANA_MBHC_MECH, 0x80, 7, 0),
 620         WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN",
 621                           WCD9335_ANA_MBHC_MECH, 0x40, 6, 0),
 622         WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE",
 623                           WCD9335_ANA_MBHC_MECH, 0x20, 5, 0),
 624         WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL",
 625                           WCD9335_MBHC_PLUG_DETECT_CTL, 0x30, 4, 0),
 626         WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE",
 627                           WCD9335_ANA_MBHC_ELECT, 0x08, 3, 0),
 628         WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL",
 629                           WCD9335_MBHC_PLUG_DETECT_CTL, 0xC0, 6, 0),
 630         WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL",
 631                           WCD9335_ANA_MBHC_MECH, 0x04, 2, 0),
 632         WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE",
 633                           WCD9335_ANA_MBHC_MECH, 0x10, 4, 0),
 634         WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE",
 635                           WCD9335_ANA_MBHC_MECH, 0x08, 3, 0),
 636         WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND",
 637                           WCD9335_ANA_MBHC_MECH, 0x01, 0, 0),
 638         WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC",
 639                           WCD9335_ANA_MBHC_ELECT, 0x06, 1, 0),
 640         WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN",
 641                           WCD9335_ANA_MBHC_ELECT, 0x80, 7, 0),
 642         WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC",
 643                           WCD9335_MBHC_PLUG_DETECT_CTL, 0x0F, 0, 0),
 644         WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC",
 645                           WCD9335_MBHC_CTL_1, 0x03, 0, 0),
 646         WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF",
 647                           WCD9335_MBHC_CTL_2, 0x03, 0, 0),
 648         WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT",
 649                           WCD9335_ANA_MBHC_RESULT_3, 0x08, 3, 0),
 650         WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT",
 651                           WCD9335_ANA_MBHC_RESULT_3, 0x20, 5, 0),
 652         WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT",
 653                           WCD9335_ANA_MBHC_RESULT_3, 0x80, 7, 0),
 654         WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT",
 655                           WCD9335_ANA_MBHC_RESULT_3, 0x40, 6, 0),
 656         WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN",
 657                           WCD9335_HPH_OCP_CTL, 0x10, 4, 0),
 658         WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT",
 659                           WCD9335_ANA_MBHC_RESULT_3, 0x07, 0, 0),
 660         WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL",
 661                           WCD9335_ANA_MBHC_ELECT, 0x70, 4, 0),
 662         WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
 663                           WCD9335_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
 664         WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
 665                           WCD9335_ANA_MICB2, 0xC0, 6, 0),
 666         WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
 667                           WCD9335_HPH_CNP_WG_TIME, 0xFF, 0, 0),
 668         WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
 669                           WCD9335_ANA_HPH, 0x40, 6, 0),
 670         WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN",
 671                           WCD9335_ANA_HPH, 0x80, 7, 0),
 672         WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN",
 673                           WCD9335_ANA_HPH, 0xC0, 6, 0),
 674         WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE",
 675                           WCD9335_ANA_MBHC_RESULT_3, 0x10, 4, 0),
 676         WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL",
 677                           0, 0, 0, 0),
 678         WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN",
 679                           WCD9335_ANA_MBHC_ZDET, 0x01, 0, 0),
 680         /*
 681          * MBHC FSM status register is only available in Tasha 2.0.
 682          * So, init with 0 later once the version is known, then values
 683          * will be updated.
 684          */
 685         WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS",
 686                           0, 0, 0, 0),
 687         WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL",
 688                           WCD9335_MBHC_CTL_2, 0x70, 4, 0),
 689 };
 690
 691 static const struct wcd_mbhc_intr intr_ids = {
 692         .mbhc_sw_intr =  WCD9335_IRQ_MBHC_SW_DET,
 693         .mbhc_btn_press_intr = WCD9335_IRQ_MBHC_BUTTON_PRESS_DET,
 694         .mbhc_btn_release_intr = WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET,
 695         .mbhc_hs_ins_intr = WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 696         .mbhc_hs_rem_intr = WCD9335_IRQ_MBHC_ELECT_INS_REM_DET,
 697         .hph_left_ocp = WCD9335_IRQ_HPH_PA_OCPL_FAULT,
 698         .hph_right_ocp = WCD9335_IRQ_HPH_PA_OCPR_FAULT,
 699 };
 700
 701 struct wcd_vbat {
 702         bool is_enabled;
 703         bool adc_config;
 704         /* Variables to cache Vbat ADC output values */
 705         u16 dcp1;
 706         u16 dcp2;
 707 };
 708
 709 struct hpf_work {
 710         struct tasha_priv *tasha;
 711         u8 decimator;
 712         u8 hpf_cut_off_freq;
 713         struct delayed_work dwork;
 714 };
 715
 716 #define WCD9335_SPK_ANC_EN_DELAY_MS 350
 717 static int spk_anc_en_delay = WCD9335_SPK_ANC_EN_DELAY_MS;
 718 module_param(spk_anc_en_delay, int, S_IRUGO | S_IWUSR | S_IWGRP);
 719 MODULE_PARM_DESC(spk_anc_en_delay, "delay to enable anc in speaker path");
 720
 721 struct spk_anc_work {
 722         struct tasha_priv *tasha;
 723         struct delayed_work dwork;
 724 };
 725
 726 struct tx_mute_work {
 727         struct tasha_priv *tasha;
 728         u8 decimator;
 729         struct delayed_work dwork;
 730 };
 731
 732 struct tasha_priv {
 733         struct device *dev;
 734         struct wcd9xxx *wcd9xxx;
 735
 736         struct snd_soc_codec *codec;
 737         u32 adc_count;
 738         u32 rx_bias_count;
 739         s32 dmic_0_1_clk_cnt;
 740         s32 dmic_2_3_clk_cnt;
 741         s32 dmic_4_5_clk_cnt;
 742         s32 ldo_h_users;
 743         s32 micb_ref[TASHA_MAX_MICBIAS];
 744         s32 pullup_ref[TASHA_MAX_MICBIAS];
 745
 746         u32 anc_slot;
 747         bool anc_func;
 748
 749         /* Vbat module */
 750         struct wcd_vbat vbat;
 751
 752         /* cal info for codec */
 753         struct fw_info *fw_data;
 754
 755         /*track tasha interface type*/
 756         u8 intf_type;
 757
 758         /* num of slim ports required */
 759         struct wcd9xxx_codec_dai_data  dai[NUM_CODEC_DAIS];
 760
 761         /* SoundWire data structure */
 762         struct tasha_swr_ctrl_data *swr_ctrl_data;
 763         int nr;
 764
 765         /*compander*/
 766         int comp_enabled[COMPANDER_MAX];
 767
 768         /* Maintain the status of AUX PGA */
 769         int aux_pga_cnt;
 770         u8 aux_l_gain;
 771         u8 aux_r_gain;
 772
 773         bool spkr_pa_widget_on;
 774         struct regulator *spkdrv_reg;
 775         struct regulator *spkdrv2_reg;
 776
 777         bool mbhc_started;
 778         /* class h specific data */
 779         struct wcd_clsh_cdc_data clsh_d;
 780
 781         struct afe_param_cdc_slimbus_slave_cfg slimbus_slave_cfg;
 782
 783         /*
 784          * list used to save/restore registers at start and
 785          * end of impedance measurement
 786          */
 787         struct list_head reg_save_restore;
 788
 789         /* handle to cpe core */
 790         struct wcd_cpe_core *cpe_core;
 791         u32 current_cpe_clk_freq;
 792         enum tasha_sido_voltage sido_voltage;
 793         int sido_ccl_cnt;
 794
 795         u32 ana_rx_supplies;
 796         /* Multiplication factor used for impedance detection */
 797         int zdet_gain_mul_fact;
 798
 799         /* to track the status */
 800         unsigned long status_mask;
 801
 802         struct work_struct tasha_add_child_devices_work;
 803         struct wcd_swr_ctrl_platform_data swr_plat_data;
 804
 805         /* Port values for Rx and Tx codec_dai */
 806         unsigned int rx_port_value[TASHA_RX_MAX];
 807         unsigned int tx_port_value;
 808
 809         unsigned int vi_feed_value;
 810         /* Tasha Interpolator Mode Select for EAR, HPH_L and HPH_R */
 811         u32 hph_mode;
 812
 813         u16 prim_int_users[TASHA_NUM_INTERPOLATORS];
 814         int spl_src_users[SPLINE_SRC_MAX];
 815
 816         struct wcd9xxx_resmgr_v2 *resmgr;
 817         struct delayed_work power_gate_work;
 818         struct mutex power_lock;
 819         struct mutex sido_lock;
 820
 821         /* mbhc module */
 822         struct wcd_mbhc mbhc;
 823         struct blocking_notifier_head notifier;
 824         struct mutex micb_lock;
 825
 826         struct clk *wcd_ext_clk;
 827         struct clk *wcd_native_clk;
 828         struct mutex swr_read_lock;
 829         struct mutex swr_write_lock;
 830         struct mutex swr_clk_lock;
 831         int swr_clk_users;
 832         int native_clk_users;
 833         int (*zdet_gpio_cb)(struct snd_soc_codec *codec, bool high);
 834
 835         struct snd_info_entry *entry;
 836         struct snd_info_entry *version_entry;
 837         int power_active_ref;
 838
 839         struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
 840
 841         int (*machine_codec_event_cb)(struct snd_soc_codec *codec,
 842                                       enum wcd9335_codec_event);
 843         int spkr_gain_offset;
 844         int spkr_mode;
 845         int ear_spkr_gain;
 846         struct hpf_work tx_hpf_work[TASHA_NUM_DECIMATORS];
 847         struct tx_mute_work tx_mute_dwork[TASHA_NUM_DECIMATORS];
 848         struct spk_anc_work spk_anc_dwork;
 849         struct mutex codec_mutex;
 850         int hph_l_gain;
 851         int hph_r_gain;
 852         int rx_7_count;
 853         int rx_8_count;
 854         bool clk_mode;
 855         bool clk_internal;
 856         /* Lock to prevent multiple functions voting at same time */
 857         struct mutex sb_clk_gear_lock;
 858         /* Count for functions voting or un-voting */
 859         u32 ref_count;
 860         /* Lock to protect mclk enablement */
 861         struct mutex mclk_lock;
 862 };
 863
 864 static int tasha_codec_vote_max_bw(struct snd_soc_codec *codec,
 865                                    bool vote);
 866
 867 static const struct tasha_reg_mask_val tasha_spkr_default[] = {
 868         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
 869         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
 870         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
 871         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
 872         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x7C, 0x50},
 873         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x7C, 0x50},
 874 };
 875
 876 static const struct tasha_reg_mask_val tasha_spkr_mode1[] = {
 877         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x00},
 878         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x00},
 879         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x00},
 880         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x00},
 881         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x7C, 0x44},
 882         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x7C, 0x44},
 883 };
 884
 885 /*
 886  * wcd9335_get_codec_info: Get codec specific information
 887  *
 888  * @wcd9xxx: pointer to wcd9xxx structure
 889  * @wcd_type: pointer to wcd9xxx_codec_type structure
 890  *
 891  * Returns 0 for success or negative error code for failure
 892  */
 893 int wcd9335_get_codec_info(struct wcd9xxx *wcd9xxx,
 894                            struct wcd9xxx_codec_type *wcd_type)
 895 {
 896         u16 id_minor, id_major;
 897         struct regmap *wcd_regmap;
 898         int rc, val, version = 0;
 899
 900         if (!wcd9xxx || !wcd_type)
 901                 return -EINVAL;
 902
 903         if (!wcd9xxx->regmap) {
 904                 dev_err(wcd9xxx->dev, "%s: wcd9xxx regmap is null!\n",
 905                         __func__);
 906                 return -EINVAL;
 907         }
 908         wcd_regmap = wcd9xxx->regmap;
 909
 910         rc = regmap_bulk_read(wcd_regmap, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
 911                         (u8 *)&id_minor, sizeof(u16));
 912         if (rc)
 913                 return -EINVAL;
 914
 915         rc = regmap_bulk_read(wcd_regmap, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2,
 916                               (u8 *)&id_major, sizeof(u16));
 917         if (rc)
 918                 return -EINVAL;
 919
 920         dev_info(wcd9xxx->dev, "%s: wcd9xxx chip id major 0x%x, minor 0x%x\n",
 921                  __func__, id_major, id_minor);
 922
 923         /* Version detection */
 924         if (id_major == TASHA_MAJOR) {
 925                 regmap_read(wcd_regmap, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0,
 926                             &val);
 927                 version = ((u8)val & 0x80) >> 7;
 928         } else if (id_major == TASHA2P0_MAJOR)
 929                 version = 2;
 930         else
 931                 dev_err(wcd9xxx->dev, "%s: wcd9335 version unknown (major 0x%x, minor 0x%x)\n",
 932                         __func__, id_major, id_minor);
 933
 934         /* Fill codec type info */
 935         wcd_type->id_major = id_major;
 936         wcd_type->id_minor = id_minor;
 937         wcd_type->num_irqs = WCD9335_NUM_IRQS;
 938         wcd_type->version = version;
 939         wcd_type->slim_slave_type = WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1;
 940         wcd_type->i2c_chip_status = 0x01;
 941         wcd_type->intr_tbl = wcd9335_intr_table;
 942         wcd_type->intr_tbl_size = ARRAY_SIZE(wcd9335_intr_table);
 943
 944         wcd_type->intr_reg[WCD9XXX_INTR_STATUS_BASE] =
 945                                                 WCD9335_INTR_PIN1_STATUS0;
 946         wcd_type->intr_reg[WCD9XXX_INTR_CLEAR_BASE] =
 947                                                 WCD9335_INTR_PIN1_CLEAR0;
 948         wcd_type->intr_reg[WCD9XXX_INTR_MASK_BASE] =
 949                                                 WCD9335_INTR_PIN1_MASK0;
 950         wcd_type->intr_reg[WCD9XXX_INTR_LEVEL_BASE] =
 951                                                 WCD9335_INTR_LEVEL0;
 952         wcd_type->intr_reg[WCD9XXX_INTR_CLR_COMMIT] =
 953                                                 WCD9335_INTR_CLR_COMMIT;
 954
 955         return rc;
 956 }
 957 EXPORT_SYMBOL(wcd9335_get_codec_info);
 958
 959 /*
 960  * wcd9335_bringdown: Bringdown WCD Codec
 961  *
 962  * @wcd9xxx: Pointer to wcd9xxx structure
 963  *
 964  * Returns 0 for success or negative error code for failure
 965  */
 966 int wcd9335_bringdown(struct wcd9xxx *wcd9xxx)
 967 {
 968         if (!wcd9xxx || !wcd9xxx->regmap)
 969                 return -EINVAL;
 970
 971         regmap_write(wcd9xxx->regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
 972                      0x04);
 973
 974         return 0;
 975 }
 976 EXPORT_SYMBOL(wcd9335_bringdown);
 977
 978 /*
 979  * wcd9335_bringup: Bringup WCD Codec
 980  *
 981  * @wcd9xxx: Pointer to the wcd9xxx structure
 982  *
 983  * Returns 0 for success or negative error code for failure
 984  */
 985 int wcd9335_bringup(struct wcd9xxx *wcd9xxx)
 986 {
 987         int ret = 0;
 988         int val, byte0;
 989         struct regmap *wcd_regmap;
 990
 991         if (!wcd9xxx)
 992                 return -EINVAL;
 993
 994         if (!wcd9xxx->regmap) {
 995                 dev_err(wcd9xxx->dev, "%s: wcd9xxx regmap is null!\n",
 996                         __func__);
 997                 return -EINVAL;
 998         }
 999         wcd_regmap = wcd9xxx->regmap;
1000
1001         regmap_read(wcd_regmap, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
1002         regmap_read(wcd_regmap, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
1003
1004         if ((val < 0) || (byte0 < 0)) {
1005                 dev_err(wcd9xxx->dev, "%s: tasha codec version detection fail!\n",
1006                         __func__);
1007                 return -EINVAL;
1008         }
1009         if ((val & 0x80) && (byte0 == 0x0)) {
1010                 dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v1.1\n",
1011                          __func__);
1012                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x01);
1013                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_CCL_2, 0xFC);
1014                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_CCL_4, 0x21);
1015                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1016                              0x5);
1017                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1018                              0x7);
1019                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1020                              0x3);
1021                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x3);
1022         } else if (byte0 == 0x1) {
1023                 dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v2.0\n",
1024                          __func__);
1025                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x01);
1026                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_TEST_2, 0x00);
1027                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
1028                 regmap_write(wcd_regmap, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
1029                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1030                              0x5);
1031                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1032                              0x7);
1033                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1034                              0x3);
1035                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x3);
1036         } else if ((byte0 == 0) && (!(val & 0x80))) {
1037                 dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v1.0\n",
1038                          __func__);
1039                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x01);
1040                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_CCL_2, 0xFC);
1041                 regmap_write(wcd_regmap, WCD9335_SIDO_SIDO_CCL_4, 0x21);
1042                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
1043                              0x3);
1044                 regmap_write(wcd_regmap, WCD9335_CODEC_RPM_RST_CTL, 0x3);
1045         } else {
1046                 dev_err(wcd9xxx->dev, "%s: tasha codec version unknown\n",
1047                         __func__);
1048                 ret = -EINVAL;
1049         }
1050
1051         return ret;
1052 }
1053 EXPORT_SYMBOL(wcd9335_bringup);
1054
1055 /**
1056  * tasha_set_spkr_gain_offset - offset the speaker path
1057  * gain with the given offset value.
1058  *
1059  * @codec: codec instance
1060  * @offset: Indicates speaker path gain offset value.
1061  *
1062  * Returns 0 on success or -EINVAL on error.
1063  */
1064 int tasha_set_spkr_gain_offset(struct snd_soc_codec *codec, int offset)
1065 {
1066         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
1067
1068         if (!priv)
1069                 return -EINVAL;
1070
1071         priv->spkr_gain_offset = offset;
1072         return 0;
1073 }
1074 EXPORT_SYMBOL(tasha_set_spkr_gain_offset);
1075
1076 /**
1077  * tasha_set_spkr_mode - Configures speaker compander and smartboost
1078  * settings based on speaker mode.
1079  *
1080  * @codec: codec instance
1081  * @mode: Indicates speaker configuration mode.
1082  *
1083  * Returns 0 on success or -EINVAL on error.
1084  */
1085 int tasha_set_spkr_mode(struct snd_soc_codec *codec, int mode)
1086 {
1087         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
1088         int i;
1089         const struct tasha_reg_mask_val *regs;
1090         int size;
1091
1092         if (!priv)
1093                 return -EINVAL;
1094
1095         switch (mode) {
1096         case SPKR_MODE_1:
1097                 regs = tasha_spkr_mode1;
1098                 size = ARRAY_SIZE(tasha_spkr_mode1);
1099                 break;
1100         default:
1101                 regs = tasha_spkr_default;
1102                 size = ARRAY_SIZE(tasha_spkr_default);
1103                 break;
1104         }
1105
1106         priv->spkr_mode = mode;
1107         for (i = 0; i < size; i++)
1108                 snd_soc_update_bits(codec, regs[i].reg,
1109                                     regs[i].mask, regs[i].val);
1110         return 0;
1111 }
1112 EXPORT_SYMBOL(tasha_set_spkr_mode);
1113
1114 static void tasha_enable_sido_buck(struct snd_soc_codec *codec)
1115 {
1116         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1117
1118         snd_soc_update_bits(codec, WCD9335_ANA_RCO, 0x80, 0x80);
1119         snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL, 0x02, 0x02);
1120         /* 100us sleep needed after IREF settings */
1121         usleep_range(100, 110);
1122         snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL, 0x04, 0x04);
1123         /* 100us sleep needed after VREF settings */
1124         usleep_range(100, 110);
1125         tasha->resmgr->sido_input_src = SIDO_SOURCE_RCO_BG;
1126 }
1127
1128 static void tasha_cdc_sido_ccl_enable(struct tasha_priv *tasha, bool ccl_flag)
1129 {
1130         struct snd_soc_codec *codec = tasha->codec;
1131
1132         if (!codec)
1133                 return;
1134
1135         if (!TASHA_IS_2_0(tasha->wcd9xxx)) {
1136                 dev_dbg(codec->dev, "%s: tasha version < 2p0, return\n",
1137                         __func__);
1138                 return;
1139         }
1140         dev_dbg(codec->dev, "%s: sido_ccl_cnt=%d, ccl_flag:%d\n",
1141                         __func__, tasha->sido_ccl_cnt, ccl_flag);
1142         if (ccl_flag) {
1143                 if (++tasha->sido_ccl_cnt == 1)
1144                         snd_soc_update_bits(codec,
1145                                 WCD9335_SIDO_SIDO_CCL_10, 0xFF, 0x6E);
1146         } else {
1147                 if (tasha->sido_ccl_cnt == 0) {
1148                         dev_dbg(codec->dev, "%s: sido_ccl already disabled\n",
1149                                 __func__);
1150                         return;
1151                 }
1152                 if (--tasha->sido_ccl_cnt == 0)
1153                         snd_soc_update_bits(codec,
1154                                 WCD9335_SIDO_SIDO_CCL_10, 0xFF, 0x02);
1155         }
1156 }
1157
1158 static bool tasha_cdc_is_svs_enabled(struct tasha_priv *tasha)
1159 {
1160         if (TASHA_IS_2_0(tasha->wcd9xxx) &&
1161                 svs_scaling_enabled)
1162                 return true;
1163
1164         return false;
1165 }
1166
1167 static int tasha_cdc_req_mclk_enable(struct tasha_priv *tasha,
1168                                      bool enable)
1169 {
1170         int ret = 0;
1171
1172         mutex_lock(&tasha->mclk_lock);
1173         if (enable) {
1174                 tasha_cdc_sido_ccl_enable(tasha, true);
1175                 ret = clk_prepare_enable(tasha->wcd_ext_clk);
1176                 if (ret) {
1177                         dev_err(tasha->dev, "%s: ext clk enable failed\n",
1178                                 __func__);
1179                         goto unlock_mutex;
1180                 }
1181                 /* get BG */
1182                 wcd_resmgr_enable_master_bias(tasha->resmgr);
1183                 /* get MCLK */
1184                 wcd_resmgr_enable_clk_block(tasha->resmgr, WCD_CLK_MCLK);
1185         } else {
1186                 /* put MCLK */
1187                 wcd_resmgr_disable_clk_block(tasha->resmgr, WCD_CLK_MCLK);
1188                 /* put BG */
1189                 wcd_resmgr_disable_master_bias(tasha->resmgr);
1190                 clk_disable_unprepare(tasha->wcd_ext_clk);
1191                 tasha_cdc_sido_ccl_enable(tasha, false);
1192         }
1193 unlock_mutex:
1194         mutex_unlock(&tasha->mclk_lock);
1195         return ret;
1196 }
1197
1198 static int tasha_cdc_check_sido_value(enum tasha_sido_voltage req_mv)
1199 {
1200         if ((req_mv != SIDO_VOLTAGE_SVS_MV) &&
1201                 (req_mv != SIDO_VOLTAGE_NOMINAL_MV))
1202                 return -EINVAL;
1203
1204         return 0;
1205 }
1206
1207 static void tasha_codec_apply_sido_voltage(
1208                                 struct tasha_priv *tasha,
1209                                 enum tasha_sido_voltage req_mv)
1210 {
1211         u32 vout_d_val;
1212         struct snd_soc_codec *codec = tasha->codec;
1213         int ret;
1214
1215         if (!codec)
1216                 return;
1217
1218         if (!tasha_cdc_is_svs_enabled(tasha))
1219                 return;
1220
1221         if ((sido_buck_svs_voltage != SIDO_VOLTAGE_SVS_MV) &&
1222                 (sido_buck_svs_voltage != SIDO_VOLTAGE_NOMINAL_MV))
1223                 sido_buck_svs_voltage = SIDO_VOLTAGE_SVS_MV;
1224
1225         ret = tasha_cdc_check_sido_value(req_mv);
1226         if (ret < 0) {
1227                 dev_dbg(codec->dev, "%s: requested mv=%d not in range\n",
1228                         __func__, req_mv);
1229                 return;
1230         }
1231         if (req_mv == tasha->sido_voltage) {
1232                 dev_dbg(codec->dev, "%s: Already at requested mv=%d\n",
1233                         __func__, req_mv);
1234                 return;
1235         }
1236         if (req_mv == sido_buck_svs_voltage) {
1237                 if (test_bit(AUDIO_NOMINAL, &tasha->status_mask) ||
1238                         test_bit(CPE_NOMINAL, &tasha->status_mask)) {
1239                         dev_dbg(codec->dev,
1240                                 "%s: nominal client running, status_mask=%lu\n",
1241                                 __func__, tasha->status_mask);
1242                         return;
1243                 }
1244         }
1245         /* compute the vout_d step value */
1246         vout_d_val = CALCULATE_VOUT_D(req_mv);
1247         snd_soc_write(codec, WCD9335_ANA_BUCK_VOUT_D, vout_d_val & 0xFF);
1248         snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL, 0x80, 0x80);
1249
1250         /* 1 msec sleep required after SIDO Vout_D voltage change */
1251         usleep_range(1000, 1100);
1252         tasha->sido_voltage = req_mv;
1253         dev_dbg(codec->dev,
1254                 "%s: updated SIDO buck Vout_D to %d, vout_d step = %u\n",
1255                 __func__, tasha->sido_voltage, vout_d_val);
1256
1257         snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL,
1258                                 0x80, 0x00);
1259 }
1260
1261 static int tasha_codec_update_sido_voltage(
1262                                 struct tasha_priv *tasha,
1263                                 enum tasha_sido_voltage req_mv)
1264 {
1265         int ret = 0;
1266
1267         if (!tasha_cdc_is_svs_enabled(tasha))
1268                 return ret;
1269
1270         mutex_lock(&tasha->sido_lock);
1271         /* enable mclk before setting SIDO voltage */
1272         ret = tasha_cdc_req_mclk_enable(tasha, true);
1273         if (ret) {
1274                 dev_err(tasha->dev, "%s: ext clk enable failed\n",
1275                         __func__);
1276                 goto err;
1277         }
1278         tasha_codec_apply_sido_voltage(tasha, req_mv);
1279         tasha_cdc_req_mclk_enable(tasha, false);
1280
1281 err:
1282         mutex_unlock(&tasha->sido_lock);
1283         return ret;
1284 }
1285
1286 int tasha_enable_efuse_sensing(struct snd_soc_codec *codec)
1287 {
1288         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
1289
1290         tasha_cdc_mclk_enable(codec, true, false);
1291
1292         if (!TASHA_IS_2_0(priv->wcd9xxx))
1293                 snd_soc_update_bits(codec, WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
1294                                     0x1E, 0x02);
1295         snd_soc_update_bits(codec, WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
1296                             0x01, 0x01);
1297         /*
1298          * 5ms sleep required after enabling efuse control
1299          * before checking the status.
1300          */
1301         usleep_range(5000, 5500);
1302         if (!(snd_soc_read(codec, WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 0x01))
1303                 WARN(1, "%s: Efuse sense is not complete\n", __func__);
1304
1305         if (TASHA_IS_2_0(priv->wcd9xxx)) {
1306                 if (!(snd_soc_read(codec,
1307                         WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0) & 0x40))
1308                         snd_soc_update_bits(codec, WCD9335_HPH_R_ATEST,
1309                                             0x04, 0x00);
1310                 tasha_enable_sido_buck(codec);
1311         }
1312
1313         tasha_cdc_mclk_enable(codec, false, false);
1314
1315         return 0;
1316 }
1317 EXPORT_SYMBOL(tasha_enable_efuse_sensing);
1318
1319 void *tasha_get_afe_config(struct snd_soc_codec *codec,
1320                            enum afe_config_type config_type)
1321 {
1322         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
1323
1324         switch (config_type) {
1325         case AFE_SLIMBUS_SLAVE_CONFIG:
1326                 return &priv->slimbus_slave_cfg;
1327         case AFE_CDC_REGISTERS_CONFIG:
1328                 return &tasha_audio_reg_cfg;
1329         case AFE_SLIMBUS_SLAVE_PORT_CONFIG:
1330                 return &tasha_slimbus_slave_port_cfg;
1331         case AFE_AANC_VERSION:
1332                 return &tasha_cdc_aanc_version;
1333         case AFE_CLIP_BANK_SEL:
1334                 return NULL;
1335         case AFE_CDC_CLIP_REGISTERS_CONFIG:
1336                 return NULL;
1337         case AFE_CDC_REGISTER_PAGE_CONFIG:
1338                 return &tasha_cdc_reg_page_cfg;
1339         default:
1340                 dev_err(codec->dev, "%s: Unknown config_type 0x%x\n",
1341                         __func__, config_type);
1342                 return NULL;
1343         }
1344 }
1345 EXPORT_SYMBOL(tasha_get_afe_config);
1346
1347 /*
1348  * tasha_event_register: Registers a machine driver callback
1349  * function with codec private data for post ADSP sub-system
1350  * restart (SSR). This callback function will be called from
1351  * codec driver once codec comes out of reset after ADSP SSR.
1352  *
1353  * @machine_event_cb: callback function from machine driver
1354  * @codec: Codec instance
1355  *
1356  * Return: none
1357  */
1358 void tasha_event_register(
1359         int (*machine_event_cb)(struct snd_soc_codec *codec,
1360                                 enum wcd9335_codec_event),
1361         struct snd_soc_codec *codec)
1362 {
1363         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1364
1365         if (tasha)
1366                 tasha->machine_codec_event_cb = machine_event_cb;
1367         else
1368                 dev_dbg(codec->dev, "%s: Invalid tasha_priv data\n", __func__);
1369 }
1370 EXPORT_SYMBOL(tasha_event_register);
1371
1372 static int tasha_mbhc_request_irq(struct snd_soc_codec *codec,
1373                                    int irq, irq_handler_t handler,
1374                                    const char *name, void *data)
1375 {
1376         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1377         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
1378         struct wcd9xxx_core_resource *core_res =
1379                                 &wcd9xxx->core_res;
1380
1381         return wcd9xxx_request_irq(core_res, irq, handler, name, data);
1382 }
1383
1384 static void tasha_mbhc_irq_control(struct snd_soc_codec *codec,
1385                                    int irq, bool enable)
1386 {
1387         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1388         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
1389         struct wcd9xxx_core_resource *core_res =
1390                                 &wcd9xxx->core_res;
1391         if (enable)
1392                 wcd9xxx_enable_irq(core_res, irq);
1393         else
1394                 wcd9xxx_disable_irq(core_res, irq);
1395 }
1396
1397 static int tasha_mbhc_free_irq(struct snd_soc_codec *codec,
1398                                int irq, void *data)
1399 {
1400         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1401         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
1402         struct wcd9xxx_core_resource *core_res =
1403                                 &wcd9xxx->core_res;
1404
1405         wcd9xxx_free_irq(core_res, irq, data);
1406         return 0;
1407 }
1408
1409 static void tasha_mbhc_clk_setup(struct snd_soc_codec *codec,
1410                                  bool enable)
1411 {
1412         if (enable)
1413                 snd_soc_update_bits(codec, WCD9335_MBHC_CTL_1,
1414                                     0x80, 0x80);
1415         else
1416                 snd_soc_update_bits(codec, WCD9335_MBHC_CTL_1,
1417                                     0x80, 0x00);
1418 }
1419
1420 static int tasha_mbhc_btn_to_num(struct snd_soc_codec *codec)
1421 {
1422         return snd_soc_read(codec, WCD9335_ANA_MBHC_RESULT_3) & 0x7;
1423 }
1424
1425 static void tasha_mbhc_mbhc_bias_control(struct snd_soc_codec *codec,
1426                                          bool enable)
1427 {
1428         if (enable)
1429                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_ELECT,
1430                                     0x01, 0x01);
1431         else
1432                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_ELECT,
1433                                     0x01, 0x00);
1434 }
1435
1436 static void tasha_mbhc_program_btn_thr(struct snd_soc_codec *codec,
1437                                        s16 *btn_low, s16 *btn_high,
1438                                        int num_btn, bool is_micbias)
1439 {
1440         int i;
1441         int vth;
1442
1443         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1444                 dev_err(codec->dev, "%s: invalid number of buttons: %d\n",
1445                         __func__, num_btn);
1446                 return;
1447         }
1448         /*
1449          * Tasha just needs one set of thresholds for button detection
1450          * due to micbias voltage ramp to pullup upon button press. So
1451          * btn_low and is_micbias are ignored and always program button
1452          * thresholds using btn_high.
1453          */
1454         for (i = 0; i < num_btn; i++) {
1455                 vth = ((btn_high[i] * 2) / 25) & 0x3F;
1456                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_BTN0 + i,
1457                                     0xFC, vth << 2);
1458                 dev_dbg(codec->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1459                         __func__, i, btn_high[i], vth);
1460         }
1461 }
1462
1463 static bool tasha_mbhc_lock_sleep(struct wcd_mbhc *mbhc, bool lock)
1464 {
1465         struct snd_soc_codec *codec = mbhc->codec;
1466         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1467         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
1468         struct wcd9xxx_core_resource *core_res =
1469                                 &wcd9xxx->core_res;
1470         if (lock)
1471                 return wcd9xxx_lock_sleep(core_res);
1472         else {
1473                 wcd9xxx_unlock_sleep(core_res);
1474                 return 0;
1475         }
1476 }
1477
1478 static int tasha_mbhc_register_notifier(struct wcd_mbhc *mbhc,
1479                                         struct notifier_block *nblock,
1480                                         bool enable)
1481 {
1482         struct snd_soc_codec *codec = mbhc->codec;
1483         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1484
1485         if (enable)
1486                 return blocking_notifier_chain_register(&tasha->notifier,
1487                                                         nblock);
1488         else
1489                 return blocking_notifier_chain_unregister(&tasha->notifier,
1490                                                           nblock);
1491 }
1492
1493 static bool tasha_mbhc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num)
1494 {
1495         u8 val;
1496         if (micb_num == MIC_BIAS_2) {
1497                 val = (snd_soc_read(mbhc->codec, WCD9335_ANA_MICB2) >> 6);
1498                 if (val == 0x01)
1499                         return true;
1500         }
1501         return false;
1502 }
1503
1504 static bool tasha_mbhc_hph_pa_on_status(struct snd_soc_codec *codec)
1505 {
1506         return (snd_soc_read(codec, WCD9335_ANA_HPH) & 0xC0) ? true : false;
1507 }
1508
1509 static void tasha_mbhc_hph_l_pull_up_control(struct snd_soc_codec *codec,
1510                                         enum mbhc_hs_pullup_iref pull_up_cur)
1511 {
1512         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1513
1514         if (!tasha)
1515                 return;
1516
1517         /* Default pull up current to 2uA */
1518         if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
1519             pull_up_cur == I_DEFAULT)
1520                 pull_up_cur = I_2P0_UA;
1521
1522         dev_dbg(codec->dev, "%s: HS pull up current:%d\n",
1523                 __func__, pull_up_cur);
1524
1525         if (TASHA_IS_2_0(tasha->wcd9xxx))
1526                 snd_soc_update_bits(codec, WCD9335_MBHC_PLUG_DETECT_CTL,
1527                             0xC0, pull_up_cur << 6);
1528         else
1529                 snd_soc_update_bits(codec, WCD9335_MBHC_PLUG_DETECT_CTL,
1530                             0xC0, 0x40);
1531 }
1532
1533 static int tasha_enable_ext_mb_source(struct wcd_mbhc *mbhc,
1534                 bool turn_on)
1535 {
1536         struct snd_soc_codec *codec = mbhc->codec;
1537         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1538         int ret = 0;
1539         struct on_demand_supply *supply;
1540
1541         if (!tasha)
1542                 return -EINVAL;
1543
1544         supply =  &tasha->on_demand_list[ON_DEMAND_MICBIAS];
1545         if (!supply->supply) {
1546                 dev_dbg(codec->dev, "%s: warning supply not present ond for %s\n",
1547                                 __func__, "onDemand Micbias");
1548                 return ret;
1549         }
1550
1551         dev_dbg(codec->dev, "%s turn_on: %d count: %d\n", __func__, turn_on,
1552                 supply->ondemand_supply_count);
1553
1554         if (turn_on) {
1555                 if (!(supply->ondemand_supply_count)) {
1556                         ret = snd_soc_dapm_force_enable_pin(
1557                                 snd_soc_codec_get_dapm(codec),
1558                                 "MICBIAS_REGULATOR");
1559                         snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
1560                 }
1561                 supply->ondemand_supply_count++;
1562         } else {
1563                 if (supply->ondemand_supply_count > 0)
1564                         supply->ondemand_supply_count--;
1565                 if (!(supply->ondemand_supply_count)) {
1566                         ret = snd_soc_dapm_disable_pin(
1567                                 snd_soc_codec_get_dapm(codec),
1568                                 "MICBIAS_REGULATOR");
1569                 snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
1570                 }
1571         }
1572
1573         if (ret)
1574                 dev_err(codec->dev, "%s: Failed to %s external micbias source\n",
1575                         __func__, turn_on ? "enable" : "disabled");
1576         else
1577                 dev_dbg(codec->dev, "%s: %s external micbias source\n",
1578                         __func__, turn_on ? "Enabled" : "Disabled");
1579
1580         return ret;
1581 }
1582
1583 static int tasha_micbias_control(struct snd_soc_codec *codec,
1584                                  int micb_num,
1585                                  int req, bool is_dapm)
1586 {
1587         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1588         int micb_index = micb_num - 1;
1589         u16 micb_reg;
1590         int pre_off_event = 0, post_off_event = 0;
1591         int post_on_event = 0, post_dapm_off = 0;
1592         int post_dapm_on = 0;
1593
1594         if ((micb_index < 0) || (micb_index > TASHA_MAX_MICBIAS - 1)) {
1595                 dev_err(codec->dev, "%s: Invalid micbias index, micb_ind:%d\n",
1596                         __func__, micb_index);
1597                 return -EINVAL;
1598         }
1599         switch (micb_num) {
1600         case MIC_BIAS_1:
1601                 micb_reg = WCD9335_ANA_MICB1;
1602                 break;
1603         case MIC_BIAS_2:
1604                 micb_reg = WCD9335_ANA_MICB2;
1605                 pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
1606                 post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
1607                 post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
1608                 post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
1609                 post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
1610                 break;
1611         case MIC_BIAS_3:
1612                 micb_reg = WCD9335_ANA_MICB3;
1613                 break;
1614         case MIC_BIAS_4:
1615                 micb_reg = WCD9335_ANA_MICB4;
1616                 break;
1617         default:
1618                 dev_err(codec->dev, "%s: Invalid micbias number: %d\n",
1619                         __func__, micb_num);
1620                 return -EINVAL;
1621         }
1622         mutex_lock(&tasha->micb_lock);
1623
1624         switch (req) {
1625         case MICB_PULLUP_ENABLE:
1626                 tasha->pullup_ref[micb_index]++;
1627                 if ((tasha->pullup_ref[micb_index] == 1) &&
1628                     (tasha->micb_ref[micb_index] == 0))
1629                         snd_soc_update_bits(codec, micb_reg, 0xC0, 0x80);
1630                 break;
1631         case MICB_PULLUP_DISABLE:
1632                 if (tasha->pullup_ref[micb_index] > 0)
1633                         tasha->pullup_ref[micb_index]--;
1634                 if ((tasha->pullup_ref[micb_index] == 0) &&
1635                     (tasha->micb_ref[micb_index] == 0))
1636                         snd_soc_update_bits(codec, micb_reg, 0xC0, 0x00);
1637                 break;
1638         case MICB_ENABLE:
1639                 tasha->micb_ref[micb_index]++;
1640                 if (tasha->micb_ref[micb_index] == 1) {
1641                         snd_soc_update_bits(codec, micb_reg, 0xC0, 0x40);
1642                         if (post_on_event)
1643                                 blocking_notifier_call_chain(&tasha->notifier,
1644                                                 post_on_event, &tasha->mbhc);
1645                 }
1646                 if (is_dapm && post_dapm_on)
1647                         blocking_notifier_call_chain(&tasha->notifier,
1648                                         post_dapm_on, &tasha->mbhc);
1649                 break;
1650         case MICB_DISABLE:
1651                 if (tasha->micb_ref[micb_index] > 0)
1652                         tasha->micb_ref[micb_index]--;
1653                 if ((tasha->micb_ref[micb_index] == 0) &&
1654                     (tasha->pullup_ref[micb_index] > 0))
1655                         snd_soc_update_bits(codec, micb_reg, 0xC0, 0x80);
1656                 else if ((tasha->micb_ref[micb_index] == 0) &&
1657                          (tasha->pullup_ref[micb_index] == 0)) {
1658                         if (pre_off_event)
1659                                 blocking_notifier_call_chain(&tasha->notifier,
1660                                                 pre_off_event, &tasha->mbhc);
1661                         snd_soc_update_bits(codec, micb_reg, 0xC0, 0x00);
1662                         if (post_off_event)
1663                                 blocking_notifier_call_chain(&tasha->notifier,
1664                                                 post_off_event, &tasha->mbhc);
1665                 }
1666                 if (is_dapm && post_dapm_off)
1667                         blocking_notifier_call_chain(&tasha->notifier,
1668                                         post_dapm_off, &tasha->mbhc);
1669                 break;
1670         };
1671
1672         dev_dbg(codec->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
1673                 __func__, micb_num, tasha->micb_ref[micb_index],
1674                 tasha->pullup_ref[micb_index]);
1675
1676         mutex_unlock(&tasha->micb_lock);
1677
1678         return 0;
1679 }
1680
1681 static int tasha_mbhc_request_micbias(struct snd_soc_codec *codec,
1682                                       int micb_num, int req)
1683 {
1684         int ret;
1685
1686         /*
1687          * If micbias is requested, make sure that there
1688          * is vote to enable mclk
1689          */
1690         if (req == MICB_ENABLE)
1691                 tasha_cdc_mclk_enable(codec, true, false);
1692
1693         ret = tasha_micbias_control(codec, micb_num, req, false);
1694
1695         /*
1696          * Release vote for mclk while requesting for
1697          * micbias disable
1698          */
1699         if (req == MICB_DISABLE)
1700                 tasha_cdc_mclk_enable(codec, false, false);
1701
1702         return ret;
1703 }
1704
1705 static void tasha_mbhc_micb_ramp_control(struct snd_soc_codec *codec,
1706                                         bool enable)
1707 {
1708         if (enable) {
1709                 snd_soc_update_bits(codec, WCD9335_ANA_MICB2_RAMP,
1710                                     0x1C, 0x0C);
1711                 snd_soc_update_bits(codec, WCD9335_ANA_MICB2_RAMP,
1712                                     0x80, 0x80);
1713         } else {
1714                 snd_soc_update_bits(codec, WCD9335_ANA_MICB2_RAMP,
1715                                     0x80, 0x00);
1716                 snd_soc_update_bits(codec, WCD9335_ANA_MICB2_RAMP,
1717                                     0x1C, 0x00);
1718         }
1719 }
1720
1721 static struct firmware_cal *tasha_get_hwdep_fw_cal(struct wcd_mbhc *mbhc,
1722                                                    enum wcd_cal_type type)
1723 {
1724         struct tasha_priv *tasha;
1725         struct firmware_cal *hwdep_cal;
1726         struct snd_soc_codec *codec = mbhc->codec;
1727
1728         if (!codec) {
1729                 pr_err("%s: NULL codec pointer\n", __func__);
1730                 return NULL;
1731         }
1732         tasha = snd_soc_codec_get_drvdata(codec);
1733         hwdep_cal = wcdcal_get_fw_cal(tasha->fw_data, type);
1734         if (!hwdep_cal)
1735                 dev_err(codec->dev, "%s: cal not sent by %d\n",
1736                         __func__, type);
1737
1738         return hwdep_cal;
1739 }
1740
1741 static int tasha_mbhc_micb_adjust_voltage(struct snd_soc_codec *codec,
1742                                           int req_volt,
1743                                           int micb_num)
1744 {
1745         int cur_vout_ctl, req_vout_ctl;
1746         int micb_reg, micb_val, micb_en;
1747
1748         switch (micb_num) {
1749         case MIC_BIAS_1:
1750                 micb_reg = WCD9335_ANA_MICB1;
1751                 break;
1752         case MIC_BIAS_2:
1753                 micb_reg = WCD9335_ANA_MICB2;
1754                 break;
1755         case MIC_BIAS_3:
1756                 micb_reg = WCD9335_ANA_MICB3;
1757                 break;
1758         case MIC_BIAS_4:
1759                 micb_reg = WCD9335_ANA_MICB4;
1760                 break;
1761         default:
1762                 return -EINVAL;
1763         }
1764
1765         /*
1766          * If requested micbias voltage is same as current micbias
1767          * voltage, then just return. Otherwise, adjust voltage as
1768          * per requested value. If micbias is already enabled, then
1769          * to avoid slow micbias ramp-up or down enable pull-up
1770          * momentarily, change the micbias value and then re-enable
1771          * micbias.
1772          */
1773         micb_val = snd_soc_read(codec, micb_reg);
1774         micb_en = (micb_val & 0xC0) >> 6;
1775         cur_vout_ctl = micb_val & 0x3F;
1776
1777         req_vout_ctl = wcd9335_get_micb_vout_ctl_val(req_volt);
1778         if (IS_ERR_VALUE(req_vout_ctl))
1779                 return -EINVAL;
1780         if (cur_vout_ctl == req_vout_ctl)
1781                 return 0;
1782
1783         dev_dbg(codec->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
1784                  __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
1785                  req_volt, micb_en);
1786
1787         if (micb_en == 0x1)
1788                 snd_soc_update_bits(codec, micb_reg, 0xC0, 0x80);
1789
1790         snd_soc_update_bits(codec, micb_reg, 0x3F, req_vout_ctl);
1791
1792         if (micb_en == 0x1) {
1793                 snd_soc_update_bits(codec, micb_reg, 0xC0, 0x40);
1794                 /*
1795                  * Add 2ms delay as per HW requirement after enabling
1796                  * micbias
1797                  */
1798                 usleep_range(2000, 2100);
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int tasha_mbhc_micb_ctrl_threshold_mic(struct snd_soc_codec *codec,
1805                                               int micb_num, bool req_en)
1806 {
1807         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1808         struct wcd9xxx_pdata *pdata = dev_get_platdata(codec->dev->parent);
1809         int rc, micb_mv;
1810
1811         if (micb_num != MIC_BIAS_2)
1812                 return -EINVAL;
1813
1814         /*
1815          * If device tree micbias level is already above the minimum
1816          * voltage needed to detect threshold microphone, then do
1817          * not change the micbias, just return.
1818          */
1819         if (pdata->micbias.micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
1820                 return 0;
1821
1822         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : pdata->micbias.micb2_mv;
1823
1824         mutex_lock(&tasha->micb_lock);
1825         rc = tasha_mbhc_micb_adjust_voltage(codec, micb_mv, MIC_BIAS_2);
1826         mutex_unlock(&tasha->micb_lock);
1827
1828         return rc;
1829 }
1830
1831 static inline void tasha_mbhc_get_result_params(struct wcd9xxx *wcd9xxx,
1832                                                 s16 *d1_a, u16 noff,
1833                                                 int32_t *zdet)
1834 {
1835         int i;
1836         int val, val1;
1837         s16 c1;
1838         s32 x1, d1;
1839         int32_t denom;
1840         int minCode_param[] = {
1841                         3277, 1639, 820, 410, 205, 103, 52, 26
1842         };
1843
1844         regmap_update_bits(wcd9xxx->regmap, WCD9335_ANA_MBHC_ZDET, 0x20, 0x20);
1845         for (i = 0; i < TASHA_ZDET_NUM_MEASUREMENTS; i++) {
1846                 regmap_read(wcd9xxx->regmap, WCD9335_ANA_MBHC_RESULT_2, &val);
1847                 if (val & 0x80)
1848                         break;
1849         }
1850         val = val << 0x8;
1851         regmap_read(wcd9xxx->regmap, WCD9335_ANA_MBHC_RESULT_1, &val1);
1852         val |= val1;
1853         regmap_update_bits(wcd9xxx->regmap, WCD9335_ANA_MBHC_ZDET, 0x20, 0x00);
1854         x1 = TASHA_MBHC_GET_X1(val);
1855         c1 = TASHA_MBHC_GET_C1(val);
1856         /* If ramp is not complete, give additional 5ms */
1857         if ((c1 < 2) && x1)
1858                 usleep_range(5000, 5050);
1859
1860         if (!c1 || !x1) {
1861                 dev_dbg(wcd9xxx->dev,
1862                         "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
1863                         __func__, c1, x1);
1864                 goto ramp_down;
1865         }
1866         d1 = d1_a[c1];
1867         denom = (x1 * d1) - (1 << (14 - noff));
1868         if (denom > 0)
1869                 *zdet = (TASHA_MBHC_ZDET_CONST * 1000) / denom;
1870         else if (x1 < minCode_param[noff])
1871                 *zdet = TASHA_ZDET_FLOATING_IMPEDANCE;
1872
1873         dev_dbg(wcd9xxx->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
1874                 __func__, d1, c1, x1, *zdet);
1875 ramp_down:
1876         i = 0;
1877         while (x1) {
1878                 regmap_bulk_read(wcd9xxx->regmap,
1879                                  WCD9335_ANA_MBHC_RESULT_1, (u8 *)&val, 2);
1880                 x1 = TASHA_MBHC_GET_X1(val);
1881                 i++;
1882                 if (i == TASHA_ZDET_NUM_MEASUREMENTS)
1883                         break;
1884         }
1885 }
1886
1887 /*
1888  * tasha_mbhc_zdet_gpio_ctrl: Register callback function for
1889  * controlling the switch on hifi amps. Default switch state
1890  * will put a 51ohm load in parallel to the hph load. So,
1891  * impedance detection function will pull the gpio high
1892  * to make the switch open.
1893  *
1894  * @zdet_gpio_cb: callback function from machine driver
1895  * @codec: Codec instance
1896  *
1897  * Return: none
1898  */
1899 void tasha_mbhc_zdet_gpio_ctrl(
1900                 int (*zdet_gpio_cb)(struct snd_soc_codec *codec, bool high),
1901                 struct snd_soc_codec *codec)
1902 {
1903         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1904
1905         tasha->zdet_gpio_cb = zdet_gpio_cb;
1906 }
1907 EXPORT_SYMBOL(tasha_mbhc_zdet_gpio_ctrl);
1908
1909 static void tasha_mbhc_zdet_ramp(struct snd_soc_codec *codec,
1910                                  struct tasha_mbhc_zdet_param *zdet_param,
1911                                  int32_t *zl, int32_t *zr, s16 *d1_a)
1912 {
1913         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
1914         int32_t zdet = 0;
1915
1916         snd_soc_update_bits(codec, WCD9335_MBHC_ZDET_ANA_CTL, 0x70,
1917                             zdet_param->ldo_ctl << 4);
1918         snd_soc_update_bits(codec, WCD9335_ANA_MBHC_BTN5, 0xFC,
1919                             zdet_param->btn5);
1920         snd_soc_update_bits(codec, WCD9335_ANA_MBHC_BTN6, 0xFC,
1921                             zdet_param->btn6);
1922         snd_soc_update_bits(codec, WCD9335_ANA_MBHC_BTN7, 0xFC,
1923                             zdet_param->btn7);
1924         snd_soc_update_bits(codec, WCD9335_MBHC_ZDET_ANA_CTL, 0x0F,
1925                             zdet_param->noff);
1926         snd_soc_update_bits(codec, WCD9335_MBHC_ZDET_RAMP_CTL, 0x0F,
1927                             zdet_param->nshift);
1928
1929         if (!zl)
1930                 goto z_right;
1931         /* Start impedance measurement for HPH_L */
1932         regmap_update_bits(wcd9xxx->regmap,
1933                            WCD9335_ANA_MBHC_ZDET, 0x80, 0x80);
1934         dev_dbg(wcd9xxx->dev, "%s: ramp for HPH_L, noff = %d\n",
1935                                         __func__, zdet_param->noff);
1936         tasha_mbhc_get_result_params(wcd9xxx, d1_a, zdet_param->noff, &zdet);
1937         regmap_update_bits(wcd9xxx->regmap,
1938                            WCD9335_ANA_MBHC_ZDET, 0x80, 0x00);
1939
1940         *zl = zdet;
1941
1942 z_right:
1943         if (!zr)
1944                 return;
1945         /* Start impedance measurement for HPH_R */
1946         regmap_update_bits(wcd9xxx->regmap,
1947                            WCD9335_ANA_MBHC_ZDET, 0x40, 0x40);
1948         dev_dbg(wcd9xxx->dev, "%s: ramp for HPH_R, noff = %d\n",
1949                                         __func__, zdet_param->noff);
1950         tasha_mbhc_get_result_params(wcd9xxx, d1_a, zdet_param->noff, &zdet);
1951         regmap_update_bits(wcd9xxx->regmap,
1952                            WCD9335_ANA_MBHC_ZDET, 0x40, 0x00);
1953
1954         *zr = zdet;
1955 }
1956
1957 static inline void tasha_wcd_mbhc_qfuse_cal(struct snd_soc_codec *codec,
1958                                         int32_t *z_val, int flag_l_r)
1959 {
1960         s16 q1;
1961         int q1_cal;
1962
1963         if (*z_val < (TASHA_ZDET_VAL_400/1000))
1964                 q1 = snd_soc_read(codec,
1965                         WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
1966         else
1967                 q1 = snd_soc_read(codec,
1968                         WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
1969         if (q1 & 0x80)
1970                 q1_cal = (10000 - ((q1 & 0x7F) * 25));
1971         else
1972                 q1_cal = (10000 + (q1 * 25));
1973         if (q1_cal > 0)
1974                 *z_val = ((*z_val) * 10000) / q1_cal;
1975 }
1976
1977 static void tasha_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
1978                                           uint32_t *zr)
1979 {
1980         struct snd_soc_codec *codec = mbhc->codec;
1981         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
1982         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
1983         s16 reg0, reg1, reg2, reg3, reg4;
1984         int32_t z1L, z1R, z1Ls;
1985         int zMono, z_diff1, z_diff2;
1986         bool is_fsm_disable = false;
1987         bool is_change = false;
1988         struct tasha_mbhc_zdet_param zdet_param[] = {
1989                 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
1990                 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
1991                 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
1992                 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
1993         };
1994         struct tasha_mbhc_zdet_param *zdet_param_ptr = NULL;
1995         s16 d1_a[][4] = {
1996                 {0, 30, 90, 30},
1997                 {0, 30, 30, 5},
1998                 {0, 30, 30, 5},
1999                 {0, 30, 30, 5},
2000         };
2001         s16 *d1 = NULL;
2002
2003         if (!TASHA_IS_2_0(wcd9xxx)) {
2004                 dev_dbg(codec->dev, "%s: Z-det is not supported for this codec version\n",
2005                                         __func__);
2006                 *zl = 0;
2007                 *zr = 0;
2008                 return;
2009         }
2010         WCD_MBHC_RSC_ASSERT_LOCKED(mbhc);
2011
2012         if (tasha->zdet_gpio_cb)
2013                 is_change = tasha->zdet_gpio_cb(codec, true);
2014
2015         reg0 = snd_soc_read(codec, WCD9335_ANA_MBHC_BTN5);
2016         reg1 = snd_soc_read(codec, WCD9335_ANA_MBHC_BTN6);
2017         reg2 = snd_soc_read(codec, WCD9335_ANA_MBHC_BTN7);
2018         reg3 = snd_soc_read(codec, WCD9335_MBHC_CTL_1);
2019         reg4 = snd_soc_read(codec, WCD9335_MBHC_ZDET_ANA_CTL);
2020
2021         if (snd_soc_read(codec, WCD9335_ANA_MBHC_ELECT) & 0x80) {
2022                 is_fsm_disable = true;
2023                 regmap_update_bits(wcd9xxx->regmap,
2024                                    WCD9335_ANA_MBHC_ELECT, 0x80, 0x00);
2025         }
2026
2027         /* For NO-jack, disable L_DET_EN before Z-det measurements */
2028         if (mbhc->hphl_swh)
2029                 regmap_update_bits(wcd9xxx->regmap,
2030                                    WCD9335_ANA_MBHC_MECH, 0x80, 0x00);
2031
2032         /* Enable AZ */
2033         snd_soc_update_bits(codec, WCD9335_MBHC_CTL_1, 0x0C, 0x04);
2034         /* Turn off 100k pull down on HPHL */
2035         regmap_update_bits(wcd9xxx->regmap,
2036                            WCD9335_ANA_MBHC_MECH, 0x01, 0x00);
2037
2038         /* First get impedance on Left */
2039         d1 = d1_a[1];
2040         zdet_param_ptr = &zdet_param[1];
2041         tasha_mbhc_zdet_ramp(codec, zdet_param_ptr, &z1L, NULL, d1);
2042
2043         if (!TASHA_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2044                 goto left_ch_impedance;
2045
2046         /* second ramp for left ch */
2047         if (z1L < TASHA_ZDET_VAL_32) {
2048                 zdet_param_ptr = &zdet_param[0];
2049                 d1 = d1_a[0];
2050         } else if ((z1L > TASHA_ZDET_VAL_400) && (z1L <= TASHA_ZDET_VAL_1200)) {
2051                 zdet_param_ptr = &zdet_param[2];
2052                 d1 = d1_a[2];
2053         } else if (z1L > TASHA_ZDET_VAL_1200) {
2054                 zdet_param_ptr = &zdet_param[3];
2055                 d1 = d1_a[3];
2056         }
2057         tasha_mbhc_zdet_ramp(codec, zdet_param_ptr, &z1L, NULL, d1);
2058
2059 left_ch_impedance:
2060         if ((z1L == TASHA_ZDET_FLOATING_IMPEDANCE) ||
2061                 (z1L > TASHA_ZDET_VAL_100K)) {
2062                 *zl = TASHA_ZDET_FLOATING_IMPEDANCE;
2063                 zdet_param_ptr = &zdet_param[1];
2064                 d1 = d1_a[1];
2065         } else {
2066                 *zl = z1L/1000;
2067                 tasha_wcd_mbhc_qfuse_cal(codec, zl, 0);
2068         }
2069         dev_dbg(codec->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2070                                 __func__, *zl);
2071
2072         /* start of right impedance ramp and calculation */
2073         tasha_mbhc_zdet_ramp(codec, zdet_param_ptr, NULL, &z1R, d1);
2074         if (TASHA_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2075                 if (((z1R > TASHA_ZDET_VAL_1200) &&
2076                         (zdet_param_ptr->noff == 0x6)) ||
2077                         ((*zl) != TASHA_ZDET_FLOATING_IMPEDANCE))
2078                         goto right_ch_impedance;
2079                 /* second ramp for right ch */
2080                 if (z1R < TASHA_ZDET_VAL_32) {
2081                         zdet_param_ptr = &zdet_param[0];
2082                         d1 = d1_a[0];
2083                 } else if ((z1R > TASHA_ZDET_VAL_400) &&
2084                         (z1R <= TASHA_ZDET_VAL_1200)) {
2085                         zdet_param_ptr = &zdet_param[2];
2086                         d1 = d1_a[2];
2087                 } else if (z1R > TASHA_ZDET_VAL_1200) {
2088                         zdet_param_ptr = &zdet_param[3];
2089                         d1 = d1_a[3];
2090                 }
2091                 tasha_mbhc_zdet_ramp(codec, zdet_param_ptr, NULL, &z1R, d1);
2092         }
2093 right_ch_impedance:
2094         if ((z1R == TASHA_ZDET_FLOATING_IMPEDANCE) ||
2095                 (z1R > TASHA_ZDET_VAL_100K)) {
2096                 *zr = TASHA_ZDET_FLOATING_IMPEDANCE;
2097         } else {
2098                 *zr = z1R/1000;
2099                 tasha_wcd_mbhc_qfuse_cal(codec, zr, 1);
2100         }
2101         dev_dbg(codec->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2102                                 __func__, *zr);
2103
2104         /* mono/stereo detection */
2105         if ((*zl == TASHA_ZDET_FLOATING_IMPEDANCE) &&
2106                 (*zr == TASHA_ZDET_FLOATING_IMPEDANCE)) {
2107                 dev_dbg(codec->dev,
2108                         "%s: plug type is invalid or extension cable\n",
2109                         __func__);
2110                 goto zdet_complete;
2111         }
2112         if ((*zl == TASHA_ZDET_FLOATING_IMPEDANCE) ||
2113             (*zr == TASHA_ZDET_FLOATING_IMPEDANCE) ||
2114             ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2115             ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2116                 dev_dbg(codec->dev,
2117                         "%s: Mono plug type with one ch floating or shorted to GND\n",
2118                         __func__);
2119                 mbhc->hph_type = WCD_MBHC_HPH_MONO;
2120                 goto zdet_complete;
2121         }
2122         snd_soc_update_bits(codec, WCD9335_HPH_R_ATEST, 0x02, 0x02);
2123         snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x40, 0x01);
2124         if (*zl < (TASHA_ZDET_VAL_32/1000))
2125                 tasha_mbhc_zdet_ramp(codec, &zdet_param[0], &z1Ls, NULL, d1);
2126         else
2127                 tasha_mbhc_zdet_ramp(codec, &zdet_param[1], &z1Ls, NULL, d1);
2128         snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x40, 0x00);
2129         snd_soc_update_bits(codec, WCD9335_HPH_R_ATEST, 0x02, 0x00);
2130         z1Ls /= 1000;
2131         tasha_wcd_mbhc_qfuse_cal(codec, &z1Ls, 0);
2132         /* parallel of left Z and 9 ohm pull down resistor */
2133         zMono = ((*zl) * 9) / ((*zl) + 9);
2134         z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2135         z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2136         if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2137                 dev_dbg(codec->dev, "%s: stereo plug type detected\n",
2138                                 __func__);
2139                 mbhc->hph_type = WCD_MBHC_HPH_STEREO;
2140         } else {
2141                 dev_dbg(codec->dev, "%s: MONO plug type detected\n",
2142                          __func__);
2143                 mbhc->hph_type = WCD_MBHC_HPH_MONO;
2144         }
2145
2146 zdet_complete:
2147         snd_soc_write(codec, WCD9335_ANA_MBHC_BTN5, reg0);
2148         snd_soc_write(codec, WCD9335_ANA_MBHC_BTN6, reg1);
2149         snd_soc_write(codec, WCD9335_ANA_MBHC_BTN7, reg2);
2150         /* Turn on 100k pull down on HPHL */
2151         regmap_update_bits(wcd9xxx->regmap,
2152                            WCD9335_ANA_MBHC_MECH, 0x01, 0x01);
2153
2154         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2155         if (mbhc->hphl_swh)
2156                 regmap_update_bits(wcd9xxx->regmap,
2157                                    WCD9335_ANA_MBHC_MECH, 0x80, 0x80);
2158
2159         snd_soc_write(codec, WCD9335_MBHC_ZDET_ANA_CTL, reg4);
2160         snd_soc_write(codec, WCD9335_MBHC_CTL_1, reg3);
2161         if (is_fsm_disable)
2162                 regmap_update_bits(wcd9xxx->regmap,
2163                                    WCD9335_ANA_MBHC_ELECT, 0x80, 0x80);
2164         if (tasha->zdet_gpio_cb && is_change)
2165                 tasha->zdet_gpio_cb(codec, false);
2166 }
2167
2168 static void tasha_mbhc_gnd_det_ctrl(struct snd_soc_codec *codec, bool enable)
2169 {
2170         if (enable) {
2171                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_MECH,
2172                                     0x02, 0x02);
2173                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_MECH,
2174                                     0x40, 0x40);
2175         } else {
2176                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_MECH,
2177                                     0x40, 0x00);
2178                 snd_soc_update_bits(codec, WCD9335_ANA_MBHC_MECH,
2179                                     0x02, 0x00);
2180         }
2181 }
2182
2183 static void tasha_mbhc_hph_pull_down_ctrl(struct snd_soc_codec *codec,
2184                                           bool enable)
2185 {
2186         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2187
2188         if (enable) {
2189                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2,
2190                                     0x40, 0x40);
2191                 if (TASHA_IS_2_0(tasha->wcd9xxx))
2192                         snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2,
2193                                             0x10, 0x10);
2194         } else {
2195                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2,
2196                                     0x40, 0x00);
2197                 if (TASHA_IS_2_0(tasha->wcd9xxx))
2198                         snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2,
2199                                             0x10, 0x00);
2200         }
2201 }
2202
2203 static void tasha_mbhc_moisture_config(struct wcd_mbhc *mbhc)
2204 {
2205         struct snd_soc_codec *codec = mbhc->codec;
2206
2207         if (mbhc->moist_vref == V_OFF)
2208                 return;
2209
2210         /* Donot enable moisture detection if jack type is NC */
2211         if (!mbhc->hphl_swh) {
2212                 dev_dbg(codec->dev, "%s: disable moisture detection for NC\n",
2213                         __func__);
2214                 return;
2215         }
2216
2217         snd_soc_update_bits(codec, WCD9335_MBHC_CTL_2,
2218                             0x0C, mbhc->moist_vref << 2);
2219         tasha_mbhc_hph_l_pull_up_control(codec, mbhc->moist_iref);
2220 }
2221
2222 static void tasha_update_anc_state(struct snd_soc_codec *codec, bool enable,
2223                                    int anc_num)
2224 {
2225         if (enable)
2226                 snd_soc_update_bits(codec, WCD9335_CDC_RX1_RX_PATH_CFG0 +
2227                                 (20 * anc_num), 0x10, 0x10);
2228         else
2229                 snd_soc_update_bits(codec, WCD9335_CDC_RX1_RX_PATH_CFG0 +
2230                                 (20 * anc_num), 0x10, 0x00);
2231 }
2232
2233 static bool tasha_is_anc_on(struct wcd_mbhc *mbhc)
2234 {
2235         bool anc_on = false;
2236         u16 ancl, ancr;
2237
2238         ancl =
2239         (snd_soc_read(mbhc->codec, WCD9335_CDC_RX1_RX_PATH_CFG0)) & 0x10;
2240         ancr =
2241         (snd_soc_read(mbhc->codec, WCD9335_CDC_RX2_RX_PATH_CFG0)) & 0x10;
2242
2243         anc_on = !!(ancl | ancr);
2244
2245         return anc_on;
2246 }
2247
2248 static const struct wcd_mbhc_cb mbhc_cb = {
2249         .request_irq = tasha_mbhc_request_irq,
2250         .irq_control = tasha_mbhc_irq_control,
2251         .free_irq = tasha_mbhc_free_irq,
2252         .clk_setup = tasha_mbhc_clk_setup,
2253         .map_btn_code_to_num = tasha_mbhc_btn_to_num,
2254         .enable_mb_source = tasha_enable_ext_mb_source,
2255         .mbhc_bias = tasha_mbhc_mbhc_bias_control,
2256         .set_btn_thr = tasha_mbhc_program_btn_thr,
2257         .lock_sleep = tasha_mbhc_lock_sleep,
2258         .register_notifier = tasha_mbhc_register_notifier,
2259         .micbias_enable_status = tasha_mbhc_micb_en_status,
2260         .hph_pa_on_status = tasha_mbhc_hph_pa_on_status,
2261         .hph_pull_up_control = tasha_mbhc_hph_l_pull_up_control,
2262         .mbhc_micbias_control = tasha_mbhc_request_micbias,
2263         .mbhc_micb_ramp_control = tasha_mbhc_micb_ramp_control,
2264         .get_hwdep_fw_cal = tasha_get_hwdep_fw_cal,
2265         .mbhc_micb_ctrl_thr_mic = tasha_mbhc_micb_ctrl_threshold_mic,
2266         .compute_impedance = tasha_wcd_mbhc_calc_impedance,
2267         .mbhc_gnd_det_ctrl = tasha_mbhc_gnd_det_ctrl,
2268         .hph_pull_down_ctrl = tasha_mbhc_hph_pull_down_ctrl,
2269         .mbhc_moisture_config = tasha_mbhc_moisture_config,
2270         .update_anc_state = tasha_update_anc_state,
2271         .is_anc_on = tasha_is_anc_on,
2272 };
2273
2274 static int tasha_get_anc_slot(struct snd_kcontrol *kcontrol,
2275         struct snd_ctl_elem_value *ucontrol)
2276 {
2277         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2278         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2279
2280         ucontrol->value.integer.value[0] = tasha->anc_slot;
2281         return 0;
2282 }
2283
2284 static int tasha_put_anc_slot(struct snd_kcontrol *kcontrol,
2285         struct snd_ctl_elem_value *ucontrol)
2286 {
2287         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2288         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2289
2290         tasha->anc_slot = ucontrol->value.integer.value[0];
2291         return 0;
2292 }
2293
2294 static int tasha_get_anc_func(struct snd_kcontrol *kcontrol,
2295         struct snd_ctl_elem_value *ucontrol)
2296 {
2297         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2298         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2299
2300         ucontrol->value.integer.value[0] = (tasha->anc_func == true ? 1 : 0);
2301         return 0;
2302 }
2303
2304 static int tasha_put_anc_func(struct snd_kcontrol *kcontrol,
2305         struct snd_ctl_elem_value *ucontrol)
2306 {
2307         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2308         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2309         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2310
2311         mutex_lock(&tasha->codec_mutex);
2312         tasha->anc_func = (!ucontrol->value.integer.value[0] ? false : true);
2313
2314         dev_dbg(codec->dev, "%s: anc_func %x", __func__, tasha->anc_func);
2315
2316         if (tasha->anc_func == true) {
2317                 snd_soc_dapm_enable_pin(dapm, "ANC LINEOUT2 PA");
2318                 snd_soc_dapm_enable_pin(dapm, "ANC LINEOUT2");
2319                 snd_soc_dapm_enable_pin(dapm, "ANC LINEOUT1 PA");
2320                 snd_soc_dapm_enable_pin(dapm, "ANC LINEOUT1");
2321                 snd_soc_dapm_enable_pin(dapm, "ANC HPHR PA");
2322                 snd_soc_dapm_enable_pin(dapm, "ANC HPHR");
2323                 snd_soc_dapm_enable_pin(dapm, "ANC HPHL PA");
2324                 snd_soc_dapm_enable_pin(dapm, "ANC HPHL");
2325                 snd_soc_dapm_enable_pin(dapm, "ANC EAR PA");
2326                 snd_soc_dapm_enable_pin(dapm, "ANC EAR");
2327                 snd_soc_dapm_enable_pin(dapm, "ANC SPK1 PA");
2328                 snd_soc_dapm_disable_pin(dapm, "LINEOUT2");
2329                 snd_soc_dapm_disable_pin(dapm, "LINEOUT2 PA");
2330                 snd_soc_dapm_disable_pin(dapm, "LINEOUT1");
2331                 snd_soc_dapm_disable_pin(dapm, "LINEOUT1 PA");
2332                 snd_soc_dapm_disable_pin(dapm, "HPHR");
2333                 snd_soc_dapm_disable_pin(dapm, "HPHL");
2334                 snd_soc_dapm_disable_pin(dapm, "HPHR PA");
2335                 snd_soc_dapm_disable_pin(dapm, "HPHL PA");
2336                 snd_soc_dapm_disable_pin(dapm, "EAR PA");
2337                 snd_soc_dapm_disable_pin(dapm, "EAR");
2338         } else {
2339                 snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT2 PA");
2340                 snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT2");
2341                 snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT1 PA");
2342                 snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT1");
2343                 snd_soc_dapm_disable_pin(dapm, "ANC HPHR");
2344                 snd_soc_dapm_disable_pin(dapm, "ANC HPHL");
2345                 snd_soc_dapm_disable_pin(dapm, "ANC HPHR PA");
2346                 snd_soc_dapm_disable_pin(dapm, "ANC HPHL PA");
2347                 snd_soc_dapm_disable_pin(dapm, "ANC EAR PA");
2348                 snd_soc_dapm_disable_pin(dapm, "ANC EAR");
2349                 snd_soc_dapm_disable_pin(dapm, "ANC SPK1 PA");
2350                 snd_soc_dapm_enable_pin(dapm, "LINEOUT2");
2351                 snd_soc_dapm_enable_pin(dapm, "LINEOUT2 PA");
2352                 snd_soc_dapm_enable_pin(dapm, "LINEOUT1");
2353                 snd_soc_dapm_enable_pin(dapm, "LINEOUT1 PA");
2354                 snd_soc_dapm_enable_pin(dapm, "HPHR");
2355                 snd_soc_dapm_enable_pin(dapm, "HPHL");
2356                 snd_soc_dapm_enable_pin(dapm, "HPHR PA");
2357                 snd_soc_dapm_enable_pin(dapm, "HPHL PA");
2358                 snd_soc_dapm_enable_pin(dapm, "EAR PA");
2359                 snd_soc_dapm_enable_pin(dapm, "EAR");
2360         }
2361         mutex_unlock(&tasha->codec_mutex);
2362         snd_soc_dapm_sync(dapm);
2363         return 0;
2364 }
2365
2366 static int tasha_get_clkmode(struct snd_kcontrol *kcontrol,
2367                             struct snd_ctl_elem_value *ucontrol)
2368 {
2369         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2370         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2371
2372         ucontrol->value.enumerated.item[0] = tasha->clk_mode;
2373         dev_dbg(codec->dev, "%s: clk_mode: %d\n", __func__, tasha->clk_mode);
2374
2375         return 0;
2376 }
2377
2378 static int tasha_put_clkmode(struct snd_kcontrol *kcontrol,
2379                             struct snd_ctl_elem_value *ucontrol)
2380 {
2381         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2382         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
2383
2384         tasha->clk_mode = ucontrol->value.enumerated.item[0];
2385         dev_dbg(codec->dev, "%s: clk_mode: %d\n", __func__, tasha->clk_mode);
2386
2387         return 0;
2388 }
2389
2390 static int tasha_get_iir_enable_audio_mixer(
2391                                         struct snd_kcontrol *kcontrol,
2392                                         struct snd_ctl_elem_value *ucontrol)
2393 {
2394         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2395         int iir_idx = ((struct soc_multi_mixer_control *)
2396                                         kcontrol->private_value)->reg;
2397         int band_idx = ((struct soc_multi_mixer_control *)
2398                                         kcontrol->private_value)->shift;
2399         /* IIR filter band registers are at integer multiples of 16 */
2400         u16 iir_reg = WCD9335_CDC_SIDETONE_IIR0_IIR_CTL + 16 * iir_idx;
2401
2402         ucontrol->value.integer.value[0] = (snd_soc_read(codec, iir_reg) &
2403                                             (1 << band_idx)) != 0;
2404
2405         dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
2406                 iir_idx, band_idx,
2407                 (uint32_t)ucontrol->value.integer.value[0]);
2408         return 0;
2409 }
2410
2411 static int tasha_hph_impedance_get(struct snd_kcontrol *kcontrol,
2412                                    struct snd_ctl_elem_value *ucontrol)
2413 {
2414         uint32_t zl, zr;
2415         bool hphr;
2416         struct soc_multi_mixer_control *mc;
2417         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2418         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
2419
2420         mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
2421         hphr = mc->shift;
2422         wcd_mbhc_get_impedance(&priv->mbhc, &zl, &zr);
2423         dev_dbg(codec->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2424         ucontrol->value.integer.value[0] = hphr ? zr : zl;
2425
2426         return 0;
2427 }
2428
2429 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2430         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
2431                        tasha_hph_impedance_get, NULL),
2432         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
2433                        tasha_hph_impedance_get, NULL),
2434 };
2435
2436 static int tasha_get_hph_type(struct snd_kcontrol *kcontrol,
2437                                 struct snd_ctl_elem_value *ucontrol)
2438 {
2439         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2440         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
2441         struct wcd_mbhc *mbhc;
2442
2443         if (!priv) {
2444                 dev_dbg(codec->dev, "%s: wcd9335 private data is NULL\n",
2445                                 __func__);
2446                 return 0;
2447         }
2448
2449         mbhc = &priv->mbhc;
2450         if (!mbhc) {
2451                 dev_dbg(codec->dev, "%s: mbhc not initialized\n", __func__);
2452                 return 0;
2453         }
2454
2455         ucontrol->value.integer.value[0] = (u32) mbhc->hph_type;
2456         dev_dbg(codec->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type);
2457
2458         return 0;
2459 }
2460
2461 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2462         SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
2463                        tasha_get_hph_type, NULL),
2464 };
2465
2466 static int tasha_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
2467                                    struct snd_ctl_elem_value *ucontrol)
2468 {
2469         struct snd_soc_dapm_widget_list *wlist =
2470                                         dapm_kcontrol_get_wlist(kcontrol);
2471         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2472         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2473         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2474
2475         ucontrol->value.integer.value[0] = tasha_p->vi_feed_value;
2476
2477         return 0;
2478 }
2479
2480 static int tasha_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
2481                                    struct snd_ctl_elem_value *ucontrol)
2482 {
2483         struct snd_soc_dapm_widget_list *wlist =
2484                                         dapm_kcontrol_get_wlist(kcontrol);
2485         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2486         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2487         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2488         struct wcd9xxx *core = tasha_p->wcd9xxx;
2489         struct soc_multi_mixer_control *mixer =
2490                 ((struct soc_multi_mixer_control *)kcontrol->private_value);
2491         u32 dai_id = widget->shift;
2492         u32 port_id = mixer->shift;
2493         u32 enable = ucontrol->value.integer.value[0];
2494
2495         dev_dbg(codec->dev, "%s: enable: %d, port_id:%d, dai_id: %d\n",
2496                 __func__, enable, port_id, dai_id);
2497
2498         tasha_p->vi_feed_value = ucontrol->value.integer.value[0];
2499
2500         mutex_lock(&tasha_p->codec_mutex);
2501         if (enable) {
2502                 if (port_id == TASHA_TX14 && !test_bit(VI_SENSE_1,
2503                                                 &tasha_p->status_mask)) {
2504                         list_add_tail(&core->tx_chs[TASHA_TX14].list,
2505                                         &tasha_p->dai[dai_id].wcd9xxx_ch_list);
2506                         set_bit(VI_SENSE_1, &tasha_p->status_mask);
2507                 }
2508                 if (port_id == TASHA_TX15 && !test_bit(VI_SENSE_2,
2509                                                 &tasha_p->status_mask)) {
2510                         list_add_tail(&core->tx_chs[TASHA_TX15].list,
2511                                         &tasha_p->dai[dai_id].wcd9xxx_ch_list);
2512                         set_bit(VI_SENSE_2, &tasha_p->status_mask);
2513                 }
2514         } else {
2515                 if (port_id == TASHA_TX14 && test_bit(VI_SENSE_1,
2516                                         &tasha_p->status_mask)) {
2517                         list_del_init(&core->tx_chs[TASHA_TX14].list);
2518                         clear_bit(VI_SENSE_1, &tasha_p->status_mask);
2519                 }
2520                 if (port_id == TASHA_TX15 && test_bit(VI_SENSE_2,
2521                                         &tasha_p->status_mask)) {
2522                         list_del_init(&core->tx_chs[TASHA_TX15].list);
2523                         clear_bit(VI_SENSE_2, &tasha_p->status_mask);
2524                 }
2525         }
2526         mutex_unlock(&tasha_p->codec_mutex);
2527         snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
2528
2529         return 0;
2530 }
2531
2532 /* virtual port entries */
2533 static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
2534                              struct snd_ctl_elem_value *ucontrol)
2535 {
2536         struct snd_soc_dapm_widget_list *wlist =
2537                                         dapm_kcontrol_get_wlist(kcontrol);
2538         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2539         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2540         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2541
2542         ucontrol->value.integer.value[0] = tasha_p->tx_port_value;
2543         return 0;
2544 }
2545
2546 static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
2547                              struct snd_ctl_elem_value *ucontrol)
2548 {
2549         struct snd_soc_dapm_widget_list *wlist =
2550                                         dapm_kcontrol_get_wlist(kcontrol);
2551         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2552         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2553         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2554         struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
2555         struct snd_soc_dapm_update *update = NULL;
2556         struct soc_multi_mixer_control *mixer =
2557                 ((struct soc_multi_mixer_control *)kcontrol->private_value);
2558         u32 dai_id = widget->shift;
2559         u32 port_id = mixer->shift;
2560         u32 enable = ucontrol->value.integer.value[0];
2561         u32 vtable;
2562
2563
2564         dev_dbg(codec->dev, "%s: wname %s cname %s value %u shift %d item %ld\n",
2565                   __func__,
2566                 widget->name, ucontrol->id.name, tasha_p->tx_port_value,
2567                 widget->shift, ucontrol->value.integer.value[0]);
2568
2569         mutex_lock(&tasha_p->codec_mutex);
2570
2571         if (tasha_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
2572                 if (dai_id != AIF1_CAP) {
2573                         dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
2574                                 __func__);
2575                         mutex_unlock(&tasha_p->codec_mutex);
2576                         return -EINVAL;
2577                 }
2578                 vtable = vport_slim_check_table[dai_id];
2579         } else {
2580                 if (dai_id >= ARRAY_SIZE(vport_i2s_check_table)) {
2581                         dev_err(codec->dev, "%s: dai_id: %d, out of bounds\n",
2582                                 __func__, dai_id);
2583                         mutex_unlock(&tasha_p->codec_mutex);
2584                         return -EINVAL;
2585                 }
2586                 vtable = vport_i2s_check_table[dai_id];
2587         }
2588         switch (dai_id) {
2589         case AIF1_CAP:
2590         case AIF2_CAP:
2591         case AIF3_CAP:
2592                 /* only add to the list if value not set */
2593                 if (enable && !(tasha_p->tx_port_value & 1 << port_id)) {
2594
2595                         if (wcd9xxx_tx_vport_validation(vtable, port_id,
2596                                         tasha_p->dai, NUM_CODEC_DAIS)) {
2597                                 dev_dbg(codec->dev, "%s: TX%u is used by other virtual port\n",
2598                                         __func__, port_id);
2599                                 mutex_unlock(&tasha_p->codec_mutex);
2600                                 return 0;
2601                         }
2602                         tasha_p->tx_port_value |= 1 << port_id;
2603                         list_add_tail(&core->tx_chs[port_id].list,
2604                               &tasha_p->dai[dai_id].wcd9xxx_ch_list
2605                                               );
2606                 } else if (!enable && (tasha_p->tx_port_value &
2607                                         1 << port_id)) {
2608                         tasha_p->tx_port_value &= ~(1 << port_id);
2609                         list_del_init(&core->tx_chs[port_id].list);
2610                 } else {
2611                         if (enable)
2612                                 dev_dbg(codec->dev, "%s: TX%u port is used by\n"
2613                                         "this virtual port\n",
2614                                         __func__, port_id);
2615                         else
2616                                 dev_dbg(codec->dev, "%s: TX%u port is not used by\n"
2617                                         "this virtual port\n",
2618                                         __func__, port_id);
2619                         /* avoid update power function */
2620                         mutex_unlock(&tasha_p->codec_mutex);
2621                         return 0;
2622                 }
2623                 break;
2624         case AIF4_MAD_TX:
2625         case AIF5_CPE_TX:
2626                 break;
2627         default:
2628                 pr_err("Unknown AIF %d\n", dai_id);
2629                 mutex_unlock(&tasha_p->codec_mutex);
2630                 return -EINVAL;
2631         }
2632         pr_debug("%s: name %s sname %s updated value %u shift %d\n", __func__,
2633                 widget->name, widget->sname, tasha_p->tx_port_value,
2634                 widget->shift);
2635
2636         mutex_unlock(&tasha_p->codec_mutex);
2637         snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
2638
2639         return 0;
2640 }
2641
2642 static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
2643                            struct snd_ctl_elem_value *ucontrol)
2644 {
2645         struct snd_soc_dapm_widget_list *wlist =
2646                                         dapm_kcontrol_get_wlist(kcontrol);
2647         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2648         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2649         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2650
2651         ucontrol->value.enumerated.item[0] =
2652                         tasha_p->rx_port_value[widget->shift];
2653         return 0;
2654 }
2655
2656 static const char *const slim_rx_mux_text[] = {
2657         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", "AIF_MIX1_PB"
2658 };
2659
2660 static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
2661                            struct snd_ctl_elem_value *ucontrol)
2662 {
2663         struct snd_soc_dapm_widget_list *wlist =
2664                                         dapm_kcontrol_get_wlist(kcontrol);
2665         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
2666         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
2667         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
2668         struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
2669         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2670         struct snd_soc_dapm_update *update = NULL;
2671         unsigned int rx_port_value;
2672         u32 port_id = widget->shift;
2673
2674         tasha_p->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
2675         rx_port_value = tasha_p->rx_port_value[port_id];
2676
2677         pr_debug("%s: wname %s cname %s value %u shift %d item %ld\n", __func__,
2678                 widget->name, ucontrol->id.name, rx_port_value,
2679                 widget->shift, ucontrol->value.integer.value[0]);
2680
2681         mutex_lock(&tasha_p->codec_mutex);
2682
2683         if (tasha_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
2684                 if (rx_port_value > 2) {
2685                         dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
2686                                 __func__);
2687                         goto err;
2688                 }
2689         }
2690         /* value need to match the Virtual port and AIF number */
2691         switch (rx_port_value) {
2692         case 0:
2693                 list_del_init(&core->rx_chs[port_id].list);
2694                 break;
2695         case 1:
2696                 if (wcd9xxx_rx_vport_validation(port_id +
2697                         TASHA_RX_PORT_START_NUMBER,
2698                         &tasha_p->dai[AIF1_PB].wcd9xxx_ch_list)) {
2699                         dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
2700                                 __func__, port_id);
2701                         goto rtn;
2702                 }
2703                 list_add_tail(&core->rx_chs[port_id].list,
2704                               &tasha_p->dai[AIF1_PB].wcd9xxx_ch_list);
2705                 break;
2706         case 2:
2707                 if (wcd9xxx_rx_vport_validation(port_id +
2708                         TASHA_RX_PORT_START_NUMBER,
2709                         &tasha_p->dai[AIF2_PB].wcd9xxx_ch_list)) {
2710                         dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
2711                                 __func__, port_id);
2712                         goto rtn;
2713                 }
2714                 list_add_tail(&core->rx_chs[port_id].list,
2715                               &tasha_p->dai[AIF2_PB].wcd9xxx_ch_list);
2716                 break;
2717         case 3:
2718                 if (wcd9xxx_rx_vport_validation(port_id +
2719                         TASHA_RX_PORT_START_NUMBER,
2720                         &tasha_p->dai[AIF3_PB].wcd9xxx_ch_list)) {
2721                         dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
2722                                 __func__, port_id);
2723                         goto rtn;
2724                 }
2725                 list_add_tail(&core->rx_chs[port_id].list,
2726                               &tasha_p->dai[AIF3_PB].wcd9xxx_ch_list);
2727                 break;
2728         case 4:
2729                 if (wcd9xxx_rx_vport_validation(port_id +
2730                         TASHA_RX_PORT_START_NUMBER,
2731                         &tasha_p->dai[AIF4_PB].wcd9xxx_ch_list)) {
2732                         dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
2733                                 __func__, port_id);
2734                         goto rtn;
2735                 }
2736                 list_add_tail(&core->rx_chs[port_id].list,
2737                               &tasha_p->dai[AIF4_PB].wcd9xxx_ch_list);
2738                 break;
2739         case 5:
2740                 if (wcd9xxx_rx_vport_validation(port_id +
2741                         TASHA_RX_PORT_START_NUMBER,
2742                         &tasha_p->dai[AIF_MIX1_PB].wcd9xxx_ch_list)) {
2743                         dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
2744                                 __func__, port_id);
2745                         goto rtn;
2746                 }
2747                 list_add_tail(&core->rx_chs[port_id].list,
2748                               &tasha_p->dai[AIF_MIX1_PB].wcd9xxx_ch_list);
2749                 break;
2750         default:
2751                 pr_err("Unknown AIF %d\n", rx_port_value);
2752                 goto err;
2753         }
2754 rtn:
2755         mutex_unlock(&tasha_p->codec_mutex);
2756         snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2757                                         rx_port_value, e, update);
2758
2759         return 0;
2760 err:
2761         mutex_unlock(&tasha_p->codec_mutex);
2762         return -EINVAL;
2763 }
2764
2765 static const struct soc_enum slim_rx_mux_enum =
2766         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
2767
2768 static const struct snd_kcontrol_new slim_rx_mux[TASHA_RX_MAX] = {
2769         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2770                           slim_rx_mux_get, slim_rx_mux_put),
2771         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2772                           slim_rx_mux_get, slim_rx_mux_put),
2773         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2774                           slim_rx_mux_get, slim_rx_mux_put),
2775         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2776                           slim_rx_mux_get, slim_rx_mux_put),
2777         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2778                           slim_rx_mux_get, slim_rx_mux_put),
2779         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2780                           slim_rx_mux_get, slim_rx_mux_put),
2781         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2782                           slim_rx_mux_get, slim_rx_mux_put),
2783         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2784                           slim_rx_mux_get, slim_rx_mux_put),
2785 };
2786
2787 static const struct snd_kcontrol_new aif4_vi_mixer[] = {
2788         SOC_SINGLE_EXT("SPKR_VI_1", SND_SOC_NOPM, TASHA_TX14, 1, 0,
2789                         tasha_vi_feed_mixer_get, tasha_vi_feed_mixer_put),
2790         SOC_SINGLE_EXT("SPKR_VI_2", SND_SOC_NOPM, TASHA_TX15, 1, 0,
2791                         tasha_vi_feed_mixer_get, tasha_vi_feed_mixer_put),
2792 };
2793
2794 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
2795         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, TASHA_TX0, 1, 0,
2796                         slim_tx_mixer_get, slim_tx_mixer_put),
2797         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TASHA_TX1, 1, 0,
2798                         slim_tx_mixer_get, slim_tx_mixer_put),
2799         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TASHA_TX2, 1, 0,
2800                         slim_tx_mixer_get, slim_tx_mixer_put),
2801         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TASHA_TX3, 1, 0,
2802                         slim_tx_mixer_get, slim_tx_mixer_put),
2803         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TASHA_TX4, 1, 0,
2804                         slim_tx_mixer_get, slim_tx_mixer_put),
2805         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TASHA_TX5, 1, 0,
2806                         slim_tx_mixer_get, slim_tx_mixer_put),
2807         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, TASHA_TX6, 1, 0,
2808                         slim_tx_mixer_get, slim_tx_mixer_put),
2809         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, TASHA_TX7, 1, 0,
2810                         slim_tx_mixer_get, slim_tx_mixer_put),
2811         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, TASHA_TX8, 1, 0,
2812                         slim_tx_mixer_get, slim_tx_mixer_put),
2813         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, TASHA_TX9, 1, 0,
2814                         slim_tx_mixer_get, slim_tx_mixer_put),
2815         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, TASHA_TX10, 1, 0,
2816                         slim_tx_mixer_get, slim_tx_mixer_put),
2817         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, TASHA_TX11, 1, 0,
2818                         slim_tx_mixer_get, slim_tx_mixer_put),
2819         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, TASHA_TX13, 1, 0,
2820                         slim_tx_mixer_get, slim_tx_mixer_put),
2821 };
2822
2823 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
2824         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, TASHA_TX0, 1, 0,
2825                         slim_tx_mixer_get, slim_tx_mixer_put),
2826         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TASHA_TX1, 1, 0,
2827                         slim_tx_mixer_get, slim_tx_mixer_put),
2828         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TASHA_TX2, 1, 0,
2829                         slim_tx_mixer_get, slim_tx_mixer_put),
2830         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TASHA_TX3, 1, 0,
2831                         slim_tx_mixer_get, slim_tx_mixer_put),
2832         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TASHA_TX4, 1, 0,
2833                         slim_tx_mixer_get, slim_tx_mixer_put),
2834         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TASHA_TX5, 1, 0,
2835                         slim_tx_mixer_get, slim_tx_mixer_put),
2836         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, TASHA_TX6, 1, 0,
2837                         slim_tx_mixer_get, slim_tx_mixer_put),
2838         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, TASHA_TX7, 1, 0,
2839                         slim_tx_mixer_get, slim_tx_mixer_put),
2840         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, TASHA_TX8, 1, 0,
2841                         slim_tx_mixer_get, slim_tx_mixer_put),
2842         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, TASHA_TX9, 1, 0,
2843                         slim_tx_mixer_get, slim_tx_mixer_put),
2844         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, TASHA_TX10, 1, 0,
2845                         slim_tx_mixer_get, slim_tx_mixer_put),
2846         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, TASHA_TX11, 1, 0,
2847                         slim_tx_mixer_get, slim_tx_mixer_put),
2848         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, TASHA_TX13, 1, 0,
2849                         slim_tx_mixer_get, slim_tx_mixer_put),
2850 };
2851
2852 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
2853         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, TASHA_TX0, 1, 0,
2854                         slim_tx_mixer_get, slim_tx_mixer_put),
2855         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TASHA_TX1, 1, 0,
2856                         slim_tx_mixer_get, slim_tx_mixer_put),
2857         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TASHA_TX2, 1, 0,
2858                         slim_tx_mixer_get, slim_tx_mixer_put),
2859         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TASHA_TX3, 1, 0,
2860                         slim_tx_mixer_get, slim_tx_mixer_put),
2861         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TASHA_TX4, 1, 0,
2862                         slim_tx_mixer_get, slim_tx_mixer_put),
2863         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TASHA_TX5, 1, 0,
2864                         slim_tx_mixer_get, slim_tx_mixer_put),
2865         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, TASHA_TX6, 1, 0,
2866                         slim_tx_mixer_get, slim_tx_mixer_put),
2867         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, TASHA_TX7, 1, 0,
2868                         slim_tx_mixer_get, slim_tx_mixer_put),
2869         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, TASHA_TX8, 1, 0,
2870                         slim_tx_mixer_get, slim_tx_mixer_put),
2871         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, TASHA_TX9, 1, 0,
2872                         slim_tx_mixer_get, slim_tx_mixer_put),
2873         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, TASHA_TX10, 1, 0,
2874                         slim_tx_mixer_get, slim_tx_mixer_put),
2875         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, TASHA_TX11, 1, 0,
2876                         slim_tx_mixer_get, slim_tx_mixer_put),
2877         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, TASHA_TX13, 1, 0,
2878                         slim_tx_mixer_get, slim_tx_mixer_put),
2879 };
2880
2881 static const struct snd_kcontrol_new aif4_mad_mixer[] = {
2882         SOC_SINGLE_EXT("SLIM TX12", SND_SOC_NOPM, TASHA_TX12, 1, 0,
2883                         slim_tx_mixer_get, slim_tx_mixer_put),
2884         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, TASHA_TX13, 1, 0,
2885                         slim_tx_mixer_get, slim_tx_mixer_put),
2886         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, 0, 1, 0,
2887                         slim_tx_mixer_get, slim_tx_mixer_put),
2888
2889 };
2890
2891 static const struct snd_kcontrol_new rx_int1_spline_mix_switch[] = {
2892         SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0)
2893 };
2894
2895 static const struct snd_kcontrol_new rx_int2_spline_mix_switch[] = {
2896         SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0)
2897 };
2898
2899 static const struct snd_kcontrol_new rx_int3_spline_mix_switch[] = {
2900         SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0)
2901 };
2902
2903 static const struct snd_kcontrol_new rx_int4_spline_mix_switch[] = {
2904         SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0)
2905 };
2906
2907 static const struct snd_kcontrol_new rx_int5_spline_mix_switch[] = {
2908         SOC_DAPM_SINGLE("LO3 Switch", SND_SOC_NOPM, 0, 1, 0)
2909 };
2910
2911 static const struct snd_kcontrol_new rx_int6_spline_mix_switch[] = {
2912         SOC_DAPM_SINGLE("LO4 Switch", SND_SOC_NOPM, 0, 1, 0)
2913 };
2914
2915 static const struct snd_kcontrol_new rx_int7_spline_mix_switch[] = {
2916         SOC_DAPM_SINGLE("SPKRL Switch", SND_SOC_NOPM, 0, 1, 0)
2917 };
2918
2919 static const struct snd_kcontrol_new rx_int8_spline_mix_switch[] = {
2920         SOC_DAPM_SINGLE("SPKRR Switch", SND_SOC_NOPM, 0, 1, 0)
2921 };
2922
2923 static const struct snd_kcontrol_new rx_int5_vbat_mix_switch[] = {
2924         SOC_DAPM_SINGLE("LO3 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
2925 };
2926
2927 static const struct snd_kcontrol_new rx_int6_vbat_mix_switch[] = {
2928         SOC_DAPM_SINGLE("LO4 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
2929 };
2930
2931 static const struct snd_kcontrol_new rx_int7_vbat_mix_switch[] = {
2932         SOC_DAPM_SINGLE("SPKRL VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
2933 };
2934
2935 static const struct snd_kcontrol_new rx_int8_vbat_mix_switch[] = {
2936         SOC_DAPM_SINGLE("SPKRR VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
2937 };
2938
2939 static const struct snd_kcontrol_new cpe_in_mix_switch[] = {
2940         SOC_DAPM_SINGLE("MAD_BYPASS", SND_SOC_NOPM, 0, 1, 0)
2941 };
2942
2943
2944
2945 static int tasha_put_iir_enable_audio_mixer(
2946                                         struct snd_kcontrol *kcontrol,
2947                                         struct snd_ctl_elem_value *ucontrol)
2948 {
2949         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2950         int iir_idx = ((struct soc_multi_mixer_control *)
2951                                         kcontrol->private_value)->reg;
2952         int band_idx = ((struct soc_multi_mixer_control *)
2953                                         kcontrol->private_value)->shift;
2954         bool iir_band_en_status;
2955         int value = ucontrol->value.integer.value[0];
2956         u16 iir_reg = WCD9335_CDC_SIDETONE_IIR0_IIR_CTL + 16 * iir_idx;
2957
2958         /* Mask first 5 bits, 6-8 are reserved */
2959         snd_soc_update_bits(codec, iir_reg, (1 << band_idx),
2960                             (value << band_idx));
2961
2962         iir_band_en_status = ((snd_soc_read(codec, iir_reg) &
2963                               (1 << band_idx)) != 0);
2964         pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
2965                 iir_idx, band_idx, iir_band_en_status);
2966         return 0;
2967 }
2968
2969 static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
2970                                 int iir_idx, int band_idx,
2971                                 int coeff_idx)
2972 {
2973         uint32_t value = 0;
2974
2975         /* Address does not automatically update if reading */
2976         snd_soc_write(codec,
2977                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx),
2978                 ((band_idx * BAND_MAX + coeff_idx)
2979                 * sizeof(uint32_t)) & 0x7F);
2980
2981         value |= snd_soc_read(codec,
2982                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx));
2983
2984         snd_soc_write(codec,
2985                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx),
2986                 ((band_idx * BAND_MAX + coeff_idx)
2987                 * sizeof(uint32_t) + 1) & 0x7F);
2988
2989         value |= (snd_soc_read(codec,
2990                                (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL +
2991                                 16 * iir_idx)) << 8);
2992
2993         snd_soc_write(codec,
2994                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx),
2995                 ((band_idx * BAND_MAX + coeff_idx)
2996                 * sizeof(uint32_t) + 2) & 0x7F);
2997
2998         value |= (snd_soc_read(codec,
2999                                (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL +
3000                                 16 * iir_idx)) << 16);
3001
3002         snd_soc_write(codec,
3003                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx),
3004                 ((band_idx * BAND_MAX + coeff_idx)
3005                 * sizeof(uint32_t) + 3) & 0x7F);
3006
3007         /* Mask bits top 2 bits since they are reserved */
3008         value |= ((snd_soc_read(codec,
3009                                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL +
3010                                  16 * iir_idx)) & 0x3F) << 24);
3011
3012         return value;
3013 }
3014
3015 static int tasha_get_iir_band_audio_mixer(
3016                                         struct snd_kcontrol *kcontrol,
3017                                         struct snd_ctl_elem_value *ucontrol)
3018 {
3019         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
3020         int iir_idx = ((struct soc_multi_mixer_control *)
3021                                         kcontrol->private_value)->reg;
3022         int band_idx = ((struct soc_multi_mixer_control *)
3023                                         kcontrol->private_value)->shift;
3024
3025         ucontrol->value.integer.value[0] =
3026                 get_iir_band_coeff(codec, iir_idx, band_idx, 0);
3027         ucontrol->value.integer.value[1] =
3028                 get_iir_band_coeff(codec, iir_idx, band_idx, 1);
3029         ucontrol->value.integer.value[2] =
3030                 get_iir_band_coeff(codec, iir_idx, band_idx, 2);
3031         ucontrol->value.integer.value[3] =
3032                 get_iir_band_coeff(codec, iir_idx, band_idx, 3);
3033         ucontrol->value.integer.value[4] =
3034                 get_iir_band_coeff(codec, iir_idx, band_idx, 4);
3035
3036         pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
3037                 "%s: IIR #%d band #%d b1 = 0x%x\n"
3038                 "%s: IIR #%d band #%d b2 = 0x%x\n"
3039                 "%s: IIR #%d band #%d a1 = 0x%x\n"
3040                 "%s: IIR #%d band #%d a2 = 0x%x\n",
3041                 __func__, iir_idx, band_idx,
3042                 (uint32_t)ucontrol->value.integer.value[0],
3043                 __func__, iir_idx, band_idx,
3044                 (uint32_t)ucontrol->value.integer.value[1],
3045                 __func__, iir_idx, band_idx,
3046                 (uint32_t)ucontrol->value.integer.value[2],
3047                 __func__, iir_idx, band_idx,
3048                 (uint32_t)ucontrol->value.integer.value[3],
3049                 __func__, iir_idx, band_idx,
3050                 (uint32_t)ucontrol->value.integer.value[4]);
3051         return 0;
3052 }
3053
3054 static void set_iir_band_coeff(struct snd_soc_codec *codec,
3055                                 int iir_idx, int band_idx,
3056                                 uint32_t value)
3057 {
3058         snd_soc_write(codec,
3059                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx),
3060                 (value & 0xFF));
3061
3062         snd_soc_write(codec,
3063                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx),
3064                 (value >> 8) & 0xFF);
3065
3066         snd_soc_write(codec,
3067                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx),
3068                 (value >> 16) & 0xFF);
3069
3070         /* Mask top 2 bits, 7-8 are reserved */
3071         snd_soc_write(codec,
3072                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx),
3073                 (value >> 24) & 0x3F);
3074 }
3075
3076 static void tasha_codec_enable_int_port(struct wcd9xxx_codec_dai_data *dai,
3077                                         struct snd_soc_codec *codec)
3078 {
3079         struct wcd9xxx_ch *ch;
3080         int port_num = 0;
3081         unsigned short reg = 0;
3082         u8 val = 0;
3083         struct tasha_priv *tasha_p;
3084
3085         if (!dai || !codec) {
3086                 pr_err("%s: Invalid params\n", __func__);
3087                 return;
3088         }
3089
3090         tasha_p = snd_soc_codec_get_drvdata(codec);
3091         list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
3092                 if (ch->port >= TASHA_RX_PORT_START_NUMBER) {
3093                         port_num = ch->port - TASHA_RX_PORT_START_NUMBER;
3094                         reg = TASHA_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3095                         val = wcd9xxx_interface_reg_read(tasha_p->wcd9xxx,
3096                                 reg);
3097                         if (!(val & BYTE_BIT_MASK(port_num))) {
3098                                 val |= BYTE_BIT_MASK(port_num);
3099                                 wcd9xxx_interface_reg_write(
3100                                         tasha_p->wcd9xxx, reg, val);
3101                                 val = wcd9xxx_interface_reg_read(
3102                                         tasha_p->wcd9xxx, reg);
3103                         }
3104                 } else {
3105                         port_num = ch->port;
3106                         reg = TASHA_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3107                         val = wcd9xxx_interface_reg_read(tasha_p->wcd9xxx,
3108                                 reg);
3109                         if (!(val & BYTE_BIT_MASK(port_num))) {
3110                                 val |= BYTE_BIT_MASK(port_num);
3111                                 wcd9xxx_interface_reg_write(tasha_p->wcd9xxx,
3112                                         reg, val);
3113                                 val = wcd9xxx_interface_reg_read(
3114                                         tasha_p->wcd9xxx, reg);
3115                         }
3116                 }
3117         }
3118 }
3119
3120 static int tasha_codec_enable_slim_chmask(struct wcd9xxx_codec_dai_data *dai,
3121                                           bool up)
3122 {
3123         int ret = 0;
3124         struct wcd9xxx_ch *ch;
3125
3126         if (up) {
3127                 list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
3128                         ret = wcd9xxx_get_slave_port(ch->ch_num);
3129                         if (ret < 0) {
3130                                 pr_err("%s: Invalid slave port ID: %d\n",
3131                                        __func__, ret);
3132                                 ret = -EINVAL;
3133                         } else {
3134                                 set_bit(ret, &dai->ch_mask);
3135                         }
3136                 }
3137         } else {
3138                 ret = wait_event_timeout(dai->dai_wait, (dai->ch_mask == 0),
3139                                          msecs_to_jiffies(
3140                                                 TASHA_SLIM_CLOSE_TIMEOUT));
3141                 if (!ret) {
3142                         pr_err("%s: Slim close tx/rx wait timeout, ch_mask:0x%lx\n",
3143                                 __func__, dai->ch_mask);
3144                         ret = -ETIMEDOUT;
3145                 } else {
3146                         ret = 0;
3147                 }
3148         }
3149         return ret;
3150 }
3151
3152 static int tasha_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
3153                                      struct snd_kcontrol *kcontrol,
3154                                      int event)
3155 {
3156         struct wcd9xxx *core;
3157         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
3158         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
3159         int ret = 0;
3160         struct wcd9xxx_codec_dai_data *dai;
3161
3162         core = dev_get_drvdata(codec->dev->parent);
3163
3164         dev_dbg(codec->dev, "%s: event called! codec name %s num_dai %d\n"
3165                 "stream name %s event %d\n",
3166                 __func__, codec->component.name,
3167                 codec->component.num_dai, w->sname, event);
3168
3169         /* Execute the callback only if interface type is slimbus */
3170         if (tasha_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
3171                 return 0;
3172
3173         dai = &tasha_p->dai[w->shift];
3174         dev_dbg(codec->dev, "%s: w->name %s w->shift %d event %d\n",
3175                  __func__, w->name, w->shift, event);
3176
3177         switch (event) {
3178         case SND_SOC_DAPM_POST_PMU:
3179                 dai->bus_down_in_recovery = false;
3180                 tasha_codec_enable_int_port(dai, codec);
3181                 (void) tasha_codec_enable_slim_chmask(dai, true);
3182                 ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
3183                                               dai->rate, dai->bit_width,
3184                                               &dai->grph);
3185                 break;
3186         case SND_SOC_DAPM_PRE_PMD:
3187                 tasha_codec_vote_max_bw(codec, true);
3188                 break;
3189         case SND_SOC_DAPM_POST_PMD:
3190                 ret = wcd9xxx_disconnect_port(core, &dai->wcd9xxx_ch_list,
3191                                               dai->grph);
3192                 dev_dbg(codec->dev, "%s: Disconnect RX port, ret = %d\n",
3193                         __func__, ret);
3194
3195                 if (!dai->bus_down_in_recovery)
3196                         ret = tasha_codec_enable_slim_chmask(dai, false);
3197                 else
3198                         dev_dbg(codec->dev,
3199                                 "%s: bus in recovery skip enable slim_chmask",
3200                                 __func__);
3201                 ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
3202                                                 dai->grph);
3203                 break;
3204         }
3205         return ret;
3206 }
3207
3208 static int tasha_codec_enable_slimvi_feedback(struct snd_soc_dapm_widget *w,
3209                                               struct snd_kcontrol *kcontrol,
3210                                               int event)
3211 {
3212         struct wcd9xxx *core = NULL;
3213         struct snd_soc_codec *codec = NULL;
3214         struct tasha_priv *tasha_p = NULL;
3215         int ret = 0;
3216         struct wcd9xxx_codec_dai_data *dai = NULL;
3217
3218         if (!w) {
3219                 pr_err("%s invalid params\n", __func__);
3220                 return -EINVAL;
3221         }
3222         codec = snd_soc_dapm_to_codec(w->dapm);
3223         tasha_p = snd_soc_codec_get_drvdata(codec);
3224         core = tasha_p->wcd9xxx;
3225
3226         dev_dbg(codec->dev, "%s: num_dai %d stream name %s\n",
3227                 __func__, codec->component.num_dai, w->sname);
3228
3229         /* Execute the callback only if interface type is slimbus */
3230         if (tasha_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
3231                 dev_err(codec->dev, "%s Interface is not correct", __func__);
3232                 return 0;
3233         }
3234
3235         dev_dbg(codec->dev, "%s(): w->name %s event %d w->shift %d\n",
3236                 __func__, w->name, event, w->shift);
3237         if (w->shift != AIF4_VIFEED) {
3238                 pr_err("%s Error in enabling the tx path\n", __func__);
3239                 ret = -EINVAL;
3240                 goto out_vi;
3241         }
3242         dai = &tasha_p->dai[w->shift];
3243         switch (event) {
3244         case SND_SOC_DAPM_POST_PMU:
3245                 if (test_bit(VI_SENSE_1, &tasha_p->status_mask)) {
3246                         dev_dbg(codec->dev, "%s: spkr1 enabled\n", __func__);
3247                         /* Enable V&I sensing */
3248                         snd_soc_update_bits(codec,
3249                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x20, 0x20);
3250                         snd_soc_update_bits(codec,
3251                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x20,
3252                                 0x20);
3253                         snd_soc_update_bits(codec,
3254                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x0F, 0x00);
3255                         snd_soc_update_bits(codec,
3256                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x0F,
3257                                 0x00);
3258                         snd_soc_update_bits(codec,
3259                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x10, 0x10);
3260                         snd_soc_update_bits(codec,
3261                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x10,
3262                                 0x10);
3263                         snd_soc_update_bits(codec,
3264                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x20, 0x00);
3265                         snd_soc_update_bits(codec,
3266                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x20,
3267                                 0x00);
3268                 }
3269                 if (test_bit(VI_SENSE_2, &tasha_p->status_mask)) {
3270                         pr_debug("%s: spkr2 enabled\n", __func__);
3271                         /* Enable V&I sensing */
3272                         snd_soc_update_bits(codec,
3273                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x20,
3274                                 0x20);
3275                         snd_soc_update_bits(codec,
3276                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x20,
3277                                 0x20);
3278                         snd_soc_update_bits(codec,
3279                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x0F,
3280                                 0x00);
3281                         snd_soc_update_bits(codec,
3282                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x0F,
3283                                 0x00);
3284                         snd_soc_update_bits(codec,
3285                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x10,
3286                                 0x10);
3287                         snd_soc_update_bits(codec,
3288                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x10,
3289                                 0x10);
3290                         snd_soc_update_bits(codec,
3291                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x20,
3292                                 0x00);
3293                         snd_soc_update_bits(codec,
3294                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x20,
3295                                 0x00);
3296                 }
3297                 dai->bus_down_in_recovery = false;
3298                 tasha_codec_enable_int_port(dai, codec);
3299                 (void) tasha_codec_enable_slim_chmask(dai, true);
3300                 ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3301                                               dai->rate, dai->bit_width,
3302                                               &dai->grph);
3303                 break;
3304         case SND_SOC_DAPM_POST_PMD:
3305                 ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3306                                                 dai->grph);
3307                 if (ret)
3308                         dev_err(codec->dev, "%s error in close_slim_sch_tx %d\n",
3309                                 __func__, ret);
3310                 if (!dai->bus_down_in_recovery)
3311                         ret = tasha_codec_enable_slim_chmask(dai, false);
3312                 if (ret < 0) {
3313                         ret = wcd9xxx_disconnect_port(core,
3314                                 &dai->wcd9xxx_ch_list,
3315                                 dai->grph);
3316                         dev_dbg(codec->dev, "%s: Disconnect TX port, ret = %d\n",
3317                                 __func__, ret);
3318                 }
3319                 if (test_bit(VI_SENSE_1, &tasha_p->status_mask)) {
3320                         /* Disable V&I sensing */
3321                         dev_dbg(codec->dev, "%s: spkr1 disabled\n", __func__);
3322                         snd_soc_update_bits(codec,
3323                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x20, 0x20);
3324                         snd_soc_update_bits(codec,
3325                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x20,
3326                                 0x20);
3327                         snd_soc_update_bits(codec,
3328                                 WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x10, 0x00);
3329                         snd_soc_update_bits(codec,
3330                                 WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x10,
3331                                 0x00);
3332                 }
3333                 if (test_bit(VI_SENSE_2, &tasha_p->status_mask)) {
3334                         /* Disable V&I sensing */
3335                         dev_dbg(codec->dev, "%s: spkr2 disabled\n", __func__);
3336                         snd_soc_update_bits(codec,
3337                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x20,
3338                                 0x20);
3339                         snd_soc_update_bits(codec,
3340                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x20,
3341                                 0x20);
3342                         snd_soc_update_bits(codec,
3343                                 WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x10,
3344                                 0x00);
3345                         snd_soc_update_bits(codec,
3346                                 WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x10,
3347                                 0x00);
3348                 }
3349                 break;
3350         }
3351 out_vi:
3352         return ret;
3353 }
3354
3355 /*
3356  * __tasha_codec_enable_slimtx: Enable the slimbus slave port
3357  *                               for TX path
3358  * @codec: Handle to the codec for which the slave port is to be
3359  *         enabled.
3360  * @dai_data: The dai specific data for dai which is enabled.
3361  */
3362 static int __tasha_codec_enable_slimtx(struct snd_soc_codec *codec,
3363                 int event, struct wcd9xxx_codec_dai_data *dai)
3364 {
3365         struct wcd9xxx *core;
3366         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
3367         int ret = 0;
3368
3369         /* Execute the callback only if interface type is slimbus */
3370         if (tasha_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
3371                 return 0;
3372
3373         dev_dbg(codec->dev,
3374                 "%s: event = %d\n", __func__, event);
3375         core = dev_get_drvdata(codec->dev->parent);
3376
3377         switch (event) {
3378         case SND_SOC_DAPM_POST_PMU:
3379                 dai->bus_down_in_recovery = false;
3380                 tasha_codec_enable_int_port(dai, codec);
3381                 (void) tasha_codec_enable_slim_chmask(dai, true);
3382                 ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3383                                               dai->rate, dai->bit_width,
3384                                               &dai->grph);
3385                 break;
3386         case SND_SOC_DAPM_POST_PMD:
3387                 ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3388                                                 dai->grph);
3389                 if (!dai->bus_down_in_recovery)
3390                         ret = tasha_codec_enable_slim_chmask(dai, false);
3391                 if (ret < 0) {
3392                         ret = wcd9xxx_disconnect_port(core,
3393                                                       &dai->wcd9xxx_ch_list,
3394                                                       dai->grph);
3395                         pr_debug("%s: Disconnect TX port, ret = %d\n",
3396                                  __func__, ret);
3397                 }
3398
3399                 break;
3400         }
3401
3402         return ret;
3403 }
3404
3405 static int tasha_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
3406                                      struct snd_kcontrol *kcontrol,
3407                                      int event)
3408 {
3409         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
3410         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
3411         struct wcd9xxx_codec_dai_data *dai;
3412
3413         dev_dbg(codec->dev,
3414                 "%s: w->name %s, w->shift = %d, num_dai %d stream name %s\n",
3415                 __func__, w->name, w->shift,
3416                 codec->component.num_dai, w->sname);
3417
3418         dai = &tasha_p->dai[w->shift];
3419         return __tasha_codec_enable_slimtx(codec, event, dai);
3420 }
3421
3422 static void tasha_codec_cpe_pp_set_cfg(struct snd_soc_codec *codec, int event)
3423 {
3424         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
3425         struct wcd9xxx_codec_dai_data *dai;
3426         u8 bit_width, rate, buf_period;
3427
3428         dai = &tasha_p->dai[AIF4_MAD_TX];
3429         switch (event) {
3430         case SND_SOC_DAPM_POST_PMU:
3431                 switch (dai->bit_width) {
3432                 case 32:
3433                         bit_width = 0xF;
3434                         break;
3435                 case 24:
3436                         bit_width = 0xE;
3437                         break;
3438                 case 20:
3439                         bit_width = 0xD;
3440                         break;
3441                 case 16:
3442                 default:
3443                         bit_width = 0x0;
3444                         break;
3445                 }
3446                 snd_soc_update_bits(codec, WCD9335_CPE_SS_TX_PP_CFG, 0x0F,
3447                                     bit_width);
3448
3449                 switch (dai->rate) {
3450                 case 384000:
3451                         rate = 0x30;
3452                         break;
3453                 case 192000:
3454                         rate = 0x20;
3455                         break;
3456                 case 48000:
3457                         rate = 0x10;
3458                         break;
3459                 case 16000:
3460                 default:
3461                         rate = 0x00;
3462                         break;
3463                 }
3464                 snd_soc_update_bits(codec, WCD9335_CPE_SS_TX_PP_CFG, 0x70,
3465                                     rate);
3466
3467                 buf_period = (dai->rate * (dai->bit_width/8)) / (16*1000);
3468                 snd_soc_update_bits(codec, WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD,
3469                                     0xFF, buf_period);
3470                 dev_dbg(codec->dev, "%s: PP buffer period= 0x%x\n",
3471                         __func__, buf_period);
3472                 break;
3473
3474         case SND_SOC_DAPM_POST_PMD:
3475                 snd_soc_write(codec, WCD9335_CPE_SS_TX_PP_CFG, 0x3C);
3476                 snd_soc_write(codec, WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD, 0x60);
3477                 break;
3478
3479         default:
3480                 break;
3481         }
3482 }
3483
3484 /*
3485  * tasha_codec_get_mad_port_id: Callback function that will be invoked
3486  *      to get the port ID for MAD.
3487  * @codec: Handle to the codec
3488  * @port_id: cpe port_id needs to enable
3489  */
3490 static int tasha_codec_get_mad_port_id(struct snd_soc_codec *codec,
3491                                        u16 *port_id)
3492 {
3493         struct tasha_priv *tasha_p;
3494         struct wcd9xxx_codec_dai_data *dai;
3495         struct wcd9xxx_ch *ch;
3496
3497         if (!port_id || !codec)
3498                 return -EINVAL;
3499
3500         tasha_p = snd_soc_codec_get_drvdata(codec);
3501         if (!tasha_p)
3502                 return -EINVAL;
3503
3504         dai = &tasha_p->dai[AIF4_MAD_TX];
3505         list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
3506                 if (ch->port == TASHA_TX12)
3507                         *port_id = WCD_CPE_AFE_OUT_PORT_2;
3508                 else if (ch->port == TASHA_TX13)
3509                         *port_id = WCD_CPE_AFE_OUT_PORT_4;
3510                 else {
3511                         dev_err(codec->dev, "%s: invalid mad_port = %d\n",
3512                                         __func__, ch->port);
3513                         return -EINVAL;
3514                 }
3515         }
3516         dev_dbg(codec->dev, "%s: port_id = %d\n", __func__, *port_id);
3517
3518         return 0;
3519 }
3520
3521 /*
3522  * tasha_codec_enable_slimtx_mad: Callback function that will be invoked
3523  *      to setup the slave port for MAD.
3524  * @codec: Handle to the codec
3525  * @event: Indicates whether to enable or disable the slave port
3526  */
3527 static int tasha_codec_enable_slimtx_mad(struct snd_soc_codec *codec,
3528                                          u8 event)
3529 {
3530         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
3531         struct wcd9xxx_codec_dai_data *dai;
3532         struct wcd9xxx_ch *ch;
3533         int dapm_event = SND_SOC_DAPM_POST_PMU;
3534         u16 port = 0;
3535         int ret = 0;
3536
3537         dai = &tasha_p->dai[AIF4_MAD_TX];
3538
3539         if (event == 0)
3540                 dapm_event = SND_SOC_DAPM_POST_PMD;
3541
3542         dev_dbg(codec->dev,
3543                 "%s: mad_channel, event = 0x%x\n",
3544                  __func__, event);
3545
3546         list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
3547                 dev_dbg(codec->dev, "%s: mad_port = %d, event = 0x%x\n",
3548                         __func__, ch->port, event);
3549                 if (ch->port == TASHA_TX13) {
3550                         tasha_codec_cpe_pp_set_cfg(codec, dapm_event);
3551                         port = TASHA_TX13;
3552                         break;
3553                 }
3554         }
3555
3556         ret = __tasha_codec_enable_slimtx(codec, dapm_event, dai);
3557
3558         if (port == TASHA_TX13) {
3559                 switch (dapm_event) {
3560                 case SND_SOC_DAPM_POST_PMU:
3561                         snd_soc_update_bits(codec,
3562                                 WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN,
3563                                 0x20, 0x00);
3564                         snd_soc_update_bits(codec,
3565                                 WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG,
3566                                 0x03, 0x02);
3567                         snd_soc_update_bits(codec, WCD9335_CPE_SS_CFG,
3568                                             0x80, 0x80);
3569                         break;
3570                 case SND_SOC_DAPM_POST_PMD:
3571                         snd_soc_update_bits(codec,
3572                                 WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN,
3573                                 0x20, 0x20);
3574                         snd_soc_update_bits(codec,
3575                                 WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG,
3576                                 0x03, 0x00);
3577                         snd_soc_update_bits(codec, WCD9335_CPE_SS_CFG,
3578                                             0x80, 0x00);
3579                         break;
3580                 }
3581         }
3582
3583         return ret;
3584 }
3585
3586 static int tasha_put_iir_band_audio_mixer(
3587                                         struct snd_kcontrol *kcontrol,
3588                                         struct snd_ctl_elem_value *ucontrol)
3589 {
3590         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
3591         int iir_idx = ((struct soc_multi_mixer_control *)
3592                                         kcontrol->private_value)->reg;
3593         int band_idx = ((struct soc_multi_mixer_control *)
3594                                         kcontrol->private_value)->shift;
3595
3596         /*
3597          * Mask top bit it is reserved
3598          * Updates addr automatically for each B2 write
3599          */
3600         snd_soc_write(codec,
3601                 (WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx),
3602                 (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
3603
3604         set_iir_band_coeff(codec, iir_idx, band_idx,
3605                                 ucontrol->value.integer.value[0]);
3606         set_iir_band_coeff(codec, iir_idx, band_idx,
3607                                 ucontrol->value.integer.value[1]);
3608         set_iir_band_coeff(codec, iir_idx, band_idx,
3609                                 ucontrol->value.integer.value[2]);
3610         set_iir_band_coeff(codec, iir_idx, band_idx,
3611                                 ucontrol->value.integer.value[3]);
3612         set_iir_band_coeff(codec, iir_idx, band_idx,
3613                                 ucontrol->value.integer.value[4]);
3614
3615         pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
3616                 "%s: IIR #%d band #%d b1 = 0x%x\n"
3617                 "%s: IIR #%d band #%d b2 = 0x%x\n"
3618                 "%s: IIR #%d band #%d a1 = 0x%x\n"
3619                 "%s: IIR #%d band #%d a2 = 0x%x\n",
3620                 __func__, iir_idx, band_idx,
3621                 get_iir_band_coeff(codec, iir_idx, band_idx, 0),
3622                 __func__, iir_idx, band_idx,
3623                 get_iir_band_coeff(codec, iir_idx, band_idx, 1),
3624                 __func__, iir_idx, band_idx,
3625                 get_iir_band_coeff(codec, iir_idx, band_idx, 2),
3626                 __func__, iir_idx, band_idx,
3627                 get_iir_band_coeff(codec, iir_idx, band_idx, 3),
3628                 __func__, iir_idx, band_idx,
3629                 get_iir_band_coeff(codec, iir_idx, band_idx, 4));
3630         return 0;
3631 }
3632
3633 static int tasha_get_compander(struct snd_kcontrol *kcontrol,
3634                                struct snd_ctl_elem_value *ucontrol)
3635 {
3636
3637         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
3638         int comp = ((struct soc_multi_mixer_control *)
3639                     kcontrol->private_value)->shift;
3640         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
3641
3642         ucontrol->value.integer.value[0] = tasha->comp_enabled[comp];
3643         return 0;
3644 }
3645
3646 static int tasha_set_compander(struct snd_kcontrol *kcontrol,
3647                                struct snd_ctl_elem_value *ucontrol)
3648 {
3649         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
3650         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
3651         int comp = ((struct soc_multi_mixer_control *)
3652                     kcontrol->private_value)->shift;
3653         int value = ucontrol->value.integer.value[0];
3654
3655         pr_debug("%s: Compander %d enable current %d, new %d\n",
3656                  __func__, comp + 1, tasha->comp_enabled[comp], value);
3657         tasha->comp_enabled[comp] = value;
3658
3659         /* Any specific register configuration for compander */
3660         switch (comp) {
3661         case COMPANDER_1:
3662                 /* Set Gain Source Select based on compander enable/disable */
3663                 snd_soc_update_bits(codec, WCD9335_HPH_L_EN, 0x20,
3664                                 (value ? 0x00:0x20));
3665                 break;
3666         case COMPANDER_2:
3667                 snd_soc_update_bits(codec, WCD9335_HPH_R_EN, 0x20,
3668                                 (value ? 0x00:0x20));
3669                 break;
3670         case COMPANDER_3:
3671                 break;
3672         case COMPANDER_4:
3673                 break;
3674         case COMPANDER_5:
3675                 snd_soc_update_bits(codec, WCD9335_SE_LO_LO3_GAIN, 0x20,
3676                                 (value ? 0x00:0x20));
3677                 break;
3678         case COMPANDER_6:
3679                 snd_soc_update_bits(codec, WCD9335_SE_LO_LO4_GAIN, 0x20,
3680                                 (value ? 0x00:0x20));
3681                 break;
3682         case COMPANDER_7:
3683                 break;
3684         case COMPANDER_8:
3685                 break;
3686         default:
3687                 /*
3688                  * if compander is not enabled for any interpolator,
3689                  * it does not cause any audio failure, so do not
3690                  * return error in this case, but just print a log
3691                  */
3692                 dev_warn(codec->dev, "%s: unknown compander: %d\n",
3693                         __func__, comp);
3694         };
3695         return 0;
3696 }
3697
3698 static void tasha_codec_init_flyback(struct snd_soc_codec *codec)
3699 {
3700         snd_soc_update_bits(codec, WCD9335_HPH_L_EN, 0xC0, 0x00);
3701         snd_soc_update_bits(codec, WCD9335_HPH_R_EN, 0xC0, 0x00);
3702         snd_soc_update_bits(codec, WCD9335_RX_BIAS_FLYB_BUFF, 0x0F, 0x00);
3703         snd_soc_update_bits(codec, WCD9335_RX_BIAS_FLYB_BUFF, 0xF0, 0x00);
3704 }
3705
3706 static int tasha_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3707                 struct snd_kcontrol *kcontrol, int event)
3708 {
3709         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
3710         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
3711
3712         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
3713
3714         switch (event) {
3715         case SND_SOC_DAPM_PRE_PMU:
3716                 tasha->rx_bias_count++;
3717                 if (tasha->rx_bias_count == 1) {
3718                         if (TASHA_IS_2_0(tasha->wcd9xxx))
3719                                 tasha_codec_init_flyback(codec);
3720                         snd_soc_update_bits(codec, WCD9335_ANA_RX_SUPPLIES,
3721                                             0x01, 0x01);
3722                 }
3723                 break;
3724         case SND_SOC_DAPM_POST_PMD:
3725                 tasha->rx_bias_count--;
3726                 if (!tasha->rx_bias_count)
3727                         snd_soc_update_bits(codec, WCD9335_ANA_RX_SUPPLIES,
3728                                             0x01, 0x00);
3729                 break;
3730         };
3731         dev_dbg(codec->dev, "%s: Current RX BIAS user count: %d\n", __func__,
3732                 tasha->rx_bias_count);
3733
3734         return 0;
3735 }
3736
3737 static void tasha_realign_anc_coeff(struct snd_soc_codec *codec,
3738                                     u16 reg1, u16 reg2)
3739 {
3740         u8 val1, val2, tmpval1, tmpval2;
3741
3742         snd_soc_write(codec, reg1, 0x00);
3743         tmpval1 = snd_soc_read(codec, reg2);
3744         tmpval2 = snd_soc_read(codec, reg2);
3745         snd_soc_write(codec, reg1, 0x00);
3746         snd_soc_write(codec, reg2, 0xFF);
3747         snd_soc_write(codec, reg1, 0x01);
3748         snd_soc_write(codec, reg2, 0xFF);
3749
3750         snd_soc_write(codec, reg1, 0x00);
3751         val1 = snd_soc_read(codec, reg2);
3752         val2 = snd_soc_read(codec, reg2);
3753
3754         if (val1 == 0x0F && val2 == 0xFF) {
3755                 dev_dbg(codec->dev, "%s: ANC0 co-eff index re-aligned\n",
3756                         __func__);
3757                 snd_soc_read(codec, reg2);
3758                 snd_soc_write(codec, reg1, 0x00);
3759                 snd_soc_write(codec, reg2, tmpval2);
3760                 snd_soc_write(codec, reg1, 0x01);
3761                 snd_soc_write(codec, reg2, tmpval1);
3762         } else if (val1 == 0xFF && val2 == 0x0F) {
3763                 dev_dbg(codec->dev, "%s: ANC1 co-eff index already aligned\n",
3764                         __func__);
3765                 snd_soc_write(codec, reg1, 0x00);
3766                 snd_soc_write(codec, reg2, tmpval1);
3767                 snd_soc_write(codec, reg1, 0x01);
3768                 snd_soc_write(codec, reg2, tmpval2);
3769         } else {
3770                 dev_err(codec->dev, "%s: ANC0 co-eff index not aligned\n",
3771                         __func__);
3772         }
3773 }
3774
3775 static int tasha_codec_enable_anc(struct snd_soc_dapm_widget *w,
3776                                   struct snd_kcontrol *kcontrol, int event)
3777 {
3778         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
3779         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
3780         const char *filename;
3781         const struct firmware *fw;
3782         int i;
3783         int ret = 0;
3784         int num_anc_slots;
3785         struct wcd9xxx_anc_header *anc_head;
3786         struct firmware_cal *hwdep_cal = NULL;
3787         u32 anc_writes_size = 0;
3788         u32 anc_cal_size = 0;
3789         int anc_size_remaining;
3790         u32 *anc_ptr;
3791         u16 reg;
3792         u8 mask, val;
3793         size_t cal_size;
3794         const void *data;
3795
3796         if (!tasha->anc_func)
3797                 return 0;
3798
3799         switch (event) {
3800         case SND_SOC_DAPM_PRE_PMU:
3801                 hwdep_cal = wcdcal_get_fw_cal(tasha->fw_data, WCD9XXX_ANC_CAL);
3802                 if (hwdep_cal) {
3803                         data = hwdep_cal->data;
3804                         cal_size = hwdep_cal->size;
3805                         dev_dbg(codec->dev, "%s: using hwdep calibration\n",
3806                                 __func__);
3807                 } else {
3808                         filename = "wcd9335/wcd9335_anc.bin";
3809                         ret = request_firmware(&fw, filename, codec->dev);
3810                         if (ret != 0) {
3811                                 dev_err(codec->dev,
3812                                 "Failed to acquire ANC data: %d\n", ret);
3813                                 return -ENODEV;
3814                         }
3815                         if (!fw) {
3816                                 dev_err(codec->dev, "failed to get anc fw");
3817                                 return -ENODEV;
3818                         }
3819                         data = fw->data;
3820                         cal_size = fw->size;
3821                         dev_dbg(codec->dev,
3822                         "%s: using request_firmware calibration\n", __func__);
3823                 }
3824                 if (cal_size < sizeof(struct wcd9xxx_anc_header)) {
3825                         dev_err(codec->dev, "Not enough data\n");
3826                         ret = -ENOMEM;
3827                         goto err;
3828                 }
3829                 /* First number is the number of register writes */
3830                 anc_head = (struct wcd9xxx_anc_header *)(data);
3831                 anc_ptr = (u32 *)(data +
3832                                   sizeof(struct wcd9xxx_anc_header));
3833                 anc_size_remaining = cal_size -
3834                                      sizeof(struct wcd9xxx_anc_header);
3835                 num_anc_slots = anc_head->num_anc_slots;
3836
3837                 if (tasha->anc_slot >= num_anc_slots) {
3838                         dev_err(codec->dev, "Invalid ANC slot selected\n");
3839                         ret = -EINVAL;
3840                         goto err;
3841                 }
3842                 for (i = 0; i < num_anc_slots; i++) {
3843                         if (anc_size_remaining < TASHA_PACKED_REG_SIZE) {
3844                                 dev_err(codec->dev,
3845                                         "Invalid register format\n");
3846                                 ret = -EINVAL;
3847                                 goto err;
3848                         }
3849                         anc_writes_size = (u32)(*anc_ptr);
3850                         anc_size_remaining -= sizeof(u32);
3851                         anc_ptr += 1;
3852
3853                         if (anc_writes_size * TASHA_PACKED_REG_SIZE
3854                                 > anc_size_remaining) {
3855                                 dev_err(codec->dev,
3856                                         "Invalid register format\n");
3857                                 ret = -EINVAL;
3858                                 goto err;
3859                         }
3860
3861                         if (tasha->anc_slot == i)
3862                                 break;
3863
3864                         anc_size_remaining -= (anc_writes_size *
3865                                 TASHA_PACKED_REG_SIZE);
3866                         anc_ptr += anc_writes_size;
3867                 }
3868                 if (i == num_anc_slots) {
3869                         dev_err(codec->dev, "Selected ANC slot not present\n");
3870                         ret = -EINVAL;
3871                         goto err;
3872                 }
3873
3874                 i = 0;
3875                 anc_cal_size = anc_writes_size;
3876
3877                 if (!strcmp(w->name, "RX INT0 DAC") ||
3878                     !strcmp(w->name, "ANC SPK1 PA"))
3879                         tasha_realign_anc_coeff(codec,
3880                                         WCD9335_CDC_ANC0_IIR_COEFF_1_CTL,
3881                                         WCD9335_CDC_ANC0_IIR_COEFF_2_CTL);
3882
3883                 if (!strcmp(w->name, "RX INT1 DAC") ||
3884                         !strcmp(w->name, "RX INT3 DAC")) {
3885                         tasha_realign_anc_coeff(codec,
3886                                         WCD9335_CDC_ANC0_IIR_COEFF_1_CTL,
3887                                         WCD9335_CDC_ANC0_IIR_COEFF_2_CTL);
3888                         anc_writes_size = anc_cal_size / 2;
3889                         snd_soc_update_bits(codec,
3890                         WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x39, 0x39);
3891                 } else if (!strcmp(w->name, "RX INT2 DAC") ||
3892                                 !strcmp(w->name, "RX INT4 DAC")) {
3893                         tasha_realign_anc_coeff(codec,
3894                                         WCD9335_CDC_ANC1_IIR_COEFF_1_CTL,
3895                                         WCD9335_CDC_ANC1_IIR_COEFF_2_CTL);
3896                         i = anc_cal_size / 2;
3897                         snd_soc_update_bits(codec,
3898                         WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x39, 0x39);
3899                 }
3900
3901                 for (; i < anc_writes_size; i++) {
3902                         TASHA_CODEC_UNPACK_ENTRY(anc_ptr[i], reg, mask, val);
3903                         snd_soc_write(codec, reg, (val & mask));
3904                 }
3905                 if (!strcmp(w->name, "RX INT1 DAC") ||
3906                         !strcmp(w->name, "RX INT3 DAC")) {
3907                         snd_soc_update_bits(codec,
3908                                 WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x08, 0x08);
3909                 } else if (!strcmp(w->name, "RX INT2 DAC") ||
3910                                 !strcmp(w->name, "RX INT4 DAC")) {
3911                         snd_soc_update_bits(codec,
3912                                 WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x08, 0x08);
3913                 }
3914
3915                 if (!hwdep_cal)
3916                         release_firmware(fw);
3917                 break;
3918         case SND_SOC_DAPM_POST_PMU:
3919                 /* Remove ANC Rx from reset */
3920                 snd_soc_update_bits(codec, WCD9335_CDC_ANC0_CLK_RESET_CTL,
3921                                     0x08, 0x00);
3922                 snd_soc_update_bits(codec, WCD9335_CDC_ANC1_CLK_RESET_CTL,
3923                                     0x08, 0x00);
3924                 break;
3925         case SND_SOC_DAPM_POST_PMD:
3926                 if (!strcmp(w->name, "ANC HPHL PA") ||
3927                     !strcmp(w->name, "ANC EAR PA") ||
3928                     !strcmp(w->name, "ANC SPK1 PA") ||
3929                     !strcmp(w->name, "ANC LINEOUT1 PA")) {
3930                         snd_soc_update_bits(codec,
3931                                 WCD9335_CDC_ANC0_MODE_1_CTL, 0x30, 0x00);
3932                         msleep(50);
3933                         snd_soc_update_bits(codec,
3934                                 WCD9335_CDC_ANC0_MODE_1_CTL, 0x01, 0x00);
3935                         snd_soc_update_bits(codec,
3936                                 WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x38, 0x38);
3937                         snd_soc_update_bits(codec,
3938                                 WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x07, 0x00);
3939                         snd_soc_update_bits(codec,
3940                                 WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x38, 0x00);
3941                 } else if (!strcmp(w->name, "ANC HPHR PA") ||
3942                            !strcmp(w->name, "ANC LINEOUT2 PA")) {
3943                         snd_soc_update_bits(codec,
3944                                 WCD9335_CDC_ANC1_MODE_1_CTL, 0x30, 0x00);
3945                         msleep(50);
3946                         snd_soc_update_bits(codec,
3947                                 WCD9335_CDC_ANC1_MODE_1_CTL, 0x01, 0x00);
3948                         snd_soc_update_bits(codec,
3949                                 WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x38, 0x38);
3950                         snd_soc_update_bits(codec,
3951                                 WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x07, 0x00);
3952                         snd_soc_update_bits(codec,
3953                                 WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x38, 0x00);
3954                 }
3955                 break;
3956         }
3957
3958         return 0;
3959 err:
3960         if (!hwdep_cal)
3961                 release_firmware(fw);
3962         return ret;
3963 }
3964
3965 static void tasha_codec_clear_anc_tx_hold(struct tasha_priv *tasha)
3966 {
3967         if (test_and_clear_bit(ANC_MIC_AMIC1, &tasha->status_mask))
3968                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC1, false);
3969         if (test_and_clear_bit(ANC_MIC_AMIC2, &tasha->status_mask))
3970                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC2, false);
3971         if (test_and_clear_bit(ANC_MIC_AMIC3, &tasha->status_mask))
3972                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC3, false);
3973         if (test_and_clear_bit(ANC_MIC_AMIC4, &tasha->status_mask))
3974                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC4, false);
3975         if (test_and_clear_bit(ANC_MIC_AMIC5, &tasha->status_mask))
3976                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC5, false);
3977         if (test_and_clear_bit(ANC_MIC_AMIC6, &tasha->status_mask))
3978                 tasha_codec_set_tx_hold(tasha->codec, WCD9335_ANA_AMIC6, false);
3979 }
3980
3981 static void tasha_codec_hph_post_pa_config(struct tasha_priv *tasha,
3982                                            int mode, int event)
3983 {
3984         u8 scale_val = 0;
3985
3986         if (!TASHA_IS_2_0(tasha->wcd9xxx))
3987                 return;
3988
3989         switch (event) {
3990         case SND_SOC_DAPM_POST_PMU:
3991                 switch (mode) {
3992                 case CLS_H_HIFI:
3993                         scale_val = 0x3;
3994                         break;
3995                 case CLS_H_LOHIFI:
3996                         scale_val = 0x1;
3997                         break;
3998                 }
3999                 if (tasha->anc_func) {
4000                         /* Clear Tx FE HOLD if both PAs are enabled */
4001                         if ((snd_soc_read(tasha->codec, WCD9335_ANA_HPH) &
4002                              0xC0) == 0xC0) {
4003                                 tasha_codec_clear_anc_tx_hold(tasha);
4004                         }
4005                 }
4006                 break;
4007         case SND_SOC_DAPM_PRE_PMD:
4008                 scale_val = 0x6;
4009                 break;
4010         }
4011
4012         if (scale_val)
4013                 snd_soc_update_bits(tasha->codec, WCD9335_HPH_PA_CTL1, 0x0E,
4014                                     scale_val << 1);
4015         if (SND_SOC_DAPM_EVENT_ON(event)) {
4016                 if (tasha->comp_enabled[COMPANDER_1] ||
4017                     tasha->comp_enabled[COMPANDER_2]) {
4018                         snd_soc_update_bits(tasha->codec, WCD9335_HPH_L_EN,
4019                                             0x20, 0x00);
4020                         snd_soc_update_bits(tasha->codec, WCD9335_HPH_R_EN,
4021                                             0x20, 0x00);
4022                         snd_soc_update_bits(tasha->codec, WCD9335_HPH_AUTO_CHOP,
4023                                             0x20, 0x20);
4024                 }
4025                 snd_soc_update_bits(tasha->codec, WCD9335_HPH_L_EN, 0x1F,
4026                                     tasha->hph_l_gain);
4027                 snd_soc_update_bits(tasha->codec, WCD9335_HPH_R_EN, 0x1F,
4028                                     tasha->hph_r_gain);
4029         }
4030
4031         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4032                 snd_soc_update_bits(tasha->codec, WCD9335_HPH_AUTO_CHOP, 0x20,
4033                                     0x00);
4034         }
4035 }
4036
4037 static void tasha_codec_override(struct snd_soc_codec *codec,
4038                                  int mode,
4039                                  int event)
4040 {
4041         if (mode == CLS_AB) {
4042                 switch (event) {
4043                 case SND_SOC_DAPM_POST_PMU:
4044                         if (!(snd_soc_read(codec,
4045                                         WCD9335_CDC_RX2_RX_PATH_CTL) & 0x10) &&
4046                                 (!(snd_soc_read(codec,
4047                                         WCD9335_CDC_RX1_RX_PATH_CTL) & 0x10)))
4048                                 snd_soc_update_bits(codec,
4049                                         WCD9XXX_A_ANA_RX_SUPPLIES, 0x02, 0x02);
4050                 break;
4051                 case SND_SOC_DAPM_POST_PMD:
4052                         snd_soc_update_bits(codec,
4053                                 WCD9XXX_A_ANA_RX_SUPPLIES, 0x02, 0x00);
4054                 break;
4055                 }
4056         }
4057 }
4058
4059 static int tasha_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4060                                       struct snd_kcontrol *kcontrol,
4061                                       int event)
4062 {
4063         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4064         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4065         int hph_mode = tasha->hph_mode;
4066         int ret = 0;
4067
4068         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4069
4070         switch (event) {
4071         case SND_SOC_DAPM_PRE_PMU:
4072                 if ((!(strcmp(w->name, "ANC HPHR PA"))) &&
4073                     (test_bit(HPH_PA_DELAY, &tasha->status_mask))) {
4074                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0xC0, 0xC0);
4075                 }
4076                 set_bit(HPH_PA_DELAY, &tasha->status_mask);
4077                 if (!(strcmp(w->name, "HPHR PA")))
4078                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x40, 0x40);
4079                 break;
4080         case SND_SOC_DAPM_POST_PMU:
4081                 if (!(strcmp(w->name, "ANC HPHR PA"))) {
4082                         if ((snd_soc_read(codec, WCD9335_ANA_HPH) & 0xC0)
4083                                                         != 0xC0)
4084                                 /*
4085                                  * If PA_EN is not set (potentially in ANC case)
4086                                  * then do nothing for POST_PMU and let left
4087                                  * channel handle everything.
4088                                  */
4089                                 break;
4090                 }
4091                 /*
4092                  * 7ms sleep is required after PA is enabled as per
4093                  * HW requirement
4094                  */
4095                 if (test_bit(HPH_PA_DELAY, &tasha->status_mask)) {
4096                         usleep_range(7000, 7100);
4097                         clear_bit(HPH_PA_DELAY, &tasha->status_mask);
4098                 }
4099                 tasha_codec_hph_post_pa_config(tasha, hph_mode, event);
4100                 snd_soc_update_bits(codec, WCD9335_CDC_RX2_RX_PATH_CTL,
4101                                     0x10, 0x00);
4102                 /* Remove mix path mute if it is enabled */
4103                 if ((snd_soc_read(codec, WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
4104                                   0x10)
4105                         snd_soc_update_bits(codec,
4106                                             WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4107                                             0x10, 0x00);
4108
4109                 if (!(strcmp(w->name, "ANC HPHR PA"))) {
4110                         /* Do everything needed for left channel */
4111                         snd_soc_update_bits(codec, WCD9335_CDC_RX1_RX_PATH_CTL,
4112                                             0x10, 0x00);
4113                         /* Remove mix path mute if it is enabled */
4114                         if ((snd_soc_read(codec,
4115                                           WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
4116                                           0x10)
4117                                 snd_soc_update_bits(codec,
4118                                                 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4119                                                 0x10, 0x00);
4120                         /* Remove ANC Rx from reset */
4121                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4122                 }
4123                 tasha_codec_override(codec, hph_mode, event);
4124                 break;
4125
4126         case SND_SOC_DAPM_PRE_PMD:
4127                 blocking_notifier_call_chain(&tasha->notifier,
4128                                         WCD_EVENT_PRE_HPHR_PA_OFF,
4129                                         &tasha->mbhc);
4130                 tasha_codec_hph_post_pa_config(tasha, hph_mode, event);
4131                 if (!(strcmp(w->name, "ANC HPHR PA")))
4132                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x40, 0x00);
4133                 if (!(strcmp(w->name, "HPHR PA")))
4134                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x40, 0x00);
4135                 break;
4136         case SND_SOC_DAPM_POST_PMD:
4137                 /* 5ms sleep is required after PA is disabled as per
4138                  * HW requirement
4139                  */
4140                 usleep_range(5000, 5500);
4141                 tasha_codec_override(codec, hph_mode, event);
4142                 blocking_notifier_call_chain(&tasha->notifier,
4143                                         WCD_EVENT_POST_HPHR_PA_OFF,
4144                                         &tasha->mbhc);
4145
4146                 if (!(strcmp(w->name, "ANC HPHR PA"))) {
4147                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4148                         snd_soc_update_bits(codec,
4149                                 WCD9335_CDC_RX2_RX_PATH_CFG0, 0x10, 0x00);
4150                 }
4151                 break;
4152         };
4153
4154         return ret;
4155 }
4156
4157 static int tasha_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4158                                       struct snd_kcontrol *kcontrol,
4159                                       int event)
4160 {
4161         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4162         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4163         int hph_mode = tasha->hph_mode;
4164         int ret = 0;
4165
4166         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4167
4168         switch (event) {
4169         case SND_SOC_DAPM_PRE_PMU:
4170                 if ((!(strcmp(w->name, "ANC HPHL PA"))) &&
4171                     (test_bit(HPH_PA_DELAY, &tasha->status_mask))) {
4172                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0xC0, 0xC0);
4173                 }
4174                 if (!(strcmp(w->name, "HPHL PA")))
4175                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x80, 0x80);
4176                 set_bit(HPH_PA_DELAY, &tasha->status_mask);
4177                 break;
4178         case SND_SOC_DAPM_POST_PMU:
4179                 if (!(strcmp(w->name, "ANC HPHL PA"))) {
4180                         if ((snd_soc_read(codec, WCD9335_ANA_HPH) & 0xC0)
4181                                                                 != 0xC0)
4182                                 /*
4183                                  * If PA_EN is not set (potentially in ANC case)
4184                                  * then do nothing for POST_PMU and let right
4185                                  * channel handle everything.
4186                                  */
4187                                 break;
4188                 }
4189                 /*
4190                  * 7ms sleep is required after PA is enabled as per
4191                  * HW requirement
4192                  */
4193                 if (test_bit(HPH_PA_DELAY, &tasha->status_mask)) {
4194                         usleep_range(7000, 7100);
4195                         clear_bit(HPH_PA_DELAY, &tasha->status_mask);
4196                 }
4197
4198                 tasha_codec_hph_post_pa_config(tasha, hph_mode, event);
4199                 snd_soc_update_bits(codec, WCD9335_CDC_RX1_RX_PATH_CTL,
4200                                     0x10, 0x00);
4201                 /* Remove mix path mute if it is enabled */
4202                 if ((snd_soc_read(codec, WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
4203                                   0x10)
4204                         snd_soc_update_bits(codec,
4205                                             WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4206                                             0x10, 0x00);
4207
4208                 if (!(strcmp(w->name, "ANC HPHL PA"))) {
4209                         /* Do everything needed for right channel */
4210                         snd_soc_update_bits(codec, WCD9335_CDC_RX2_RX_PATH_CTL,
4211                                             0x10, 0x00);
4212                         /* Remove mix path mute if it is enabled */
4213                         if ((snd_soc_read(codec,
4214                                           WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
4215                                           0x10)
4216                                 snd_soc_update_bits(codec,
4217                                                 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4218                                                 0x10, 0x00);
4219
4220                         /* Remove ANC Rx from reset */
4221                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4222                 }
4223                 tasha_codec_override(codec, hph_mode, event);
4224                 break;
4225         case SND_SOC_DAPM_PRE_PMD:
4226                 blocking_notifier_call_chain(&tasha->notifier,
4227                                         WCD_EVENT_PRE_HPHL_PA_OFF,
4228                                         &tasha->mbhc);
4229                 tasha_codec_hph_post_pa_config(tasha, hph_mode, event);
4230                 if (!(strcmp(w->name, "ANC HPHL PA")))
4231                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x80, 0x00);
4232                 if (!(strcmp(w->name, "HPHL PA")))
4233                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x80, 0x00);
4234                 break;
4235         case SND_SOC_DAPM_POST_PMD:
4236                 /* 5ms sleep is required after PA is disabled as per
4237                  * HW requirement
4238                  */
4239                 usleep_range(5000, 5500);
4240                 tasha_codec_override(codec, hph_mode, event);
4241                 blocking_notifier_call_chain(&tasha->notifier,
4242                                         WCD_EVENT_POST_HPHL_PA_OFF,
4243                                         &tasha->mbhc);
4244
4245                 if (!(strcmp(w->name, "ANC HPHL PA"))) {
4246                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4247                         snd_soc_update_bits(codec,
4248                                 WCD9335_CDC_RX1_RX_PATH_CFG0, 0x10, 0x00);
4249                 }
4250                 break;
4251         };
4252
4253         return ret;
4254 }
4255
4256 static int tasha_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
4257                                          struct snd_kcontrol *kcontrol,
4258                                          int event)
4259 {
4260         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4261         u16 lineout_vol_reg = 0, lineout_mix_vol_reg = 0;
4262         int ret = 0;
4263
4264         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4265
4266         if (w->reg == WCD9335_ANA_LO_1_2) {
4267                 if (w->shift == 7) {
4268                         lineout_vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
4269                         lineout_mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
4270                 } else if (w->shift == 6) {
4271                         lineout_vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
4272                         lineout_mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
4273                 }
4274         } else if (w->reg == WCD9335_ANA_LO_3_4) {
4275                 if (w->shift == 7) {
4276                         lineout_vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
4277                         lineout_mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
4278                 } else if (w->shift == 6) {
4279                         lineout_vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
4280                         lineout_mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
4281                 }
4282         } else {
4283                 dev_err(codec->dev, "%s: Error enabling lineout PA\n",
4284                         __func__);
4285                 return -EINVAL;
4286         }
4287
4288         switch (event) {
4289         case SND_SOC_DAPM_POST_PMU:
4290                 /* 5ms sleep is required after PA is enabled as per
4291                  * HW requirement
4292                  */
4293                 usleep_range(5000, 5500);
4294                 snd_soc_update_bits(codec, lineout_vol_reg,
4295                                     0x10, 0x00);
4296                 /* Remove mix path mute if it is enabled */
4297                 if ((snd_soc_read(codec, lineout_mix_vol_reg)) & 0x10)
4298                         snd_soc_update_bits(codec,
4299                                             lineout_mix_vol_reg,
4300                                             0x10, 0x00);
4301                 if (!(strcmp(w->name, "ANC LINEOUT1 PA")) ||
4302                     !(strcmp(w->name, "ANC LINEOUT2 PA")))
4303                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4304                 tasha_codec_override(codec, CLS_AB, event);
4305                 break;
4306         case SND_SOC_DAPM_POST_PMD:
4307                 /* 5ms sleep is required after PA is disabled as per
4308                  * HW requirement
4309                  */
4310                 usleep_range(5000, 5500);
4311                 tasha_codec_override(codec, CLS_AB, event);
4312                 if (!(strcmp(w->name, "ANC LINEOUT1 PA")) ||
4313                         !(strcmp(w->name, "ANC LINEOUT2 PA"))) {
4314                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4315                         if (!(strcmp(w->name, "ANC LINEOUT1 PA")))
4316                                 snd_soc_update_bits(codec,
4317                                 WCD9335_CDC_RX3_RX_PATH_CFG0, 0x10, 0x10);
4318                         else
4319                                 snd_soc_update_bits(codec,
4320                                 WCD9335_CDC_RX4_RX_PATH_CFG0, 0x10, 0x10);
4321                 }
4322                 break;
4323         };
4324
4325         return ret;
4326 }
4327
4328 static void tasha_spk_anc_update_callback(struct work_struct *work)
4329 {
4330         struct spk_anc_work *spk_anc_dwork;
4331         struct tasha_priv *tasha;
4332         struct delayed_work *delayed_work;
4333         struct snd_soc_codec *codec;
4334
4335         delayed_work = to_delayed_work(work);
4336         spk_anc_dwork = container_of(delayed_work, struct spk_anc_work, dwork);
4337         tasha = spk_anc_dwork->tasha;
4338         codec = tasha->codec;
4339
4340         snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_CFG0, 0x10, 0x10);
4341 }
4342
4343 static int tasha_codec_enable_spk_anc(struct snd_soc_dapm_widget *w,
4344                                       struct snd_kcontrol *kcontrol,
4345                                       int event)
4346 {
4347         int ret = 0;
4348         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4349         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4350
4351         dev_dbg(codec->dev, "%s %s %d %d\n", __func__, w->name, event,
4352                 tasha->anc_func);
4353
4354         if (!tasha->anc_func)
4355                 return 0;
4356
4357         switch (event) {
4358         case SND_SOC_DAPM_PRE_PMU:
4359                 ret = tasha_codec_enable_anc(w, kcontrol, event);
4360                 queue_delayed_work(system_power_efficient_wq, &tasha->spk_anc_dwork.dwork,
4361                                       msecs_to_jiffies(spk_anc_en_delay));
4362                 break;
4363         case SND_SOC_DAPM_POST_PMD:
4364                 cancel_delayed_work_sync(&tasha->spk_anc_dwork.dwork);
4365                 snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_CFG0,
4366                                     0x10, 0x00);
4367                 ret = tasha_codec_enable_anc(w, kcontrol, event);
4368                 break;
4369         }
4370         return ret;
4371 }
4372
4373 static int tasha_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
4374                                      struct snd_kcontrol *kcontrol,
4375                                      int event)
4376 {
4377         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4378         int ret = 0;
4379
4380         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4381
4382         switch (event) {
4383         case SND_SOC_DAPM_POST_PMU:
4384                 /* 5ms sleep is required after PA is enabled as per
4385                  * HW requirement
4386                  */
4387                 usleep_range(5000, 5500);
4388                 snd_soc_update_bits(codec, WCD9335_CDC_RX0_RX_PATH_CTL,
4389                                     0x10, 0x00);
4390                 /* Remove mix path mute if it is enabled */
4391                 if ((snd_soc_read(codec, WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
4392                      0x10)
4393                         snd_soc_update_bits(codec,
4394                                             WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4395                                             0x10, 0x00);
4396                 break;
4397         case SND_SOC_DAPM_POST_PMD:
4398                 /* 5ms sleep is required after PA is disabled as per
4399                  * HW requirement
4400                  */
4401                 usleep_range(5000, 5500);
4402
4403                 if (!(strcmp(w->name, "ANC EAR PA"))) {
4404                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4405                         snd_soc_update_bits(codec,
4406                                 WCD9335_CDC_RX0_RX_PATH_CFG0, 0x10, 0x00);
4407                 }
4408                 break;
4409         };
4410
4411         return ret;
4412 }
4413
4414 static void tasha_codec_hph_mode_gain_opt(struct snd_soc_codec *codec,
4415                                           u8 gain)
4416 {
4417         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4418         u8 hph_l_en, hph_r_en;
4419         u8 l_val, r_val;
4420         u8 hph_pa_status;
4421         bool is_hphl_pa, is_hphr_pa;
4422
4423         hph_pa_status = snd_soc_read(codec, WCD9335_ANA_HPH);
4424         is_hphl_pa = hph_pa_status >> 7;
4425         is_hphr_pa = (hph_pa_status & 0x40) >> 6;
4426
4427         hph_l_en = snd_soc_read(codec, WCD9335_HPH_L_EN);
4428         hph_r_en = snd_soc_read(codec, WCD9335_HPH_R_EN);
4429
4430         l_val = (hph_l_en & 0xC0) | 0x20 | gain;
4431         r_val = (hph_r_en & 0xC0) | 0x20 | gain;
4432
4433         /*
4434          * Set HPH_L & HPH_R gain source selection to REGISTER
4435          * for better click and pop only if corresponding PAs are
4436          * not enabled. Also cache the values of the HPHL/R
4437          * PA gains to be applied after PAs are enabled
4438          */
4439         if ((l_val != hph_l_en) && !is_hphl_pa) {
4440                 snd_soc_write(codec, WCD9335_HPH_L_EN, l_val);
4441                 tasha->hph_l_gain = hph_l_en & 0x1F;
4442         }
4443
4444         if ((r_val != hph_r_en) && !is_hphr_pa) {
4445                 snd_soc_write(codec, WCD9335_HPH_R_EN, r_val);
4446                 tasha->hph_r_gain = hph_r_en & 0x1F;
4447         }
4448 }
4449
4450 static void tasha_codec_hph_lohifi_config(struct snd_soc_codec *codec,
4451                                           int event)
4452 {
4453         if (SND_SOC_DAPM_EVENT_ON(event)) {
4454                 snd_soc_update_bits(codec, WCD9335_RX_BIAS_HPH_PA, 0x0F, 0x06);
4455                 snd_soc_update_bits(codec, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
4456                                     0xF0, 0x40);
4457                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x03);
4458                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x08);
4459                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL1, 0x0E, 0x0C);
4460                 tasha_codec_hph_mode_gain_opt(codec, 0x11);
4461         }
4462
4463         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4464                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x00);
4465                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x02);
4466                 snd_soc_write(codec, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A);
4467                 snd_soc_update_bits(codec, WCD9335_RX_BIAS_HPH_PA, 0x0F, 0x0A);
4468         }
4469 }
4470
4471 static void tasha_codec_hph_lp_config(struct snd_soc_codec *codec,
4472                                       int event)
4473 {
4474         if (SND_SOC_DAPM_EVENT_ON(event)) {
4475                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL1, 0x0E, 0x0C);
4476                 tasha_codec_hph_mode_gain_opt(codec, 0x10);
4477                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x03);
4478                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x08);
4479                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x04, 0x04);
4480                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x20, 0x20);
4481                 snd_soc_update_bits(codec, WCD9335_HPH_RDAC_LDO_CTL, 0x07,
4482                                     0x01);
4483                 snd_soc_update_bits(codec, WCD9335_HPH_RDAC_LDO_CTL, 0x70,
4484                                     0x10);
4485                 snd_soc_update_bits(codec, WCD9335_RX_BIAS_HPH_RDAC_LDO,
4486                                     0x0F, 0x01);
4487                 snd_soc_update_bits(codec, WCD9335_RX_BIAS_HPH_RDAC_LDO,
4488                                     0xF0, 0x10);
4489         }
4490
4491         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4492                 snd_soc_write(codec, WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x88);
4493                 snd_soc_write(codec, WCD9335_HPH_RDAC_LDO_CTL, 0x33);
4494                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x20, 0x00);
4495                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x04, 0x00);
4496                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x00);
4497                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x02);
4498                 snd_soc_update_bits(codec, WCD9335_HPH_R_EN, 0xC0, 0x80);
4499                 snd_soc_update_bits(codec, WCD9335_HPH_L_EN, 0xC0, 0x80);
4500         }
4501 }
4502
4503 static void tasha_codec_hph_hifi_config(struct snd_soc_codec *codec,
4504                                         int event)
4505 {
4506         if (SND_SOC_DAPM_EVENT_ON(event)) {
4507                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x03);
4508                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x08);
4509                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL1, 0x0E, 0x0C);
4510                 tasha_codec_hph_mode_gain_opt(codec, 0x11);
4511         }
4512
4513         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4514                 snd_soc_update_bits(codec, WCD9335_HPH_PA_CTL2, 0x08, 0x00);
4515                 snd_soc_update_bits(codec, WCD9335_HPH_CNP_WG_CTL, 0x07, 0x02);
4516         }
4517 }
4518
4519 static void tasha_codec_hph_mode_config(struct snd_soc_codec *codec,
4520                                         int event, int mode)
4521 {
4522         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4523
4524         if (!TASHA_IS_2_0(tasha->wcd9xxx))
4525                 return;
4526
4527         switch (mode) {
4528         case CLS_H_LP:
4529                 tasha_codec_hph_lp_config(codec, event);
4530                 break;
4531         case CLS_H_LOHIFI:
4532                 tasha_codec_hph_lohifi_config(codec, event);
4533                 break;
4534         case CLS_H_HIFI:
4535                 tasha_codec_hph_hifi_config(codec, event);
4536                 break;
4537         }
4538 }
4539
4540 static int tasha_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4541                                       struct snd_kcontrol *kcontrol,
4542                                       int event)
4543 {
4544         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4545         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4546         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
4547         int hph_mode = tasha->hph_mode;
4548         u8 dem_inp;
4549         int ret = 0;
4550
4551         dev_dbg(codec->dev, "%s wname: %s event: %d hph_mode: %d\n", __func__,
4552                 w->name, event, hph_mode);
4553
4554         switch (event) {
4555         case SND_SOC_DAPM_PRE_PMU:
4556                 if (!(strcmp(w->name, "RX INT2 DAC"))) {
4557                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x20, 0x20);
4558                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x10, 0x10);
4559                 }
4560                 if (tasha->anc_func) {
4561                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4562                         /* 40 msec delay is needed to avoid click and pop */
4563                         msleep(40);
4564                 }
4565
4566                 /* Read DEM INP Select */
4567                 dem_inp = snd_soc_read(codec, WCD9335_CDC_RX2_RX_PATH_SEC0) &
4568                           0x03;
4569                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4570                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4571                         dev_err(codec->dev, "%s: DEM Input not set correctly, hph_mode: %d\n",
4572                                         __func__, hph_mode);
4573                         return -EINVAL;
4574                 }
4575                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4576                              WCD_CLSH_EVENT_PRE_DAC,
4577                              WCD_CLSH_STATE_HPHR,
4578                              ((hph_mode == CLS_H_LOHIFI) ?
4579                                CLS_H_HIFI : hph_mode));
4580
4581                 tasha_codec_hph_mode_config(codec, event, hph_mode);
4582
4583                 if (tasha->anc_func)
4584                         snd_soc_update_bits(codec,
4585                                 WCD9335_CDC_RX2_RX_PATH_CFG0, 0x10, 0x10);
4586
4587                 break;
4588         case SND_SOC_DAPM_POST_PMU:
4589                 /* 1000us required as per HW requirement */
4590                 usleep_range(1000, 1100);
4591                 if ((hph_mode == CLS_H_LP) &&
4592                    (TASHA_IS_1_1(wcd9xxx))) {
4593                         snd_soc_update_bits(codec, WCD9335_HPH_L_DAC_CTL,
4594                                             0x03, 0x03);
4595                 }
4596                 break;
4597         case SND_SOC_DAPM_PRE_PMD:
4598                 if (!(strcmp(w->name, "RX INT2 DAC")))
4599                         snd_soc_update_bits(codec, WCD9335_ANA_HPH, 0x30, 0x00);
4600                 if ((hph_mode == CLS_H_LP) &&
4601                    (TASHA_IS_1_1(wcd9xxx))) {
4602                         snd_soc_update_bits(codec, WCD9335_HPH_L_DAC_CTL,
4603                                             0x03, 0x00);
4604                 }
4605                 break;
4606         case SND_SOC_DAPM_POST_PMD:
4607                 /* 1000us required as per HW requirement */
4608                 usleep_range(1000, 1100);
4609
4610                 if (!(wcd_clsh_get_clsh_state(&tasha->clsh_d) &
4611                      WCD_CLSH_STATE_HPHL))
4612                         tasha_codec_hph_mode_config(codec, event, hph_mode);
4613
4614                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4615                              WCD_CLSH_EVENT_POST_PA,
4616                              WCD_CLSH_STATE_HPHR,
4617                              ((hph_mode == CLS_H_LOHIFI) ?
4618                                CLS_H_HIFI : hph_mode));
4619                 break;
4620         };
4621
4622         return ret;
4623 }
4624
4625 static int tasha_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4626                                       struct snd_kcontrol *kcontrol,
4627                                       int event)
4628 {
4629         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4630         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4631         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
4632         int hph_mode = tasha->hph_mode;
4633         u8 dem_inp;
4634         int ret = 0;
4635         uint32_t impedl = 0, impedr = 0;
4636
4637         dev_dbg(codec->dev, "%s wname: %s event: %d hph_mode: %d\n", __func__,
4638                 w->name, event, hph_mode);
4639
4640         switch (event) {
4641         case SND_SOC_DAPM_PRE_PMU:
4642                 if (tasha->anc_func) {
4643                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4644                         /* 40 msec delay is needed to avoid click and pop */
4645                         msleep(40);
4646                 }
4647
4648                 /* Read DEM INP Select */
4649                 dem_inp = snd_soc_read(codec, WCD9335_CDC_RX1_RX_PATH_SEC0) &
4650                           0x03;
4651                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4652                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4653                         dev_err(codec->dev, "%s: DEM Input not set correctly, hph_mode: %d\n",
4654                                         __func__, hph_mode);
4655                         return -EINVAL;
4656                 }
4657                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4658                              WCD_CLSH_EVENT_PRE_DAC,
4659                              WCD_CLSH_STATE_HPHL,
4660                              ((hph_mode == CLS_H_LOHIFI) ?
4661                                CLS_H_HIFI : hph_mode));
4662
4663                 tasha_codec_hph_mode_config(codec, event, hph_mode);
4664
4665                 if (tasha->anc_func)
4666                         snd_soc_update_bits(codec,
4667                                 WCD9335_CDC_RX1_RX_PATH_CFG0, 0x10, 0x10);
4668
4669                 ret = wcd_mbhc_get_impedance(&tasha->mbhc,
4670                                         &impedl, &impedr);
4671                 if (!ret) {
4672                         wcd_clsh_imped_config(codec, impedl, false);
4673                         set_bit(CLASSH_CONFIG, &tasha->status_mask);
4674                 } else {
4675                         dev_dbg(codec->dev, "%s: Failed to get mbhc impedance %d\n",
4676                                                 __func__, ret);
4677                         ret = 0;
4678                 }
4679
4680
4681                 break;
4682         case SND_SOC_DAPM_POST_PMU:
4683                 /* 1000us required as per HW requirement */
4684                 usleep_range(1000, 1100);
4685                 if ((hph_mode == CLS_H_LP) &&
4686                    (TASHA_IS_1_1(wcd9xxx))) {
4687                         snd_soc_update_bits(codec, WCD9335_HPH_L_DAC_CTL,
4688                                             0x03, 0x03);
4689                 }
4690                 break;
4691         case SND_SOC_DAPM_PRE_PMD:
4692                 if ((hph_mode == CLS_H_LP) &&
4693                    (TASHA_IS_1_1(wcd9xxx))) {
4694                         snd_soc_update_bits(codec, WCD9335_HPH_L_DAC_CTL,
4695                                             0x03, 0x00);
4696                 }
4697                 break;
4698         case SND_SOC_DAPM_POST_PMD:
4699                 /* 1000us required as per HW requirement */
4700                 usleep_range(1000, 1100);
4701
4702                 if (!(wcd_clsh_get_clsh_state(&tasha->clsh_d) &
4703                      WCD_CLSH_STATE_HPHR))
4704                         tasha_codec_hph_mode_config(codec, event, hph_mode);
4705                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4706                              WCD_CLSH_EVENT_POST_PA,
4707                              WCD_CLSH_STATE_HPHL,
4708                              ((hph_mode == CLS_H_LOHIFI) ?
4709                                CLS_H_HIFI : hph_mode));
4710
4711                 if (test_bit(CLASSH_CONFIG, &tasha->status_mask)) {
4712                         wcd_clsh_imped_config(codec, impedl, true);
4713                         clear_bit(CLASSH_CONFIG, &tasha->status_mask);
4714                 } else
4715                         dev_dbg(codec->dev, "%s: Failed to get mbhc impedance %d\n",
4716                                                 __func__, ret);
4717
4718
4719                 break;
4720         };
4721
4722         return ret;
4723 }
4724
4725 static int tasha_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4726                                          struct snd_kcontrol *kcontrol,
4727                                          int event)
4728 {
4729         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4730         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4731         int ret = 0;
4732
4733         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4734
4735         switch (event) {
4736         case SND_SOC_DAPM_PRE_PMU:
4737                 if (tasha->anc_func &&
4738                         (!strcmp(w->name, "RX INT3 DAC") ||
4739                                 !strcmp(w->name, "RX INT4 DAC")))
4740                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4741
4742                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4743                              WCD_CLSH_EVENT_PRE_DAC,
4744                              WCD_CLSH_STATE_LO,
4745                              CLS_AB);
4746
4747                 if (tasha->anc_func) {
4748                         if (!strcmp(w->name, "RX INT3 DAC"))
4749                                 snd_soc_update_bits(codec,
4750                                 WCD9335_CDC_RX3_RX_PATH_CFG0, 0x10, 0x10);
4751                         else if (!strcmp(w->name, "RX INT4 DAC"))
4752                                 snd_soc_update_bits(codec,
4753                                 WCD9335_CDC_RX4_RX_PATH_CFG0, 0x10, 0x10);
4754                 }
4755                 break;
4756         case SND_SOC_DAPM_POST_PMD:
4757                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4758                              WCD_CLSH_EVENT_POST_PA,
4759                              WCD_CLSH_STATE_LO,
4760                              CLS_AB);
4761                 break;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static const struct snd_soc_dapm_widget tasha_dapm_i2s_widgets[] = {
4768         SND_SOC_DAPM_SUPPLY("RX_I2S_CTL", WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL,
4769         0, 0, NULL, 0),
4770         SND_SOC_DAPM_SUPPLY("TX_I2S_CTL", WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL,
4771         0, 0, NULL, 0),
4772 };
4773
4774 static int tasha_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4775                                      struct snd_kcontrol *kcontrol,
4776                                      int event)
4777 {
4778         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4779         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4780         int ret = 0;
4781
4782         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4783
4784         switch (event) {
4785         case SND_SOC_DAPM_PRE_PMU:
4786                 if (tasha->anc_func)
4787                         ret = tasha_codec_enable_anc(w, kcontrol, event);
4788
4789                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4790                              WCD_CLSH_EVENT_PRE_DAC,
4791                              WCD_CLSH_STATE_EAR,
4792                              CLS_H_NORMAL);
4793                 if (tasha->anc_func)
4794                         snd_soc_update_bits(codec,
4795                                 WCD9335_CDC_RX0_RX_PATH_CFG0, 0x10, 0x10);
4796
4797                 break;
4798         case SND_SOC_DAPM_POST_PMU:
4799                 break;
4800         case SND_SOC_DAPM_PRE_PMD:
4801                 break;
4802         case SND_SOC_DAPM_POST_PMD:
4803                 wcd_clsh_fsm(codec, &tasha->clsh_d,
4804                              WCD_CLSH_EVENT_POST_PA,
4805                              WCD_CLSH_STATE_EAR,
4806                              CLS_H_NORMAL);
4807                 break;
4808         };
4809
4810         return ret;
4811 }
4812
4813 static int tasha_codec_spk_boost_event(struct snd_soc_dapm_widget *w,
4814                                 struct snd_kcontrol *kcontrol,
4815                                 int event)
4816 {
4817         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
4818         u16 boost_path_ctl, boost_path_cfg1;
4819         u16 reg, reg_mix;
4820
4821         dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
4822
4823         if (!strcmp(w->name, "RX INT7 CHAIN")) {
4824                 boost_path_ctl = WCD9335_CDC_BOOST0_BOOST_PATH_CTL;
4825                 boost_path_cfg1 = WCD9335_CDC_RX7_RX_PATH_CFG1;
4826                 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
4827                 reg_mix = WCD9335_CDC_RX7_RX_PATH_MIX_CTL;
4828         } else if (!strcmp(w->name, "RX INT8 CHAIN")) {
4829                 boost_path_ctl = WCD9335_CDC_BOOST1_BOOST_PATH_CTL;
4830                 boost_path_cfg1 = WCD9335_CDC_RX8_RX_PATH_CFG1;
4831                 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
4832                 reg_mix = WCD9335_CDC_RX8_RX_PATH_MIX_CTL;
4833         } else {
4834                 dev_err(codec->dev, "%s: unknown widget: %s\n",
4835                         __func__, w->name);
4836                 return -EINVAL;
4837         }
4838
4839         switch (event) {
4840         case SND_SOC_DAPM_PRE_PMU:
4841                 snd_soc_update_bits(codec, boost_path_ctl, 0x10, 0x10);
4842                 snd_soc_update_bits(codec, boost_path_cfg1, 0x01, 0x01);
4843                 snd_soc_update_bits(codec, reg, 0x10, 0x00);
4844                 if ((snd_soc_read(codec, reg_mix)) & 0x10)
4845                         snd_soc_update_bits(codec, reg_mix, 0x10, 0x00);
4846                 break;
4847         case SND_SOC_DAPM_POST_PMD:
4848                 snd_soc_update_bits(codec, boost_path_cfg1, 0x01, 0x00);
4849                 snd_soc_update_bits(codec, boost_path_ctl, 0x10, 0x00);
4850                 break;
4851         };
4852
4853         return 0;
4854 }
4855
4856 static u16 tasha_interp_get_primary_reg(u16 reg, u16 *ind)
4857 {
4858         u16 prim_int_reg = 0;
4859
4860         switch (reg) {
4861         case WCD9335_CDC_RX0_RX_PATH_CTL:
4862         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
4863                 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
4864                 *ind = 0;
4865                 break;
4866         case WCD9335_CDC_RX1_RX_PATH_CTL:
4867         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
4868                 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
4869                 *ind = 1;
4870                 break;
4871         case WCD9335_CDC_RX2_RX_PATH_CTL:
4872         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
4873                 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
4874                 *ind = 2;
4875                 break;
4876         case WCD9335_CDC_RX3_RX_PATH_CTL:
4877         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
4878                 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
4879                 *ind = 3;
4880                 break;
4881         case WCD9335_CDC_RX4_RX_PATH_CTL:
4882         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
4883                 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
4884                 *ind = 4;
4885                 break;
4886         case WCD9335_CDC_RX5_RX_PATH_CTL:
4887         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
4888                 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
4889                 *ind = 5;
4890                 break;
4891         case WCD9335_CDC_RX6_RX_PATH_CTL:
4892         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
4893                 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
4894                 *ind = 6;
4895                 break;
4896         case WCD9335_CDC_RX7_RX_PATH_CTL:
4897         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
4898                 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
4899                 *ind = 7;
4900                 break;
4901         case WCD9335_CDC_RX8_RX_PATH_CTL:
4902         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
4903                 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
4904                 *ind = 8;
4905                 break;
4906         };
4907
4908         return prim_int_reg;
4909 }
4910
4911 static void tasha_codec_hd2_control(struct snd_soc_codec *codec,
4912                                     u16 prim_int_reg, int event)
4913 {
4914         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4915         u16 hd2_scale_reg;
4916         u16 hd2_enable_reg = 0;
4917
4918         if (!TASHA_IS_2_0(tasha->wcd9xxx))
4919                 return;
4920
4921         if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
4922                 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
4923                 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
4924         }
4925         if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
4926                 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
4927                 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
4928         }
4929
4930         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
4931                 snd_soc_update_bits(codec, hd2_scale_reg, 0x3C, 0x10);
4932                 snd_soc_update_bits(codec, hd2_scale_reg, 0x03, 0x01);
4933                 snd_soc_update_bits(codec, hd2_enable_reg, 0x04, 0x04);
4934         }
4935
4936         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
4937                 snd_soc_update_bits(codec, hd2_enable_reg, 0x04, 0x00);
4938                 snd_soc_update_bits(codec, hd2_scale_reg, 0x03, 0x00);
4939                 snd_soc_update_bits(codec, hd2_scale_reg, 0x3C, 0x00);
4940         }
4941 }
4942
4943 static int tasha_codec_enable_prim_interpolator(
4944                                 struct snd_soc_codec *codec,
4945                                 u16 reg, int event)
4946 {
4947         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
4948         u16 prim_int_reg;
4949         u16 ind = 0;
4950
4951         prim_int_reg = tasha_interp_get_primary_reg(reg, &ind);
4952
4953         switch (event) {
4954         case SND_SOC_DAPM_PRE_PMU:
4955                 tasha->prim_int_users[ind]++;
4956                 if (tasha->prim_int_users[ind] == 1) {
4957                         snd_soc_update_bits(codec, prim_int_reg,
4958                                             0x10, 0x10);
4959                         tasha_codec_hd2_control(codec, prim_int_reg, event);
4960                         snd_soc_update_bits(codec, prim_int_reg,
4961                                             1 << 0x5, 1 << 0x5);
4962                 }
4963                 if ((reg != prim_int_reg) &&
4964                     ((snd_soc_read(codec, prim_int_reg)) & 0x10))
4965                         snd_soc_update_bits(codec, reg, 0x10, 0x10);
4966                 break;
4967         case SND_SOC_DAPM_POST_PMD:
4968                 tasha->prim_int_users[ind]--;
4969                 if (tasha->prim_int_users[ind] == 0) {
4970                         snd_soc_update_bits(codec, prim_int_reg,
4971                                         1 << 0x5, 0 << 0x5);
4972                         snd_soc_update_bits(codec, prim_int_reg,
4973                                         0x40, 0x40);
4974                         snd_soc_update_bits(codec, prim_int_reg,
4975                                         0x40, 0x00);
4976                         tasha_codec_hd2_control(codec, prim_int_reg, event);
4977                 }
4978                 break;
4979         };
4980
4981         dev_dbg(codec->dev, "%s: primary interpolator: INT%d, users: %d\n",
4982                 __func__, ind, tasha->prim_int_users[ind]);
4983         return 0;
4984 }
4985
4986 static int tasha_codec_enable_spline_src(struct snd_soc_codec *codec,
4987                                          int src_num,
4988                                          int event)
4989 {
4990         u16 src_paired_reg = 0;
4991         struct tasha_priv *tasha;
4992         u16 rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
4993         u16 rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
4994         int *src_users, count, spl_src = SPLINE_SRC0;
4995         u16 src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
4996
4997         tasha = snd_soc_codec_get_drvdata(codec);
4998
4999         switch (src_num) {
5000         case SRC_IN_HPHL:
5001                 rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
5002                 src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
5003                 src_paired_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
5004                 rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
5005                 spl_src = SPLINE_SRC0;
5006                 break;
5007         case SRC_IN_LO1:
5008                 rx_path_cfg_reg = WCD9335_CDC_RX3_RX_PATH_CFG0;
5009                 src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
5010                 src_paired_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
5011                 rx_path_ctl_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
5012                 spl_src = SPLINE_SRC0;
5013                 break;
5014         case SRC_IN_HPHR:
5015                 rx_path_cfg_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
5016                 src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
5017                 src_paired_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
5018                 rx_path_ctl_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
5019                 spl_src = SPLINE_SRC1;
5020                 break;
5021         case SRC_IN_LO2:
5022                 rx_path_cfg_reg = WCD9335_CDC_RX4_RX_PATH_CFG0;
5023                 src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
5024                 src_paired_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
5025                 rx_path_ctl_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
5026                 spl_src = SPLINE_SRC1;
5027                 break;
5028         case SRC_IN_SPKRL:
5029                 rx_path_cfg_reg = WCD9335_CDC_RX7_RX_PATH_CFG0;
5030                 src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
5031                 src_paired_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
5032                 rx_path_ctl_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
5033                 spl_src = SPLINE_SRC2;
5034                 break;
5035         case SRC_IN_LO3:
5036                 rx_path_cfg_reg = WCD9335_CDC_RX5_RX_PATH_CFG0;
5037                 src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
5038                 src_paired_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
5039                 rx_path_ctl_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
5040                 spl_src = SPLINE_SRC2;
5041                 break;
5042         case SRC_IN_SPKRR:
5043                 rx_path_cfg_reg = WCD9335_CDC_RX8_RX_PATH_CFG0;
5044                 src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
5045                 src_paired_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
5046                 rx_path_ctl_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
5047                 spl_src = SPLINE_SRC3;
5048                 break;
5049         case SRC_IN_LO4:
5050                 rx_path_cfg_reg = WCD9335_CDC_RX6_RX_PATH_CFG0;
5051                 src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
5052                 src_paired_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
5053                 rx_path_ctl_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
5054                 spl_src = SPLINE_SRC3;
5055                 break;
5056         default:
5057                 return -EINVAL;
5058         };
5059
5060         src_users = &tasha->spl_src_users[spl_src];
5061
5062         switch (event) {
5063         case SND_SOC_DAPM_PRE_PMU:
5064                 count = *src_users;
5065                 count++;
5066                 if (count == 1) {
5067                         if ((snd_soc_read(codec, src_clk_reg) & 0x02) ||
5068                             (snd_soc_read(codec, src_paired_reg) & 0x02)) {
5069                                 snd_soc_update_bits(codec, src_clk_reg, 0x02,
5070                                                     0x00);
5071                                 snd_soc_update_bits(codec, src_paired_reg,
5072                                                     0x02, 0x00);
5073                         }
5074                         snd_soc_update_bits(codec, src_clk_reg, 0x01, 0x01);
5075                         snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80,
5076                                             0x80);
5077                 }
5078                 *src_users = count;
5079                 break;
5080         case SND_SOC_DAPM_POST_PMD:
5081                 count = *src_users;
5082                 count--;
5083                 if (count == 0) {
5084                         snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80,
5085                                             0x00);
5086                         snd_soc_update_bits(codec, src_clk_reg, 0x03, 0x02);
5087                         /* default sample rate */
5088                         snd_soc_update_bits(codec, rx_path_ctl_reg, 0x0f,
5089                                             0x04);
5090                 }
5091                 *src_users = count;
5092                 break;
5093         };
5094
5095         dev_dbg(codec->dev, "%s: Spline SRC%d, users: %d\n",
5096                 __func__, spl_src, *src_users);
5097         return 0;
5098 }
5099
5100 static int tasha_codec_enable_spline_resampler(struct snd_soc_dapm_widget *w,
5101                                 struct snd_kcontrol *kcontrol,
5102                                 int event)
5103 {
5104         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5105         int ret = 0;
5106         u8 src_in;
5107
5108         src_in = snd_soc_read(codec, WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0);
5109         if (!(src_in & 0xFF)) {
5110                 dev_err(codec->dev, "%s: Spline SRC%u input not selected\n",
5111                         __func__, w->shift);
5112                 return -EINVAL;
5113         }
5114
5115         switch (w->shift) {
5116         case SPLINE_SRC0:
5117                 ret = tasha_codec_enable_spline_src(codec,
5118                         ((src_in & 0x03) == 1) ? SRC_IN_HPHL : SRC_IN_LO1,
5119                         event);
5120                 break;
5121         case SPLINE_SRC1:
5122                 ret = tasha_codec_enable_spline_src(codec,
5123                         ((src_in & 0x0C) == 4) ? SRC_IN_HPHR : SRC_IN_LO2,
5124                         event);
5125                 break;
5126         case SPLINE_SRC2:
5127                 ret = tasha_codec_enable_spline_src(codec,
5128                         ((src_in & 0x30) == 0x10) ? SRC_IN_LO3 : SRC_IN_SPKRL,
5129                         event);
5130                 break;
5131         case SPLINE_SRC3:
5132                 ret = tasha_codec_enable_spline_src(codec,
5133                         ((src_in & 0xC0) == 0x40) ? SRC_IN_LO4 : SRC_IN_SPKRR,
5134                         event);
5135                 break;
5136         default:
5137                 dev_err(codec->dev, "%s: Invalid spline src:%u\n", __func__,
5138                         w->shift);
5139                 ret = -EINVAL;
5140         };
5141
5142         return ret;
5143 }
5144
5145 static int tasha_codec_enable_swr(struct snd_soc_dapm_widget *w,
5146                 struct snd_kcontrol *kcontrol, int event)
5147 {
5148         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5149         struct tasha_priv *tasha;
5150         int i, ch_cnt;
5151
5152         tasha = snd_soc_codec_get_drvdata(codec);
5153
5154         if (!tasha->nr)
5155                 return 0;
5156
5157         switch (event) {
5158         case SND_SOC_DAPM_PRE_PMU:
5159                 if ((strnstr(w->name, "INT7_", sizeof("RX INT7_"))) &&
5160                     !tasha->rx_7_count)
5161                         tasha->rx_7_count++;
5162                 if ((strnstr(w->name, "INT8_", sizeof("RX INT8_"))) &&
5163                     !tasha->rx_8_count)
5164                         tasha->rx_8_count++;
5165                 ch_cnt = tasha->rx_7_count + tasha->rx_8_count;
5166
5167                 for (i = 0; i < tasha->nr; i++) {
5168                         swrm_wcd_notify(tasha->swr_ctrl_data[i].swr_pdev,
5169                                         SWR_DEVICE_UP, NULL);
5170                         swrm_wcd_notify(tasha->swr_ctrl_data[i].swr_pdev,
5171                                         SWR_SET_NUM_RX_CH, &ch_cnt);
5172                 }
5173                 break;
5174         case SND_SOC_DAPM_POST_PMD:
5175                 if ((strnstr(w->name, "INT7_", sizeof("RX INT7_"))) &&
5176                     tasha->rx_7_count)
5177                         tasha->rx_7_count--;
5178                 if ((strnstr(w->name, "INT8_", sizeof("RX INT8_"))) &&
5179                     tasha->rx_8_count)
5180                         tasha->rx_8_count--;
5181                 ch_cnt = tasha->rx_7_count + tasha->rx_8_count;
5182
5183                 for (i = 0; i < tasha->nr; i++)
5184                         swrm_wcd_notify(tasha->swr_ctrl_data[i].swr_pdev,
5185                                         SWR_SET_NUM_RX_CH, &ch_cnt);
5186
5187                 break;
5188         }
5189         dev_dbg(tasha->dev, "%s: current swr ch cnt: %d\n",
5190                 __func__, tasha->rx_7_count + tasha->rx_8_count);
5191
5192         return 0;
5193 }
5194
5195 static int tasha_codec_config_ear_spkr_gain(struct snd_soc_codec *codec,
5196                                             int event, int gain_reg)
5197 {
5198         int comp_gain_offset, val;
5199         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5200
5201         switch (tasha->spkr_mode) {
5202         /* Compander gain in SPKR_MODE1 case is 12 dB */
5203         case SPKR_MODE_1:
5204                 comp_gain_offset = -12;
5205                 break;
5206         /* Default case compander gain is 15 dB */
5207         default:
5208                 comp_gain_offset = -15;
5209                 break;
5210         }
5211
5212         switch (event) {
5213         case SND_SOC_DAPM_POST_PMU:
5214                 /* Apply ear spkr gain only if compander is enabled */
5215                 if (tasha->comp_enabled[COMPANDER_7] &&
5216                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_CTL ||
5217                      gain_reg == WCD9335_CDC_RX7_RX_VOL_MIX_CTL) &&
5218                     (tasha->ear_spkr_gain != 0)) {
5219                         /* For example, val is -8(-12+5-1) for 4dB of gain */
5220                         val = comp_gain_offset + tasha->ear_spkr_gain - 1;
5221                         snd_soc_write(codec, gain_reg, val);
5222
5223                         dev_dbg(codec->dev, "%s: RX7 Volume %d dB\n",
5224                                 __func__, val);
5225                 }
5226                 break;
5227         case SND_SOC_DAPM_POST_PMD:
5228                 /*
5229                  * Reset RX7 volume to 0 dB if compander is enabled and
5230                  * ear_spkr_gain is non-zero.
5231                  */
5232                 if (tasha->comp_enabled[COMPANDER_7] &&
5233                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_CTL ||
5234                      gain_reg == WCD9335_CDC_RX7_RX_VOL_MIX_CTL) &&
5235                     (tasha->ear_spkr_gain != 0)) {
5236                         snd_soc_write(codec, gain_reg, 0x0);
5237
5238                         dev_dbg(codec->dev, "%s: Reset RX7 Volume to 0 dB\n",
5239                                 __func__);
5240                 }
5241                 break;
5242         }
5243
5244         return 0;
5245 }
5246
5247 static int tasha_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
5248                 struct snd_kcontrol *kcontrol, int event)
5249 {
5250         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5251         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5252         u16 gain_reg;
5253         int offset_val = 0;
5254         int val = 0;
5255
5256         dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
5257
5258         switch (w->reg) {
5259         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
5260                 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
5261                 break;
5262         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
5263                 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
5264                 break;
5265         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
5266                 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
5267                 break;
5268         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
5269                 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
5270                 break;
5271         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
5272                 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
5273                 break;
5274         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
5275                 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
5276                 break;
5277         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
5278                 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
5279                 break;
5280         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
5281                 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
5282                 break;
5283         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
5284                 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
5285                 break;
5286         default:
5287                 dev_err(codec->dev, "%s: No gain register avail for %s\n",
5288                         __func__, w->name);
5289                 return 0;
5290         };
5291
5292         switch (event) {
5293         case SND_SOC_DAPM_POST_PMU:
5294                 if ((tasha->spkr_gain_offset == RX_GAIN_OFFSET_M1P5_DB) &&
5295                     (tasha->comp_enabled[COMPANDER_7] ||
5296                      tasha->comp_enabled[COMPANDER_8]) &&
5297                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_MIX_CTL ||
5298                      gain_reg == WCD9335_CDC_RX8_RX_VOL_MIX_CTL)) {
5299                         snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_SEC1,
5300                                             0x01, 0x01);
5301                         snd_soc_update_bits(codec,
5302                                             WCD9335_CDC_RX7_RX_PATH_MIX_SEC0,
5303                                             0x01, 0x01);
5304                         snd_soc_update_bits(codec, WCD9335_CDC_RX8_RX_PATH_SEC1,
5305                                             0x01, 0x01);
5306                         snd_soc_update_bits(codec,
5307                                             WCD9335_CDC_RX8_RX_PATH_MIX_SEC0,
5308                                             0x01, 0x01);
5309                         offset_val = -2;
5310                 }
5311                 val = snd_soc_read(codec, gain_reg);
5312                 val += offset_val;
5313                 snd_soc_write(codec, gain_reg, val);
5314                 tasha_codec_config_ear_spkr_gain(codec, event, gain_reg);
5315                 break;
5316         case SND_SOC_DAPM_POST_PMD:
5317                 if ((tasha->spkr_gain_offset == RX_GAIN_OFFSET_M1P5_DB) &&
5318                     (tasha->comp_enabled[COMPANDER_7] ||
5319                      tasha->comp_enabled[COMPANDER_8]) &&
5320                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_MIX_CTL ||
5321                      gain_reg == WCD9335_CDC_RX8_RX_VOL_MIX_CTL)) {
5322                         snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_SEC1,
5323                                             0x01, 0x00);
5324                         snd_soc_update_bits(codec,
5325                                             WCD9335_CDC_RX7_RX_PATH_MIX_SEC0,
5326                                             0x01, 0x00);
5327                         snd_soc_update_bits(codec, WCD9335_CDC_RX8_RX_PATH_SEC1,
5328                                             0x01, 0x00);
5329                         snd_soc_update_bits(codec,
5330                                             WCD9335_CDC_RX8_RX_PATH_MIX_SEC0,
5331                                             0x01, 0x00);
5332                         offset_val = 2;
5333                         val = snd_soc_read(codec, gain_reg);
5334                         val += offset_val;
5335                         snd_soc_write(codec, gain_reg, val);
5336                 }
5337                 tasha_codec_config_ear_spkr_gain(codec, event, gain_reg);
5338                 break;
5339         };
5340
5341         return 0;
5342 }
5343
5344 static int __tasha_cdc_native_clk_enable(struct tasha_priv *tasha,
5345                                          bool enable)
5346 {
5347         int ret = 0;
5348         struct snd_soc_codec *codec = tasha->codec;
5349
5350         if (!tasha->wcd_native_clk) {
5351                 dev_err(tasha->dev, "%s: wcd native clock is NULL\n", __func__);
5352                 return -EINVAL;
5353         }
5354
5355         dev_dbg(tasha->dev, "%s: native_clk_enable = %u\n", __func__, enable);
5356
5357         if (enable) {
5358                 ret = clk_prepare_enable(tasha->wcd_native_clk);
5359                 if (ret) {
5360                         dev_err(tasha->dev, "%s: native clk enable failed\n",
5361                                 __func__);
5362                         goto err;
5363                 }
5364                 if (++tasha->native_clk_users == 1) {
5365                         snd_soc_update_bits(codec, WCD9335_CLOCK_TEST_CTL,
5366                                             0x10, 0x10);
5367                         snd_soc_update_bits(codec, WCD9335_CLOCK_TEST_CTL,
5368                                             0x80, 0x80);
5369                         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_GATE,
5370                                             0x04, 0x00);
5371                         snd_soc_update_bits(codec,
5372                                         WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
5373                                         0x02, 0x02);
5374                 }
5375         } else {
5376                 if (tasha->native_clk_users &&
5377                     (--tasha->native_clk_users == 0)) {
5378                         snd_soc_update_bits(codec,
5379                                         WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
5380                                         0x02, 0x00);
5381                         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_GATE,
5382                                             0x04, 0x04);
5383                         snd_soc_update_bits(codec, WCD9335_CLOCK_TEST_CTL,
5384                                             0x80, 0x00);
5385                         snd_soc_update_bits(codec, WCD9335_CLOCK_TEST_CTL,
5386                                             0x10, 0x00);
5387                 }
5388                 clk_disable_unprepare(tasha->wcd_native_clk);
5389         }
5390
5391         dev_dbg(codec->dev, "%s: native_clk_users: %d\n", __func__,
5392                 tasha->native_clk_users);
5393 err:
5394         return ret;
5395 }
5396
5397 static int tasha_codec_get_native_fifo_sync_mask(struct snd_soc_codec *codec,
5398                                                  int interp_n)
5399 {
5400         int mask = 0;
5401         u16 reg;
5402         u8 val1, val2, inp0 = 0;
5403         u8 inp1 = 0, inp2 = 0;
5404
5405         reg = WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 + (2 * interp_n) - 2;
5406
5407         val1 = snd_soc_read(codec, reg);
5408         val2 = snd_soc_read(codec, reg + 1);
5409
5410         inp0 = val1 & 0x0F;
5411         inp1 = (val1 >> 4) & 0x0F;
5412         inp2 = (val2 >> 4) & 0x0F;
5413
5414         if (IS_VALID_NATIVE_FIFO_PORT(inp0))
5415                 mask |= (1 << (inp0 - 5));
5416         if (IS_VALID_NATIVE_FIFO_PORT(inp1))
5417                 mask |= (1 << (inp1 - 5));
5418         if (IS_VALID_NATIVE_FIFO_PORT(inp2))
5419                 mask |= (1 << (inp2 - 5));
5420
5421         dev_dbg(codec->dev, "%s: native fifo mask: 0x%x\n", __func__, mask);
5422         if (!mask)
5423                 dev_err(codec->dev, "native fifo err,int:%d,inp0:%d,inp1:%d,inp2:%d\n",
5424                         interp_n, inp0, inp1, inp2);
5425         return mask;
5426 }
5427
5428 static int tasha_enable_native_supply(struct snd_soc_dapm_widget *w,
5429                                       struct snd_kcontrol *kcontrol, int event)
5430 {
5431         int mask;
5432         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5433         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5434         u16 interp_reg;
5435
5436         dev_dbg(codec->dev, "%s: event: %d, shift:%d\n", __func__, event,
5437                 w->shift);
5438
5439         if (w->shift < INTERP_HPHL || w->shift > INTERP_LO2)
5440                 return -EINVAL;
5441
5442         interp_reg = WCD9335_CDC_RX1_RX_PATH_CTL + 20 * (w->shift - 1);
5443
5444         mask = tasha_codec_get_native_fifo_sync_mask(codec, w->shift);
5445         if (!mask)
5446                 return -EINVAL;
5447
5448         switch (event) {
5449         case SND_SOC_DAPM_PRE_PMU:
5450                 /* Adjust interpolator rate to 44P1_NATIVE */
5451                 snd_soc_update_bits(codec, interp_reg, 0x0F, 0x09);
5452                 __tasha_cdc_native_clk_enable(tasha, true);
5453                 snd_soc_update_bits(codec, WCD9335_DATA_HUB_NATIVE_FIFO_SYNC,
5454                                     mask, mask);
5455                 break;
5456         case SND_SOC_DAPM_PRE_PMD:
5457                 snd_soc_update_bits(codec, WCD9335_DATA_HUB_NATIVE_FIFO_SYNC,
5458                                     mask, 0x0);
5459                 __tasha_cdc_native_clk_enable(tasha, false);
5460                 /* Adjust interpolator rate to default */
5461                 snd_soc_update_bits(codec, interp_reg, 0x0F, 0x04);
5462                 break;
5463         }
5464
5465         return 0;
5466 }
5467
5468 static int tasha_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
5469                 struct snd_kcontrol *kcontrol, int event)
5470 {
5471         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5472         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5473         u16 gain_reg;
5474         u16 reg;
5475         int val;
5476         int offset_val = 0;
5477
5478         dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
5479
5480         if (!(strcmp(w->name, "RX INT0 INTERP"))) {
5481                 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
5482                 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
5483         } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
5484                 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
5485                 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
5486         } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
5487                 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
5488                 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
5489         } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
5490                 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
5491                 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
5492         } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
5493                 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
5494                 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
5495         } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
5496                 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
5497                 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
5498         } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
5499                 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
5500                 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
5501         } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
5502                 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
5503                 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
5504         } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
5505                 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
5506                 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
5507         } else {
5508                 dev_err(codec->dev, "%s: Interpolator reg not found\n",
5509                         __func__);
5510                 return -EINVAL;
5511         }
5512
5513         switch (event) {
5514         case SND_SOC_DAPM_PRE_PMU:
5515                 tasha_codec_vote_max_bw(codec, true);
5516                 /* Reset if needed */
5517                 tasha_codec_enable_prim_interpolator(codec, reg, event);
5518                 break;
5519         case SND_SOC_DAPM_POST_PMU:
5520                 tasha_config_compander(codec, w->shift, event);
5521                 /* apply gain after int clk is enabled */
5522                 if ((tasha->spkr_gain_offset == RX_GAIN_OFFSET_M1P5_DB) &&
5523                     (tasha->comp_enabled[COMPANDER_7] ||
5524                      tasha->comp_enabled[COMPANDER_8]) &&
5525                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_CTL ||
5526                      gain_reg == WCD9335_CDC_RX8_RX_VOL_CTL)) {
5527                         snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_SEC1,
5528                                             0x01, 0x01);
5529                         snd_soc_update_bits(codec,
5530                                             WCD9335_CDC_RX7_RX_PATH_MIX_SEC0,
5531                                             0x01, 0x01);
5532                         snd_soc_update_bits(codec, WCD9335_CDC_RX8_RX_PATH_SEC1,
5533                                             0x01, 0x01);
5534                         snd_soc_update_bits(codec,
5535                                             WCD9335_CDC_RX8_RX_PATH_MIX_SEC0,
5536                                             0x01, 0x01);
5537                         offset_val = -2;
5538                 }
5539                 val = snd_soc_read(codec, gain_reg);
5540                 val += offset_val;
5541                 snd_soc_write(codec, gain_reg, val);
5542                 tasha_codec_config_ear_spkr_gain(codec, event, gain_reg);
5543                 break;
5544         case SND_SOC_DAPM_POST_PMD:
5545                 tasha_config_compander(codec, w->shift, event);
5546                 tasha_codec_enable_prim_interpolator(codec, reg, event);
5547                 if ((tasha->spkr_gain_offset == RX_GAIN_OFFSET_M1P5_DB) &&
5548                     (tasha->comp_enabled[COMPANDER_7] ||
5549                      tasha->comp_enabled[COMPANDER_8]) &&
5550                     (gain_reg == WCD9335_CDC_RX7_RX_VOL_CTL ||
5551                      gain_reg == WCD9335_CDC_RX8_RX_VOL_CTL)) {
5552                         snd_soc_update_bits(codec, WCD9335_CDC_RX7_RX_PATH_SEC1,
5553                                             0x01, 0x00);
5554                         snd_soc_update_bits(codec,
5555                                             WCD9335_CDC_RX7_RX_PATH_MIX_SEC0,
5556                                             0x01, 0x00);
5557                         snd_soc_update_bits(codec, WCD9335_CDC_RX8_RX_PATH_SEC1,
5558                                             0x01, 0x00);
5559                         snd_soc_update_bits(codec,
5560                                             WCD9335_CDC_RX8_RX_PATH_MIX_SEC0,
5561                                             0x01, 0x00);
5562                         offset_val = 2;
5563                         val = snd_soc_read(codec, gain_reg);
5564                         val += offset_val;
5565                         snd_soc_write(codec, gain_reg, val);
5566                 }
5567                 tasha_codec_config_ear_spkr_gain(codec, event, gain_reg);
5568                 break;
5569         };
5570
5571         return 0;
5572 }
5573
5574 static int tasha_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
5575                                     struct snd_kcontrol *kcontrol, int event)
5576 {
5577         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5578
5579         dev_dbg(codec->dev, "%s: event = %d\n", __func__, event);
5580
5581         switch (event) {
5582         case SND_SOC_DAPM_POST_PMU: /* fall through */
5583         case SND_SOC_DAPM_PRE_PMD:
5584                 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
5585                         snd_soc_write(codec,
5586                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5587                                 snd_soc_read(codec,
5588                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
5589                         snd_soc_write(codec,
5590                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
5591                                 snd_soc_read(codec,
5592                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
5593                         snd_soc_write(codec,
5594                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
5595                                 snd_soc_read(codec,
5596                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
5597                         snd_soc_write(codec,
5598                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
5599                                 snd_soc_read(codec,
5600                                 WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
5601                 } else {
5602                         snd_soc_write(codec,
5603                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5604                                 snd_soc_read(codec,
5605                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
5606                         snd_soc_write(codec,
5607                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
5608                                 snd_soc_read(codec,
5609                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
5610                         snd_soc_write(codec,
5611                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
5612                                 snd_soc_read(codec,
5613                                 WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
5614                 }
5615                 break;
5616         }
5617         return 0;
5618 }
5619
5620 static int tasha_codec_enable_on_demand_supply(
5621         struct snd_soc_dapm_widget *w,
5622         struct snd_kcontrol *kcontrol, int event)
5623 {
5624         int ret = 0;
5625         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5626         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5627         struct on_demand_supply *supply;
5628
5629         if (w->shift >= ON_DEMAND_SUPPLIES_MAX) {
5630                 dev_err(codec->dev, "%s: error index > MAX Demand supplies",
5631                         __func__);
5632                 ret = -EINVAL;
5633                 goto out;
5634         }
5635
5636         dev_dbg(codec->dev, "%s: supply: %s event: %d\n",
5637                 __func__, on_demand_supply_name[w->shift], event);
5638
5639         supply = &tasha->on_demand_list[w->shift];
5640         WARN_ONCE(!supply->supply, "%s isn't defined\n",
5641                 on_demand_supply_name[w->shift]);
5642         if (!supply->supply) {
5643                 dev_err(codec->dev, "%s: err supply not present ond for %d",
5644                         __func__, w->shift);
5645                 goto out;
5646         }
5647
5648         switch (event) {
5649         case SND_SOC_DAPM_PRE_PMU:
5650                 ret = regulator_enable(supply->supply);
5651                 if (ret)
5652                         dev_err(codec->dev, "%s: Failed to enable %s\n",
5653                                 __func__,
5654                                 on_demand_supply_name[w->shift]);
5655                 break;
5656         case SND_SOC_DAPM_POST_PMD:
5657                 ret = regulator_disable(supply->supply);
5658                 if (ret)
5659                         dev_err(codec->dev, "%s: Failed to disable %s\n",
5660                                 __func__,
5661                                 on_demand_supply_name[w->shift]);
5662                 break;
5663         default:
5664                 break;
5665         };
5666
5667 out:
5668         return ret;
5669 }
5670
5671 static int tasha_codec_find_amic_input(struct snd_soc_codec *codec,
5672                                        int adc_mux_n)
5673 {
5674         u16 mask, shift, adc_mux_in_reg;
5675         u16 amic_mux_sel_reg;
5676         bool is_amic;
5677
5678         if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
5679             adc_mux_n == WCD9335_INVALID_ADC_MUX)
5680                 return 0;
5681
5682         /* Check whether adc mux input is AMIC or DMIC */
5683         if (adc_mux_n < 4) {
5684                 adc_mux_in_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
5685                                  2 * adc_mux_n;
5686                 amic_mux_sel_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
5687                                    2 * adc_mux_n;
5688                 mask = 0x03;
5689                 shift = 0;
5690         } else {
5691                 adc_mux_in_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
5692                                  adc_mux_n - 4;
5693                 amic_mux_sel_reg = adc_mux_in_reg;
5694                 mask = 0xC0;
5695                 shift = 6;
5696         }
5697         is_amic = (((snd_soc_read(codec, adc_mux_in_reg) & mask) >> shift)
5698                     == 1);
5699         if (!is_amic)
5700                 return 0;
5701
5702         return snd_soc_read(codec, amic_mux_sel_reg) & 0x07;
5703 }
5704
5705 static void tasha_codec_set_tx_hold(struct snd_soc_codec *codec,
5706                                     u16 amic_reg, bool set)
5707 {
5708         u8 mask = 0x20;
5709         u8 val;
5710
5711         if (amic_reg == WCD9335_ANA_AMIC1 ||
5712             amic_reg == WCD9335_ANA_AMIC3 ||
5713             amic_reg == WCD9335_ANA_AMIC5)
5714                 mask = 0x40;
5715
5716         val = set ? mask : 0x00;
5717
5718         switch (amic_reg) {
5719         case WCD9335_ANA_AMIC1:
5720         case WCD9335_ANA_AMIC2:
5721                 snd_soc_update_bits(codec, WCD9335_ANA_AMIC2, mask, val);
5722                 break;
5723         case WCD9335_ANA_AMIC3:
5724         case WCD9335_ANA_AMIC4:
5725                 snd_soc_update_bits(codec, WCD9335_ANA_AMIC4, mask, val);
5726                 break;
5727         case WCD9335_ANA_AMIC5:
5728         case WCD9335_ANA_AMIC6:
5729                 snd_soc_update_bits(codec, WCD9335_ANA_AMIC6, mask, val);
5730                 break;
5731         default:
5732                 dev_dbg(codec->dev, "%s: invalid amic: %d\n",
5733                         __func__, amic_reg);
5734                 break;
5735         }
5736 }
5737
5738 static int tasha_codec_tx_adc_cfg(struct snd_soc_dapm_widget *w,
5739                                   struct snd_kcontrol *kcontrol, int event)
5740 {
5741         int adc_mux_n = w->shift;
5742         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5743         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5744         int amic_n;
5745
5746         dev_dbg(codec->dev, "%s: event: %d\n", __func__, event);
5747
5748         switch (event) {
5749         case SND_SOC_DAPM_POST_PMU:
5750                 amic_n = tasha_codec_find_amic_input(codec, adc_mux_n);
5751                 if (amic_n) {
5752                         /*
5753                          * Prevent ANC Rx pop by leaving Tx FE in HOLD
5754                          * state until PA is up. Track AMIC being used
5755                          * so we can release the HOLD later.
5756                          */
5757                         set_bit(ANC_MIC_AMIC1 + amic_n - 1,
5758                                 &tasha->status_mask);
5759                 }
5760                 break;
5761         default:
5762                 break;
5763         }
5764
5765         return 0;
5766 }
5767
5768 static u16 tasha_codec_get_amic_pwlvl_reg(struct snd_soc_codec *codec, int amic)
5769 {
5770         u16 pwr_level_reg = 0;
5771
5772         switch (amic) {
5773         case 1:
5774         case 2:
5775                 pwr_level_reg = WCD9335_ANA_AMIC1;
5776                 break;
5777
5778         case 3:
5779         case 4:
5780                 pwr_level_reg = WCD9335_ANA_AMIC3;
5781                 break;
5782
5783         case 5:
5784         case 6:
5785                 pwr_level_reg = WCD9335_ANA_AMIC5;
5786                 break;
5787         default:
5788                 dev_dbg(codec->dev, "%s: invalid amic: %d\n",
5789                         __func__, amic);
5790                 break;
5791         }
5792
5793         return pwr_level_reg;
5794 }
5795
5796 #define  TX_HPF_CUT_OFF_FREQ_MASK       0x60
5797 #define  CF_MIN_3DB_4HZ                 0x0
5798 #define  CF_MIN_3DB_75HZ                0x1
5799 #define  CF_MIN_3DB_150HZ               0x2
5800
5801 static void tasha_tx_hpf_corner_freq_callback(struct work_struct *work)
5802 {
5803         struct delayed_work *hpf_delayed_work;
5804         struct hpf_work *hpf_work;
5805         struct tasha_priv *tasha;
5806         struct snd_soc_codec *codec;
5807         u16 dec_cfg_reg, amic_reg;
5808         u8 hpf_cut_off_freq;
5809         int amic_n;
5810
5811         hpf_delayed_work = to_delayed_work(work);
5812         hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
5813         tasha = hpf_work->tasha;
5814         codec = tasha->codec;
5815         hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
5816
5817         dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * hpf_work->decimator;
5818
5819         dev_dbg(codec->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",
5820                 __func__, hpf_work->decimator, hpf_cut_off_freq);
5821
5822         amic_n = tasha_codec_find_amic_input(codec, hpf_work->decimator);
5823         if (amic_n) {
5824                 amic_reg = WCD9335_ANA_AMIC1 + amic_n - 1;
5825                 tasha_codec_set_tx_hold(codec, amic_reg, false);
5826         }
5827         tasha_codec_vote_max_bw(codec, true);
5828         snd_soc_update_bits(codec, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
5829                             hpf_cut_off_freq << 5);
5830         tasha_codec_vote_max_bw(codec, false);
5831 }
5832
5833 static void tasha_tx_mute_update_callback(struct work_struct *work)
5834 {
5835         struct tx_mute_work *tx_mute_dwork;
5836         struct tasha_priv *tasha;
5837         struct delayed_work *delayed_work;
5838         struct snd_soc_codec *codec;
5839         u16 tx_vol_ctl_reg, hpf_gate_reg;
5840
5841         delayed_work = to_delayed_work(work);
5842         tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
5843         tasha = tx_mute_dwork->tasha;
5844         codec = tasha->codec;
5845
5846         tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL +
5847                                         16 * tx_mute_dwork->decimator;
5848         hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 +
5849                                         16 * tx_mute_dwork->decimator;
5850         snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x01);
5851         snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x00);
5852 }
5853
5854 static int tasha_codec_enable_dec(struct snd_soc_dapm_widget *w,
5855         struct snd_kcontrol *kcontrol, int event)
5856 {
5857         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5858         unsigned int decimator;
5859         char *dec_adc_mux_name = NULL;
5860         char *widget_name = NULL;
5861         char *wname;
5862         int ret = 0, amic_n;
5863         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
5864         u16 tx_gain_ctl_reg;
5865         char *dec;
5866         u8 hpf_cut_off_freq;
5867         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
5868
5869         dev_dbg(codec->dev, "%s %d\n", __func__, event);
5870
5871         widget_name = kstrndup(w->name, 15, GFP_KERNEL);
5872         if (!widget_name)
5873                 return -ENOMEM;
5874
5875         wname = widget_name;
5876         dec_adc_mux_name = strsep(&widget_name, " ");
5877         if (!dec_adc_mux_name) {
5878                 dev_err(codec->dev, "%s: Invalid decimator = %s\n",
5879                         __func__, w->name);
5880                 ret =  -EINVAL;
5881                 goto out;
5882         }
5883         dec_adc_mux_name = widget_name;
5884
5885         dec = strpbrk(dec_adc_mux_name, "012345678");
5886         if (!dec) {
5887                 dev_err(codec->dev, "%s: decimator index not found\n",
5888                         __func__);
5889                 ret =  -EINVAL;
5890                 goto out;
5891         }
5892
5893         ret = kstrtouint(dec, 10, &decimator);
5894         if (ret < 0) {
5895                 dev_err(codec->dev, "%s: Invalid decimator = %s\n",
5896                         __func__, wname);
5897                 ret =  -EINVAL;
5898                 goto out;
5899         }
5900
5901         dev_dbg(codec->dev, "%s(): widget = %s decimator = %u\n", __func__,
5902                         w->name, decimator);
5903
5904         tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5905         hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5906         dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5907         tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5908
5909         switch (event) {
5910         case SND_SOC_DAPM_PRE_PMU:
5911                 amic_n = tasha_codec_find_amic_input(codec, decimator);
5912                 if (amic_n)
5913                         pwr_level_reg = tasha_codec_get_amic_pwlvl_reg(codec,
5914                                                                        amic_n);
5915
5916                 if (pwr_level_reg) {
5917                         switch ((snd_soc_read(codec, pwr_level_reg) &
5918                                               WCD9335_AMIC_PWR_LVL_MASK) >>
5919                                               WCD9335_AMIC_PWR_LVL_SHIFT) {
5920                         case WCD9335_AMIC_PWR_LEVEL_LP:
5921                                 snd_soc_update_bits(codec, dec_cfg_reg,
5922                                                     WCD9335_DEC_PWR_LVL_MASK,
5923                                                     WCD9335_DEC_PWR_LVL_LP);
5924                                 break;
5925
5926                         case WCD9335_AMIC_PWR_LEVEL_HP:
5927                                 snd_soc_update_bits(codec, dec_cfg_reg,
5928                                                     WCD9335_DEC_PWR_LVL_MASK,
5929                                                     WCD9335_DEC_PWR_LVL_HP);
5930                                 break;
5931                         case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
5932                         default:
5933                                 snd_soc_update_bits(codec, dec_cfg_reg,
5934                                                     WCD9335_DEC_PWR_LVL_MASK,
5935                                                     WCD9335_DEC_PWR_LVL_DF);
5936                                 break;
5937                         }
5938                 }
5939                 hpf_cut_off_freq = (snd_soc_read(codec, dec_cfg_reg) &
5940                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5941                 tasha->tx_hpf_work[decimator].hpf_cut_off_freq =
5942                                                         hpf_cut_off_freq;
5943
5944                 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
5945                         snd_soc_update_bits(codec, dec_cfg_reg,
5946                                             TX_HPF_CUT_OFF_FREQ_MASK,
5947                                             CF_MIN_3DB_150HZ << 5);
5948                 /* Enable TX PGA Mute */
5949                 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10);
5950 #ifdef CONFIG_MACH_XIAOMI_MSM8998
5951                 /* Disable APC */
5952                 snd_soc_update_bits(codec, dec_cfg_reg, 0x08, 0x00);
5953 #endif
5954                 break;
5955         case SND_SOC_DAPM_POST_PMU:
5956                 snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x00);
5957
5958                 if (decimator == 0) {
5959                         snd_soc_write(codec, WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
5960                         snd_soc_write(codec, WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
5961                         snd_soc_write(codec, WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
5962                         snd_soc_write(codec, WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
5963                 }
5964                 /* schedule work queue to Remove Mute */
5965                 queue_delayed_work(system_power_efficient_wq, &tasha->tx_mute_dwork[decimator].dwork,
5966                                       msecs_to_jiffies(tx_unmute_delay));
5967                 if (tasha->tx_hpf_work[decimator].hpf_cut_off_freq !=
5968                                                         CF_MIN_3DB_150HZ)
5969                         queue_delayed_work(system_power_efficient_wq,
5970                                         &tasha->tx_hpf_work[decimator].dwork,
5971                                         msecs_to_jiffies(300));
5972                 /* apply gain after decimator is enabled */
5973                 snd_soc_write(codec, tx_gain_ctl_reg,
5974                               snd_soc_read(codec, tx_gain_ctl_reg));
5975                 break;
5976         case SND_SOC_DAPM_PRE_PMD:
5977                 hpf_cut_off_freq =
5978                         tasha->tx_hpf_work[decimator].hpf_cut_off_freq;
5979                 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10);
5980                 if (cancel_delayed_work_sync(
5981                     &tasha->tx_hpf_work[decimator].dwork)) {
5982                         if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
5983                                 tasha_codec_vote_max_bw(codec, true);
5984                                 snd_soc_update_bits(codec, dec_cfg_reg,
5985                                                     TX_HPF_CUT_OFF_FREQ_MASK,
5986                                                     hpf_cut_off_freq << 5);
5987                                 tasha_codec_vote_max_bw(codec, false);
5988                         }
5989                 }
5990                 cancel_delayed_work_sync(
5991                                 &tasha->tx_mute_dwork[decimator].dwork);
5992                 break;
5993         case SND_SOC_DAPM_POST_PMD:
5994                 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x00);
5995                 break;
5996         };
5997 out:
5998         kfree(wname);
5999         return ret;
6000 }
6001
6002 static u32 tasha_get_dmic_sample_rate(struct snd_soc_codec *codec,
6003                                 unsigned int dmic, struct wcd9xxx_pdata *pdata)
6004 {
6005         u8 tx_stream_fs;
6006         u8 adc_mux_index = 0, adc_mux_sel = 0;
6007         bool dec_found = false;
6008         u16 adc_mux_ctl_reg, tx_fs_reg;
6009         u32 dmic_fs;
6010
6011         while (dec_found == 0 && adc_mux_index < WCD9335_MAX_VALID_ADC_MUX) {
6012                 if (adc_mux_index < 4) {
6013                         adc_mux_ctl_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
6014                                                 (adc_mux_index * 2);
6015                         adc_mux_sel = ((snd_soc_read(codec, adc_mux_ctl_reg) &
6016                                                 0x78) >> 3) - 1;
6017                 } else if (adc_mux_index < 9) {
6018                         adc_mux_ctl_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
6019                                                 ((adc_mux_index - 4) * 1);
6020                         adc_mux_sel = ((snd_soc_read(codec, adc_mux_ctl_reg) &
6021                                                 0x38) >> 3) - 1;
6022                 } else if (adc_mux_index == 9) {
6023                         ++adc_mux_index;
6024                         continue;
6025                 }
6026                 if (adc_mux_sel == dmic)
6027                         dec_found = true;
6028                 else
6029                         ++adc_mux_index;
6030         }
6031
6032         if (dec_found == true && adc_mux_index <= 8) {
6033                 tx_fs_reg = WCD9335_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
6034                 tx_stream_fs = snd_soc_read(codec, tx_fs_reg) & 0x0F;
6035                 dmic_fs = tx_stream_fs <= 4 ? WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ :
6036                                         WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
6037
6038                 /*
6039                  * Check for ECPP path selection and DEC1 not connected to
6040                  * any other audio path to apply ECPP DMIC sample rate
6041                  */
6042                 if ((adc_mux_index == 1) &&
6043                     ((snd_soc_read(codec, WCD9335_CPE_SS_US_EC_MUX_CFG)
6044                                    & 0x0F) == 0x0A) &&
6045                     ((snd_soc_read(codec, WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0)
6046                                    & 0x0C) == 0x00)) {
6047                         dmic_fs = pdata->ecpp_dmic_sample_rate;
6048                 }
6049         } else {
6050                 dmic_fs = pdata->dmic_sample_rate;
6051         }
6052
6053         return dmic_fs;
6054 }
6055
6056 static u8 tasha_get_dmic_clk_val(struct snd_soc_codec *codec,
6057                                  u32 mclk_rate, u32 dmic_clk_rate)
6058 {
6059         u32 div_factor;
6060         u8 dmic_ctl_val;
6061
6062         dev_dbg(codec->dev,
6063                 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
6064                 __func__, mclk_rate, dmic_clk_rate);
6065
6066         /* Default value to return in case of error */
6067         if (mclk_rate == TASHA_MCLK_CLK_9P6MHZ)
6068                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
6069         else
6070                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
6071
6072         if (dmic_clk_rate == 0) {
6073                 dev_err(codec->dev,
6074                         "%s: dmic_sample_rate cannot be 0\n",
6075                         __func__);
6076                 goto done;
6077         }
6078
6079         div_factor = mclk_rate / dmic_clk_rate;
6080         switch (div_factor) {
6081         case 2:
6082                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
6083                 break;
6084         case 3:
6085                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
6086                 break;
6087         case 4:
6088                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
6089                 break;
6090         case 6:
6091                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
6092                 break;
6093         case 8:
6094                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
6095                 break;
6096         case 16:
6097                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
6098                 break;
6099         default:
6100                 dev_err(codec->dev,
6101                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
6102                         __func__, div_factor, mclk_rate, dmic_clk_rate);
6103                 break;
6104         }
6105
6106 done:
6107         return dmic_ctl_val;
6108 }
6109
6110 static int tasha_codec_enable_adc(struct snd_soc_dapm_widget *w,
6111                 struct snd_kcontrol *kcontrol, int event)
6112 {
6113         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6114
6115         dev_dbg(codec->dev, "%s: event:%d\n", __func__, event);
6116
6117         switch (event) {
6118         case SND_SOC_DAPM_PRE_PMU:
6119                 tasha_codec_set_tx_hold(codec, w->reg, true);
6120                 break;
6121         default:
6122                 break;
6123         }
6124
6125         return 0;
6126 }
6127
6128 static int tasha_codec_enable_dmic(struct snd_soc_dapm_widget *w,
6129                 struct snd_kcontrol *kcontrol, int event)
6130 {
6131         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6132         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
6133         struct wcd9xxx_pdata *pdata = dev_get_platdata(codec->dev->parent);
6134         u8  dmic_clk_en = 0x01;
6135         u16 dmic_clk_reg;
6136         s32 *dmic_clk_cnt;
6137         u8 dmic_rate_val, dmic_rate_shift = 1;
6138         unsigned int dmic;
6139         u32 dmic_sample_rate;
6140         int ret;
6141         char *wname;
6142
6143         wname = strpbrk(w->name, "012345");
6144         if (!wname) {
6145                 dev_err(codec->dev, "%s: widget not found\n", __func__);
6146                 return -EINVAL;
6147         }
6148
6149         ret = kstrtouint(wname, 10, &dmic);
6150         if (ret < 0) {
6151                 dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
6152                         __func__);
6153                 return -EINVAL;
6154         }
6155
6156         switch (dmic) {
6157         case 0:
6158         case 1:
6159                 dmic_clk_cnt = &(tasha->dmic_0_1_clk_cnt);
6160                 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
6161                 break;
6162         case 2:
6163         case 3:
6164                 dmic_clk_cnt = &(tasha->dmic_2_3_clk_cnt);
6165                 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
6166                 break;
6167         case 4:
6168         case 5:
6169                 dmic_clk_cnt = &(tasha->dmic_4_5_clk_cnt);
6170                 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
6171                 break;
6172         default:
6173                 dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
6174                         __func__);
6175                 return -EINVAL;
6176         };
6177         dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
6178                         __func__, event,  dmic, *dmic_clk_cnt);
6179
6180         switch (event) {
6181         case SND_SOC_DAPM_PRE_PMU:
6182                 dmic_sample_rate = tasha_get_dmic_sample_rate(codec, dmic,
6183                                                 pdata);
6184                 dmic_rate_val =
6185                         tasha_get_dmic_clk_val(codec,
6186                                         pdata->mclk_rate,
6187                                         dmic_sample_rate);
6188
6189                 (*dmic_clk_cnt)++;
6190                 if (*dmic_clk_cnt == 1) {
6191                         snd_soc_update_bits(codec, dmic_clk_reg,
6192                                 0x07 << dmic_rate_shift,
6193                                 dmic_rate_val << dmic_rate_shift);
6194                         snd_soc_update_bits(codec, dmic_clk_reg,
6195                                         dmic_clk_en, dmic_clk_en);
6196                 }
6197
6198                 break;
6199         case SND_SOC_DAPM_POST_PMD:
6200                 dmic_rate_val =
6201                         tasha_get_dmic_clk_val(codec,
6202                                         pdata->mclk_rate,
6203                                         pdata->mad_dmic_sample_rate);
6204                 (*dmic_clk_cnt)--;
6205                 if (*dmic_clk_cnt  == 0) {
6206                         snd_soc_update_bits(codec, dmic_clk_reg,
6207                                         dmic_clk_en, 0);
6208                         snd_soc_update_bits(codec, dmic_clk_reg,
6209                                 0x07 << dmic_rate_shift,
6210                                 dmic_rate_val << dmic_rate_shift);
6211                 }
6212                 break;
6213         };
6214
6215         return 0;
6216 }
6217
6218 static int __tasha_codec_enable_micbias(struct snd_soc_dapm_widget *w,
6219                                         int event)
6220 {
6221         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6222         int micb_num;
6223
6224         dev_dbg(codec->dev, "%s: wname: %s, event: %d\n",
6225                 __func__, w->name, event);
6226
6227         if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
6228                 micb_num = MIC_BIAS_1;
6229         else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
6230                 micb_num = MIC_BIAS_2;
6231         else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
6232                 micb_num = MIC_BIAS_3;
6233         else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
6234                 micb_num = MIC_BIAS_4;
6235         else
6236                 return -EINVAL;
6237
6238         switch (event) {
6239         case SND_SOC_DAPM_PRE_PMU:
6240                 /*
6241                  * MIC BIAS can also be requested by MBHC,
6242                  * so use ref count to handle micbias pullup
6243                  * and enable requests
6244                  */
6245                 tasha_micbias_control(codec, micb_num, MICB_ENABLE, true);
6246                 break;
6247         case SND_SOC_DAPM_POST_PMU:
6248                 /* wait for cnp time */
6249                 usleep_range(1000, 1100);
6250                 break;
6251         case SND_SOC_DAPM_POST_PMD:
6252                 tasha_micbias_control(codec, micb_num, MICB_DISABLE, true);
6253                 break;
6254         };
6255
6256         return 0;
6257 }
6258
6259 static int tasha_codec_ldo_h_control(struct snd_soc_dapm_widget *w,
6260                                      int event)
6261 {
6262         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6263         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
6264
6265         if (SND_SOC_DAPM_EVENT_ON(event)) {
6266                 tasha->ldo_h_users++;
6267
6268                 if (tasha->ldo_h_users == 1)
6269                         snd_soc_update_bits(codec, WCD9335_LDOH_MODE,
6270                                             0x80, 0x80);
6271         }
6272
6273         if (SND_SOC_DAPM_EVENT_OFF(event)) {
6274                 tasha->ldo_h_users--;
6275
6276                 if (tasha->ldo_h_users < 0)
6277                         tasha->ldo_h_users = 0;
6278
6279                 if (tasha->ldo_h_users == 0)
6280                         snd_soc_update_bits(codec, WCD9335_LDOH_MODE,
6281                                             0x80, 0x00);
6282         }
6283
6284         return 0;
6285 }
6286
6287 static int tasha_codec_force_enable_ldo_h(struct snd_soc_dapm_widget *w,
6288                                           struct snd_kcontrol *kcontrol,
6289                                           int event)
6290 {
6291         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6292         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
6293
6294         switch (event) {
6295         case SND_SOC_DAPM_PRE_PMU:
6296                 wcd_resmgr_enable_master_bias(tasha->resmgr);
6297                 tasha_codec_ldo_h_control(w, event);
6298                 break;
6299         case SND_SOC_DAPM_POST_PMD:
6300                 tasha_codec_ldo_h_control(w, event);
6301                 wcd_resmgr_disable_master_bias(tasha->resmgr);
6302                 break;
6303         }
6304
6305         return 0;
6306 }
6307
6308 static int tasha_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
6309                                             struct snd_kcontrol *kcontrol,
6310                                             int event)
6311 {
6312         int ret = 0;
6313         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6314         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
6315
6316         switch (event) {
6317         case SND_SOC_DAPM_PRE_PMU:
6318                 wcd_resmgr_enable_master_bias(tasha->resmgr);
6319                 tasha_cdc_mclk_enable(codec, true, true);
6320                 ret = __tasha_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
6321                 /* Wait for 1ms for better cnp */
6322                 usleep_range(1000, 1100);
6323                 tasha_cdc_mclk_enable(codec, false, true);
6324                 break;
6325         case SND_SOC_DAPM_POST_PMD:
6326                 ret = __tasha_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
6327                 wcd_resmgr_disable_master_bias(tasha->resmgr);
6328                 break;
6329         }
6330
6331         return ret;
6332 }
6333
6334 static int tasha_codec_enable_micbias(struct snd_soc_dapm_widget *w,
6335                 struct snd_kcontrol *kcontrol, int event)
6336 {
6337         return __tasha_codec_enable_micbias(w, event);
6338 }
6339
6340 static int tasha_codec_enable_standalone_ldo_h(struct snd_soc_codec *codec,
6341                                                bool enable)
6342 {
6343         int rc;
6344
6345         if (enable)
6346                 rc = snd_soc_dapm_force_enable_pin(
6347                                         snd_soc_codec_get_dapm(codec),
6348                                         DAPM_LDO_H_STANDALONE);
6349         else
6350                 rc = snd_soc_dapm_disable_pin(
6351                                         snd_soc_codec_get_dapm(codec),
6352                                         DAPM_LDO_H_STANDALONE);
6353
6354         if (!rc)
6355                 snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
6356         else
6357                 dev_err(codec->dev, "%s: ldo_h force %s pin failed\n",
6358                         __func__, (enable ? "enable" : "disable"));
6359
6360         return rc;
6361 }
6362
6363 /*
6364  * tasha_codec_enable_standalone_micbias - enable micbias standalone
6365  * @codec: pointer to codec instance
6366  * @micb_num: number of micbias to be enabled
6367  * @enable: true to enable micbias or false to disable
6368  *
6369  * This function is used to enable micbias (1, 2, 3 or 4) during
6370  * standalone independent of whether TX use-case is running or not
6371  *
6372  * Return: error code in case of failure or 0 for success
6373  */
6374 int tasha_codec_enable_standalone_micbias(struct snd_soc_codec *codec,
6375                                           int micb_num,
6376                                           bool enable)
6377 {
6378         const char * const micb_names[] = {
6379                 DAPM_MICBIAS1_STANDALONE, DAPM_MICBIAS2_STANDALONE,
6380                 DAPM_MICBIAS3_STANDALONE, DAPM_MICBIAS4_STANDALONE
6381         };
6382         int micb_index = micb_num - 1;
6383         int rc;
6384
6385         if (!codec) {
6386                 pr_err("%s: Codec memory is NULL\n", __func__);
6387                 return -EINVAL;
6388         }
6389
6390         if ((micb_index < 0) || (micb_index > TASHA_MAX_MICBIAS - 1)) {
6391                 dev_err(codec->dev, "%s: Invalid micbias index, micb_ind:%d\n",
6392                         __func__, micb_index);
6393                 return -EINVAL;
6394         }
6395
6396         if (enable)
6397                 rc = snd_soc_dapm_force_enable_pin(
6398                                                  snd_soc_codec_get_dapm(codec),
6399                                                    micb_names[micb_index]);
6400         else
6401                 rc = snd_soc_dapm_disable_pin(snd_soc_codec_get_dapm(codec),
6402                                               micb_names[micb_index]);
6403
6404         if (!rc)
6405                 snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec));
6406         else
6407                 dev_err(codec->dev, "%s: micbias%d force %s pin failed\n",
6408                         __func__, micb_num, (enable ? "enable" : "disable"));
6409
6410         return rc;
6411 }
6412 EXPORT_SYMBOL(tasha_codec_enable_standalone_micbias);
6413
6414 static const char *const tasha_anc_func_text[] = {"OFF", "ON"};
6415 static const struct soc_enum tasha_anc_func_enum =
6416                 SOC_ENUM_SINGLE_EXT(2, tasha_anc_func_text);
6417
6418 static const char *const tasha_clkmode_text[] = {"EXTERNAL", "INTERNAL"};
6419 static SOC_ENUM_SINGLE_EXT_DECL(tasha_clkmode_enum, tasha_clkmode_text);
6420
6421 /* Cutoff frequency for high pass filter */
6422 static const char * const cf_text[] = {
6423         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
6424 };
6425
6426 static const char * const rx_cf_text[] = {
6427         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
6428         "CF_NEG_3DB_0P48HZ"
6429 };
6430
6431 static const struct soc_enum cf_dec0_enum =
6432         SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
6433
6434 static const struct soc_enum cf_dec1_enum =
6435         SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
6436
6437 static const struct soc_enum cf_dec2_enum =
6438         SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
6439
6440 static const struct soc_enum cf_dec3_enum =
6441         SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
6442
6443 static const struct soc_enum cf_dec4_enum =
6444         SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
6445
6446 static const struct soc_enum cf_dec5_enum =
6447         SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
6448
6449 static const struct soc_enum cf_dec6_enum =
6450         SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
6451
6452 static const struct soc_enum cf_dec7_enum =
6453         SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
6454
6455 static const struct soc_enum cf_dec8_enum =
6456         SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
6457
6458 static const struct soc_enum cf_int0_1_enum =
6459         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
6460
6461 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
6462                      rx_cf_text);
6463
6464 static const struct soc_enum cf_int1_1_enum =
6465         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
6466
6467 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
6468                      rx_cf_text);
6469
6470 static const struct soc_enum cf_int2_1_enum =
6471         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
6472
6473 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
6474                      rx_cf_text);
6475
6476 static const struct soc_enum cf_int3_1_enum =
6477         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
6478
6479 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
6480                      rx_cf_text);
6481
6482 static const struct soc_enum cf_int4_1_enum =
6483         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
6484
6485 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
6486                      rx_cf_text);
6487
6488 static const struct soc_enum cf_int5_1_enum =
6489         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
6490
6491 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
6492                      rx_cf_text);
6493
6494 static const struct soc_enum cf_int6_1_enum =
6495         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
6496
6497 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
6498                      rx_cf_text);
6499
6500 static const struct soc_enum cf_int7_1_enum =
6501         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
6502
6503 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
6504                      rx_cf_text);
6505
6506 static const struct soc_enum cf_int8_1_enum =
6507         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
6508
6509 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
6510                      rx_cf_text);
6511
6512 static const struct snd_soc_dapm_route audio_i2s_map[] = {
6513         {"SLIM RX0 MUX", NULL, "RX_I2S_CTL"},
6514         {"SLIM RX1 MUX", NULL, "RX_I2S_CTL"},
6515         {"SLIM RX2 MUX", NULL, "RX_I2S_CTL"},
6516         {"SLIM RX3 MUX", NULL, "RX_I2S_CTL"},
6517
6518         {"SLIM TX6 MUX", NULL, "TX_I2S_CTL"},
6519         {"SLIM TX7 MUX", NULL, "TX_I2S_CTL"},
6520         {"SLIM TX8 MUX", NULL, "TX_I2S_CTL"},
6521         {"SLIM TX11 MUX", NULL, "TX_I2S_CTL"},
6522 };
6523
6524 static const struct snd_soc_dapm_route audio_map[] = {
6525
6526         /* MAD */
6527         {"MAD_SEL MUX", "SPE", "MAD_CPE_INPUT"},
6528         {"MAD_SEL MUX", "MSM", "MADINPUT"},
6529         {"MADONOFF", "Switch", "MAD_SEL MUX"},
6530         {"MAD_BROADCAST", "Switch", "MAD_SEL MUX"},
6531         {"TX13 INP MUX", "CPE_TX_PP", "MADONOFF"},
6532
6533         /* CPE HW MAD bypass */
6534         {"CPE IN Mixer", "MAD_BYPASS", "SLIM TX1 MUX"},
6535
6536         {"AIF4_MAD Mixer", "SLIM TX1", "CPE IN Mixer"},
6537         {"AIF4_MAD Mixer", "SLIM TX12", "MADONOFF"},
6538         {"AIF4_MAD Mixer", "SLIM TX13", "TX13 INP MUX"},
6539         {"AIF4 MAD", NULL, "AIF4_MAD Mixer"},
6540         {"AIF4 MAD", NULL, "AIF4"},
6541
6542         {"EC BUF MUX INP", "DEC1", "ADC MUX1"},
6543         {"AIF5 CPE", NULL, "EC BUF MUX INP"},
6544
6545         /* SLIMBUS Connections */
6546         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
6547         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
6548         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
6549
6550         /* VI Feedback */
6551         {"AIF4_VI Mixer", "SPKR_VI_1", "VIINPUT"},
6552         {"AIF4_VI Mixer", "SPKR_VI_2", "VIINPUT"},
6553         {"AIF4 VI", NULL, "AIF4_VI Mixer"},
6554
6555         /* SLIM_MIXER("AIF1_CAP Mixer"),*/
6556         {"AIF1_CAP Mixer", "SLIM TX0", "SLIM TX0 MUX"},
6557         {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
6558         {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
6559         {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
6560         {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
6561         {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
6562         {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
6563         {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
6564         {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
6565         {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
6566         {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
6567         {"AIF1_CAP Mixer", "SLIM TX11", "SLIM TX11 MUX"},
6568         {"AIF1_CAP Mixer", "SLIM TX13", "TX13 INP MUX"},
6569         /* SLIM_MIXER("AIF2_CAP Mixer"),*/
6570         {"AIF2_CAP Mixer", "SLIM TX0", "SLIM TX0 MUX"},
6571         {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
6572         {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
6573         {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
6574         {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
6575         {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
6576         {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
6577         {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
6578         {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
6579         {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
6580         {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
6581         {"AIF2_CAP Mixer", "SLIM TX11", "SLIM TX11 MUX"},
6582         {"AIF2_CAP Mixer", "SLIM TX13", "TX13 INP MUX"},
6583         /* SLIM_MIXER("AIF3_CAP Mixer"),*/
6584         {"AIF3_CAP Mixer", "SLIM TX0", "SLIM TX0 MUX"},
6585         {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
6586         {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
6587         {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
6588         {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
6589         {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
6590         {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
6591         {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
6592         {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
6593         {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
6594         {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
6595         {"AIF3_CAP Mixer", "SLIM TX11", "SLIM TX11 MUX"},
6596         {"AIF3_CAP Mixer", "SLIM TX13", "TX13 INP MUX"},
6597
6598         {"SLIM TX0 MUX", "DEC0", "ADC MUX0"},
6599         {"SLIM TX0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
6600         {"SLIM TX0 MUX", "DEC0_192", "ADC US MUX0"},
6601
6602         {"SLIM TX1 MUX", "DEC1", "ADC MUX1"},
6603         {"SLIM TX1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
6604         {"SLIM TX1 MUX", "DEC1_192", "ADC US MUX1"},
6605
6606         {"SLIM TX2 MUX", "DEC2", "ADC MUX2"},
6607         {"SLIM TX2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
6608         {"SLIM TX2 MUX", "DEC2_192", "ADC US MUX2"},
6609
6610         {"SLIM TX3 MUX", "DEC3", "ADC MUX3"},
6611         {"SLIM TX3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
6612         {"SLIM TX3 MUX", "DEC3_192", "ADC US MUX3"},
6613
6614         {"SLIM TX4 MUX", "DEC4", "ADC MUX4"},
6615         {"SLIM TX4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
6616         {"SLIM TX4 MUX", "DEC4_192", "ADC US MUX4"},
6617
6618         {"SLIM TX5 MUX", "DEC5", "ADC MUX5"},
6619         {"SLIM TX5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
6620         {"SLIM TX5 MUX", "DEC5_192", "ADC US MUX5"},
6621
6622         {"SLIM TX6 MUX", "DEC6", "ADC MUX6"},
6623         {"SLIM TX6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
6624         {"SLIM TX6 MUX", "DEC6_192", "ADC US MUX6"},
6625
6626         {"SLIM TX7 MUX", "DEC7", "ADC MUX7"},
6627         {"SLIM TX7 MUX", "RX_MIX_TX7", "RX MIX TX7 MUX"},
6628         {"SLIM TX7 MUX", "DEC7_192", "ADC US MUX7"},
6629
6630         {"SLIM TX8 MUX", "DEC8", "ADC MUX8"},
6631         {"SLIM TX8 MUX", "RX_MIX_TX8", "RX MIX TX8 MUX"},
6632         {"SLIM TX8 MUX", "DEC8_192", "ADC US MUX8"},
6633
6634         {"SLIM TX9 MUX", "DEC7", "ADC MUX7"},
6635         {"SLIM TX9 MUX", "DEC7_192", "ADC US MUX7"},
6636         {"SLIM TX10 MUX", "DEC6", "ADC MUX6"},
6637         {"SLIM TX10 MUX", "DEC6_192", "ADC US MUX6"},
6638
6639         {"SLIM TX11 MUX", "DEC_0_5", "SLIM TX11 INP1 MUX"},
6640         {"SLIM TX11 MUX", "DEC_9_12", "SLIM TX11 INP1 MUX"},
6641         {"SLIM TX11 INP1 MUX", "DEC0", "ADC MUX0"},
6642         {"SLIM TX11 INP1 MUX", "DEC1", "ADC MUX1"},
6643         {"SLIM TX11 INP1 MUX", "DEC2", "ADC MUX2"},
6644         {"SLIM TX11 INP1 MUX", "DEC3", "ADC MUX3"},
6645         {"SLIM TX11 INP1 MUX", "DEC4", "ADC MUX4"},
6646         {"SLIM TX11 INP1 MUX", "DEC5", "ADC MUX5"},
6647         {"SLIM TX11 INP1 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
6648
6649         {"TX13 INP MUX", "MAD_BRDCST", "MAD_BROADCAST"},
6650         {"TX13 INP MUX", "CDC_DEC_5", "SLIM TX13 MUX"},
6651         {"SLIM TX13 MUX", "DEC5", "ADC MUX5"},
6652
6653         {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6654         {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6655         {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6656         {"RX MIX TX0 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6657         {"RX MIX TX0 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6658         {"RX MIX TX0 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6659         {"RX MIX TX0 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6660         {"RX MIX TX0 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6661         {"RX MIX TX0 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6662         {"RX MIX TX0 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6663         {"RX MIX TX0 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6664         {"RX MIX TX0 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6665         {"RX MIX TX0 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6666
6667         {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6668         {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6669         {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6670         {"RX MIX TX1 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6671         {"RX MIX TX1 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6672         {"RX MIX TX1 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6673         {"RX MIX TX1 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6674         {"RX MIX TX1 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6675         {"RX MIX TX1 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6676         {"RX MIX TX1 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6677         {"RX MIX TX1 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6678         {"RX MIX TX1 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6679         {"RX MIX TX1 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6680
6681         {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6682         {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6683         {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6684         {"RX MIX TX2 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6685         {"RX MIX TX2 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6686         {"RX MIX TX2 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6687         {"RX MIX TX2 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6688         {"RX MIX TX2 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6689         {"RX MIX TX2 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6690         {"RX MIX TX2 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6691         {"RX MIX TX2 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6692         {"RX MIX TX2 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6693         {"RX MIX TX2 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6694
6695         {"RX MIX TX3 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6696         {"RX MIX TX3 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6697         {"RX MIX TX3 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6698         {"RX MIX TX3 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6699         {"RX MIX TX3 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6700         {"RX MIX TX3 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6701         {"RX MIX TX3 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6702         {"RX MIX TX3 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6703         {"RX MIX TX3 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6704         {"RX MIX TX3 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6705         {"RX MIX TX3 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6706         {"RX MIX TX3 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6707         {"RX MIX TX3 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6708
6709         {"RX MIX TX4 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6710         {"RX MIX TX4 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6711         {"RX MIX TX4 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6712         {"RX MIX TX4 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6713         {"RX MIX TX4 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6714         {"RX MIX TX4 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6715         {"RX MIX TX4 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6716         {"RX MIX TX4 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6717         {"RX MIX TX4 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6718         {"RX MIX TX4 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6719         {"RX MIX TX4 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6720         {"RX MIX TX4 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6721         {"RX MIX TX4 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6722
6723         {"RX MIX TX5 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6724         {"RX MIX TX5 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6725         {"RX MIX TX5 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6726         {"RX MIX TX5 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6727         {"RX MIX TX5 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6728         {"RX MIX TX5 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6729         {"RX MIX TX5 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6730         {"RX MIX TX5 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6731         {"RX MIX TX5 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6732         {"RX MIX TX5 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6733         {"RX MIX TX5 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6734         {"RX MIX TX5 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6735         {"RX MIX TX5 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6736
6737         {"RX MIX TX6 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6738         {"RX MIX TX6 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6739         {"RX MIX TX6 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6740         {"RX MIX TX6 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6741         {"RX MIX TX6 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6742         {"RX MIX TX6 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6743         {"RX MIX TX6 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6744         {"RX MIX TX6 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6745         {"RX MIX TX6 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6746         {"RX MIX TX6 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6747         {"RX MIX TX6 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6748         {"RX MIX TX6 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6749         {"RX MIX TX6 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6750
6751         {"RX MIX TX7 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6752         {"RX MIX TX7 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6753         {"RX MIX TX7 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6754         {"RX MIX TX7 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6755         {"RX MIX TX7 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6756         {"RX MIX TX7 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6757         {"RX MIX TX7 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6758         {"RX MIX TX7 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6759         {"RX MIX TX7 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6760         {"RX MIX TX7 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6761         {"RX MIX TX7 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6762         {"RX MIX TX7 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6763         {"RX MIX TX7 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6764
6765         {"RX MIX TX8 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
6766         {"RX MIX TX8 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
6767         {"RX MIX TX8 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
6768         {"RX MIX TX8 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
6769         {"RX MIX TX8 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
6770         {"RX MIX TX8 MUX", "RX_MIX5", "RX INT5 SEC MIX"},
6771         {"RX MIX TX8 MUX", "RX_MIX6", "RX INT6 SEC MIX"},
6772         {"RX MIX TX8 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
6773         {"RX MIX TX8 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
6774         {"RX MIX TX8 MUX", "RX_MIX_VBAT5", "RX INT5 VBAT"},
6775         {"RX MIX TX8 MUX", "RX_MIX_VBAT6", "RX INT6 VBAT"},
6776         {"RX MIX TX8 MUX", "RX_MIX_VBAT7", "RX INT7 VBAT"},
6777         {"RX MIX TX8 MUX", "RX_MIX_VBAT8", "RX INT8 VBAT"},
6778
6779         {"ADC US MUX0", "US_Switch", "ADC MUX0"},
6780         {"ADC US MUX1", "US_Switch", "ADC MUX1"},
6781         {"ADC US MUX2", "US_Switch", "ADC MUX2"},
6782         {"ADC US MUX3", "US_Switch", "ADC MUX3"},
6783         {"ADC US MUX4", "US_Switch", "ADC MUX4"},
6784         {"ADC US MUX5", "US_Switch", "ADC MUX5"},
6785         {"ADC US MUX6", "US_Switch", "ADC MUX6"},
6786         {"ADC US MUX7", "US_Switch", "ADC MUX7"},
6787         {"ADC US MUX8", "US_Switch", "ADC MUX8"},
6788         {"ADC MUX0", "DMIC", "DMIC MUX0"},
6789         {"ADC MUX0", "AMIC", "AMIC MUX0"},
6790         {"ADC MUX1", "DMIC", "DMIC MUX1"},
6791         {"ADC MUX1", "AMIC", "AMIC MUX1"},
6792         {"ADC MUX2", "DMIC", "DMIC MUX2"},
6793         {"ADC MUX2", "AMIC", "AMIC MUX2"},
6794         {"ADC MUX3", "DMIC", "DMIC MUX3"},
6795         {"ADC MUX3", "AMIC", "AMIC MUX3"},
6796         {"ADC MUX4", "DMIC", "DMIC MUX4"},
6797         {"ADC MUX4", "AMIC", "AMIC MUX4"},
6798         {"ADC MUX5", "DMIC", "DMIC MUX5"},
6799         {"ADC MUX5", "AMIC", "AMIC MUX5"},
6800         {"ADC MUX6", "DMIC", "DMIC MUX6"},
6801         {"ADC MUX6", "AMIC", "AMIC MUX6"},
6802         {"ADC MUX7", "DMIC", "DMIC MUX7"},
6803         {"ADC MUX7", "AMIC", "AMIC MUX7"},
6804         {"ADC MUX8", "DMIC", "DMIC MUX8"},
6805         {"ADC MUX8", "AMIC", "AMIC MUX8"},
6806         {"ADC MUX10", "DMIC", "DMIC MUX10"},
6807         {"ADC MUX10", "AMIC", "AMIC MUX10"},
6808         {"ADC MUX11", "DMIC", "DMIC MUX11"},
6809         {"ADC MUX11", "AMIC", "AMIC MUX11"},
6810         {"ADC MUX12", "DMIC", "DMIC MUX12"},
6811         {"ADC MUX12", "AMIC", "AMIC MUX12"},
6812         {"ADC MUX13", "DMIC", "DMIC MUX13"},
6813         {"ADC MUX13", "AMIC", "AMIC MUX13"},
6814
6815         {"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX10"},
6816         {"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX11"},
6817         {"ADC MUX0", "ANC_FB_TUNE2", "ADC MUX12"},
6818         {"ADC MUX0", "ANC_FB_TUNE2", "ADC MUX13"},
6819         {"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX10"},
6820         {"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX11"},
6821         {"ADC MUX1", "ANC_FB_TUNE2", "ADC MUX12"},
6822         {"ADC MUX1", "ANC_FB_TUNE2", "ADC MUX13"},
6823         {"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX10"},
6824         {"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX11"},
6825         {"ADC MUX2", "ANC_FB_TUNE2", "ADC MUX12"},
6826         {"ADC MUX2", "ANC_FB_TUNE2", "ADC MUX13"},
6827         {"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX10"},
6828         {"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX11"},
6829         {"ADC MUX3", "ANC_FB_TUNE2", "ADC MUX12"},
6830         {"ADC MUX3", "ANC_FB_TUNE2", "ADC MUX13"},
6831         {"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX10"},
6832         {"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX11"},
6833         {"ADC MUX4", "ANC_FB_TUNE2", "ADC MUX12"},
6834         {"ADC MUX4", "ANC_FB_TUNE2", "ADC MUX13"},
6835         {"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX10"},
6836         {"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX11"},
6837         {"ADC MUX5", "ANC_FB_TUNE2", "ADC MUX12"},
6838         {"ADC MUX5", "ANC_FB_TUNE2", "ADC MUX13"},
6839         {"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX10"},
6840         {"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX11"},
6841         {"ADC MUX6", "ANC_FB_TUNE2", "ADC MUX12"},
6842         {"ADC MUX6", "ANC_FB_TUNE2", "ADC MUX13"},
6843         {"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX10"},
6844         {"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX11"},
6845         {"ADC MUX7", "ANC_FB_TUNE2", "ADC MUX12"},
6846         {"ADC MUX7", "ANC_FB_TUNE2", "ADC MUX13"},
6847         {"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX10"},
6848         {"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX11"},
6849         {"ADC MUX8", "ANC_FB_TUNE2", "ADC MUX12"},
6850         {"ADC MUX8", "ANC_FB_TUNE2", "ADC MUX13"},
6851
6852         {"DMIC MUX0", "DMIC0", "DMIC0"},
6853         {"DMIC MUX0", "DMIC1", "DMIC1"},
6854         {"DMIC MUX0", "DMIC2", "DMIC2"},
6855         {"DMIC MUX0", "DMIC3", "DMIC3"},
6856         {"DMIC MUX0", "DMIC4", "DMIC4"},
6857         {"DMIC MUX0", "DMIC5", "DMIC5"},
6858         {"AMIC MUX0", "ADC1", "ADC1"},
6859         {"AMIC MUX0", "ADC2", "ADC2"},
6860         {"AMIC MUX0", "ADC3", "ADC3"},
6861         {"AMIC MUX0", "ADC4", "ADC4"},
6862         {"AMIC MUX0", "ADC5", "ADC5"},
6863         {"AMIC MUX0", "ADC6", "ADC6"},
6864
6865         {"DMIC MUX1", "DMIC0", "DMIC0"},
6866         {"DMIC MUX1", "DMIC1", "DMIC1"},
6867         {"DMIC MUX1", "DMIC2", "DMIC2"},
6868         {"DMIC MUX1", "DMIC3", "DMIC3"},
6869         {"DMIC MUX1", "DMIC4", "DMIC4"},
6870         {"DMIC MUX1", "DMIC5", "DMIC5"},
6871         {"AMIC MUX1", "ADC1", "ADC1"},
6872         {"AMIC MUX1", "ADC2", "ADC2"},
6873         {"AMIC MUX1", "ADC3", "ADC3"},
6874         {"AMIC MUX1", "ADC4", "ADC4"},
6875         {"AMIC MUX1", "ADC5", "ADC5"},
6876         {"AMIC MUX1", "ADC6", "ADC6"},
6877
6878         {"DMIC MUX2", "DMIC0", "DMIC0"},
6879         {"DMIC MUX2", "DMIC1", "DMIC1"},
6880         {"DMIC MUX2", "DMIC2", "DMIC2"},
6881         {"DMIC MUX2", "DMIC3", "DMIC3"},
6882         {"DMIC MUX2", "DMIC4", "DMIC4"},
6883         {"DMIC MUX2", "DMIC5", "DMIC5"},
6884         {"AMIC MUX2", "ADC1", "ADC1"},
6885         {"AMIC MUX2", "ADC2", "ADC2"},
6886         {"AMIC MUX2", "ADC3", "ADC3"},
6887         {"AMIC MUX2", "ADC4", "ADC4"},
6888         {"AMIC MUX2", "ADC5", "ADC5"},
6889         {"AMIC MUX2", "ADC6", "ADC6"},
6890
6891         {"DMIC MUX3", "DMIC0", "DMIC0"},
6892         {"DMIC MUX3", "DMIC1", "DMIC1"},
6893         {"DMIC MUX3", "DMIC2", "DMIC2"},
6894         {"DMIC MUX3", "DMIC3", "DMIC3"},
6895         {"DMIC MUX3", "DMIC4", "DMIC4"},
6896         {"DMIC MUX3", "DMIC5", "DMIC5"},
6897         {"AMIC MUX3", "ADC1", "ADC1"},
6898         {"AMIC MUX3", "ADC2", "ADC2"},
6899         {"AMIC MUX3", "ADC3", "ADC3"},
6900         {"AMIC MUX3", "ADC4", "ADC4"},
6901         {"AMIC MUX3", "ADC5", "ADC5"},
6902         {"AMIC MUX3", "ADC6", "ADC6"},
6903
6904         {"DMIC MUX4", "DMIC0", "DMIC0"},
6905         {"DMIC MUX4", "DMIC1", "DMIC1"},
6906         {"DMIC MUX4", "DMIC2", "DMIC2"},
6907         {"DMIC MUX4", "DMIC3", "DMIC3"},
6908         {"DMIC MUX4", "DMIC4", "DMIC4"},
6909         {"DMIC MUX4", "DMIC5", "DMIC5"},
6910         {"AMIC MUX4", "ADC1", "ADC1"},
6911         {"AMIC MUX4", "ADC2", "ADC2"},
6912         {"AMIC MUX4", "ADC3", "ADC3"},
6913         {"AMIC MUX4", "ADC4", "ADC4"},
6914         {"AMIC MUX4", "ADC5", "ADC5"},
6915         {"AMIC MUX4", "ADC6", "ADC6"},
6916
6917         {"DMIC MUX5", "DMIC0", "DMIC0"},
6918         {"DMIC MUX5", "DMIC1", "DMIC1"},
6919         {"DMIC MUX5", "DMIC2", "DMIC2"},
6920         {"DMIC MUX5", "DMIC3", "DMIC3"},
6921         {"DMIC MUX5", "DMIC4", "DMIC4"},
6922         {"DMIC MUX5", "DMIC5", "DMIC5"},
6923         {"AMIC MUX5", "ADC1", "ADC1"},
6924         {"AMIC MUX5", "ADC2", "ADC2"},
6925         {"AMIC MUX5", "ADC3", "ADC3"},
6926         {"AMIC MUX5", "ADC4", "ADC4"},
6927         {"AMIC MUX5", "ADC5", "ADC5"},
6928         {"AMIC MUX5", "ADC6", "ADC6"},
6929
6930         {"DMIC MUX6", "DMIC0", "DMIC0"},
6931         {"DMIC MUX6", "DMIC1", "DMIC1"},
6932         {"DMIC MUX6", "DMIC2", "DMIC2"},
6933         {"DMIC MUX6", "DMIC3", "DMIC3"},
6934         {"DMIC MUX6", "DMIC4", "DMIC4"},
6935         {"DMIC MUX6", "DMIC5", "DMIC5"},
6936         {"AMIC MUX6", "ADC1", "ADC1"},
6937         {"AMIC MUX6", "ADC2", "ADC2"},
6938         {"AMIC MUX6", "ADC3", "ADC3"},
6939         {"AMIC MUX6", "ADC4", "ADC4"},
6940         {"AMIC MUX6", "ADC5", "ADC5"},
6941         {"AMIC MUX6", "ADC6", "ADC6"},
6942
6943         {"DMIC MUX7", "DMIC0", "DMIC0"},
6944         {"DMIC MUX7", "DMIC1", "DMIC1"},
6945         {"DMIC MUX7", "DMIC2", "DMIC2"},
6946         {"DMIC MUX7", "DMIC3", "DMIC3"},
6947         {"DMIC MUX7", "DMIC4", "DMIC4"},
6948         {"DMIC MUX7", "DMIC5", "DMIC5"},
6949         {"AMIC MUX7", "ADC1", "ADC1"},
6950         {"AMIC MUX7", "ADC2", "ADC2"},
6951         {"AMIC MUX7", "ADC3", "ADC3"},
6952         {"AMIC MUX7", "ADC4", "ADC4"},
6953         {"AMIC MUX7", "ADC5", "ADC5"},
6954         {"AMIC MUX7", "ADC6", "ADC6"},
6955
6956         {"DMIC MUX8", "DMIC0", "DMIC0"},
6957         {"DMIC MUX8", "DMIC1", "DMIC1"},
6958         {"DMIC MUX8", "DMIC2", "DMIC2"},
6959         {"DMIC MUX8", "DMIC3", "DMIC3"},
6960         {"DMIC MUX8", "DMIC4", "DMIC4"},
6961         {"DMIC MUX8", "DMIC5", "DMIC5"},
6962         {"AMIC MUX8", "ADC1", "ADC1"},
6963         {"AMIC MUX8", "ADC2", "ADC2"},
6964         {"AMIC MUX8", "ADC3", "ADC3"},
6965         {"AMIC MUX8", "ADC4", "ADC4"},
6966         {"AMIC MUX8", "ADC5", "ADC5"},
6967         {"AMIC MUX8", "ADC6", "ADC6"},
6968
6969         {"DMIC MUX10", "DMIC0", "DMIC0"},
6970         {"DMIC MUX10", "DMIC1", "DMIC1"},
6971         {"DMIC MUX10", "DMIC2", "DMIC2"},
6972         {"DMIC MUX10", "DMIC3", "DMIC3"},
6973         {"DMIC MUX10", "DMIC4", "DMIC4"},
6974         {"DMIC MUX10", "DMIC5", "DMIC5"},
6975         {"AMIC MUX10", "ADC1", "ADC1"},
6976         {"AMIC MUX10", "ADC2", "ADC2"},
6977         {"AMIC MUX10", "ADC3", "ADC3"},
6978         {"AMIC MUX10", "ADC4", "ADC4"},
6979         {"AMIC MUX10", "ADC5", "ADC5"},
6980         {"AMIC MUX10", "ADC6", "ADC6"},
6981
6982         {"DMIC MUX11", "DMIC0", "DMIC0"},
6983         {"DMIC MUX11", "DMIC1", "DMIC1"},
6984         {"DMIC MUX11", "DMIC2", "DMIC2"},
6985         {"DMIC MUX11", "DMIC3", "DMIC3"},
6986         {"DMIC MUX11", "DMIC4", "DMIC4"},
6987         {"DMIC MUX11", "DMIC5", "DMIC5"},
6988         {"AMIC MUX11", "ADC1", "ADC1"},
6989         {"AMIC MUX11", "ADC2", "ADC2"},
6990         {"AMIC MUX11", "ADC3", "ADC3"},
6991         {"AMIC MUX11", "ADC4", "ADC4"},
6992         {"AMIC MUX11", "ADC5", "ADC5"},
6993         {"AMIC MUX11", "ADC6", "ADC6"},
6994
6995         {"DMIC MUX12", "DMIC0", "DMIC0"},
6996         {"DMIC MUX12", "DMIC1", "DMIC1"},
6997         {"DMIC MUX12", "DMIC2", "DMIC2"},
6998         {"DMIC MUX12", "DMIC3", "DMIC3"},
6999         {"DMIC MUX12", "DMIC4", "DMIC4"},
7000         {"DMIC MUX12", "DMIC5", "DMIC5"},
7001         {"AMIC MUX12", "ADC1", "ADC1"},
7002         {"AMIC MUX12", "ADC2", "ADC2"},
7003         {"AMIC MUX12", "ADC3", "ADC3"},
7004         {"AMIC MUX12", "ADC4", "ADC4"},
7005         {"AMIC MUX12", "ADC5", "ADC5"},
7006         {"AMIC MUX12", "ADC6", "ADC6"},
7007
7008         {"DMIC MUX13", "DMIC0", "DMIC0"},
7009         {"DMIC MUX13", "DMIC1", "DMIC1"},
7010         {"DMIC MUX13", "DMIC2", "DMIC2"},
7011         {"DMIC MUX13", "DMIC3", "DMIC3"},
7012         {"DMIC MUX13", "DMIC4", "DMIC4"},
7013         {"DMIC MUX13", "DMIC5", "DMIC5"},
7014         {"AMIC MUX13", "ADC1", "ADC1"},
7015         {"AMIC MUX13", "ADC2", "ADC2"},
7016         {"AMIC MUX13", "ADC3", "ADC3"},
7017         {"AMIC MUX13", "ADC4", "ADC4"},
7018         {"AMIC MUX13", "ADC5", "ADC5"},
7019         {"AMIC MUX13", "ADC6", "ADC6"},
7020         /* ADC Connections */
7021         {"ADC1", NULL, "AMIC1"},
7022         {"ADC2", NULL, "AMIC2"},
7023         {"ADC3", NULL, "AMIC3"},
7024         {"ADC4", NULL, "AMIC4"},
7025         {"ADC5", NULL, "AMIC5"},
7026         {"ADC6", NULL, "AMIC6"},
7027
7028         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
7029         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
7030         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
7031         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
7032         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
7033         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
7034         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
7035         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
7036         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
7037         {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP0"},
7038         {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP1"},
7039         {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP2"},
7040         {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP0"},
7041         {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP1"},
7042         {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP2"},
7043         {"RX INT5_1 MIX1", NULL, "RX INT5_1 MIX1 INP0"},
7044         {"RX INT5_1 MIX1", NULL, "RX INT5_1 MIX1 INP1"},
7045         {"RX INT5_1 MIX1", NULL, "RX INT5_1 MIX1 INP2"},
7046         {"RX INT6_1 MIX1", NULL, "RX INT6_1 MIX1 INP0"},
7047         {"RX INT6_1 MIX1", NULL, "RX INT6_1 MIX1 INP1"},
7048         {"RX INT6_1 MIX1", NULL, "RX INT6_1 MIX1 INP2"},
7049         {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP0"},
7050         {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP1"},
7051         {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP2"},
7052         {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP0"},
7053         {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP1"},
7054         {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP2"},
7055
7056         {"RX INT0 SEC MIX", NULL, "RX INT0_1 MIX1"},
7057         {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
7058         {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
7059         {"RX INT0 INTERP", NULL, "RX INT0 MIX2"},
7060         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
7061         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
7062         {"RX INT0 DAC", NULL, "RX_BIAS"},
7063         {"EAR PA", NULL, "RX INT0 DAC"},
7064         {"EAR", NULL, "EAR PA"},
7065
7066         {"SPL SRC0 MUX", "SRC_IN_HPHL", "RX INT1_1 MIX1"},
7067         {"RX INT1 SPLINE MIX", NULL, "RX INT1_1 MIX1"},
7068         {"RX INT1 SPLINE MIX", "HPHL Switch", "SPL SRC0 MUX"},
7069         {"RX INT1_1 NATIVE MUX", "ON", "RX INT1_1 MIX1"},
7070         {"RX INT1 SPLINE MIX", NULL, "RX INT1_1 NATIVE MUX"},
7071         {"RX INT1_1 NATIVE MUX", NULL, "RX INT1 NATIVE SUPPLY"},
7072         {"RX INT1 SEC MIX", NULL, "RX INT1 SPLINE MIX"},
7073         {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
7074         {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
7075         {"RX INT1 INTERP", NULL, "RX INT1 MIX2"},
7076         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
7077         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
7078         {"RX INT1 DAC", NULL, "RX_BIAS"},
7079         {"HPHL PA", NULL, "RX INT1 DAC"},
7080         {"HPHL", NULL, "HPHL PA"},
7081
7082         {"SPL SRC1 MUX", "SRC_IN_HPHR", "RX INT2_1 MIX1"},
7083         {"RX INT2 SPLINE MIX", NULL, "RX INT2_1 MIX1"},
7084         {"RX INT2 SPLINE MIX", "HPHR Switch", "SPL SRC1 MUX"},
7085         {"RX INT2_1 NATIVE MUX", "ON", "RX INT2_1 MIX1"},
7086         {"RX INT2 SPLINE MIX", NULL, "RX INT2_1 NATIVE MUX"},
7087         {"RX INT2_1 NATIVE MUX", NULL, "RX INT2 NATIVE SUPPLY"},
7088         {"RX INT2 SEC MIX", NULL, "RX INT2 SPLINE MIX"},
7089         {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
7090         {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
7091         {"RX INT2 INTERP", NULL, "RX INT2 MIX2"},
7092         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
7093         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
7094         {"RX INT2 DAC", NULL, "RX_BIAS"},
7095         {"HPHR PA", NULL, "RX INT2 DAC"},
7096         {"HPHR", NULL, "HPHR PA"},
7097
7098         {"SPL SRC0 MUX", "SRC_IN_LO1", "RX INT3_1 MIX1"},
7099         {"RX INT3 SPLINE MIX", NULL, "RX INT3_1 MIX1"},
7100         {"RX INT3 SPLINE MIX", "LO1 Switch", "SPL SRC0 MUX"},
7101         {"RX INT3_1 NATIVE MUX", "ON", "RX INT3_1 MIX1"},
7102         {"RX INT3 SPLINE MIX", NULL, "RX INT3_1 NATIVE MUX"},
7103         {"RX INT3_1 NATIVE MUX", NULL, "RX INT3 NATIVE SUPPLY"},
7104         {"RX INT3 SEC MIX", NULL, "RX INT3 SPLINE MIX"},
7105         {"RX INT3 MIX2", NULL, "RX INT3 SEC MIX"},
7106         {"RX INT3 MIX2", NULL, "RX INT3 MIX2 INP"},
7107         {"RX INT3 INTERP", NULL, "RX INT3 MIX2"},
7108         {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
7109         {"RX INT3 DAC", NULL, "RX_BIAS"},
7110         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
7111         {"LINEOUT1", NULL, "LINEOUT1 PA"},
7112
7113         {"SPL SRC1 MUX", "SRC_IN_LO2", "RX INT4_1 MIX1"},
7114         {"RX INT4 SPLINE MIX", NULL, "RX INT4_1 MIX1"},
7115         {"RX INT4 SPLINE MIX", "LO2 Switch", "SPL SRC1 MUX"},
7116         {"RX INT4_1 NATIVE MUX", "ON", "RX INT4_1 MIX1"},
7117         {"RX INT4 SPLINE MIX", NULL, "RX INT4_1 NATIVE MUX"},
7118         {"RX INT4_1 NATIVE MUX", NULL, "RX INT4 NATIVE SUPPLY"},
7119         {"RX INT4 SEC MIX", NULL, "RX INT4 SPLINE MIX"},
7120         {"RX INT4 MIX2", NULL, "RX INT4 SEC MIX"},
7121         {"RX INT4 MIX2", NULL, "RX INT4 MIX2 INP"},
7122         {"RX INT4 INTERP", NULL, "RX INT4 MIX2"},
7123         {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
7124         {"RX INT4 DAC", NULL, "RX_BIAS"},
7125         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
7126         {"LINEOUT2", NULL, "LINEOUT2 PA"},
7127
7128         {"SPL SRC2 MUX", "SRC_IN_LO3", "RX INT5_1 MIX1"},
7129         {"RX INT5 SPLINE MIX", NULL, "RX INT5_1 MIX1"},
7130         {"RX INT5 SPLINE MIX", "LO3 Switch", "SPL SRC2 MUX"},
7131         {"RX INT5 SEC MIX", NULL, "RX INT5 SPLINE MIX"},
7132         {"RX INT5 MIX2", NULL, "RX INT5 SEC MIX"},
7133         {"RX INT5 INTERP", NULL, "RX INT5 MIX2"},
7134
7135         {"RX INT5 VBAT", "LO3 VBAT Enable", "RX INT5 INTERP"},
7136         {"RX INT5 DAC", NULL, "RX INT5 VBAT"},
7137
7138         {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
7139         {"RX INT5 DAC", NULL, "RX_BIAS"},
7140         {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
7141         {"LINEOUT3", NULL, "LINEOUT3 PA"},
7142
7143         {"SPL SRC3 MUX", "SRC_IN_LO4", "RX INT6_1 MIX1"},
7144         {"RX INT6 SPLINE MIX", NULL, "RX INT6_1 MIX1"},
7145         {"RX INT6 SPLINE MIX", "LO4 Switch", "SPL SRC3 MUX"},
7146         {"RX INT6 SEC MIX", NULL, "RX INT6 SPLINE MIX"},
7147         {"RX INT6 MIX2", NULL, "RX INT6 SEC MIX"},
7148         {"RX INT6 INTERP", NULL, "RX INT6 MIX2"},
7149
7150         {"RX INT6 VBAT", "LO4 VBAT Enable", "RX INT6 INTERP"},
7151         {"RX INT6 DAC", NULL, "RX INT6 VBAT"},
7152
7153         {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
7154         {"RX INT6 DAC", NULL, "RX_BIAS"},
7155         {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
7156         {"LINEOUT4", NULL, "LINEOUT4 PA"},
7157
7158         {"SPL SRC2 MUX", "SRC_IN_SPKRL", "RX INT7_1 MIX1"},
7159         {"RX INT7 SPLINE MIX", NULL, "RX INT7_1 MIX1"},
7160         {"RX INT7 SPLINE MIX", "SPKRL Switch", "SPL SRC2 MUX"},
7161         {"RX INT7 SEC MIX", NULL, "RX INT7 SPLINE MIX"},
7162         {"RX INT7 MIX2", NULL, "RX INT7 SEC MIX"},
7163         {"RX INT7 MIX2", NULL, "RX INT7 MIX2 INP"},
7164
7165         {"RX INT7 INTERP", NULL, "RX INT7 MIX2"},
7166
7167         {"RX INT7 VBAT", "SPKRL VBAT Enable", "RX INT7 INTERP"},
7168         {"RX INT7 CHAIN", NULL, "RX INT7 VBAT"},
7169
7170         {"RX INT7 CHAIN", NULL, "RX INT7 INTERP"},
7171         {"RX INT7 CHAIN", NULL, "RX_BIAS"},
7172         {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
7173
7174         {"ANC SPKR PA Enable", "Switch", "RX INT7 CHAIN"},
7175         {"ANC SPK1 PA", NULL, "ANC SPKR PA Enable"},
7176         {"SPK1 OUT", NULL, "ANC SPK1 PA"},
7177
7178         {"SPL SRC3 MUX", "SRC_IN_SPKRR", "RX INT8_1 MIX1"},
7179         {"RX INT8 SPLINE MIX", NULL, "RX INT8_1 MIX1"},
7180         {"RX INT8 SPLINE MIX", "SPKRR Switch", "SPL SRC3 MUX"},
7181         {"RX INT8 SEC MIX", NULL, "RX INT8 SPLINE MIX"},
7182         {"RX INT8 INTERP", NULL, "RX INT8 SEC MIX"},
7183
7184         {"RX INT8 VBAT", "SPKRR VBAT Enable", "RX INT8 INTERP"},
7185         {"RX INT8 CHAIN", NULL, "RX INT8 VBAT"},
7186
7187         {"RX INT8 CHAIN", NULL, "RX INT8 INTERP"},
7188         {"RX INT8 CHAIN", NULL, "RX_BIAS"},
7189         {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
7190
7191         {"ANC0 FB MUX", "ANC_IN_EAR", "RX INT0 MIX2"},
7192         {"ANC0 FB MUX", "ANC_IN_HPHL", "RX INT1 MIX2"},
7193         {"ANC0 FB MUX", "ANC_IN_LO1", "RX INT3 MIX2"},
7194         {"ANC0 FB MUX", "ANC_IN_EAR_SPKR", "RX INT7 MIX2"},
7195         {"ANC1 FB MUX", "ANC_IN_HPHR", "RX INT2 MIX2"},
7196         {"ANC1 FB MUX", "ANC_IN_LO2", "RX INT4 MIX2"},
7197
7198         {"ANC HPHL Enable", "Switch", "ADC MUX10"},
7199         {"ANC HPHL Enable", "Switch", "ADC MUX11"},
7200         {"RX INT1 MIX2", NULL, "ANC HPHL Enable"},
7201
7202         {"ANC HPHR Enable", "Switch", "ADC MUX12"},
7203         {"ANC HPHR Enable", "Switch", "ADC MUX13"},
7204         {"RX INT2 MIX2", NULL, "ANC HPHR Enable"},
7205
7206         {"ANC EAR Enable", "Switch", "ADC MUX10"},
7207         {"ANC EAR Enable", "Switch", "ADC MUX11"},
7208         {"RX INT0 MIX2", NULL, "ANC EAR Enable"},
7209
7210         {"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX10"},
7211         {"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX11"},
7212         {"RX INT7 MIX2", NULL, "ANC OUT EAR SPKR Enable"},
7213
7214         {"ANC LINEOUT1 Enable", "Switch", "ADC MUX10"},
7215         {"ANC LINEOUT1 Enable", "Switch", "ADC MUX11"},
7216         {"RX INT3 MIX2", NULL, "ANC LINEOUT1 Enable"},
7217
7218         {"ANC LINEOUT2 Enable", "Switch", "ADC MUX12"},
7219         {"ANC LINEOUT2 Enable", "Switch", "ADC MUX13"},
7220         {"RX INT4 MIX2", NULL, "ANC LINEOUT2 Enable"},
7221
7222         {"ANC EAR PA", NULL, "RX INT0 DAC"},
7223         {"ANC EAR", NULL, "ANC EAR PA"},
7224         {"ANC HPHL PA", NULL, "RX INT1 DAC"},
7225         {"ANC HPHL", NULL, "ANC HPHL PA"},
7226         {"ANC HPHR PA", NULL, "RX INT2 DAC"},
7227         {"ANC HPHR", NULL, "ANC HPHR PA"},
7228         {"ANC LINEOUT1 PA", NULL, "RX INT3 DAC"},
7229         {"ANC LINEOUT1", NULL, "ANC LINEOUT1 PA"},
7230         {"ANC LINEOUT2 PA", NULL, "RX INT4 DAC"},
7231         {"ANC LINEOUT2", NULL, "ANC LINEOUT2 PA"},
7232
7233         /* SLIM_MUX("AIF1_PB", "AIF1 PB"),*/
7234         {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
7235         {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
7236         {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
7237         {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
7238         {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
7239         {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
7240         {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
7241         {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
7242         /* SLIM_MUX("AIF2_PB", "AIF2 PB"),*/
7243         {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
7244         {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
7245         {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
7246         {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
7247         {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
7248         {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
7249         {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
7250         {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
7251         /* SLIM_MUX("AIF3_PB", "AIF3 PB"),*/
7252         {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
7253         {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
7254         {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
7255         {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
7256         {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
7257         {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
7258         {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
7259         {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
7260         /* SLIM_MUX("AIF4_PB", "AIF4 PB"),*/
7261         {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
7262         {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
7263         {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
7264         {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
7265         {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
7266         {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
7267         {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
7268         {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
7269
7270         /* SLIM_MUX("AIF_MIX1_PB", "AIF MIX1 PB"),*/
7271         {"SLIM RX0 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7272         {"SLIM RX1 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7273         {"SLIM RX2 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7274         {"SLIM RX3 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7275         {"SLIM RX4 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7276         {"SLIM RX5 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7277         {"SLIM RX6 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7278         {"SLIM RX7 MUX", "AIF_MIX1_PB", "AIF MIX1 PB"},
7279
7280         {"SLIM RX0", NULL, "SLIM RX0 MUX"},
7281         {"SLIM RX1", NULL, "SLIM RX1 MUX"},
7282         {"SLIM RX2", NULL, "SLIM RX2 MUX"},
7283         {"SLIM RX3", NULL, "SLIM RX3 MUX"},
7284         {"SLIM RX4", NULL, "SLIM RX4 MUX"},
7285         {"SLIM RX5", NULL, "SLIM RX5 MUX"},
7286         {"SLIM RX6", NULL, "SLIM RX6 MUX"},
7287         {"SLIM RX7", NULL, "SLIM RX7 MUX"},
7288
7289         {"RX INT0_1 MIX1 INP0", "RX0", "SLIM RX0"},
7290         {"RX INT0_1 MIX1 INP0", "RX1", "SLIM RX1"},
7291         {"RX INT0_1 MIX1 INP0", "RX2", "SLIM RX2"},
7292         {"RX INT0_1 MIX1 INP0", "RX3", "SLIM RX3"},
7293         {"RX INT0_1 MIX1 INP0", "RX4", "SLIM RX4"},
7294         {"RX INT0_1 MIX1 INP0", "RX5", "SLIM RX5"},
7295         {"RX INT0_1 MIX1 INP0", "RX6", "SLIM RX6"},
7296         {"RX INT0_1 MIX1 INP0", "RX7", "SLIM RX7"},
7297         {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
7298         {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
7299         {"RX INT0_1 MIX1 INP1", "RX0", "SLIM RX0"},
7300         {"RX INT0_1 MIX1 INP1", "RX1", "SLIM RX1"},
7301         {"RX INT0_1 MIX1 INP1", "RX2", "SLIM RX2"},
7302         {"RX INT0_1 MIX1 INP1", "RX3", "SLIM RX3"},
7303         {"RX INT0_1 MIX1 INP1", "RX4", "SLIM RX4"},
7304         {"RX INT0_1 MIX1 INP1", "RX5", "SLIM RX5"},
7305         {"RX INT0_1 MIX1 INP1", "RX6", "SLIM RX6"},
7306         {"RX INT0_1 MIX1 INP1", "RX7", "SLIM RX7"},
7307         {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
7308         {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
7309         {"RX INT0_1 MIX1 INP2", "RX0", "SLIM RX0"},
7310         {"RX INT0_1 MIX1 INP2", "RX1", "SLIM RX1"},
7311         {"RX INT0_1 MIX1 INP2", "RX2", "SLIM RX2"},
7312         {"RX INT0_1 MIX1 INP2", "RX3", "SLIM RX3"},
7313         {"RX INT0_1 MIX1 INP2", "RX4", "SLIM RX4"},
7314         {"RX INT0_1 MIX1 INP2", "RX5", "SLIM RX5"},
7315         {"RX INT0_1 MIX1 INP2", "RX6", "SLIM RX6"},
7316         {"RX INT0_1 MIX1 INP2", "RX7", "SLIM RX7"},
7317         {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
7318         {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
7319
7320         /* MIXing path INT0 */
7321         {"RX INT0_2 MUX", "RX0", "SLIM RX0"},
7322         {"RX INT0_2 MUX", "RX1", "SLIM RX1"},
7323         {"RX INT0_2 MUX", "RX2", "SLIM RX2"},
7324         {"RX INT0_2 MUX", "RX3", "SLIM RX3"},
7325         {"RX INT0_2 MUX", "RX4", "SLIM RX4"},
7326         {"RX INT0_2 MUX", "RX5", "SLIM RX5"},
7327         {"RX INT0_2 MUX", "RX6", "SLIM RX6"},
7328         {"RX INT0_2 MUX", "RX7", "SLIM RX7"},
7329         {"RX INT0 SEC MIX", NULL, "RX INT0_2 MUX"},
7330
7331         /* MIXing path INT1 */
7332         {"RX INT1_2 MUX", "RX0", "SLIM RX0"},
7333         {"RX INT1_2 MUX", "RX1", "SLIM RX1"},
7334         {"RX INT1_2 MUX", "RX2", "SLIM RX2"},
7335         {"RX INT1_2 MUX", "RX3", "SLIM RX3"},
7336         {"RX INT1_2 MUX", "RX4", "SLIM RX4"},
7337         {"RX INT1_2 MUX", "RX5", "SLIM RX5"},
7338         {"RX INT1_2 MUX", "RX6", "SLIM RX6"},
7339         {"RX INT1_2 MUX", "RX7", "SLIM RX7"},
7340         {"RX INT1 SEC MIX", NULL, "RX INT1_2 MUX"},
7341
7342         /* MIXing path INT2 */
7343         {"RX INT2_2 MUX", "RX0", "SLIM RX0"},
7344         {"RX INT2_2 MUX", "RX1", "SLIM RX1"},
7345         {"RX INT2_2 MUX", "RX2", "SLIM RX2"},
7346         {"RX INT2_2 MUX", "RX3", "SLIM RX3"},
7347         {"RX INT2_2 MUX", "RX4", "SLIM RX4"},
7348         {"RX INT2_2 MUX", "RX5", "SLIM RX5"},
7349         {"RX INT2_2 MUX", "RX6", "SLIM RX6"},
7350         {"RX INT2_2 MUX", "RX7", "SLIM RX7"},
7351         {"RX INT2 SEC MIX", NULL, "RX INT2_2 MUX"},
7352
7353         /* MIXing path INT3 */
7354         {"RX INT3_2 MUX", "RX0", "SLIM RX0"},
7355         {"RX INT3_2 MUX", "RX1", "SLIM RX1"},
7356         {"RX INT3_2 MUX", "RX2", "SLIM RX2"},
7357         {"RX INT3_2 MUX", "RX3", "SLIM RX3"},
7358         {"RX INT3_2 MUX", "RX4", "SLIM RX4"},
7359         {"RX INT3_2 MUX", "RX5", "SLIM RX5"},
7360         {"RX INT3_2 MUX", "RX6", "SLIM RX6"},
7361         {"RX INT3_2 MUX", "RX7", "SLIM RX7"},
7362         {"RX INT3 SEC MIX", NULL, "RX INT3_2 MUX"},
7363
7364         /* MIXing path INT4 */
7365         {"RX INT4_2 MUX", "RX0", "SLIM RX0"},
7366         {"RX INT4_2 MUX", "RX1", "SLIM RX1"},
7367         {"RX INT4_2 MUX", "RX2", "SLIM RX2"},
7368         {"RX INT4_2 MUX", "RX3", "SLIM RX3"},
7369         {"RX INT4_2 MUX", "RX4", "SLIM RX4"},
7370         {"RX INT4_2 MUX", "RX5", "SLIM RX5"},
7371         {"RX INT4_2 MUX", "RX6", "SLIM RX6"},
7372         {"RX INT4_2 MUX", "RX7", "SLIM RX7"},
7373         {"RX INT4 SEC MIX", NULL, "RX INT4_2 MUX"},
7374
7375         /* MIXing path INT5 */
7376         {"RX INT5_2 MUX", "RX0", "SLIM RX0"},
7377         {"RX INT5_2 MUX", "RX1", "SLIM RX1"},
7378         {"RX INT5_2 MUX", "RX2", "SLIM RX2"},
7379         {"RX INT5_2 MUX", "RX3", "SLIM RX3"},
7380         {"RX INT5_2 MUX", "RX4", "SLIM RX4"},
7381         {"RX INT5_2 MUX", "RX5", "SLIM RX5"},
7382         {"RX INT5_2 MUX", "RX6", "SLIM RX6"},
7383         {"RX INT5_2 MUX", "RX7", "SLIM RX7"},
7384         {"RX INT5 SEC MIX", NULL, "RX INT5_2 MUX"},
7385
7386         /* MIXing path INT6 */
7387         {"RX INT6_2 MUX", "RX0", "SLIM RX0"},
7388         {"RX INT6_2 MUX", "RX1", "SLIM RX1"},
7389         {"RX INT6_2 MUX", "RX2", "SLIM RX2"},
7390         {"RX INT6_2 MUX", "RX3", "SLIM RX3"},
7391         {"RX INT6_2 MUX", "RX4", "SLIM RX4"},
7392         {"RX INT6_2 MUX", "RX5", "SLIM RX5"},
7393         {"RX INT6_2 MUX", "RX6", "SLIM RX6"},
7394         {"RX INT6_2 MUX", "RX7", "SLIM RX7"},
7395         {"RX INT6 SEC MIX", NULL, "RX INT6_2 MUX"},
7396
7397         /* MIXing path INT7 */
7398         {"RX INT7_2 MUX", "RX0", "SLIM RX0"},
7399         {"RX INT7_2 MUX", "RX1", "SLIM RX1"},
7400         {"RX INT7_2 MUX", "RX2", "SLIM RX2"},
7401         {"RX INT7_2 MUX", "RX3", "SLIM RX3"},
7402         {"RX INT7_2 MUX", "RX4", "SLIM RX4"},
7403         {"RX INT7_2 MUX", "RX5", "SLIM RX5"},
7404         {"RX INT7_2 MUX", "RX6", "SLIM RX6"},
7405         {"RX INT7_2 MUX", "RX7", "SLIM RX7"},
7406         {"RX INT7 SEC MIX", NULL, "RX INT7_2 MUX"},
7407
7408         /* MIXing path INT8 */
7409         {"RX INT8_2 MUX", "RX0", "SLIM RX0"},
7410         {"RX INT8_2 MUX", "RX1", "SLIM RX1"},
7411         {"RX INT8_2 MUX", "RX2", "SLIM RX2"},
7412         {"RX INT8_2 MUX", "RX3", "SLIM RX3"},
7413         {"RX INT8_2 MUX", "RX4", "SLIM RX4"},
7414         {"RX INT8_2 MUX", "RX5", "SLIM RX5"},
7415         {"RX INT8_2 MUX", "RX6", "SLIM RX6"},
7416         {"RX INT8_2 MUX", "RX7", "SLIM RX7"},
7417         {"RX INT8 SEC MIX", NULL, "RX INT8_2 MUX"},
7418
7419         {"RX INT1_1 MIX1 INP0", "RX0", "SLIM RX0"},
7420         {"RX INT1_1 MIX1 INP0", "RX1", "SLIM RX1"},
7421         {"RX INT1_1 MIX1 INP0", "RX2", "SLIM RX2"},
7422         {"RX INT1_1 MIX1 INP0", "RX3", "SLIM RX3"},
7423         {"RX INT1_1 MIX1 INP0", "RX4", "SLIM RX4"},
7424         {"RX INT1_1 MIX1 INP0", "RX5", "SLIM RX5"},
7425         {"RX INT1_1 MIX1 INP0", "RX6", "SLIM RX6"},
7426         {"RX INT1_1 MIX1 INP0", "RX7", "SLIM RX7"},
7427         {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
7428         {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
7429         {"RX INT1_1 MIX1 INP1", "RX0", "SLIM RX0"},
7430         {"RX INT1_1 MIX1 INP1", "RX1", "SLIM RX1"},
7431         {"RX INT1_1 MIX1 INP1", "RX2", "SLIM RX2"},
7432         {"RX INT1_1 MIX1 INP1", "RX3", "SLIM RX3"},
7433         {"RX INT1_1 MIX1 INP1", "RX4", "SLIM RX4"},
7434         {"RX INT1_1 MIX1 INP1", "RX5", "SLIM RX5"},
7435         {"RX INT1_1 MIX1 INP1", "RX6", "SLIM RX6"},
7436         {"RX INT1_1 MIX1 INP1", "RX7", "SLIM RX7"},
7437         {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
7438         {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
7439         {"RX INT1_1 MIX1 INP2", "RX0", "SLIM RX0"},
7440         {"RX INT1_1 MIX1 INP2", "RX1", "SLIM RX1"},
7441         {"RX INT1_1 MIX1 INP2", "RX2", "SLIM RX2"},
7442         {"RX INT1_1 MIX1 INP2", "RX3", "SLIM RX3"},
7443         {"RX INT1_1 MIX1 INP2", "RX4", "SLIM RX4"},
7444         {"RX INT1_1 MIX1 INP2", "RX5", "SLIM RX5"},
7445         {"RX INT1_1 MIX1 INP2", "RX6", "SLIM RX6"},
7446         {"RX INT1_1 MIX1 INP2", "RX7", "SLIM RX7"},
7447         {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
7448         {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
7449         {"RX INT2_1 MIX1 INP0", "RX0", "SLIM RX0"},
7450         {"RX INT2_1 MIX1 INP0", "RX1", "SLIM RX1"},
7451         {"RX INT2_1 MIX1 INP0", "RX2", "SLIM RX2"},
7452         {"RX INT2_1 MIX1 INP0", "RX3", "SLIM RX3"},
7453         {"RX INT2_1 MIX1 INP0", "RX4", "SLIM RX4"},
7454         {"RX INT2_1 MIX1 INP0", "RX5", "SLIM RX5"},
7455         {"RX INT2_1 MIX1 INP0", "RX6", "SLIM RX6"},
7456         {"RX INT2_1 MIX1 INP0", "RX7", "SLIM RX7"},
7457         {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
7458         {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
7459         {"RX INT2_1 MIX1 INP1", "RX0", "SLIM RX0"},
7460         {"RX INT2_1 MIX1 INP1", "RX1", "SLIM RX1"},
7461         {"RX INT2_1 MIX1 INP1", "RX2", "SLIM RX2"},
7462         {"RX INT2_1 MIX1 INP1", "RX3", "SLIM RX3"},
7463         {"RX INT2_1 MIX1 INP1", "RX4", "SLIM RX4"},
7464         {"RX INT2_1 MIX1 INP1", "RX5", "SLIM RX5"},
7465         {"RX INT2_1 MIX1 INP1", "RX6", "SLIM RX6"},
7466         {"RX INT2_1 MIX1 INP1", "RX7", "SLIM RX7"},
7467         {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
7468         {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
7469         {"RX INT2_1 MIX1 INP2", "RX0", "SLIM RX0"},
7470         {"RX INT2_1 MIX1 INP2", "RX1", "SLIM RX1"},
7471         {"RX INT2_1 MIX1 INP2", "RX2", "SLIM RX2"},
7472         {"RX INT2_1 MIX1 INP2", "RX3", "SLIM RX3"},
7473         {"RX INT2_1 MIX1 INP2", "RX4", "SLIM RX4"},
7474         {"RX INT2_1 MIX1 INP2", "RX5", "SLIM RX5"},
7475         {"RX INT2_1 MIX1 INP2", "RX6", "SLIM RX6"},
7476         {"RX INT2_1 MIX1 INP2", "RX7", "SLIM RX7"},
7477         {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
7478         {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
7479
7480         {"RX INT3_1 MIX1 INP0", "RX0", "SLIM RX0"},
7481         {"RX INT3_1 MIX1 INP0", "RX1", "SLIM RX1"},
7482         {"RX INT3_1 MIX1 INP0", "RX2", "SLIM RX2"},
7483         {"RX INT3_1 MIX1 INP0", "RX3", "SLIM RX3"},
7484         {"RX INT3_1 MIX1 INP0", "RX4", "SLIM RX4"},
7485         {"RX INT3_1 MIX1 INP0", "RX5", "SLIM RX5"},
7486         {"RX INT3_1 MIX1 INP0", "RX6", "SLIM RX6"},
7487         {"RX INT3_1 MIX1 INP0", "RX7", "SLIM RX7"},
7488         {"RX INT3_1 MIX1 INP0", "IIR0", "IIR0"},
7489         {"RX INT3_1 MIX1 INP0", "IIR1", "IIR1"},
7490         {"RX INT3_1 MIX1 INP1", "RX0", "SLIM RX0"},
7491         {"RX INT3_1 MIX1 INP1", "RX1", "SLIM RX1"},
7492         {"RX INT3_1 MIX1 INP1", "RX2", "SLIM RX2"},
7493         {"RX INT3_1 MIX1 INP1", "RX3", "SLIM RX3"},
7494         {"RX INT3_1 MIX1 INP1", "RX4", "SLIM RX4"},
7495         {"RX INT3_1 MIX1 INP1", "RX5", "SLIM RX5"},
7496         {"RX INT3_1 MIX1 INP1", "RX6", "SLIM RX6"},
7497         {"RX INT3_1 MIX1 INP1", "RX7", "SLIM RX7"},
7498         {"RX INT3_1 MIX1 INP1", "IIR0", "IIR0"},
7499         {"RX INT3_1 MIX1 INP1", "IIR1", "IIR1"},
7500         {"RX INT3_1 MIX1 INP2", "RX0", "SLIM RX0"},
7501         {"RX INT3_1 MIX1 INP2", "RX1", "SLIM RX1"},
7502         {"RX INT3_1 MIX1 INP2", "RX2", "SLIM RX2"},
7503         {"RX INT3_1 MIX1 INP2", "RX3", "SLIM RX3"},
7504         {"RX INT3_1 MIX1 INP2", "RX4", "SLIM RX4"},
7505         {"RX INT3_1 MIX1 INP2", "RX5", "SLIM RX5"},
7506         {"RX INT3_1 MIX1 INP2", "RX6", "SLIM RX6"},
7507         {"RX INT3_1 MIX1 INP2", "RX7", "SLIM RX7"},
7508         {"RX INT3_1 MIX1 INP2", "IIR0", "IIR0"},
7509         {"RX INT3_1 MIX1 INP2", "IIR1", "IIR1"},
7510
7511         {"RX INT4_1 MIX1 INP0", "RX0", "SLIM RX0"},
7512         {"RX INT4_1 MIX1 INP0", "RX1", "SLIM RX1"},
7513         {"RX INT4_1 MIX1 INP0", "RX2", "SLIM RX2"},
7514         {"RX INT4_1 MIX1 INP0", "RX3", "SLIM RX3"},
7515         {"RX INT4_1 MIX1 INP0", "RX4", "SLIM RX4"},
7516         {"RX INT4_1 MIX1 INP0", "RX5", "SLIM RX5"},
7517         {"RX INT4_1 MIX1 INP0", "RX6", "SLIM RX6"},
7518         {"RX INT4_1 MIX1 INP0", "RX7", "SLIM RX7"},
7519         {"RX INT4_1 MIX1 INP0", "IIR0", "IIR0"},
7520         {"RX INT4_1 MIX1 INP0", "IIR1", "IIR1"},
7521         {"RX INT4_1 MIX1 INP1", "RX0", "SLIM RX0"},
7522         {"RX INT4_1 MIX1 INP1", "RX1", "SLIM RX1"},
7523         {"RX INT4_1 MIX1 INP1", "RX2", "SLIM RX2"},
7524         {"RX INT4_1 MIX1 INP1", "RX3", "SLIM RX3"},
7525         {"RX INT4_1 MIX1 INP1", "RX4", "SLIM RX4"},
7526         {"RX INT4_1 MIX1 INP1", "RX5", "SLIM RX5"},
7527         {"RX INT4_1 MIX1 INP1", "RX6", "SLIM RX6"},
7528         {"RX INT4_1 MIX1 INP1", "RX7", "SLIM RX7"},
7529         {"RX INT4_1 MIX1 INP1", "IIR0", "IIR0"},
7530         {"RX INT4_1 MIX1 INP1", "IIR1", "IIR1"},
7531         {"RX INT4_1 MIX1 INP2", "RX0", "SLIM RX0"},
7532         {"RX INT4_1 MIX1 INP2", "RX1", "SLIM RX1"},
7533         {"RX INT4_1 MIX1 INP2", "RX2", "SLIM RX2"},
7534         {"RX INT4_1 MIX1 INP2", "RX3", "SLIM RX3"},
7535         {"RX INT4_1 MIX1 INP2", "RX4", "SLIM RX4"},
7536         {"RX INT4_1 MIX1 INP2", "RX5", "SLIM RX5"},
7537         {"RX INT4_1 MIX1 INP2", "RX6", "SLIM RX6"},
7538         {"RX INT4_1 MIX1 INP2", "RX7", "SLIM RX7"},
7539         {"RX INT4_1 MIX1 INP2", "IIR0", "IIR0"},
7540         {"RX INT4_1 MIX1 INP2", "IIR1", "IIR1"},
7541
7542         {"RX INT5_1 MIX1 INP0", "RX0", "SLIM RX0"},
7543         {"RX INT5_1 MIX1 INP0", "RX1", "SLIM RX1"},
7544         {"RX INT5_1 MIX1 INP0", "RX2", "SLIM RX2"},
7545         {"RX INT5_1 MIX1 INP0", "RX3", "SLIM RX3"},
7546         {"RX INT5_1 MIX1 INP0", "RX4", "SLIM RX4"},
7547         {"RX INT5_1 MIX1 INP0", "RX5", "SLIM RX5"},
7548         {"RX INT5_1 MIX1 INP0", "RX6", "SLIM RX6"},
7549         {"RX INT5_1 MIX1 INP0", "RX7", "SLIM RX7"},
7550         {"RX INT5_1 MIX1 INP0", "IIR0", "IIR0"},
7551         {"RX INT5_1 MIX1 INP0", "IIR1", "IIR1"},
7552         {"RX INT5_1 MIX1 INP1", "RX0", "SLIM RX0"},
7553         {"RX INT5_1 MIX1 INP1", "RX1", "SLIM RX1"},
7554         {"RX INT5_1 MIX1 INP1", "RX2", "SLIM RX2"},
7555         {"RX INT5_1 MIX1 INP1", "RX3", "SLIM RX3"},
7556         {"RX INT5_1 MIX1 INP1", "RX4", "SLIM RX4"},
7557         {"RX INT5_1 MIX1 INP1", "RX5", "SLIM RX5"},
7558         {"RX INT5_1 MIX1 INP1", "RX6", "SLIM RX6"},
7559         {"RX INT5_1 MIX1 INP1", "RX7", "SLIM RX7"},
7560         {"RX INT5_1 MIX1 INP1", "IIR0", "IIR0"},
7561         {"RX INT5_1 MIX1 INP1", "IIR1", "IIR1"},
7562         {"RX INT5_1 MIX1 INP2", "RX0", "SLIM RX0"},
7563         {"RX INT5_1 MIX1 INP2", "RX1", "SLIM RX1"},
7564         {"RX INT5_1 MIX1 INP2", "RX2", "SLIM RX2"},
7565         {"RX INT5_1 MIX1 INP2", "RX3", "SLIM RX3"},
7566         {"RX INT5_1 MIX1 INP2", "RX4", "SLIM RX4"},
7567         {"RX INT5_1 MIX1 INP2", "RX5", "SLIM RX5"},
7568         {"RX INT5_1 MIX1 INP2", "RX6", "SLIM RX6"},
7569         {"RX INT5_1 MIX1 INP2", "RX7", "SLIM RX7"},
7570         {"RX INT5_1 MIX1 INP2", "IIR0", "IIR0"},
7571         {"RX INT5_1 MIX1 INP2", "IIR1", "IIR1"},
7572
7573         {"RX INT6_1 MIX1 INP0", "RX0", "SLIM RX0"},
7574         {"RX INT6_1 MIX1 INP0", "RX1", "SLIM RX1"},
7575         {"RX INT6_1 MIX1 INP0", "RX2", "SLIM RX2"},
7576         {"RX INT6_1 MIX1 INP0", "RX3", "SLIM RX3"},
7577         {"RX INT6_1 MIX1 INP0", "RX4", "SLIM RX4"},
7578         {"RX INT6_1 MIX1 INP0", "RX5", "SLIM RX5"},
7579         {"RX INT6_1 MIX1 INP0", "RX6", "SLIM RX6"},
7580         {"RX INT6_1 MIX1 INP0", "RX7", "SLIM RX7"},
7581         {"RX INT6_1 MIX1 INP0", "IIR0", "IIR0"},
7582         {"RX INT6_1 MIX1 INP0", "IIR1", "IIR1"},
7583         {"RX INT6_1 MIX1 INP1", "RX0", "SLIM RX0"},
7584         {"RX INT6_1 MIX1 INP1", "RX1", "SLIM RX1"},
7585         {"RX INT6_1 MIX1 INP1", "RX2", "SLIM RX2"},
7586         {"RX INT6_1 MIX1 INP1", "RX3", "SLIM RX3"},
7587         {"RX INT6_1 MIX1 INP1", "RX4", "SLIM RX4"},
7588         {"RX INT6_1 MIX1 INP1", "RX5", "SLIM RX5"},
7589         {"RX INT6_1 MIX1 INP1", "RX6", "SLIM RX6"},
7590         {"RX INT6_1 MIX1 INP1", "RX7", "SLIM RX7"},
7591         {"RX INT6_1 MIX1 INP1", "IIR0", "IIR0"},
7592         {"RX INT6_1 MIX1 INP1", "IIR1", "IIR1"},
7593         {"RX INT6_1 MIX1 INP2", "RX0", "SLIM RX0"},
7594         {"RX INT6_1 MIX1 INP2", "RX1", "SLIM RX1"},
7595         {"RX INT6_1 MIX1 INP2", "RX2", "SLIM RX2"},
7596         {"RX INT6_1 MIX1 INP2", "RX3", "SLIM RX3"},
7597         {"RX INT6_1 MIX1 INP2", "RX4", "SLIM RX4"},
7598         {"RX INT6_1 MIX1 INP2", "RX5", "SLIM RX5"},
7599         {"RX INT6_1 MIX1 INP2", "RX6", "SLIM RX6"},
7600         {"RX INT6_1 MIX1 INP2", "RX7", "SLIM RX7"},
7601         {"RX INT6_1 MIX1 INP2", "IIR0", "IIR0"},
7602         {"RX INT6_1 MIX1 INP2", "IIR1", "IIR1"},
7603
7604         {"RX INT7_1 MIX1 INP0", "RX0", "SLIM RX0"},
7605         {"RX INT7_1 MIX1 INP0", "RX1", "SLIM RX1"},
7606         {"RX INT7_1 MIX1 INP0", "RX2", "SLIM RX2"},
7607         {"RX INT7_1 MIX1 INP0", "RX3", "SLIM RX3"},
7608         {"RX INT7_1 MIX1 INP0", "RX4", "SLIM RX4"},
7609         {"RX INT7_1 MIX1 INP0", "RX5", "SLIM RX5"},
7610         {"RX INT7_1 MIX1 INP0", "RX6", "SLIM RX6"},
7611         {"RX INT7_1 MIX1 INP0", "RX7", "SLIM RX7"},
7612         {"RX INT7_1 MIX1 INP0", "IIR0", "IIR0"},
7613         {"RX INT7_1 MIX1 INP0", "IIR1", "IIR1"},
7614         {"RX INT7_1 MIX1 INP1", "RX0", "SLIM RX0"},
7615         {"RX INT7_1 MIX1 INP1", "RX1", "SLIM RX1"},
7616         {"RX INT7_1 MIX1 INP1", "RX2", "SLIM RX2"},
7617         {"RX INT7_1 MIX1 INP1", "RX3", "SLIM RX3"},
7618         {"RX INT7_1 MIX1 INP1", "RX4", "SLIM RX4"},
7619         {"RX INT7_1 MIX1 INP1", "RX5", "SLIM RX5"},
7620         {"RX INT7_1 MIX1 INP1", "RX6", "SLIM RX6"},
7621         {"RX INT7_1 MIX1 INP1", "RX7", "SLIM RX7"},
7622         {"RX INT7_1 MIX1 INP1", "IIR0", "IIR0"},
7623         {"RX INT7_1 MIX1 INP1", "IIR1", "IIR1"},
7624         {"RX INT7_1 MIX1 INP2", "RX0", "SLIM RX0"},
7625         {"RX INT7_1 MIX1 INP2", "RX1", "SLIM RX1"},
7626         {"RX INT7_1 MIX1 INP2", "RX2", "SLIM RX2"},
7627         {"RX INT7_1 MIX1 INP2", "RX3", "SLIM RX3"},
7628         {"RX INT7_1 MIX1 INP2", "RX4", "SLIM RX4"},
7629         {"RX INT7_1 MIX1 INP2", "RX5", "SLIM RX5"},
7630         {"RX INT7_1 MIX1 INP2", "RX6", "SLIM RX6"},
7631         {"RX INT7_1 MIX1 INP2", "RX7", "SLIM RX7"},
7632         {"RX INT7_1 MIX1 INP2", "IIR0", "IIR0"},
7633         {"RX INT7_1 MIX1 INP2", "IIR1", "IIR1"},
7634
7635         {"RX INT8_1 MIX1 INP0", "RX0", "SLIM RX0"},
7636         {"RX INT8_1 MIX1 INP0", "RX1", "SLIM RX1"},
7637         {"RX INT8_1 MIX1 INP0", "RX2", "SLIM RX2"},
7638         {"RX INT8_1 MIX1 INP0", "RX3", "SLIM RX3"},
7639         {"RX INT8_1 MIX1 INP0", "RX4", "SLIM RX4"},
7640         {"RX INT8_1 MIX1 INP0", "RX5", "SLIM RX5"},
7641         {"RX INT8_1 MIX1 INP0", "RX6", "SLIM RX6"},
7642         {"RX INT8_1 MIX1 INP0", "RX7", "SLIM RX7"},
7643         {"RX INT8_1 MIX1 INP0", "IIR0", "IIR0"},
7644         {"RX INT8_1 MIX1 INP0", "IIR1", "IIR1"},
7645         {"RX INT8_1 MIX1 INP1", "RX0", "SLIM RX0"},
7646         {"RX INT8_1 MIX1 INP1", "RX1", "SLIM RX1"},
7647         {"RX INT8_1 MIX1 INP1", "RX2", "SLIM RX2"},
7648         {"RX INT8_1 MIX1 INP1", "RX3", "SLIM RX3"},
7649         {"RX INT8_1 MIX1 INP1", "RX4", "SLIM RX4"},
7650         {"RX INT8_1 MIX1 INP1", "RX5", "SLIM RX5"},
7651         {"RX INT8_1 MIX1 INP1", "RX6", "SLIM RX6"},
7652         {"RX INT8_1 MIX1 INP1", "RX7", "SLIM RX7"},
7653         {"RX INT8_1 MIX1 INP1", "IIR0", "IIR0"},
7654         {"RX INT8_1 MIX1 INP1", "IIR1", "IIR1"},
7655         {"RX INT8_1 MIX1 INP2", "RX0", "SLIM RX0"},
7656         {"RX INT8_1 MIX1 INP2", "RX1", "SLIM RX1"},
7657         {"RX INT8_1 MIX1 INP2", "RX2", "SLIM RX2"},
7658         {"RX INT8_1 MIX1 INP2", "RX3", "SLIM RX3"},
7659         {"RX INT8_1 MIX1 INP2", "RX4", "SLIM RX4"},
7660         {"RX INT8_1 MIX1 INP2", "RX5", "SLIM RX5"},
7661         {"RX INT8_1 MIX1 INP2", "RX6", "SLIM RX6"},
7662         {"RX INT8_1 MIX1 INP2", "RX7", "SLIM RX7"},
7663         {"RX INT8_1 MIX1 INP2", "IIR0", "IIR0"},
7664         {"RX INT8_1 MIX1 INP2", "IIR1", "IIR1"},
7665
7666         /* SRC0, SRC1 inputs to Sidetone RX Mixer
7667          * on RX0, RX1, RX2, RX3, RX4 and RX7 chains
7668          */
7669         {"IIR0", NULL, "IIR0 INP0 MUX"},
7670         {"IIR0 INP0 MUX", "DEC0", "ADC MUX0"},
7671         {"IIR0 INP0 MUX", "DEC1", "ADC MUX1"},
7672         {"IIR0 INP0 MUX", "DEC2", "ADC MUX2"},
7673         {"IIR0 INP0 MUX", "DEC3", "ADC MUX3"},
7674         {"IIR0 INP0 MUX", "DEC4", "ADC MUX4"},
7675         {"IIR0 INP0 MUX", "DEC5", "ADC MUX5"},
7676         {"IIR0 INP0 MUX", "DEC6", "ADC MUX6"},
7677         {"IIR0 INP0 MUX", "DEC7", "ADC MUX7"},
7678         {"IIR0 INP0 MUX", "DEC8", "ADC MUX8"},
7679         {"IIR0 INP0 MUX", "RX0", "SLIM RX0"},
7680         {"IIR0 INP0 MUX", "RX1", "SLIM RX1"},
7681         {"IIR0 INP0 MUX", "RX2", "SLIM RX2"},
7682         {"IIR0 INP0 MUX", "RX3", "SLIM RX3"},
7683         {"IIR0 INP0 MUX", "RX4", "SLIM RX4"},
7684         {"IIR0 INP0 MUX", "RX5", "SLIM RX5"},
7685         {"IIR0 INP0 MUX", "RX6", "SLIM RX6"},
7686         {"IIR0 INP0 MUX", "RX7", "SLIM RX7"},
7687         {"IIR0", NULL, "IIR0 INP1 MUX"},
7688         {"IIR0 INP1 MUX", "DEC0", "ADC MUX0"},
7689         {"IIR0 INP1 MUX", "DEC1", "ADC MUX1"},
7690         {"IIR0 INP1 MUX", "DEC2", "ADC MUX2"},
7691         {"IIR0 INP1 MUX", "DEC3", "ADC MUX3"},
7692         {"IIR0 INP1 MUX", "DEC4", "ADC MUX4"},
7693         {"IIR0 INP1 MUX", "DEC5", "ADC MUX5"},
7694         {"IIR0 INP1 MUX", "DEC6", "ADC MUX6"},
7695         {"IIR0 INP1 MUX", "DEC7", "ADC MUX7"},
7696         {"IIR0 INP1 MUX", "DEC8", "ADC MUX8"},
7697         {"IIR0 INP1 MUX", "RX0", "SLIM RX0"},
7698         {"IIR0 INP1 MUX", "RX1", "SLIM RX1"},
7699         {"IIR0 INP1 MUX", "RX2", "SLIM RX2"},
7700         {"IIR0 INP1 MUX", "RX3", "SLIM RX3"},
7701         {"IIR0 INP1 MUX", "RX4", "SLIM RX4"},
7702         {"IIR0 INP1 MUX", "RX5", "SLIM RX5"},
7703         {"IIR0 INP1 MUX", "RX6", "SLIM RX6"},
7704         {"IIR0 INP1 MUX", "RX7", "SLIM RX7"},
7705         {"IIR0", NULL, "IIR0 INP2 MUX"},
7706         {"IIR0 INP2 MUX", "DEC0", "ADC MUX0"},
7707         {"IIR0 INP2 MUX", "DEC1", "ADC MUX1"},
7708         {"IIR0 INP2 MUX", "DEC2", "ADC MUX2"},
7709         {"IIR0 INP2 MUX", "DEC3", "ADC MUX3"},
7710         {"IIR0 INP2 MUX", "DEC4", "ADC MUX4"},
7711         {"IIR0 INP2 MUX", "DEC5", "ADC MUX5"},
7712         {"IIR0 INP2 MUX", "DEC6", "ADC MUX6"},
7713         {"IIR0 INP2 MUX", "DEC7", "ADC MUX7"},
7714         {"IIR0 INP2 MUX", "DEC8", "ADC MUX8"},
7715         {"IIR0 INP2 MUX", "RX0", "SLIM RX0"},
7716         {"IIR0 INP2 MUX", "RX1", "SLIM RX1"},
7717         {"IIR0 INP2 MUX", "RX2", "SLIM RX2"},
7718         {"IIR0 INP2 MUX", "RX3", "SLIM RX3"},
7719         {"IIR0 INP2 MUX", "RX4", "SLIM RX4"},
7720         {"IIR0 INP2 MUX", "RX5", "SLIM RX5"},
7721         {"IIR0 INP2 MUX", "RX6", "SLIM RX6"},
7722         {"IIR0 INP2 MUX", "RX7", "SLIM RX7"},
7723         {"IIR0", NULL, "IIR0 INP3 MUX"},
7724         {"IIR0 INP3 MUX", "DEC0", "ADC MUX0"},
7725         {"IIR0 INP3 MUX", "DEC1", "ADC MUX1"},
7726         {"IIR0 INP3 MUX", "DEC2", "ADC MUX2"},
7727         {"IIR0 INP3 MUX", "DEC3", "ADC MUX3"},
7728         {"IIR0 INP3 MUX", "DEC4", "ADC MUX4"},
7729         {"IIR0 INP3 MUX", "DEC5", "ADC MUX5"},
7730         {"IIR0 INP3 MUX", "DEC6", "ADC MUX6"},
7731         {"IIR0 INP3 MUX", "DEC7", "ADC MUX7"},
7732         {"IIR0 INP3 MUX", "DEC8", "ADC MUX8"},
7733         {"IIR0 INP3 MUX", "RX0", "SLIM RX0"},
7734         {"IIR0 INP3 MUX", "RX1", "SLIM RX1"},
7735         {"IIR0 INP3 MUX", "RX2", "SLIM RX2"},
7736         {"IIR0 INP3 MUX", "RX3", "SLIM RX3"},
7737         {"IIR0 INP3 MUX", "RX4", "SLIM RX4"},
7738         {"IIR0 INP3 MUX", "RX5", "SLIM RX5"},
7739         {"IIR0 INP3 MUX", "RX6", "SLIM RX6"},
7740         {"IIR0 INP3 MUX", "RX7", "SLIM RX7"},
7741
7742         {"IIR1", NULL, "IIR1 INP0 MUX"},
7743         {"IIR1 INP0 MUX", "DEC0", "ADC MUX0"},
7744         {"IIR1 INP0 MUX", "DEC1", "ADC MUX1"},
7745         {"IIR1 INP0 MUX", "DEC2", "ADC MUX2"},
7746         {"IIR1 INP0 MUX", "DEC3", "ADC MUX3"},
7747         {"IIR1 INP0 MUX", "DEC4", "ADC MUX4"},
7748         {"IIR1 INP0 MUX", "DEC5", "ADC MUX5"},
7749         {"IIR1 INP0 MUX", "DEC6", "ADC MUX6"},
7750         {"IIR1 INP0 MUX", "DEC7", "ADC MUX7"},
7751         {"IIR1 INP0 MUX", "DEC8", "ADC MUX8"},
7752         {"IIR1 INP0 MUX", "RX0", "SLIM RX0"},
7753         {"IIR1 INP0 MUX", "RX1", "SLIM RX1"},
7754         {"IIR1 INP0 MUX", "RX2", "SLIM RX2"},
7755         {"IIR1 INP0 MUX", "RX3", "SLIM RX3"},
7756         {"IIR1 INP0 MUX", "RX4", "SLIM RX4"},
7757         {"IIR1 INP0 MUX", "RX5", "SLIM RX5"},
7758         {"IIR1 INP0 MUX", "RX6", "SLIM RX6"},
7759         {"IIR1 INP0 MUX", "RX7", "SLIM RX7"},
7760         {"IIR1", NULL, "IIR1 INP1 MUX"},
7761         {"IIR1 INP1 MUX", "DEC0", "ADC MUX0"},
7762         {"IIR1 INP1 MUX", "DEC1", "ADC MUX1"},
7763         {"IIR1 INP1 MUX", "DEC2", "ADC MUX2"},
7764         {"IIR1 INP1 MUX", "DEC3", "ADC MUX3"},
7765         {"IIR1 INP1 MUX", "DEC4", "ADC MUX4"},
7766         {"IIR1 INP1 MUX", "DEC5", "ADC MUX5"},
7767         {"IIR1 INP1 MUX", "DEC6", "ADC MUX6"},
7768         {"IIR1 INP1 MUX", "DEC7", "ADC MUX7"},
7769         {"IIR1 INP1 MUX", "DEC8", "ADC MUX8"},
7770         {"IIR1 INP1 MUX", "RX0", "SLIM RX0"},
7771         {"IIR1 INP1 MUX", "RX1", "SLIM RX1"},
7772         {"IIR1 INP1 MUX", "RX2", "SLIM RX2"},
7773         {"IIR1 INP1 MUX", "RX3", "SLIM RX3"},
7774         {"IIR1 INP1 MUX", "RX4", "SLIM RX4"},
7775         {"IIR1 INP1 MUX", "RX5", "SLIM RX5"},
7776         {"IIR1 INP1 MUX", "RX6", "SLIM RX6"},
7777         {"IIR1 INP1 MUX", "RX7", "SLIM RX7"},
7778         {"IIR1", NULL, "IIR1 INP2 MUX"},
7779         {"IIR1 INP2 MUX", "DEC0", "ADC MUX0"},
7780         {"IIR1 INP2 MUX", "DEC1", "ADC MUX1"},
7781         {"IIR1 INP2 MUX", "DEC2", "ADC MUX2"},
7782         {"IIR1 INP2 MUX", "DEC3", "ADC MUX3"},
7783         {"IIR1 INP2 MUX", "DEC4", "ADC MUX4"},
7784         {"IIR1 INP2 MUX", "DEC5", "ADC MUX5"},
7785         {"IIR1 INP2 MUX", "DEC6", "ADC MUX6"},
7786         {"IIR1 INP2 MUX", "DEC7", "ADC MUX7"},
7787         {"IIR1 INP2 MUX", "DEC8", "ADC MUX8"},
7788         {"IIR1 INP2 MUX", "RX0", "SLIM RX0"},
7789         {"IIR1 INP2 MUX", "RX1", "SLIM RX1"},
7790         {"IIR1 INP2 MUX", "RX2", "SLIM RX2"},
7791         {"IIR1 INP2 MUX", "RX3", "SLIM RX3"},
7792         {"IIR1 INP2 MUX", "RX4", "SLIM RX4"},
7793         {"IIR1 INP2 MUX", "RX5", "SLIM RX5"},
7794         {"IIR1 INP2 MUX", "RX6", "SLIM RX6"},
7795         {"IIR1 INP2 MUX", "RX7", "SLIM RX7"},
7796         {"IIR1", NULL, "IIR1 INP3 MUX"},
7797         {"IIR1 INP3 MUX", "DEC0", "ADC MUX0"},
7798         {"IIR1 INP3 MUX", "DEC1", "ADC MUX1"},
7799         {"IIR1 INP3 MUX", "DEC2", "ADC MUX2"},
7800         {"IIR1 INP3 MUX", "DEC3", "ADC MUX3"},
7801         {"IIR1 INP3 MUX", "DEC4", "ADC MUX4"},
7802         {"IIR1 INP3 MUX", "DEC5", "ADC MUX5"},
7803         {"IIR1 INP3 MUX", "DEC6", "ADC MUX6"},
7804         {"IIR1 INP3 MUX", "DEC7", "ADC MUX7"},
7805         {"IIR1 INP3 MUX", "DEC8", "ADC MUX8"},
7806         {"IIR1 INP3 MUX", "RX0", "SLIM RX0"},
7807         {"IIR1 INP3 MUX", "RX1", "SLIM RX1"},
7808         {"IIR1 INP3 MUX", "RX2", "SLIM RX2"},
7809         {"IIR1 INP3 MUX", "RX3", "SLIM RX3"},
7810         {"IIR1 INP3 MUX", "RX4", "SLIM RX4"},
7811         {"IIR1 INP3 MUX", "RX5", "SLIM RX5"},
7812         {"IIR1 INP3 MUX", "RX6", "SLIM RX6"},
7813         {"IIR1 INP3 MUX", "RX7", "SLIM RX7"},
7814
7815         {"SRC0", NULL, "IIR0"},
7816         {"SRC1", NULL, "IIR1"},
7817         {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
7818         {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
7819         {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
7820         {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
7821         {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
7822         {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
7823         {"RX INT3 MIX2 INP", "SRC0", "SRC0"},
7824         {"RX INT3 MIX2 INP", "SRC1", "SRC1"},
7825         {"RX INT4 MIX2 INP", "SRC0", "SRC0"},
7826         {"RX INT4 MIX2 INP", "SRC1", "SRC1"},
7827         {"RX INT7 MIX2 INP", "SRC0", "SRC0"},
7828         {"RX INT7 MIX2 INP", "SRC1", "SRC1"},
7829 };
7830
7831 static int tasha_amic_pwr_lvl_get(struct snd_kcontrol *kcontrol,
7832                                  struct snd_ctl_elem_value *ucontrol)
7833 {
7834         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7835         u16 amic_reg;
7836
7837         if (!strcmp(kcontrol->id.name, "AMIC_1_2 PWR MODE"))
7838                 amic_reg = WCD9335_ANA_AMIC1;
7839         if (!strcmp(kcontrol->id.name, "AMIC_3_4 PWR MODE"))
7840                 amic_reg = WCD9335_ANA_AMIC3;
7841         if (!strcmp(kcontrol->id.name, "AMIC_5_6 PWR MODE"))
7842                 amic_reg = WCD9335_ANA_AMIC5;
7843
7844         ucontrol->value.integer.value[0] =
7845                 (snd_soc_read(codec, amic_reg) & WCD9335_AMIC_PWR_LVL_MASK) >>
7846                              WCD9335_AMIC_PWR_LVL_SHIFT;
7847
7848         return 0;
7849 }
7850
7851 static int tasha_amic_pwr_lvl_put(struct snd_kcontrol *kcontrol,
7852                                   struct snd_ctl_elem_value *ucontrol)
7853 {
7854         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7855         u32 mode_val;
7856         u16 amic_reg;
7857
7858         mode_val = ucontrol->value.enumerated.item[0];
7859
7860         dev_dbg(codec->dev, "%s: mode: %d\n",
7861                 __func__, mode_val);
7862
7863         if (!strcmp(kcontrol->id.name, "AMIC_1_2 PWR MODE"))
7864                 amic_reg = WCD9335_ANA_AMIC1;
7865         if (!strcmp(kcontrol->id.name, "AMIC_3_4 PWR MODE"))
7866                 amic_reg = WCD9335_ANA_AMIC3;
7867         if (!strcmp(kcontrol->id.name, "AMIC_5_6 PWR MODE"))
7868                 amic_reg = WCD9335_ANA_AMIC5;
7869
7870         snd_soc_update_bits(codec, amic_reg, WCD9335_AMIC_PWR_LVL_MASK,
7871                             mode_val << WCD9335_AMIC_PWR_LVL_SHIFT);
7872
7873         return 0;
7874 }
7875
7876 static int tasha_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
7877                                  struct snd_ctl_elem_value *ucontrol)
7878 {
7879         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7880         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
7881
7882         ucontrol->value.integer.value[0] = tasha->hph_mode;
7883         return 0;
7884 }
7885
7886 static int tasha_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
7887                                  struct snd_ctl_elem_value *ucontrol)
7888 {
7889         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7890         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
7891         u32 mode_val;
7892
7893         mode_val = ucontrol->value.enumerated.item[0];
7894
7895         dev_dbg(codec->dev, "%s: mode: %d\n",
7896                 __func__, mode_val);
7897
7898         if (mode_val == 0) {
7899                 dev_warn(codec->dev, "%s:Invalid HPH Mode, default to Cls-H HiFi\n",
7900                         __func__);
7901                 mode_val = CLS_H_HIFI;
7902         }
7903         tasha->hph_mode = mode_val;
7904         return 0;
7905 }
7906
7907 static const char *const tasha_conn_mad_text[] = {
7908         "NOTUSED1", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6",
7909         "NOTUSED2", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4",
7910         "DMIC5", "NOTUSED3", "NOTUSED4"
7911 };
7912
7913 static const struct soc_enum tasha_conn_mad_enum =
7914         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tasha_conn_mad_text),
7915                             tasha_conn_mad_text);
7916
7917 static int tasha_enable_ldo_h_get(struct snd_kcontrol *kcontrol,
7918                                   struct snd_ctl_elem_value *ucontrol)
7919 {
7920         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7921         u8 val = 0;
7922
7923         if (codec)
7924                 val = snd_soc_read(codec, WCD9335_LDOH_MODE) & 0x80;
7925
7926         ucontrol->value.integer.value[0] = !!val;
7927
7928         return 0;
7929 }
7930
7931 static int tasha_enable_ldo_h_put(struct snd_kcontrol *kcontrol,
7932                                   struct snd_ctl_elem_value *ucontrol)
7933 {
7934         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7935         int value = ucontrol->value.integer.value[0];
7936         bool enable;
7937
7938         enable = !!value;
7939         if (codec)
7940                 tasha_codec_enable_standalone_ldo_h(codec, enable);
7941
7942         return 0;
7943 }
7944
7945 static int tasha_mad_input_get(struct snd_kcontrol *kcontrol,
7946         struct snd_ctl_elem_value *ucontrol)
7947 {
7948         u8 tasha_mad_input;
7949         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7950
7951         tasha_mad_input = snd_soc_read(codec,
7952                                 WCD9335_SOC_MAD_INP_SEL) & 0x0F;
7953         ucontrol->value.integer.value[0] = tasha_mad_input;
7954
7955         dev_dbg(codec->dev,
7956                 "%s: tasha_mad_input = %s\n", __func__,
7957                 tasha_conn_mad_text[tasha_mad_input]);
7958         return 0;
7959 }
7960
7961 static int tasha_mad_input_put(struct snd_kcontrol *kcontrol,
7962         struct snd_ctl_elem_value *ucontrol)
7963 {
7964         u8 tasha_mad_input;
7965         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
7966         struct snd_soc_card *card = codec->component.card;
7967         char mad_amic_input_widget[6];
7968         const char *mad_input_widget;
7969         const char *source_widget = NULL;
7970         u32 adc, i, mic_bias_found = 0;
7971         int ret = 0;
7972         char *mad_input;
7973
7974         tasha_mad_input = ucontrol->value.integer.value[0];
7975
7976         if (tasha_mad_input >= ARRAY_SIZE(tasha_conn_mad_text)) {
7977                 dev_err(codec->dev,
7978                         "%s: tasha_mad_input = %d out of bounds\n",
7979                         __func__, tasha_mad_input);
7980                 return -EINVAL;
7981         }
7982
7983         if (!strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED1") ||
7984             !strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED2") ||
7985             !strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED3") ||
7986             !strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED4")) {
7987                 dev_err(codec->dev,
7988                         "%s: Unsupported tasha_mad_input = %s\n",
7989                         __func__, tasha_conn_mad_text[tasha_mad_input]);
7990                 return -EINVAL;
7991         }
7992
7993         if (strnstr(tasha_conn_mad_text[tasha_mad_input],
7994                     "ADC", sizeof("ADC"))) {
7995                 mad_input = strpbrk(tasha_conn_mad_text[tasha_mad_input],
7996                                     "123456");
7997                 if (!mad_input) {
7998                         dev_err(codec->dev, "%s: Invalid MAD input %s\n",
7999                                 __func__,
8000                                 tasha_conn_mad_text[tasha_mad_input]);
8001                         return -EINVAL;
8002                 }
8003                 ret = kstrtouint(mad_input, 10, &adc);
8004                 if ((ret < 0) || (adc > 6)) {
8005                         dev_err(codec->dev,
8006                                 "%s: Invalid ADC = %s\n", __func__,
8007                                 tasha_conn_mad_text[tasha_mad_input]);
8008                         ret =  -EINVAL;
8009                 }
8010
8011                 snprintf(mad_amic_input_widget, 6, "%s%u", "AMIC", adc);
8012
8013                 mad_input_widget = mad_amic_input_widget;
8014         } else {
8015                 /* DMIC type input widget*/
8016                 mad_input_widget = tasha_conn_mad_text[tasha_mad_input];
8017         }
8018
8019         dev_dbg(codec->dev,
8020                 "%s: tasha input widget = %s\n", __func__,
8021                 mad_input_widget);
8022
8023         for (i = 0; i < card->num_of_dapm_routes; i++) {
8024                 if (!strcmp(card->of_dapm_routes[i].sink, mad_input_widget)) {
8025                         source_widget = card->of_dapm_routes[i].source;
8026                         if (!source_widget) {
8027                                 dev_err(codec->dev,
8028                                         "%s: invalid source widget\n",
8029                                         __func__);
8030                                 return -EINVAL;
8031                         }
8032
8033                         if (strnstr(source_widget,
8034                                 "MIC BIAS1", sizeof("MIC BIAS1"))) {
8035                                 mic_bias_found = 1;
8036                                 break;
8037                         } else if (strnstr(source_widget,
8038                                 "MIC BIAS2", sizeof("MIC BIAS2"))) {
8039                                 mic_bias_found = 2;
8040                                 break;
8041                         } else if (strnstr(source_widget,
8042                                 "MIC BIAS3", sizeof("MIC BIAS3"))) {
8043                                 mic_bias_found = 3;
8044                                 break;
8045                         } else if (strnstr(source_widget,
8046                                 "MIC BIAS4", sizeof("MIC BIAS4"))) {
8047                                 mic_bias_found = 4;
8048                                 break;
8049                         }
8050                 }
8051         }
8052
8053         if (!mic_bias_found) {
8054                 dev_err(codec->dev,
8055                         "%s: mic bias source not found for input = %s\n",
8056                         __func__, mad_input_widget);
8057                 return -EINVAL;
8058         }
8059
8060         dev_dbg(codec->dev,
8061                 "%s: mic_bias found = %d\n", __func__,
8062                 mic_bias_found);
8063
8064         snd_soc_update_bits(codec, WCD9335_SOC_MAD_INP_SEL,
8065                             0x0F, tasha_mad_input);
8066         snd_soc_update_bits(codec, WCD9335_ANA_MAD_SETUP,
8067                             0x07, mic_bias_found);
8068
8069         return 0;
8070 }
8071
8072 static int tasha_pinctl_mode_get(struct snd_kcontrol *kcontrol,
8073         struct snd_ctl_elem_value *ucontrol)
8074 {
8075         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8076         u16 ctl_reg;
8077         u8 reg_val, pinctl_position;
8078
8079         pinctl_position = ((struct soc_multi_mixer_control *)
8080                                         kcontrol->private_value)->shift;
8081         switch (pinctl_position >> 3) {
8082         case 0:
8083                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_0;
8084                 break;
8085         case 1:
8086                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_1;
8087                 break;
8088         case 2:
8089                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_2;
8090                 break;
8091         case 3:
8092                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_3;
8093                 break;
8094         default:
8095                 dev_err(codec->dev, "%s: Invalid pinctl position = %d\n",
8096                         __func__, pinctl_position);
8097                 return -EINVAL;
8098         }
8099
8100         reg_val = snd_soc_read(codec, ctl_reg);
8101         reg_val = (reg_val >> (pinctl_position & 0x07)) & 0x1;
8102         ucontrol->value.integer.value[0] = reg_val;
8103
8104         return 0;
8105 }
8106
8107 static int tasha_pinctl_mode_put(struct snd_kcontrol *kcontrol,
8108         struct snd_ctl_elem_value *ucontrol)
8109 {
8110         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8111         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8112         u16 ctl_reg, cfg_reg;
8113         u8 ctl_val, cfg_val, pinctl_position, pinctl_mode, mask;
8114
8115         /* 1- high or low; 0- high Z */
8116         pinctl_mode = ucontrol->value.integer.value[0];
8117         pinctl_position = ((struct soc_multi_mixer_control *)
8118                                         kcontrol->private_value)->shift;
8119
8120         switch (pinctl_position >> 3) {
8121         case 0:
8122                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_0;
8123                 break;
8124         case 1:
8125                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_1;
8126                 break;
8127         case 2:
8128                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_2;
8129                 break;
8130         case 3:
8131                 ctl_reg = WCD9335_TEST_DEBUG_PIN_CTL_OE_3;
8132                 break;
8133         default:
8134                 dev_err(codec->dev, "%s: Invalid pinctl position = %d\n",
8135                         __func__, pinctl_position);
8136                 return -EINVAL;
8137         }
8138
8139         ctl_val = pinctl_mode << (pinctl_position & 0x07);
8140         mask = 1 << (pinctl_position & 0x07);
8141         snd_soc_update_bits(codec, ctl_reg, mask, ctl_val);
8142
8143         cfg_reg = WCD9335_TLMM_BIST_MODE_PINCFG + pinctl_position;
8144         if (!pinctl_mode) {
8145                 if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
8146                         cfg_val = 0x4;
8147                 else
8148                         cfg_val = 0xC;
8149         } else {
8150                 cfg_val = 0;
8151         }
8152         snd_soc_update_bits(codec, cfg_reg, 0x07, cfg_val);
8153
8154         dev_dbg(codec->dev, "%s: reg=0x%x mask=0x%x val=%d reg=0x%x val=%d\n",
8155                         __func__, ctl_reg, mask, ctl_val, cfg_reg, cfg_val);
8156
8157         return 0;
8158 }
8159
8160 static void wcd_vbat_adc_out_config_2_0(struct wcd_vbat *vbat,
8161                                         struct snd_soc_codec *codec)
8162 {
8163         u8 val1, val2;
8164
8165         /*
8166          * Measure dcp1 by using "ALT" branch of band gap
8167          * voltage(Vbg) and use it in FAST mode
8168          */
8169         snd_soc_update_bits(codec, WCD9335_BIAS_CTL, 0x82, 0x82);
8170         snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x10, 0x10);
8171         snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x01, 0x01);
8172         snd_soc_update_bits(codec, WCD9335_ANA_VBADC, 0x80, 0x80);
8173         snd_soc_update_bits(codec, WCD9335_VBADC_SUBBLOCK_EN, 0x20, 0x00);
8174
8175         snd_soc_update_bits(codec, WCD9335_VBADC_FE_CTRL, 0x20, 0x20);
8176         /* Wait 100 usec after calibration select as Vbg */
8177         usleep_range(100, 110);
8178
8179         snd_soc_update_bits(codec, WCD9335_VBADC_ADC_IO, 0x40, 0x40);
8180         val1 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTMSB);
8181         val2 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTLSB);
8182         snd_soc_update_bits(codec, WCD9335_VBADC_ADC_IO, 0x40, 0x00);
8183
8184         vbat->dcp1 = (((val1 & 0xFF) << 3) | (val2 & 0x07));
8185
8186         snd_soc_update_bits(codec, WCD9335_BIAS_CTL, 0x40, 0x40);
8187         /* Wait 100 usec after selecting Vbg as 1.05V */
8188         usleep_range(100, 110);
8189
8190         snd_soc_update_bits(codec, WCD9335_VBADC_ADC_IO, 0x40, 0x40);
8191         val1 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTMSB);
8192         val2 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTLSB);
8193         snd_soc_update_bits(codec, WCD9335_VBADC_ADC_IO, 0x40, 0x00);
8194
8195         vbat->dcp2 = (((val1 & 0xFF) << 3) | (val2 & 0x07));
8196
8197         dev_dbg(codec->dev, "%s: dcp1:0x%x, dcp2:0x%x\n",
8198                 __func__, vbat->dcp1, vbat->dcp2);
8199
8200         snd_soc_write(codec, WCD9335_BIAS_CTL, 0x28);
8201         /* Wait 100 usec after selecting Vbg as 0.85V */
8202         usleep_range(100, 110);
8203
8204         snd_soc_update_bits(codec, WCD9335_VBADC_FE_CTRL, 0x20, 0x00);
8205         snd_soc_update_bits(codec, WCD9335_VBADC_SUBBLOCK_EN, 0x20, 0x20);
8206         snd_soc_update_bits(codec, WCD9335_ANA_VBADC, 0x80, 0x00);
8207
8208         snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x10, 0x00);
8209         snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x01, 0x00);
8210 }
8211
8212 static void wcd_vbat_adc_out_config_1_x(struct wcd_vbat *vbat,
8213                                         struct snd_soc_codec *codec)
8214 {
8215         u8 val1, val2;
8216
8217         /*
8218          * Measure dcp1 by applying band gap voltage(Vbg)
8219          * of 0.85V
8220          */
8221         snd_soc_write(codec, WCD9335_ANA_BIAS, 0x20);
8222         snd_soc_write(codec, WCD9335_BIAS_CTL, 0x28);
8223         snd_soc_write(codec, WCD9335_BIAS_VBG_FINE_ADJ, 0x05);
8224         snd_soc_write(codec, WCD9335_ANA_BIAS, 0xA0);
8225         /* Wait 2 sec after enabling band gap bias */
8226         usleep_range(2000000, 2000100);
8227
8228         snd_soc_write(codec, WCD9335_ANA_CLK_TOP, 0x82);
8229         snd_soc_write(codec, WCD9335_ANA_CLK_TOP, 0x87);
8230         snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x10, 0x10);
8231         snd_soc_write(codec, WCD9335_CDC_VBAT_VBAT_CFG, 0x0D);
8232         snd_soc_write(codec, WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x01);
8233
8234         snd_soc_write(codec, WCD9335_ANA_VBADC, 0x80);
8235         snd_soc_write(codec, WCD9335_VBADC_SUBBLOCK_EN, 0xDE);
8236         snd_soc_write(codec, WCD9335_VBADC_FE_CTRL, 0x3C);
8237         /* Wait 1 msec after calibration select as Vbg */
8238         usleep_range(1000, 1100);
8239
8240         snd_soc_write(codec, WCD9335_VBADC_ADC_IO, 0xC0);
8241         val1 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTMSB);
8242         val2 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTLSB);
8243         snd_soc_write(codec, WCD9335_VBADC_ADC_IO, 0x80);
8244
8245         vbat->dcp1 = (((val1 & 0xFF) << 3) | (val2 & 0x07));
8246
8247         /*
8248          * Measure dcp2 by applying band gap voltage(Vbg)
8249          * of 1.05V
8250          */
8251         snd_soc_write(codec, WCD9335_ANA_BIAS, 0x80);
8252         snd_soc_write(codec, WCD9335_ANA_BIAS, 0xC0);
8253         snd_soc_write(codec, WCD9335_BIAS_CTL, 0x68);
8254         /* Wait 2 msec after selecting Vbg as 1.05V */
8255         usleep_range(2000, 2100);
8256
8257         snd_soc_write(codec, WCD9335_ANA_BIAS, 0x80);
8258         /* Wait 1 sec after enabling band gap bias */
8259         usleep_range(1000000, 1000100);
8260
8261         snd_soc_write(codec, WCD9335_VBADC_ADC_IO, 0xC0);
8262         val1 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTMSB);
8263         val2 = snd_soc_read(codec, WCD9335_VBADC_ADC_DOUTLSB);
8264         snd_soc_write(codec, WCD9335_VBADC_ADC_IO, 0x80);
8265
8266         vbat->dcp2 = (((val1 & 0xFF) << 3) | (val2 & 0x07));
8267
8268         dev_dbg(codec->dev, "%s: dcp1:0x%x, dcp2:0x%x\n",
8269                 __func__, vbat->dcp1, vbat->dcp2);
8270
8271         /* Reset the Vbat ADC configuration */
8272         snd_soc_write(codec, WCD9335_ANA_BIAS, 0x80);
8273         snd_soc_write(codec, WCD9335_ANA_BIAS, 0xC0);
8274
8275         snd_soc_write(codec, WCD9335_BIAS_CTL, 0x28);
8276         /* Wait 2 msec after selecting Vbg as 0.85V */
8277         usleep_range(2000, 2100);
8278
8279         snd_soc_write(codec, WCD9335_ANA_BIAS, 0xA0);
8280         /* Wait 1 sec after enabling band gap bias */
8281         usleep_range(1000000, 1000100);
8282
8283         snd_soc_write(codec, WCD9335_VBADC_FE_CTRL, 0x1C);
8284         snd_soc_write(codec, WCD9335_VBADC_SUBBLOCK_EN, 0xFE);
8285         snd_soc_write(codec, WCD9335_VBADC_ADC_IO, 0x80);
8286         snd_soc_write(codec, WCD9335_ANA_VBADC, 0x00);
8287
8288         snd_soc_write(codec, WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x00);
8289         snd_soc_write(codec, WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x00);
8290         snd_soc_write(codec, WCD9335_CDC_VBAT_VBAT_CFG, 0x0A);
8291 }
8292
8293 static void wcd_vbat_adc_out_config(struct wcd_vbat *vbat,
8294                                 struct snd_soc_codec *codec)
8295 {
8296         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
8297
8298         if (!vbat->adc_config) {
8299                 tasha_cdc_mclk_enable(codec, true, false);
8300
8301                 if (TASHA_IS_2_0(wcd9xxx))
8302                         wcd_vbat_adc_out_config_2_0(vbat, codec);
8303                 else
8304                         wcd_vbat_adc_out_config_1_x(vbat, codec);
8305
8306                 tasha_cdc_mclk_enable(codec, false, false);
8307                 vbat->adc_config = true;
8308         }
8309 }
8310
8311 static int tasha_update_vbat_reg_config(struct snd_soc_codec *codec)
8312 {
8313         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8314         struct firmware_cal *hwdep_cal = NULL;
8315         struct vbat_monitor_reg *vbat_reg_ptr = NULL;
8316         const void *data;
8317         size_t cal_size, vbat_size_remaining;
8318         int ret = 0, i;
8319         u32 vbat_writes_size = 0;
8320         u16 reg;
8321         u8 mask, val, old_val;
8322
8323         hwdep_cal = wcdcal_get_fw_cal(tasha->fw_data, WCD9XXX_VBAT_CAL);
8324         if (hwdep_cal) {
8325                 data = hwdep_cal->data;
8326                 cal_size = hwdep_cal->size;
8327                 dev_dbg(codec->dev, "%s: using hwdep calibration\n",
8328                         __func__);
8329         } else {
8330                 dev_err(codec->dev, "%s: Vbat cal not received\n",
8331                         __func__);
8332                 ret = -EINVAL;
8333                 goto done;
8334         }
8335
8336         if (cal_size < sizeof(*vbat_reg_ptr)) {
8337                 dev_err(codec->dev,
8338                         "%s: Incorrect size %zd for Vbat Cal, expected %zd\n",
8339                         __func__, cal_size, sizeof(*vbat_reg_ptr));
8340                 ret = -EINVAL;
8341                 goto done;
8342         }
8343
8344         vbat_reg_ptr = (struct vbat_monitor_reg *) (data);
8345
8346         if (!vbat_reg_ptr) {
8347                 dev_err(codec->dev,
8348                         "%s: Invalid calibration data for Vbat\n",
8349                         __func__);
8350                 ret = -EINVAL;
8351                 goto done;
8352         }
8353
8354         vbat_writes_size = vbat_reg_ptr->size;
8355         vbat_size_remaining = cal_size - sizeof(u32);
8356         dev_dbg(codec->dev, "%s: vbat_writes_sz: %d, vbat_sz_remaining: %zd\n",
8357                         __func__, vbat_writes_size, vbat_size_remaining);
8358
8359         if ((vbat_writes_size * TASHA_PACKED_REG_SIZE)
8360                                         > vbat_size_remaining) {
8361                 pr_err("%s: Incorrect Vbat calibration data\n", __func__);
8362                 ret = -EINVAL;
8363                 goto done;
8364         }
8365
8366         for (i = 0 ; i < vbat_writes_size; i++) {
8367                 TASHA_CODEC_UNPACK_ENTRY(vbat_reg_ptr->writes[i],
8368                                         reg, mask, val);
8369                 old_val = snd_soc_read(codec, reg);
8370                 snd_soc_write(codec, reg, (old_val & ~mask) | (val & mask));
8371         }
8372
8373 done:
8374         return ret;
8375 }
8376
8377 static int tasha_vbat_adc_data_get(struct snd_kcontrol *kcontrol,
8378                 struct snd_ctl_elem_value *ucontrol)
8379 {
8380         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8381         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8382
8383         wcd_vbat_adc_out_config(&tasha->vbat, codec);
8384
8385         ucontrol->value.integer.value[0] = tasha->vbat.dcp1;
8386         ucontrol->value.integer.value[1] = tasha->vbat.dcp2;
8387
8388         dev_dbg(codec->dev,
8389                 "%s: Vbat ADC output values, Dcp1 : %lu, Dcp2: %lu\n",
8390                 __func__, ucontrol->value.integer.value[0],
8391                 ucontrol->value.integer.value[1]);
8392
8393         return 0;
8394 }
8395
8396 static const char * const tasha_vbat_gsm_mode_text[] = {
8397         "OFF", "ON"};
8398
8399 static const struct soc_enum tasha_vbat_gsm_mode_enum =
8400         SOC_ENUM_SINGLE_EXT(2, tasha_vbat_gsm_mode_text);
8401
8402 static int tasha_vbat_gsm_mode_func_get(struct snd_kcontrol *kcontrol,
8403         struct snd_ctl_elem_value *ucontrol)
8404 {
8405         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8406
8407         ucontrol->value.integer.value[0] =
8408                 ((snd_soc_read(codec, WCD9335_CDC_VBAT_VBAT_CFG) & 0x04) ?
8409                   1 : 0);
8410
8411         dev_dbg(codec->dev, "%s: value: %lu\n", __func__,
8412                 ucontrol->value.integer.value[0]);
8413
8414         return 0;
8415 }
8416
8417 static int tasha_vbat_gsm_mode_func_put(struct snd_kcontrol *kcontrol,
8418                                         struct snd_ctl_elem_value *ucontrol)
8419 {
8420         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8421
8422         dev_dbg(codec->dev, "%s: value: %lu\n", __func__,
8423                 ucontrol->value.integer.value[0]);
8424
8425         /* Set Vbat register configuration for GSM mode bit based on value */
8426         if (ucontrol->value.integer.value[0])
8427                 snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_CFG,
8428                                                 0x04, 0x04);
8429         else
8430                 snd_soc_update_bits(codec, WCD9335_CDC_VBAT_VBAT_CFG,
8431                                                 0x04, 0x00);
8432
8433         return 0;
8434 }
8435
8436 static int tasha_codec_vbat_enable_event(struct snd_soc_dapm_widget *w,
8437                                 struct snd_kcontrol *kcontrol,
8438                                 int event)
8439 {
8440         int ret = 0;
8441         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
8442         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8443         u16 vbat_path_ctl, vbat_cfg, vbat_path_cfg;
8444
8445         vbat_path_ctl = WCD9335_CDC_VBAT_VBAT_PATH_CTL;
8446         vbat_cfg = WCD9335_CDC_VBAT_VBAT_CFG;
8447         vbat_path_cfg = WCD9335_CDC_RX8_RX_PATH_CFG1;
8448
8449         if (!strcmp(w->name, "RX INT8 VBAT"))
8450                 vbat_path_cfg = WCD9335_CDC_RX8_RX_PATH_CFG1;
8451         else if (!strcmp(w->name, "RX INT7 VBAT"))
8452                 vbat_path_cfg = WCD9335_CDC_RX7_RX_PATH_CFG1;
8453         else if (!strcmp(w->name, "RX INT6 VBAT"))
8454                 vbat_path_cfg = WCD9335_CDC_RX6_RX_PATH_CFG1;
8455         else if (!strcmp(w->name, "RX INT5 VBAT"))
8456                 vbat_path_cfg = WCD9335_CDC_RX5_RX_PATH_CFG1;
8457
8458         switch (event) {
8459         case SND_SOC_DAPM_PRE_PMU:
8460                 ret = tasha_update_vbat_reg_config(codec);
8461                 if (ret) {
8462                         dev_dbg(codec->dev,
8463                                 "%s : VBAT isn't calibrated, So not enabling it\n",
8464                                 __func__);
8465                         return 0;
8466                 }
8467                 snd_soc_write(codec, WCD9335_ANA_VBADC, 0x80);
8468                 snd_soc_update_bits(codec, vbat_path_cfg, 0x02, 0x02);
8469                 snd_soc_update_bits(codec, vbat_path_ctl, 0x10, 0x10);
8470                 snd_soc_update_bits(codec, vbat_cfg, 0x01, 0x01);
8471                 tasha->vbat.is_enabled = true;
8472                 break;
8473         case SND_SOC_DAPM_POST_PMD:
8474                 if (tasha->vbat.is_enabled) {
8475                         snd_soc_update_bits(codec, vbat_cfg, 0x01, 0x00);
8476                         snd_soc_update_bits(codec, vbat_path_ctl, 0x10, 0x00);
8477                         snd_soc_update_bits(codec, vbat_path_cfg, 0x02, 0x00);
8478                         snd_soc_write(codec, WCD9335_ANA_VBADC, 0x00);
8479                         tasha->vbat.is_enabled = false;
8480                 }
8481                 break;
8482         };
8483
8484         return ret;
8485 }
8486
8487 static const char * const rx_hph_mode_mux_text[] = {
8488         "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI"
8489 };
8490
8491 static const struct soc_enum rx_hph_mode_mux_enum =
8492         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
8493                             rx_hph_mode_mux_text);
8494
8495 static const char * const amic_pwr_lvl_text[] = {
8496         "LOW_PWR", "DEFAULT", "HIGH_PERF"
8497 };
8498
8499 static const struct soc_enum amic_pwr_lvl_enum =
8500         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amic_pwr_lvl_text),
8501                             amic_pwr_lvl_text);
8502
8503 static const struct snd_kcontrol_new tasha_snd_controls[] = {
8504         SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
8505                 0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8506         SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
8507                 0, -84, 40, digital_gain),
8508         SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
8509                 0, -84, 40, digital_gain),
8510         SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
8511                 0, -84, 40, digital_gain),
8512         SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
8513                 0, -84, 40, digital_gain),
8514         SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
8515                 0, -84, 40, digital_gain),
8516         SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
8517                 0, -84, 40, digital_gain),
8518         SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
8519                 0, -84, 40, digital_gain),
8520         SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
8521                 0, -84, 40, digital_gain),
8522
8523         SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume",
8524                           WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
8525                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8526         SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume",
8527                           WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
8528                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8529         SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume",
8530                           WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
8531                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8532         SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume",
8533                           WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
8534                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8535         SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume",
8536                           WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
8537                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8538         SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume",
8539                           WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
8540                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8541         SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume",
8542                           WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
8543                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8544         SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume",
8545                           WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
8546                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8547         SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume",
8548                           WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
8549                           0, -84, 40, digital_gain), /* -84dB min - 40dB max */
8550
8551         SOC_SINGLE_SX_TLV("DEC0 Volume", WCD9335_CDC_TX0_TX_VOL_CTL, 0,
8552                                           -84, 40, digital_gain),
8553         SOC_SINGLE_SX_TLV("DEC1 Volume", WCD9335_CDC_TX1_TX_VOL_CTL, 0,
8554                                           -84, 40, digital_gain),
8555         SOC_SINGLE_SX_TLV("DEC2 Volume", WCD9335_CDC_TX2_TX_VOL_CTL, 0,
8556                                           -84, 40, digital_gain),
8557         SOC_SINGLE_SX_TLV("DEC3 Volume", WCD9335_CDC_TX3_TX_VOL_CTL, 0,
8558                                           -84, 40, digital_gain),
8559         SOC_SINGLE_SX_TLV("DEC4 Volume", WCD9335_CDC_TX4_TX_VOL_CTL, 0,
8560                                           -84, 40, digital_gain),
8561         SOC_SINGLE_SX_TLV("DEC5 Volume", WCD9335_CDC_TX5_TX_VOL_CTL, 0,
8562                                           -84, 40, digital_gain),
8563         SOC_SINGLE_SX_TLV("DEC6 Volume", WCD9335_CDC_TX6_TX_VOL_CTL, 0,
8564                                           -84, 40, digital_gain),
8565         SOC_SINGLE_SX_TLV("DEC7 Volume", WCD9335_CDC_TX7_TX_VOL_CTL, 0,
8566                                           -84, 40, digital_gain),
8567         SOC_SINGLE_SX_TLV("DEC8 Volume", WCD9335_CDC_TX8_TX_VOL_CTL, 0,
8568                                           -84, 40, digital_gain),
8569
8570         SOC_SINGLE_SX_TLV("IIR0 INP0 Volume",
8571                           WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0, -84,
8572                           40, digital_gain),
8573         SOC_SINGLE_SX_TLV("IIR0 INP1 Volume",
8574                           WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0, -84,
8575                           40, digital_gain),
8576         SOC_SINGLE_SX_TLV("IIR0 INP2 Volume",
8577                           WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0, -84,
8578                           40, digital_gain),
8579         SOC_SINGLE_SX_TLV("IIR0 INP3 Volume",
8580                           WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0, -84,
8581                           40, digital_gain),
8582         SOC_SINGLE_SX_TLV("IIR1 INP0 Volume",
8583                           WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0, -84,
8584                           40, digital_gain),
8585         SOC_SINGLE_SX_TLV("IIR1 INP1 Volume",
8586                           WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0, -84,
8587                           40, digital_gain),
8588         SOC_SINGLE_SX_TLV("IIR1 INP2 Volume",
8589                           WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0, -84,
8590                           40, digital_gain),
8591         SOC_SINGLE_SX_TLV("IIR1 INP3 Volume",
8592                           WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0, -84,
8593                           40, digital_gain),
8594
8595         SOC_SINGLE_EXT("ANC Slot", SND_SOC_NOPM, 0, 100, 0, tasha_get_anc_slot,
8596                        tasha_put_anc_slot),
8597         SOC_ENUM_EXT("ANC Function", tasha_anc_func_enum, tasha_get_anc_func,
8598                      tasha_put_anc_func),
8599
8600         SOC_ENUM_EXT("CLK MODE", tasha_clkmode_enum, tasha_get_clkmode,
8601                      tasha_put_clkmode),
8602
8603         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
8604         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
8605         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
8606         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
8607         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
8608         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
8609         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
8610         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
8611         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
8612
8613         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
8614         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
8615         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
8616         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
8617         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
8618         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
8619         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
8620         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
8621         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
8622         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
8623         SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
8624         SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
8625         SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
8626         SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
8627         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
8628         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
8629         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
8630         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
8631
8632         SOC_SINGLE_EXT("IIR0 Enable Band1", IIR0, BAND1, 1, 0,
8633         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8634         SOC_SINGLE_EXT("IIR0 Enable Band2", IIR0, BAND2, 1, 0,
8635         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8636         SOC_SINGLE_EXT("IIR0 Enable Band3", IIR0, BAND3, 1, 0,
8637         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8638         SOC_SINGLE_EXT("IIR0 Enable Band4", IIR0, BAND4, 1, 0,
8639         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8640         SOC_SINGLE_EXT("IIR0 Enable Band5", IIR0, BAND5, 1, 0,
8641         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8642         SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
8643         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8644         SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
8645         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8646         SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
8647         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8648         SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
8649         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8650         SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
8651         tasha_get_iir_enable_audio_mixer, tasha_put_iir_enable_audio_mixer),
8652
8653         SOC_SINGLE_MULTI_EXT("IIR0 Band1", IIR0, BAND1, 255, 0, 5,
8654         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8655         SOC_SINGLE_MULTI_EXT("IIR0 Band2", IIR0, BAND2, 255, 0, 5,
8656         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8657         SOC_SINGLE_MULTI_EXT("IIR0 Band3", IIR0, BAND3, 255, 0, 5,
8658         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8659         SOC_SINGLE_MULTI_EXT("IIR0 Band4", IIR0, BAND4, 255, 0, 5,
8660         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8661         SOC_SINGLE_MULTI_EXT("IIR0 Band5", IIR0, BAND5, 255, 0, 5,
8662         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8663         SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
8664         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8665         SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
8666         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8667         SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
8668         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8669         SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
8670         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8671         SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
8672         tasha_get_iir_band_audio_mixer, tasha_put_iir_band_audio_mixer),
8673
8674         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
8675                        tasha_get_compander, tasha_set_compander),
8676         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
8677                        tasha_get_compander, tasha_set_compander),
8678         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
8679                        tasha_get_compander, tasha_set_compander),
8680         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
8681                        tasha_get_compander, tasha_set_compander),
8682         SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
8683                        tasha_get_compander, tasha_set_compander),
8684         SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
8685                        tasha_get_compander, tasha_set_compander),
8686         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
8687                        tasha_get_compander, tasha_set_compander),
8688         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
8689                        tasha_get_compander, tasha_set_compander),
8690
8691         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
8692                        tasha_rx_hph_mode_get, tasha_rx_hph_mode_put),
8693
8694         SOC_ENUM_EXT("MAD Input", tasha_conn_mad_enum,
8695                      tasha_mad_input_get, tasha_mad_input_put),
8696         SOC_SINGLE_EXT("LDO_H Enable", SND_SOC_NOPM, 0, 1, 0,
8697                         tasha_enable_ldo_h_get, tasha_enable_ldo_h_put),
8698
8699         SOC_SINGLE_EXT("DMIC1_CLK_PIN_MODE", SND_SOC_NOPM, 17, 1, 0,
8700                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8701
8702         SOC_SINGLE_EXT("DMIC1_DATA_PIN_MODE", SND_SOC_NOPM, 18, 1, 0,
8703                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8704
8705         SOC_SINGLE_EXT("DMIC2_CLK_PIN_MODE", SND_SOC_NOPM, 19, 1, 0,
8706                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8707
8708         SOC_SINGLE_EXT("DMIC2_DATA_PIN_MODE", SND_SOC_NOPM, 20, 1, 0,
8709                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8710
8711         SOC_SINGLE_EXT("DMIC3_CLK_PIN_MODE", SND_SOC_NOPM, 21, 1, 0,
8712                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8713
8714         SOC_SINGLE_EXT("DMIC3_DATA_PIN_MODE", SND_SOC_NOPM, 22, 1, 0,
8715                        tasha_pinctl_mode_get, tasha_pinctl_mode_put),
8716         SOC_ENUM_EXT("AMIC_1_2 PWR MODE", amic_pwr_lvl_enum,
8717                        tasha_amic_pwr_lvl_get, tasha_amic_pwr_lvl_put),
8718         SOC_ENUM_EXT("AMIC_3_4 PWR MODE", amic_pwr_lvl_enum,
8719                        tasha_amic_pwr_lvl_get, tasha_amic_pwr_lvl_put),
8720         SOC_ENUM_EXT("AMIC_5_6 PWR MODE", amic_pwr_lvl_enum,
8721                        tasha_amic_pwr_lvl_get, tasha_amic_pwr_lvl_put),
8722
8723         SOC_SINGLE_MULTI_EXT("Vbat ADC data", SND_SOC_NOPM, 0, 0xFFFF, 0, 2,
8724                         tasha_vbat_adc_data_get, NULL),
8725
8726         SOC_ENUM_EXT("GSM mode Enable", tasha_vbat_gsm_mode_enum,
8727                         tasha_vbat_gsm_mode_func_get,
8728                         tasha_vbat_gsm_mode_func_put),
8729 };
8730
8731 static int tasha_put_dec_enum(struct snd_kcontrol *kcontrol,
8732                               struct snd_ctl_elem_value *ucontrol)
8733 {
8734         struct snd_soc_dapm_widget_list *wlist =
8735                                         dapm_kcontrol_get_wlist(kcontrol);
8736         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
8737         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
8738         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
8739         unsigned int val;
8740         u16 mic_sel_reg;
8741         u8 mic_sel;
8742
8743         val = ucontrol->value.enumerated.item[0];
8744         if (val > e->items - 1)
8745                 return -EINVAL;
8746
8747         dev_dbg(codec->dev, "%s: wname: %s, val: 0x%x\n", __func__,
8748                 widget->name, val);
8749
8750         switch (e->reg) {
8751         case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
8752                 mic_sel_reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
8753                 break;
8754         case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
8755                 mic_sel_reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
8756                 break;
8757         case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
8758                 mic_sel_reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
8759                 break;
8760         case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
8761                 mic_sel_reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
8762                 break;
8763         case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
8764                 mic_sel_reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
8765                 break;
8766         case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
8767                 mic_sel_reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
8768                 break;
8769         case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
8770                 mic_sel_reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
8771                 break;
8772         case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
8773                 mic_sel_reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
8774                 break;
8775         case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
8776                 mic_sel_reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
8777                 break;
8778         default:
8779                 dev_err(codec->dev, "%s: e->reg: 0x%x not expected\n",
8780                         __func__, e->reg);
8781                 return -EINVAL;
8782         }
8783
8784         /* ADC: 0, DMIC: 1 */
8785         mic_sel = val ? 0x0 : 0x1;
8786         snd_soc_update_bits(codec, mic_sel_reg, 1 << 7, mic_sel << 7);
8787
8788         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
8789 }
8790
8791 static int tasha_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
8792                                  struct snd_ctl_elem_value *ucontrol)
8793 {
8794         struct snd_soc_dapm_widget_list *wlist =
8795                                         dapm_kcontrol_get_wlist(kcontrol);
8796         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
8797         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
8798         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
8799         unsigned int val;
8800         unsigned short look_ahead_dly_reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
8801
8802         val = ucontrol->value.enumerated.item[0];
8803         if (val >= e->items)
8804                 return -EINVAL;
8805
8806         dev_dbg(codec->dev, "%s: wname: %s, val: 0x%x\n", __func__,
8807                 widget->name, val);
8808
8809         if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
8810                 look_ahead_dly_reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
8811         else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
8812                 look_ahead_dly_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
8813         else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
8814                 look_ahead_dly_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
8815
8816         /* Set Look Ahead Delay */
8817         snd_soc_update_bits(codec, look_ahead_dly_reg,
8818                             0x08, (val ? 0x08 : 0x00));
8819         /* Set DEM INP Select */
8820         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
8821 }
8822
8823 static int tasha_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
8824                                 struct snd_ctl_elem_value *ucontrol)
8825 {
8826         u8 ear_pa_gain;
8827         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8828
8829         ear_pa_gain = snd_soc_read(codec, WCD9335_ANA_EAR);
8830
8831         ear_pa_gain = (ear_pa_gain & 0x70) >> 4;
8832
8833         ucontrol->value.integer.value[0] = ear_pa_gain;
8834
8835         dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
8836                 ear_pa_gain);
8837
8838         return 0;
8839 }
8840
8841 static int tasha_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
8842                                 struct snd_ctl_elem_value *ucontrol)
8843 {
8844         u8 ear_pa_gain;
8845         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8846
8847         dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0]  = %ld\n",
8848                         __func__, ucontrol->value.integer.value[0]);
8849
8850         ear_pa_gain =  ucontrol->value.integer.value[0] << 4;
8851
8852         snd_soc_update_bits(codec, WCD9335_ANA_EAR, 0x70, ear_pa_gain);
8853         return 0;
8854 }
8855
8856 static int tasha_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
8857                                       struct snd_ctl_elem_value *ucontrol)
8858 {
8859         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8860         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8861
8862         ucontrol->value.integer.value[0] = tasha->ear_spkr_gain;
8863
8864         dev_dbg(codec->dev, "%s: ear_spkr_gain = %ld\n", __func__,
8865                 ucontrol->value.integer.value[0]);
8866
8867         return 0;
8868 }
8869
8870 static int tasha_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
8871                                       struct snd_ctl_elem_value *ucontrol)
8872 {
8873         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8874         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8875
8876         dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0]  = %ld\n",
8877                 __func__, ucontrol->value.integer.value[0]);
8878
8879         tasha->ear_spkr_gain =  ucontrol->value.integer.value[0];
8880
8881         return 0;
8882 }
8883
8884 static int tasha_config_compander(struct snd_soc_codec *codec, int interp_n,
8885                                   int event)
8886 {
8887         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8888         int comp;
8889         u16 comp_ctl0_reg, rx_path_cfg0_reg;
8890
8891         /* EAR does not have compander */
8892         if (!interp_n)
8893                 return 0;
8894
8895         comp = interp_n - 1;
8896         dev_dbg(codec->dev, "%s: event %d compander %d, enabled %d\n",
8897                 __func__, event, comp + 1, tasha->comp_enabled[comp]);
8898
8899         if (!tasha->comp_enabled[comp])
8900                 return 0;
8901
8902         comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL0 + (comp * 8);
8903         rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG0 + (comp * 20);
8904
8905         if (SND_SOC_DAPM_EVENT_ON(event)) {
8906                 /* Enable Compander Clock */
8907                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x01, 0x01);
8908                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x02);
8909                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x00);
8910                 snd_soc_update_bits(codec, rx_path_cfg0_reg, 0x02, 0x02);
8911         }
8912
8913         if (SND_SOC_DAPM_EVENT_OFF(event)) {
8914                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x04, 0x04);
8915                 snd_soc_update_bits(codec, rx_path_cfg0_reg, 0x02, 0x00);
8916                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x02);
8917                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x00);
8918                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x01, 0x00);
8919                 snd_soc_update_bits(codec, comp_ctl0_reg, 0x04, 0x00);
8920         }
8921
8922         return 0;
8923 }
8924
8925 static int tasha_codec_config_mad(struct snd_soc_codec *codec)
8926 {
8927         int ret = 0;
8928         int idx;
8929         const struct firmware *fw;
8930         struct firmware_cal *hwdep_cal = NULL;
8931         struct wcd_mad_audio_cal *mad_cal = NULL;
8932         const void *data;
8933         const char *filename = TASHA_MAD_AUDIO_FIRMWARE_PATH;
8934         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
8935         size_t cal_size;
8936
8937         hwdep_cal = wcdcal_get_fw_cal(tasha->fw_data, WCD9XXX_MAD_CAL);
8938         if (hwdep_cal) {
8939                 data = hwdep_cal->data;
8940                 cal_size = hwdep_cal->size;
8941                 dev_dbg(codec->dev, "%s: using hwdep calibration\n",
8942                         __func__);
8943         } else {
8944                 ret = request_firmware(&fw, filename, codec->dev);
8945                 if (ret || !fw) {
8946                         dev_err(codec->dev,
8947                                 "%s: MAD firmware acquire failed, err = %d\n",
8948                                 __func__, ret);
8949                         return -ENODEV;
8950                 }
8951                 data = fw->data;
8952                 cal_size = fw->size;
8953                 dev_dbg(codec->dev, "%s: using request_firmware calibration\n",
8954                         __func__);
8955         }
8956
8957         if (cal_size < sizeof(*mad_cal)) {
8958                 dev_err(codec->dev,
8959                         "%s: Incorrect size %zd for MAD Cal, expected %zd\n",
8960                         __func__, cal_size, sizeof(*mad_cal));
8961                 ret = -ENOMEM;
8962                 goto done;
8963         }
8964
8965         mad_cal = (struct wcd_mad_audio_cal *) (data);
8966         if (!mad_cal) {
8967                 dev_err(codec->dev,
8968                         "%s: Invalid calibration data\n",
8969                         __func__);
8970                 ret = -EINVAL;
8971                 goto done;
8972         }
8973
8974         snd_soc_write(codec, WCD9335_SOC_MAD_MAIN_CTL_2,
8975                       mad_cal->microphone_info.cycle_time);
8976         snd_soc_update_bits(codec, WCD9335_SOC_MAD_MAIN_CTL_1, 0xFF << 3,
8977                             ((uint16_t)mad_cal->microphone_info.settle_time)
8978                             << 3);
8979
8980         /* Audio */
8981         snd_soc_write(codec, WCD9335_SOC_MAD_AUDIO_CTL_8,
8982                       mad_cal->audio_info.rms_omit_samples);
8983         snd_soc_update_bits(codec, WCD9335_SOC_MAD_AUDIO_CTL_1,
8984                             0x07 << 4, mad_cal->audio_info.rms_comp_time << 4);
8985         snd_soc_update_bits(codec, WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03 << 2,
8986                             mad_cal->audio_info.detection_mechanism << 2);
8987         snd_soc_write(codec, WCD9335_SOC_MAD_AUDIO_CTL_7,
8988                       mad_cal->audio_info.rms_diff_threshold & 0x3F);
8989         snd_soc_write(codec, WCD9335_SOC_MAD_AUDIO_CTL_5,
8990                       mad_cal->audio_info.rms_threshold_lsb);
8991         snd_soc_write(codec, WCD9335_SOC_MAD_AUDIO_CTL_6,
8992                       mad_cal->audio_info.rms_threshold_msb);
8993
8994         for (idx = 0; idx < ARRAY_SIZE(mad_cal->audio_info.iir_coefficients);
8995              idx++) {
8996                 snd_soc_update_bits(codec, WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR,
8997                                     0x3F, idx);
8998                 snd_soc_write(codec, WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL,
8999                               mad_cal->audio_info.iir_coefficients[idx]);
9000                 dev_dbg(codec->dev, "%s:MAD Audio IIR Coef[%d] = 0X%x",
9001                         __func__, idx,
9002                         mad_cal->audio_info.iir_coefficients[idx]);
9003         }
9004
9005         /* Beacon */
9006         snd_soc_write(codec, WCD9335_SOC_MAD_BEACON_CTL_8,
9007                       mad_cal->beacon_info.rms_omit_samples);
9008         snd_soc_update_bits(codec, WCD9335_SOC_MAD_BEACON_CTL_1,
9009                             0x07 << 4, mad_cal->beacon_info.rms_comp_time << 4);
9010         snd_soc_update_bits(codec, WCD9335_SOC_MAD_BEACON_CTL_2, 0x03 << 2,
9011                             mad_cal->beacon_info.detection_mechanism << 2);
9012         snd_soc_write(codec, WCD9335_SOC_MAD_BEACON_CTL_7,
9013                       mad_cal->beacon_info.rms_diff_threshold & 0x1F);
9014         snd_soc_write(codec, WCD9335_SOC_MAD_BEACON_CTL_5,
9015                       mad_cal->beacon_info.rms_threshold_lsb);
9016         snd_soc_write(codec, WCD9335_SOC_MAD_BEACON_CTL_6,
9017                       mad_cal->beacon_info.rms_threshold_msb);
9018
9019         for (idx = 0; idx < ARRAY_SIZE(mad_cal->beacon_info.iir_coefficients);
9020              idx++) {
9021                 snd_soc_update_bits(codec, WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR,
9022                                     0x3F, idx);
9023                 snd_soc_write(codec, WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL,
9024                               mad_cal->beacon_info.iir_coefficients[idx]);
9025                 dev_dbg(codec->dev, "%s:MAD Beacon IIR Coef[%d] = 0X%x",
9026                         __func__, idx,
9027                         mad_cal->beacon_info.iir_coefficients[idx]);
9028         }
9029
9030         /* Ultrasound */
9031         snd_soc_update_bits(codec, WCD9335_SOC_MAD_ULTR_CTL_1,
9032                             0x07 << 4,
9033                             mad_cal->ultrasound_info.rms_comp_time << 4);
9034         snd_soc_update_bits(codec, WCD9335_SOC_MAD_ULTR_CTL_2, 0x03 << 2,
9035                             mad_cal->ultrasound_info.detection_mechanism << 2);
9036         snd_soc_write(codec, WCD9335_SOC_MAD_ULTR_CTL_7,
9037                       mad_cal->ultrasound_info.rms_diff_threshold & 0x1F);
9038         snd_soc_write(codec, WCD9335_SOC_MAD_ULTR_CTL_5,
9039                       mad_cal->ultrasound_info.rms_threshold_lsb);
9040         snd_soc_write(codec, WCD9335_SOC_MAD_ULTR_CTL_6,
9041                       mad_cal->ultrasound_info.rms_threshold_msb);
9042
9043 done:
9044         if (!hwdep_cal)
9045                 release_firmware(fw);
9046
9047         return ret;
9048 }
9049
9050 static int tasha_codec_enable_mad(struct snd_soc_dapm_widget *w,
9051         struct snd_kcontrol *kcontrol, int event)
9052 {
9053         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
9054         int ret = 0;
9055
9056         dev_dbg(codec->dev,
9057                 "%s: event = %d\n", __func__, event);
9058
9059         /* Return if CPE INPUT is DEC1 */
9060         if (snd_soc_read(codec, WCD9335_CPE_SS_SVA_CFG) & 0x01)
9061                 return ret;
9062
9063         switch (event) {
9064         case SND_SOC_DAPM_PRE_PMU:
9065
9066                 /* Turn on MAD clk */
9067                 snd_soc_update_bits(codec, WCD9335_CPE_SS_MAD_CTL,
9068                                     0x01, 0x01);
9069
9070                 /* Undo reset for MAD */
9071                 snd_soc_update_bits(codec, WCD9335_CPE_SS_MAD_CTL,
9072                                     0x02, 0x00);
9073                 ret = tasha_codec_config_mad(codec);
9074                 if (ret)
9075                         dev_err(codec->dev,
9076                                 "%s: Failed to config MAD, err = %d\n",
9077                                 __func__, ret);
9078                 break;
9079         case SND_SOC_DAPM_POST_PMD:
9080                 /* Reset the MAD block */
9081                 snd_soc_update_bits(codec, WCD9335_CPE_SS_MAD_CTL,
9082                                     0x02, 0x02);
9083                 /* Turn off MAD clk */
9084                 snd_soc_update_bits(codec, WCD9335_CPE_SS_MAD_CTL,
9085                                     0x01, 0x00);
9086                 break;
9087         }
9088
9089         return ret;
9090 }
9091
9092 static int tasha_codec_configure_cpe_input(struct snd_soc_dapm_widget *w,
9093         struct snd_kcontrol *kcontrol, int event)
9094 {
9095         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
9096
9097         dev_dbg(codec->dev,
9098                 "%s: event = %d\n", __func__, event);
9099
9100         switch (event) {
9101         case SND_SOC_DAPM_PRE_PMU:
9102                 /* Configure CPE input as DEC1 */
9103                 snd_soc_update_bits(codec, WCD9335_CPE_SS_SVA_CFG,
9104                                     0x01, 0x01);
9105
9106                 /* Configure DEC1 Tx out with sample rate as 16K */
9107                 snd_soc_update_bits(codec, WCD9335_CDC_TX1_TX_PATH_CTL,
9108                                     0x0F, 0x01);
9109
9110                 break;
9111         case SND_SOC_DAPM_POST_PMD:
9112                 /* Reset DEC1 Tx out sample rate */
9113                 snd_soc_update_bits(codec, WCD9335_CDC_TX1_TX_PATH_CTL,
9114                                     0x0F, 0x04);
9115                 snd_soc_update_bits(codec, WCD9335_CPE_SS_SVA_CFG,
9116                                     0x01, 0x00);
9117
9118                 break;
9119         }
9120
9121         return 0;
9122 }
9123
9124
9125 static int tasha_codec_aif4_mixer_switch_get(struct snd_kcontrol *kcontrol,
9126                 struct snd_ctl_elem_value *ucontrol)
9127 {
9128         struct snd_soc_dapm_widget_list *wlist =
9129                         dapm_kcontrol_get_wlist(kcontrol);
9130         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
9131         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
9132         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
9133
9134         if (test_bit(AIF4_SWITCH_VALUE, &tasha_p->status_mask))
9135                 ucontrol->value.integer.value[0] = 1;
9136         else
9137                 ucontrol->value.integer.value[0] = 0;
9138
9139         dev_dbg(codec->dev, "%s: AIF4 switch value = %ld\n",
9140                 __func__, ucontrol->value.integer.value[0]);
9141         return 0;
9142 }
9143
9144 static int tasha_codec_aif4_mixer_switch_put(struct snd_kcontrol *kcontrol,
9145                 struct snd_ctl_elem_value *ucontrol)
9146 {
9147         struct snd_soc_dapm_widget_list *wlist =
9148                         dapm_kcontrol_get_wlist(kcontrol);
9149         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
9150         struct snd_soc_dapm_update *update = NULL;
9151         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm);
9152         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(codec);
9153
9154         dev_dbg(codec->dev, "%s: AIF4 switch value = %ld\n",
9155                 __func__, ucontrol->value.integer.value[0]);
9156
9157         if (ucontrol->value.integer.value[0]) {
9158                 snd_soc_dapm_mixer_update_power(widget->dapm,
9159                                                 kcontrol, 1, update);
9160                 set_bit(AIF4_SWITCH_VALUE, &tasha_p->status_mask);
9161         } else {
9162                 snd_soc_dapm_mixer_update_power(widget->dapm,
9163                                                 kcontrol, 0, update);
9164                 clear_bit(AIF4_SWITCH_VALUE, &tasha_p->status_mask);
9165         }
9166
9167         return 1;
9168 }
9169
9170 static const char * const tasha_ear_pa_gain_text[] = {
9171         "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB",
9172         "G_0_DB", "G_M2P5_DB", "UNDEFINED", "G_M12_DB"
9173 };
9174
9175 static const char * const tasha_ear_spkr_pa_gain_text[] = {
9176         "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", "G_4_DB",
9177         "G_5_DB", "G_6_DB"
9178 };
9179
9180 static const struct soc_enum tasha_ear_pa_gain_enum =
9181         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tasha_ear_pa_gain_text),
9182                         tasha_ear_pa_gain_text);
9183
9184 static const struct soc_enum tasha_ear_spkr_pa_gain_enum =
9185         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tasha_ear_spkr_pa_gain_text),
9186                             tasha_ear_spkr_pa_gain_text);
9187
9188 static const struct snd_kcontrol_new tasha_analog_gain_controls[] = {
9189         SOC_ENUM_EXT("EAR PA Gain", tasha_ear_pa_gain_enum,
9190                 tasha_ear_pa_gain_get, tasha_ear_pa_gain_put),
9191
9192         SOC_ENUM_EXT("EAR SPKR PA Gain", tasha_ear_spkr_pa_gain_enum,
9193                      tasha_ear_spkr_pa_gain_get, tasha_ear_spkr_pa_gain_put),
9194
9195         SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
9196                 line_gain),
9197         SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
9198                 line_gain),
9199         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
9200                         3, 16, 1, line_gain),
9201         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
9202                         3, 16, 1, line_gain),
9203         SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
9204                         line_gain),
9205         SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
9206                         line_gain),
9207
9208         SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
9209                         analog_gain),
9210         SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
9211                         analog_gain),
9212         SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
9213                         analog_gain),
9214         SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
9215                         analog_gain),
9216         SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
9217                         analog_gain),
9218         SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
9219                         analog_gain),
9220 };
9221
9222 static const char * const spl_src0_mux_text[] = {
9223         "ZERO", "SRC_IN_HPHL", "SRC_IN_LO1",
9224 };
9225
9226 static const char * const spl_src1_mux_text[] = {
9227         "ZERO", "SRC_IN_HPHR", "SRC_IN_LO2",
9228 };
9229
9230 static const char * const spl_src2_mux_text[] = {
9231         "ZERO", "SRC_IN_LO3", "SRC_IN_SPKRL",
9232 };
9233
9234 static const char * const spl_src3_mux_text[] = {
9235         "ZERO", "SRC_IN_LO4", "SRC_IN_SPKRR",
9236 };
9237
9238 static const char * const rx_int0_7_mix_mux_text[] = {
9239         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
9240         "RX6", "RX7", "PROXIMITY"
9241 };
9242
9243 static const char * const rx_int_mix_mux_text[] = {
9244         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
9245         "RX6", "RX7"
9246 };
9247
9248 static const char * const rx_prim_mix_text[] = {
9249         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
9250         "RX3", "RX4", "RX5", "RX6", "RX7"
9251 };
9252
9253 static const char * const rx_sidetone_mix_text[] = {
9254         "ZERO", "SRC0", "SRC1", "SRC_SUM"
9255 };
9256
9257 static const char * const sb_tx0_mux_text[] = {
9258         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
9259 };
9260
9261 static const char * const sb_tx1_mux_text[] = {
9262         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
9263 };
9264
9265 static const char * const sb_tx2_mux_text[] = {
9266         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
9267 };
9268
9269 static const char * const sb_tx3_mux_text[] = {
9270         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
9271 };
9272
9273 static const char * const sb_tx4_mux_text[] = {
9274         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
9275 };
9276
9277 static const char * const sb_tx5_mux_text[] = {
9278         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
9279 };
9280
9281 static const char * const sb_tx6_mux_text[] = {
9282         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
9283 };
9284
9285 static const char * const sb_tx7_mux_text[] = {
9286         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
9287 };
9288
9289 static const char * const sb_tx8_mux_text[] = {
9290         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
9291 };
9292
9293 static const char * const sb_tx9_mux_text[] = {
9294         "ZERO", "DEC7", "DEC7_192"
9295 };
9296
9297 static const char * const sb_tx10_mux_text[] = {
9298         "ZERO", "DEC6", "DEC6_192"
9299 };
9300
9301 static const char * const sb_tx11_mux_text[] = {
9302         "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
9303 };
9304
9305 static const char * const sb_tx11_inp1_mux_text[] = {
9306         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
9307         "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
9308 };
9309
9310 static const char * const sb_tx13_mux_text[] = {
9311         "ZERO", "DEC5", "DEC5_192"
9312 };
9313
9314 static const char * const tx13_inp_mux_text[] = {
9315         "CDC_DEC_5", "MAD_BRDCST", "CPE_TX_PP"
9316 };
9317
9318 static const char * const iir_inp_mux_text[] = {
9319         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
9320         "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
9321 };
9322
9323 static const char * const rx_int_dem_inp_mux_text[] = {
9324         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
9325 };
9326
9327 static const char * const rx_int0_interp_mux_text[] = {
9328         "ZERO", "RX INT0 MIX2",
9329 };
9330
9331 static const char * const rx_int1_interp_mux_text[] = {
9332         "ZERO", "RX INT1 MIX2",
9333 };
9334
9335 static const char * const rx_int2_interp_mux_text[] = {
9336         "ZERO", "RX INT2 MIX2",
9337 };
9338
9339 static const char * const rx_int3_interp_mux_text[] = {
9340         "ZERO", "RX INT3 MIX2",
9341 };
9342
9343 static const char * const rx_int4_interp_mux_text[] = {
9344         "ZERO", "RX INT4 MIX2",
9345 };
9346
9347 static const char * const rx_int5_interp_mux_text[] = {
9348         "ZERO", "RX INT5 MIX2",
9349 };
9350
9351 static const char * const rx_int6_interp_mux_text[] = {
9352         "ZERO", "RX INT6 MIX2",
9353 };
9354
9355 static const char * const rx_int7_interp_mux_text[] = {
9356         "ZERO", "RX INT7 MIX2",
9357 };
9358
9359 static const char * const rx_int8_interp_mux_text[] = {
9360         "ZERO", "RX INT8 SEC MIX"
9361 };
9362
9363 static const char * const mad_sel_text[] = {
9364         "SPE", "MSM"
9365 };
9366
9367 static const char * const adc_mux_text[] = {
9368         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
9369 };
9370
9371 static const char * const dmic_mux_text[] = {
9372         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
9373         "SMIC0", "SMIC1", "SMIC2", "SMIC3"
9374 };
9375
9376 static const char * const dmic_mux_alt_text[] = {
9377         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
9378 };
9379
9380 static const char * const amic_mux_text[] = {
9381         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
9382 };
9383
9384 static const char * const rx_echo_mux_text[] = {
9385         "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2", "RX_MIX3", "RX_MIX4",
9386         "RX_MIX5", "RX_MIX6", "RX_MIX7", "RX_MIX8", "RX_MIX_VBAT5",
9387         "RX_MIX_VBAT6", "RX_MIX_VBAT7", "RX_MIX_VBAT8"
9388 };
9389
9390 static const char * const anc0_fb_mux_text[] = {
9391         "ZERO", "ANC_IN_HPHL", "ANC_IN_EAR", "ANC_IN_EAR_SPKR",
9392         "ANC_IN_LO1"
9393 };
9394
9395 static const char * const anc1_fb_mux_text[] = {
9396         "ZERO", "ANC_IN_HPHR", "ANC_IN_LO2"
9397 };
9398
9399 static const char * const native_mux_text[] = {
9400         "OFF", "ON",
9401 };
9402
9403 static const struct soc_enum spl_src0_mux_chain_enum =
9404         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 0, 3,
9405                         spl_src0_mux_text);
9406
9407 static const struct soc_enum spl_src1_mux_chain_enum =
9408         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 2, 3,
9409                         spl_src1_mux_text);
9410
9411 static const struct soc_enum spl_src2_mux_chain_enum =
9412         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 4, 3,
9413                         spl_src2_mux_text);
9414
9415 static const struct soc_enum spl_src3_mux_chain_enum =
9416         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 6, 3,
9417                         spl_src3_mux_text);
9418
9419 static const struct soc_enum rx_int0_2_mux_chain_enum =
9420         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
9421                         rx_int0_7_mix_mux_text);
9422
9423 static const struct soc_enum rx_int1_2_mux_chain_enum =
9424         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
9425                         rx_int_mix_mux_text);
9426
9427 static const struct soc_enum rx_int2_2_mux_chain_enum =
9428         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
9429                         rx_int_mix_mux_text);
9430
9431 static const struct soc_enum rx_int3_2_mux_chain_enum =
9432         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
9433                         rx_int_mix_mux_text);
9434
9435 static const struct soc_enum rx_int4_2_mux_chain_enum =
9436         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
9437                         rx_int_mix_mux_text);
9438
9439 static const struct soc_enum rx_int5_2_mux_chain_enum =
9440         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
9441                         rx_int_mix_mux_text);
9442
9443 static const struct soc_enum rx_int6_2_mux_chain_enum =
9444         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
9445                         rx_int_mix_mux_text);
9446
9447 static const struct soc_enum rx_int7_2_mux_chain_enum =
9448         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
9449                         rx_int0_7_mix_mux_text);
9450
9451 static const struct soc_enum rx_int8_2_mux_chain_enum =
9452         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
9453                         rx_int_mix_mux_text);
9454
9455 static const struct soc_enum int1_1_native_enum =
9456         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(native_mux_text),
9457                         native_mux_text);
9458
9459 static const struct soc_enum int2_1_native_enum =
9460         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(native_mux_text),
9461                         native_mux_text);
9462
9463 static const struct soc_enum int3_1_native_enum =
9464         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(native_mux_text),
9465                         native_mux_text);
9466
9467 static const struct soc_enum int4_1_native_enum =
9468         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(native_mux_text),
9469                         native_mux_text);
9470
9471 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
9472         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
9473                         rx_prim_mix_text);
9474
9475 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
9476         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
9477                         rx_prim_mix_text);
9478
9479 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
9480         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
9481                         rx_prim_mix_text);
9482
9483 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
9484         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
9485                         rx_prim_mix_text);
9486
9487 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
9488         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
9489                         rx_prim_mix_text);
9490
9491 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
9492         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
9493                         rx_prim_mix_text);
9494
9495 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
9496         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
9497                         rx_prim_mix_text);
9498
9499 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
9500         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
9501                         rx_prim_mix_text);
9502
9503 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
9504         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
9505                         rx_prim_mix_text);
9506
9507 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
9508         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
9509                         rx_prim_mix_text);
9510
9511 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
9512         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
9513                         rx_prim_mix_text);
9514
9515 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
9516         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
9517                         rx_prim_mix_text);
9518
9519 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
9520         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
9521                         rx_prim_mix_text);
9522
9523 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
9524         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
9525                         rx_prim_mix_text);
9526
9527 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
9528         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
9529                         rx_prim_mix_text);
9530
9531 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
9532         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
9533                         rx_prim_mix_text);
9534
9535 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
9536         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
9537                         rx_prim_mix_text);
9538
9539 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
9540         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
9541                         rx_prim_mix_text);
9542
9543 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
9544         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
9545                         rx_prim_mix_text);
9546
9547 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
9548         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
9549                         rx_prim_mix_text);
9550
9551 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
9552         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
9553                         rx_prim_mix_text);
9554
9555 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
9556         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
9557                         rx_prim_mix_text);
9558
9559 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
9560         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
9561                         rx_prim_mix_text);
9562
9563 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
9564         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
9565                         rx_prim_mix_text);
9566
9567 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
9568         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
9569                         rx_prim_mix_text);
9570
9571 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
9572         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
9573                         rx_prim_mix_text);
9574
9575 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
9576         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
9577                         rx_prim_mix_text);
9578
9579 static const struct soc_enum rx_int0_sidetone_mix_chain_enum =
9580         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
9581                         rx_sidetone_mix_text);
9582
9583 static const struct soc_enum rx_int1_sidetone_mix_chain_enum =
9584         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
9585                         rx_sidetone_mix_text);
9586
9587 static const struct soc_enum rx_int2_sidetone_mix_chain_enum =
9588         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
9589                         rx_sidetone_mix_text);
9590
9591 static const struct soc_enum rx_int3_sidetone_mix_chain_enum =
9592         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
9593                         rx_sidetone_mix_text);
9594
9595 static const struct soc_enum rx_int4_sidetone_mix_chain_enum =
9596         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
9597                         rx_sidetone_mix_text);
9598
9599 static const struct soc_enum rx_int7_sidetone_mix_chain_enum =
9600         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
9601                         rx_sidetone_mix_text);
9602
9603 static const struct soc_enum tx_adc_mux0_chain_enum =
9604         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
9605                         adc_mux_text);
9606
9607 static const struct soc_enum tx_adc_mux1_chain_enum =
9608         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
9609                         adc_mux_text);
9610
9611 static const struct soc_enum tx_adc_mux2_chain_enum =
9612         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
9613                         adc_mux_text);
9614
9615 static const struct soc_enum tx_adc_mux3_chain_enum =
9616         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
9617                         adc_mux_text);
9618
9619 static const struct soc_enum tx_adc_mux4_chain_enum =
9620         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
9621                         adc_mux_text);
9622
9623 static const struct soc_enum tx_adc_mux5_chain_enum =
9624         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
9625                         adc_mux_text);
9626
9627 static const struct soc_enum tx_adc_mux6_chain_enum =
9628         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
9629                         adc_mux_text);
9630
9631 static const struct soc_enum tx_adc_mux7_chain_enum =
9632         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
9633                         adc_mux_text);
9634
9635 static const struct soc_enum tx_adc_mux8_chain_enum =
9636         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
9637                         adc_mux_text);
9638
9639 static const struct soc_enum tx_adc_mux10_chain_enum =
9640         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 6, 4,
9641                         adc_mux_text);
9642
9643 static const struct soc_enum tx_adc_mux11_chain_enum =
9644         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 6, 4,
9645                         adc_mux_text);
9646
9647 static const struct soc_enum tx_adc_mux12_chain_enum =
9648         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 6, 4,
9649                         adc_mux_text);
9650
9651 static const struct soc_enum tx_adc_mux13_chain_enum =
9652         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 6, 4,
9653                         adc_mux_text);
9654
9655 static const struct soc_enum tx_dmic_mux0_enum =
9656         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
9657                         dmic_mux_text);
9658
9659 static const struct soc_enum tx_dmic_mux1_enum =
9660         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
9661                         dmic_mux_text);
9662
9663 static const struct soc_enum tx_dmic_mux2_enum =
9664         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
9665                         dmic_mux_text);
9666
9667 static const struct soc_enum tx_dmic_mux3_enum =
9668         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
9669                         dmic_mux_text);
9670
9671 static const struct soc_enum tx_dmic_mux4_enum =
9672         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
9673                         dmic_mux_alt_text);
9674
9675 static const struct soc_enum tx_dmic_mux5_enum =
9676         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
9677                         dmic_mux_alt_text);
9678
9679 static const struct soc_enum tx_dmic_mux6_enum =
9680         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
9681                         dmic_mux_alt_text);
9682
9683 static const struct soc_enum tx_dmic_mux7_enum =
9684         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
9685                         dmic_mux_alt_text);
9686
9687 static const struct soc_enum tx_dmic_mux8_enum =
9688         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
9689                         dmic_mux_alt_text);
9690
9691 static const struct soc_enum tx_dmic_mux10_enum =
9692         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 3, 7,
9693                         dmic_mux_alt_text);
9694
9695 static const struct soc_enum tx_dmic_mux11_enum =
9696         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 3, 7,
9697                         dmic_mux_alt_text);
9698
9699 static const struct soc_enum tx_dmic_mux12_enum =
9700         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 3, 7,
9701                         dmic_mux_alt_text);
9702
9703 static const struct soc_enum tx_dmic_mux13_enum =
9704         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 3, 7,
9705                         dmic_mux_alt_text);
9706
9707 static const struct soc_enum tx_amic_mux0_enum =
9708         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
9709                         amic_mux_text);
9710
9711 static const struct soc_enum tx_amic_mux1_enum =
9712         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
9713                         amic_mux_text);
9714
9715 static const struct soc_enum tx_amic_mux2_enum =
9716         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
9717                         amic_mux_text);
9718
9719 static const struct soc_enum tx_amic_mux3_enum =
9720         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
9721                         amic_mux_text);
9722
9723 static const struct soc_enum tx_amic_mux4_enum =
9724         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
9725                         amic_mux_text);
9726
9727 static const struct soc_enum tx_amic_mux5_enum =
9728         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
9729                         amic_mux_text);
9730
9731 static const struct soc_enum tx_amic_mux6_enum =
9732         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
9733                         amic_mux_text);
9734
9735 static const struct soc_enum tx_amic_mux7_enum =
9736         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
9737                         amic_mux_text);
9738
9739 static const struct soc_enum tx_amic_mux8_enum =
9740         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
9741                         amic_mux_text);
9742
9743 static const struct soc_enum tx_amic_mux10_enum =
9744         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 0, 7,
9745                         amic_mux_text);
9746
9747 static const struct soc_enum tx_amic_mux11_enum =
9748         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 0, 7,
9749                         amic_mux_text);
9750
9751 static const struct soc_enum tx_amic_mux12_enum =
9752         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 0, 7,
9753                         amic_mux_text);
9754
9755 static const struct soc_enum tx_amic_mux13_enum =
9756         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 0, 7,
9757                         amic_mux_text);
9758
9759 static const struct soc_enum sb_tx0_mux_enum =
9760         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
9761                         sb_tx0_mux_text);
9762
9763 static const struct soc_enum sb_tx1_mux_enum =
9764         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
9765                         sb_tx1_mux_text);
9766
9767 static const struct soc_enum sb_tx2_mux_enum =
9768         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
9769                         sb_tx2_mux_text);
9770
9771 static const struct soc_enum sb_tx3_mux_enum =
9772         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
9773                         sb_tx3_mux_text);
9774
9775 static const struct soc_enum sb_tx4_mux_enum =
9776         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
9777                         sb_tx4_mux_text);
9778
9779 static const struct soc_enum sb_tx5_mux_enum =
9780         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
9781                         sb_tx5_mux_text);
9782
9783 static const struct soc_enum sb_tx6_mux_enum =
9784         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
9785                         sb_tx6_mux_text);
9786
9787 static const struct soc_enum sb_tx7_mux_enum =
9788         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
9789                         sb_tx7_mux_text);
9790
9791 static const struct soc_enum sb_tx8_mux_enum =
9792         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
9793                         sb_tx8_mux_text);
9794
9795 static const struct soc_enum sb_tx9_mux_enum =
9796         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 3,
9797                         sb_tx9_mux_text);
9798
9799 static const struct soc_enum sb_tx10_mux_enum =
9800         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 3,
9801                         sb_tx10_mux_text);
9802
9803 static const struct soc_enum sb_tx11_mux_enum =
9804         SOC_ENUM_SINGLE(WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG, 0, 4,
9805                         sb_tx11_mux_text);
9806
9807 static const struct soc_enum sb_tx11_inp1_mux_enum =
9808         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 10,
9809                         sb_tx11_inp1_mux_text);
9810
9811 static const struct soc_enum sb_tx13_mux_enum =
9812         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 3,
9813                         sb_tx13_mux_text);
9814
9815 static const struct soc_enum tx13_inp_mux_enum =
9816         SOC_ENUM_SINGLE(WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG, 0, 3,
9817                         tx13_inp_mux_text);
9818
9819 static const struct soc_enum rx_mix_tx0_mux_enum =
9820         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0, 0, 14,
9821                         rx_echo_mux_text);
9822
9823 static const struct soc_enum rx_mix_tx1_mux_enum =
9824         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0, 4, 14,
9825                         rx_echo_mux_text);
9826
9827 static const struct soc_enum rx_mix_tx2_mux_enum =
9828         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1, 0, 14,
9829                         rx_echo_mux_text);
9830
9831 static const struct soc_enum rx_mix_tx3_mux_enum =
9832         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1, 4, 14,
9833                         rx_echo_mux_text);
9834
9835 static const struct soc_enum rx_mix_tx4_mux_enum =
9836         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2, 0, 14,
9837                         rx_echo_mux_text);
9838
9839 static const struct soc_enum rx_mix_tx5_mux_enum =
9840         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2, 4, 14,
9841                         rx_echo_mux_text);
9842
9843 static const struct soc_enum rx_mix_tx6_mux_enum =
9844         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3, 0, 14,
9845                         rx_echo_mux_text);
9846
9847 static const struct soc_enum rx_mix_tx7_mux_enum =
9848         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3, 4, 14,
9849                         rx_echo_mux_text);
9850
9851 static const struct soc_enum rx_mix_tx8_mux_enum =
9852         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 14,
9853                         rx_echo_mux_text);
9854
9855 static const struct soc_enum iir0_inp0_mux_enum =
9856         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 0, 18,
9857                         iir_inp_mux_text);
9858
9859 static const struct soc_enum iir0_inp1_mux_enum =
9860         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 0, 18,
9861                         iir_inp_mux_text);
9862
9863 static const struct soc_enum iir0_inp2_mux_enum =
9864         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 0, 18,
9865                         iir_inp_mux_text);
9866
9867 static const struct soc_enum iir0_inp3_mux_enum =
9868         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 0, 18,
9869                         iir_inp_mux_text);
9870
9871 static const struct soc_enum iir1_inp0_mux_enum =
9872         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 0, 18,
9873                         iir_inp_mux_text);
9874
9875 static const struct soc_enum iir1_inp1_mux_enum =
9876         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 0, 18,
9877                         iir_inp_mux_text);
9878
9879 static const struct soc_enum iir1_inp2_mux_enum =
9880         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 0, 18,
9881                         iir_inp_mux_text);
9882
9883 static const struct soc_enum iir1_inp3_mux_enum =
9884         SOC_ENUM_SINGLE(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 0, 18,
9885                         iir_inp_mux_text);
9886
9887 static const struct soc_enum rx_int0_dem_inp_mux_enum =
9888         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
9889                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
9890                         rx_int_dem_inp_mux_text);
9891
9892 static const struct soc_enum rx_int1_dem_inp_mux_enum =
9893         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
9894                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
9895                         rx_int_dem_inp_mux_text);
9896
9897 static const struct soc_enum rx_int2_dem_inp_mux_enum =
9898         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
9899                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
9900                         rx_int_dem_inp_mux_text);
9901
9902 static const struct soc_enum rx_int0_interp_mux_enum =
9903         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
9904                         rx_int0_interp_mux_text);
9905
9906 static const struct soc_enum rx_int1_interp_mux_enum =
9907         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
9908                         rx_int1_interp_mux_text);
9909
9910 static const struct soc_enum rx_int2_interp_mux_enum =
9911         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
9912                         rx_int2_interp_mux_text);
9913
9914 static const struct soc_enum rx_int3_interp_mux_enum =
9915         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
9916                         rx_int3_interp_mux_text);
9917
9918 static const struct soc_enum rx_int4_interp_mux_enum =
9919         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
9920                         rx_int4_interp_mux_text);
9921
9922 static const struct soc_enum rx_int5_interp_mux_enum =
9923         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
9924                         rx_int5_interp_mux_text);
9925
9926 static const struct soc_enum rx_int6_interp_mux_enum =
9927         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
9928                         rx_int6_interp_mux_text);
9929
9930 static const struct soc_enum rx_int7_interp_mux_enum =
9931         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
9932                         rx_int7_interp_mux_text);
9933
9934 static const struct soc_enum rx_int8_interp_mux_enum =
9935         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
9936                         rx_int8_interp_mux_text);
9937
9938 static const struct soc_enum mad_sel_enum =
9939         SOC_ENUM_SINGLE(WCD9335_CPE_SS_CFG, 0, 2, mad_sel_text);
9940
9941 static const struct soc_enum anc0_fb_mux_enum =
9942         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_ANC_CFG0, 0, 5,
9943                         anc0_fb_mux_text);
9944
9945 static const struct soc_enum anc1_fb_mux_enum =
9946         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_ANC_CFG0, 3, 3,
9947                         anc1_fb_mux_text);
9948
9949 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
9950         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
9951                           snd_soc_dapm_get_enum_double,
9952                           tasha_int_dem_inp_mux_put);
9953
9954 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
9955         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
9956                           snd_soc_dapm_get_enum_double,
9957                           tasha_int_dem_inp_mux_put);
9958
9959 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
9960         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
9961                           snd_soc_dapm_get_enum_double,
9962                           tasha_int_dem_inp_mux_put);
9963
9964 static const struct snd_kcontrol_new spl_src0_mux =
9965         SOC_DAPM_ENUM("SPL SRC0 MUX Mux", spl_src0_mux_chain_enum);
9966
9967 static const struct snd_kcontrol_new spl_src1_mux =
9968         SOC_DAPM_ENUM("SPL SRC1 MUX Mux", spl_src1_mux_chain_enum);
9969
9970 static const struct snd_kcontrol_new spl_src2_mux =
9971         SOC_DAPM_ENUM("SPL SRC2 MUX Mux", spl_src2_mux_chain_enum);
9972
9973 static const struct snd_kcontrol_new spl_src3_mux =
9974         SOC_DAPM_ENUM("SPL SRC3 MUX Mux", spl_src3_mux_chain_enum);
9975
9976 static const struct snd_kcontrol_new rx_int0_2_mux =
9977         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
9978
9979 static const struct snd_kcontrol_new rx_int1_2_mux =
9980         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
9981
9982 static const struct snd_kcontrol_new rx_int2_2_mux =
9983         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
9984
9985 static const struct snd_kcontrol_new rx_int3_2_mux =
9986         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
9987
9988 static const struct snd_kcontrol_new rx_int4_2_mux =
9989         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
9990
9991 static const struct snd_kcontrol_new rx_int5_2_mux =
9992         SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
9993
9994 static const struct snd_kcontrol_new rx_int6_2_mux =
9995         SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
9996
9997 static const struct snd_kcontrol_new rx_int7_2_mux =
9998         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
9999
10000 static const struct snd_kcontrol_new rx_int8_2_mux =
10001         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
10002
10003 static const struct snd_kcontrol_new int1_1_native_mux =
10004         SOC_DAPM_ENUM("RX INT1_1 NATIVE MUX Mux", int1_1_native_enum);
10005
10006 static const struct snd_kcontrol_new int2_1_native_mux =
10007         SOC_DAPM_ENUM("RX INT2_1 NATIVE MUX Mux", int2_1_native_enum);
10008
10009 static const struct snd_kcontrol_new int3_1_native_mux =
10010         SOC_DAPM_ENUM("RX INT3_1 NATIVE MUX Mux", int3_1_native_enum);
10011
10012 static const struct snd_kcontrol_new int4_1_native_mux =
10013         SOC_DAPM_ENUM("RX INT4_1 NATIVE MUX Mux", int4_1_native_enum);
10014
10015 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
10016         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
10017
10018 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
10019         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
10020
10021 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
10022         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
10023
10024 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
10025         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
10026
10027 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
10028         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
10029
10030 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
10031         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
10032
10033 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
10034         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
10035
10036 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
10037         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
10038
10039 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
10040         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
10041
10042 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
10043         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
10044
10045 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
10046         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
10047
10048 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
10049         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
10050
10051 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
10052         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
10053
10054 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
10055         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
10056
10057 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
10058         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
10059
10060 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
10061         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
10062
10063 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
10064         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
10065
10066 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
10067         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
10068
10069 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
10070         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
10071
10072 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
10073         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
10074
10075 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
10076         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
10077
10078 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
10079         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
10080
10081 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
10082         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
10083
10084 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
10085         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
10086
10087 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
10088         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
10089
10090 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
10091         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
10092
10093 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
10094         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
10095
10096 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
10097         SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_sidetone_mix_chain_enum);
10098
10099 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
10100         SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_sidetone_mix_chain_enum);
10101
10102 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
10103         SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_sidetone_mix_chain_enum);
10104
10105 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
10106         SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_sidetone_mix_chain_enum);
10107
10108 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
10109         SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_sidetone_mix_chain_enum);
10110
10111 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
10112         SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_sidetone_mix_chain_enum);
10113
10114 static const struct snd_kcontrol_new tx_adc_mux0 =
10115         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
10116                           snd_soc_dapm_get_enum_double,
10117                           tasha_put_dec_enum);
10118
10119 static const struct snd_kcontrol_new tx_adc_mux1 =
10120         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
10121                           snd_soc_dapm_get_enum_double,
10122                           tasha_put_dec_enum);
10123
10124 static const struct snd_kcontrol_new tx_adc_mux2 =
10125         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
10126                           snd_soc_dapm_get_enum_double,
10127                           tasha_put_dec_enum);
10128
10129 static const struct snd_kcontrol_new tx_adc_mux3 =
10130         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
10131                           snd_soc_dapm_get_enum_double,
10132                           tasha_put_dec_enum);
10133
10134 static const struct snd_kcontrol_new tx_adc_mux4 =
10135         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
10136                           snd_soc_dapm_get_enum_double,
10137                           tasha_put_dec_enum);
10138
10139 static const struct snd_kcontrol_new tx_adc_mux5 =
10140         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
10141                           snd_soc_dapm_get_enum_double,
10142                           tasha_put_dec_enum);
10143
10144 static const struct snd_kcontrol_new tx_adc_mux6 =
10145         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
10146                           snd_soc_dapm_get_enum_double,
10147                           tasha_put_dec_enum);
10148
10149 static const struct snd_kcontrol_new tx_adc_mux7 =
10150         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
10151                           snd_soc_dapm_get_enum_double,
10152                           tasha_put_dec_enum);
10153
10154 static const struct snd_kcontrol_new tx_adc_mux8 =
10155         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
10156                           snd_soc_dapm_get_enum_double,
10157                           tasha_put_dec_enum);
10158
10159 static const struct snd_kcontrol_new tx_adc_mux10 =
10160         SOC_DAPM_ENUM("ADC MUX10 Mux", tx_adc_mux10_chain_enum);
10161
10162 static const struct snd_kcontrol_new tx_adc_mux11 =
10163         SOC_DAPM_ENUM("ADC MUX11 Mux", tx_adc_mux11_chain_enum);
10164
10165 static const struct snd_kcontrol_new tx_adc_mux12 =
10166         SOC_DAPM_ENUM("ADC MUX12 Mux", tx_adc_mux12_chain_enum);
10167
10168 static const struct snd_kcontrol_new tx_adc_mux13 =
10169         SOC_DAPM_ENUM("ADC MUX13 Mux", tx_adc_mux13_chain_enum);
10170
10171 static const struct snd_kcontrol_new tx_dmic_mux0 =
10172         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
10173
10174 static const struct snd_kcontrol_new tx_dmic_mux1 =
10175         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
10176
10177 static const struct snd_kcontrol_new tx_dmic_mux2 =
10178         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
10179
10180 static const struct snd_kcontrol_new tx_dmic_mux3 =
10181         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
10182
10183 static const struct snd_kcontrol_new tx_dmic_mux4 =
10184         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
10185
10186 static const struct snd_kcontrol_new tx_dmic_mux5 =
10187         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
10188
10189 static const struct snd_kcontrol_new tx_dmic_mux6 =
10190         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
10191
10192 static const struct snd_kcontrol_new tx_dmic_mux7 =
10193         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
10194
10195 static const struct snd_kcontrol_new tx_dmic_mux8 =
10196         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
10197
10198 static const struct snd_kcontrol_new tx_dmic_mux10 =
10199         SOC_DAPM_ENUM("DMIC MUX10 Mux", tx_dmic_mux10_enum);
10200
10201 static const struct snd_kcontrol_new tx_dmic_mux11 =
10202         SOC_DAPM_ENUM("DMIC MUX11 Mux", tx_dmic_mux11_enum);
10203
10204 static const struct snd_kcontrol_new tx_dmic_mux12 =
10205         SOC_DAPM_ENUM("DMIC MUX12 Mux", tx_dmic_mux12_enum);
10206
10207 static const struct snd_kcontrol_new tx_dmic_mux13 =
10208         SOC_DAPM_ENUM("DMIC MUX13 Mux", tx_dmic_mux13_enum);
10209
10210 static const struct snd_kcontrol_new tx_amic_mux0 =
10211         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
10212
10213 static const struct snd_kcontrol_new tx_amic_mux1 =
10214         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
10215
10216 static const struct snd_kcontrol_new tx_amic_mux2 =
10217         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
10218
10219 static const struct snd_kcontrol_new tx_amic_mux3 =
10220         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
10221
10222 static const struct snd_kcontrol_new tx_amic_mux4 =
10223         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
10224
10225 static const struct snd_kcontrol_new tx_amic_mux5 =
10226         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
10227
10228 static const struct snd_kcontrol_new tx_amic_mux6 =
10229         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
10230
10231 static const struct snd_kcontrol_new tx_amic_mux7 =
10232         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
10233
10234 static const struct snd_kcontrol_new tx_amic_mux8 =
10235         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
10236
10237 static const struct snd_kcontrol_new tx_amic_mux10 =
10238         SOC_DAPM_ENUM("AMIC MUX10 Mux", tx_amic_mux10_enum);
10239
10240 static const struct snd_kcontrol_new tx_amic_mux11 =
10241         SOC_DAPM_ENUM("AMIC MUX11 Mux", tx_amic_mux11_enum);
10242
10243 static const struct snd_kcontrol_new tx_amic_mux12 =
10244         SOC_DAPM_ENUM("AMIC MUX12 Mux", tx_amic_mux12_enum);
10245
10246 static const struct snd_kcontrol_new tx_amic_mux13 =
10247         SOC_DAPM_ENUM("AMIC MUX13 Mux", tx_amic_mux13_enum);
10248
10249 static const struct snd_kcontrol_new sb_tx0_mux =
10250         SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
10251
10252 static const struct snd_kcontrol_new sb_tx1_mux =
10253         SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
10254
10255 static const struct snd_kcontrol_new sb_tx2_mux =
10256         SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
10257
10258 static const struct snd_kcontrol_new sb_tx3_mux =
10259         SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
10260
10261 static const struct snd_kcontrol_new sb_tx4_mux =
10262         SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
10263
10264 static const struct snd_kcontrol_new sb_tx5_mux =
10265         SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
10266
10267 static const struct snd_kcontrol_new sb_tx6_mux =
10268         SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
10269
10270 static const struct snd_kcontrol_new sb_tx7_mux =
10271         SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
10272
10273 static const struct snd_kcontrol_new sb_tx8_mux =
10274         SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
10275
10276 static const struct snd_kcontrol_new sb_tx9_mux =
10277         SOC_DAPM_ENUM("SLIM TX9 MUX Mux", sb_tx9_mux_enum);
10278
10279 static const struct snd_kcontrol_new sb_tx10_mux =
10280         SOC_DAPM_ENUM("SLIM TX10 MUX Mux", sb_tx10_mux_enum);
10281
10282 static const struct snd_kcontrol_new sb_tx11_mux =
10283         SOC_DAPM_ENUM("SLIM TX11 MUX Mux", sb_tx11_mux_enum);
10284
10285 static const struct snd_kcontrol_new sb_tx11_inp1_mux =
10286         SOC_DAPM_ENUM("SLIM TX11 INP1 MUX Mux", sb_tx11_inp1_mux_enum);
10287
10288 static const struct snd_kcontrol_new sb_tx13_mux =
10289         SOC_DAPM_ENUM("SLIM TX13 MUX Mux", sb_tx13_mux_enum);
10290
10291 static const struct snd_kcontrol_new tx13_inp_mux =
10292         SOC_DAPM_ENUM("TX13 INP MUX Mux", tx13_inp_mux_enum);
10293
10294 static const struct snd_kcontrol_new rx_mix_tx0_mux =
10295         SOC_DAPM_ENUM("RX MIX TX0 MUX Mux", rx_mix_tx0_mux_enum);
10296
10297 static const struct snd_kcontrol_new rx_mix_tx1_mux =
10298         SOC_DAPM_ENUM("RX MIX TX1 MUX Mux", rx_mix_tx1_mux_enum);
10299
10300 static const struct snd_kcontrol_new rx_mix_tx2_mux =
10301         SOC_DAPM_ENUM("RX MIX TX2 MUX Mux", rx_mix_tx2_mux_enum);
10302
10303 static const struct snd_kcontrol_new rx_mix_tx3_mux =
10304         SOC_DAPM_ENUM("RX MIX TX3 MUX Mux", rx_mix_tx3_mux_enum);
10305
10306 static const struct snd_kcontrol_new rx_mix_tx4_mux =
10307         SOC_DAPM_ENUM("RX MIX TX4 MUX Mux", rx_mix_tx4_mux_enum);
10308
10309 static const struct snd_kcontrol_new rx_mix_tx5_mux =
10310         SOC_DAPM_ENUM("RX MIX TX5 MUX Mux", rx_mix_tx5_mux_enum);
10311
10312 static const struct snd_kcontrol_new rx_mix_tx6_mux =
10313         SOC_DAPM_ENUM("RX MIX TX6 MUX Mux", rx_mix_tx6_mux_enum);
10314
10315 static const struct snd_kcontrol_new rx_mix_tx7_mux =
10316         SOC_DAPM_ENUM("RX MIX TX7 MUX Mux", rx_mix_tx7_mux_enum);
10317
10318 static const struct snd_kcontrol_new rx_mix_tx8_mux =
10319         SOC_DAPM_ENUM("RX MIX TX8 MUX Mux", rx_mix_tx8_mux_enum);
10320
10321 static const struct snd_kcontrol_new iir0_inp0_mux =
10322         SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
10323
10324 static const struct snd_kcontrol_new iir0_inp1_mux =
10325         SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
10326
10327 static const struct snd_kcontrol_new iir0_inp2_mux =
10328         SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
10329
10330 static const struct snd_kcontrol_new iir0_inp3_mux =
10331         SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
10332
10333 static const struct snd_kcontrol_new iir1_inp0_mux =
10334         SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
10335
10336 static const struct snd_kcontrol_new iir1_inp1_mux =
10337         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
10338
10339 static const struct snd_kcontrol_new iir1_inp2_mux =
10340         SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
10341
10342 static const struct snd_kcontrol_new iir1_inp3_mux =
10343         SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
10344
10345 static const struct snd_kcontrol_new rx_int0_interp_mux =
10346         SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
10347
10348 static const struct snd_kcontrol_new rx_int1_interp_mux =
10349         SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
10350
10351 static const struct snd_kcontrol_new rx_int2_interp_mux =
10352         SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
10353
10354 static const struct snd_kcontrol_new rx_int3_interp_mux =
10355         SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
10356
10357 static const struct snd_kcontrol_new rx_int4_interp_mux =
10358         SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
10359
10360 static const struct snd_kcontrol_new rx_int5_interp_mux =
10361         SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
10362
10363 static const struct snd_kcontrol_new rx_int6_interp_mux =
10364         SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
10365
10366 static const struct snd_kcontrol_new rx_int7_interp_mux =
10367         SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
10368
10369 static const struct snd_kcontrol_new rx_int8_interp_mux =
10370         SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
10371
10372 static const struct snd_kcontrol_new mad_sel_mux =
10373         SOC_DAPM_ENUM("MAD_SEL MUX Mux", mad_sel_enum);
10374
10375 static const struct snd_kcontrol_new aif4_mad_switch =
10376         SOC_DAPM_SINGLE("Switch", WCD9335_CPE_SS_CFG, 5, 1, 0);
10377
10378 static const struct snd_kcontrol_new mad_brdcst_switch =
10379         SOC_DAPM_SINGLE("Switch", WCD9335_CPE_SS_CFG, 6, 1, 0);
10380
10381 static const struct snd_kcontrol_new aif4_switch_mixer_controls =
10382         SOC_SINGLE_EXT("Switch", SND_SOC_NOPM,
10383                         0, 1, 0, tasha_codec_aif4_mixer_switch_get,
10384                         tasha_codec_aif4_mixer_switch_put);
10385
10386 static const struct snd_kcontrol_new anc_hphl_switch =
10387         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10388
10389 static const struct snd_kcontrol_new anc_hphr_switch =
10390         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10391
10392 static const struct snd_kcontrol_new anc_ear_switch =
10393         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10394
10395 static const struct snd_kcontrol_new anc_ear_spkr_switch =
10396         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10397
10398 static const struct snd_kcontrol_new anc_lineout1_switch =
10399         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10400
10401 static const struct snd_kcontrol_new anc_lineout2_switch =
10402         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10403
10404 static const struct snd_kcontrol_new anc_spkr_pa_switch =
10405         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
10406
10407 static const struct snd_kcontrol_new adc_us_mux0_switch =
10408         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10409
10410 static const struct snd_kcontrol_new adc_us_mux1_switch =
10411         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10412
10413 static const struct snd_kcontrol_new adc_us_mux2_switch =
10414         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10415
10416 static const struct snd_kcontrol_new adc_us_mux3_switch =
10417         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10418
10419 static const struct snd_kcontrol_new adc_us_mux4_switch =
10420         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10421
10422 static const struct snd_kcontrol_new adc_us_mux5_switch =
10423         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10424
10425 static const struct snd_kcontrol_new adc_us_mux6_switch =
10426         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10427
10428 static const struct snd_kcontrol_new adc_us_mux7_switch =
10429         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10430
10431 static const struct snd_kcontrol_new adc_us_mux8_switch =
10432         SOC_DAPM_SINGLE("US_Switch", SND_SOC_NOPM, 0, 1, 0);
10433
10434 static const struct snd_kcontrol_new anc0_fb_mux =
10435         SOC_DAPM_ENUM("ANC0 FB MUX Mux", anc0_fb_mux_enum);
10436
10437 static const struct snd_kcontrol_new anc1_fb_mux =
10438         SOC_DAPM_ENUM("ANC1 FB MUX Mux", anc1_fb_mux_enum);
10439
10440 static int tasha_codec_ec_buf_mux_enable(struct snd_soc_dapm_widget *w,
10441                                          struct snd_kcontrol *kcontrol,
10442                                          int event)
10443 {
10444         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
10445
10446         dev_dbg(codec->dev, "%s: event = %d name = %s\n",
10447                 __func__, event, w->name);
10448
10449         switch (event) {
10450         case SND_SOC_DAPM_POST_PMU:
10451                 snd_soc_write(codec, WCD9335_CPE_SS_EC_BUF_INT_PERIOD, 0x3B);
10452                 snd_soc_update_bits(codec, WCD9335_CPE_SS_CFG, 0x08, 0x08);
10453                 snd_soc_update_bits(codec, WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0,
10454                                     0x08, 0x08);
10455                 break;
10456         case SND_SOC_DAPM_POST_PMD:
10457                 snd_soc_update_bits(codec, WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0,
10458                                     0x08, 0x00);
10459                 snd_soc_update_bits(codec, WCD9335_CPE_SS_CFG, 0x08, 0x00);
10460                 snd_soc_write(codec, WCD9335_CPE_SS_EC_BUF_INT_PERIOD, 0x00);
10461                 break;
10462         }
10463
10464         return 0;
10465 };
10466
10467 static const char * const ec_buf_mux_text[] = {
10468         "ZERO", "RXMIXEC", "SB_RX0", "SB_RX1", "SB_RX2", "SB_RX3",
10469         "I2S_RX_SD0_L", "I2S_RX_SD0_R", "I2S_RX_SD1_L", "I2S_RX_SD1_R",
10470         "DEC1"
10471 };
10472
10473 static SOC_ENUM_SINGLE_DECL(ec_buf_mux_enum, WCD9335_CPE_SS_US_EC_MUX_CFG,
10474                             0, ec_buf_mux_text);
10475
10476 static const struct snd_kcontrol_new ec_buf_mux =
10477         SOC_DAPM_ENUM("EC BUF Mux", ec_buf_mux_enum);
10478
10479 static const struct snd_soc_dapm_widget tasha_dapm_widgets[] = {
10480         SND_SOC_DAPM_OUTPUT("EAR"),
10481         SND_SOC_DAPM_OUTPUT("ANC EAR"),
10482         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
10483                                 AIF1_PB, 0, tasha_codec_enable_slimrx,
10484                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
10485                                 SND_SOC_DAPM_POST_PMD),
10486         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
10487                                 AIF2_PB, 0, tasha_codec_enable_slimrx,
10488                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
10489                                 SND_SOC_DAPM_POST_PMD),
10490         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
10491                                 AIF3_PB, 0, tasha_codec_enable_slimrx,
10492                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
10493                                 SND_SOC_DAPM_POST_PMD),
10494         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
10495                                 AIF4_PB, 0, tasha_codec_enable_slimrx,
10496                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
10497                                 SND_SOC_DAPM_POST_PMD),
10498         SND_SOC_DAPM_AIF_IN_E("AIF MIX1 PB", "AIF Mix Playback", 0,
10499                                SND_SOC_NOPM, AIF_MIX1_PB, 0,
10500                                tasha_codec_enable_slimrx,
10501                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
10502                                SND_SOC_DAPM_POST_PMD),
10503
10504         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, TASHA_RX0, 0,
10505                                 &slim_rx_mux[TASHA_RX0]),
10506         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, TASHA_RX1, 0,
10507                                 &slim_rx_mux[TASHA_RX1]),
10508         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, TASHA_RX2, 0,
10509                                 &slim_rx_mux[TASHA_RX2]),
10510         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, TASHA_RX3, 0,
10511                                 &slim_rx_mux[TASHA_RX3]),
10512         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, TASHA_RX4, 0,
10513                                 &slim_rx_mux[TASHA_RX4]),
10514         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, TASHA_RX5, 0,
10515                                 &slim_rx_mux[TASHA_RX5]),
10516         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, TASHA_RX6, 0,
10517                                 &slim_rx_mux[TASHA_RX6]),
10518         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, TASHA_RX7, 0,
10519                                 &slim_rx_mux[TASHA_RX7]),
10520
10521         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
10522         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10523         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10524         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
10525         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
10526         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
10527         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
10528         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
10529
10530         SND_SOC_DAPM_MUX_E("SPL SRC0 MUX", SND_SOC_NOPM, SPLINE_SRC0, 0,
10531                          &spl_src0_mux, tasha_codec_enable_spline_resampler,
10532                          SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10533         SND_SOC_DAPM_MUX_E("SPL SRC1 MUX", SND_SOC_NOPM, SPLINE_SRC1, 0,
10534                          &spl_src1_mux, tasha_codec_enable_spline_resampler,
10535                          SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10536         SND_SOC_DAPM_MUX_E("SPL SRC2 MUX", SND_SOC_NOPM, SPLINE_SRC2, 0,
10537                          &spl_src2_mux, tasha_codec_enable_spline_resampler,
10538                          SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10539         SND_SOC_DAPM_MUX_E("SPL SRC3 MUX", SND_SOC_NOPM, SPLINE_SRC3, 0,
10540                          &spl_src3_mux, tasha_codec_enable_spline_resampler,
10541                          SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10542
10543         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
10544                         5, 0, &rx_int0_2_mux, tasha_codec_enable_mix_path,
10545                         SND_SOC_DAPM_POST_PMU),
10546         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
10547                         5, 0, &rx_int1_2_mux, tasha_codec_enable_mix_path,
10548                         SND_SOC_DAPM_POST_PMU),
10549         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
10550                         5, 0, &rx_int2_2_mux, tasha_codec_enable_mix_path,
10551                         SND_SOC_DAPM_POST_PMU),
10552         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
10553                         5, 0, &rx_int3_2_mux, tasha_codec_enable_mix_path,
10554                         SND_SOC_DAPM_POST_PMU),
10555         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
10556                         5, 0, &rx_int4_2_mux, tasha_codec_enable_mix_path,
10557                         SND_SOC_DAPM_POST_PMU),
10558         SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
10559                         5, 0, &rx_int5_2_mux, tasha_codec_enable_mix_path,
10560                         SND_SOC_DAPM_POST_PMU),
10561         SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
10562                         5, 0, &rx_int6_2_mux, tasha_codec_enable_mix_path,
10563                         SND_SOC_DAPM_POST_PMU),
10564         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
10565                         5, 0, &rx_int7_2_mux, tasha_codec_enable_mix_path,
10566                         SND_SOC_DAPM_POST_PMU),
10567         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
10568                         5, 0, &rx_int8_2_mux, tasha_codec_enable_mix_path,
10569                         SND_SOC_DAPM_POST_PMU),
10570
10571         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10572                 &rx_int0_1_mix_inp0_mux),
10573         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10574                 &rx_int0_1_mix_inp1_mux),
10575         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10576                 &rx_int0_1_mix_inp2_mux),
10577         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10578                 &rx_int1_1_mix_inp0_mux),
10579         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10580                 &rx_int1_1_mix_inp1_mux),
10581         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10582                 &rx_int1_1_mix_inp2_mux),
10583         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10584                 &rx_int2_1_mix_inp0_mux),
10585         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10586                 &rx_int2_1_mix_inp1_mux),
10587         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10588                 &rx_int2_1_mix_inp2_mux),
10589         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10590                 &rx_int3_1_mix_inp0_mux),
10591         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10592                 &rx_int3_1_mix_inp1_mux),
10593         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10594                 &rx_int3_1_mix_inp2_mux),
10595         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10596                 &rx_int4_1_mix_inp0_mux),
10597         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10598                 &rx_int4_1_mix_inp1_mux),
10599         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10600                 &rx_int4_1_mix_inp2_mux),
10601         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10602                 &rx_int5_1_mix_inp0_mux),
10603         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10604                 &rx_int5_1_mix_inp1_mux),
10605         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10606                 &rx_int5_1_mix_inp2_mux),
10607         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10608                 &rx_int6_1_mix_inp0_mux),
10609         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10610                 &rx_int6_1_mix_inp1_mux),
10611         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10612                 &rx_int6_1_mix_inp2_mux),
10613         SND_SOC_DAPM_MUX_E("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10614                 &rx_int7_1_mix_inp0_mux, tasha_codec_enable_swr,
10615                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10616         SND_SOC_DAPM_MUX_E("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10617                 &rx_int7_1_mix_inp1_mux, tasha_codec_enable_swr,
10618                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10619         SND_SOC_DAPM_MUX_E("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10620                 &rx_int7_1_mix_inp2_mux, tasha_codec_enable_swr,
10621                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10622         SND_SOC_DAPM_MUX_E("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
10623                 &rx_int8_1_mix_inp0_mux, tasha_codec_enable_swr,
10624                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10625         SND_SOC_DAPM_MUX_E("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
10626                 &rx_int8_1_mix_inp1_mux, tasha_codec_enable_swr,
10627                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10628         SND_SOC_DAPM_MUX_E("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
10629                 &rx_int8_1_mix_inp2_mux, tasha_codec_enable_swr,
10630                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10631
10632         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10633         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10634         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10635         SND_SOC_DAPM_MIXER("RX INT1 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10636                         rx_int1_spline_mix_switch,
10637                         ARRAY_SIZE(rx_int1_spline_mix_switch)),
10638         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10639         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10640         SND_SOC_DAPM_MIXER("RX INT2 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10641                         rx_int2_spline_mix_switch,
10642                         ARRAY_SIZE(rx_int2_spline_mix_switch)),
10643         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10644         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10645         SND_SOC_DAPM_MIXER("RX INT3 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10646                         rx_int3_spline_mix_switch,
10647                         ARRAY_SIZE(rx_int3_spline_mix_switch)),
10648         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10649         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10650         SND_SOC_DAPM_MIXER("RX INT4 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10651                         rx_int4_spline_mix_switch,
10652                         ARRAY_SIZE(rx_int4_spline_mix_switch)),
10653         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10654         SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10655         SND_SOC_DAPM_MIXER("RX INT5 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10656                         rx_int5_spline_mix_switch,
10657                         ARRAY_SIZE(rx_int5_spline_mix_switch)),
10658         SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10659
10660         SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10661         SND_SOC_DAPM_MIXER("RX INT6 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10662                         rx_int6_spline_mix_switch,
10663                         ARRAY_SIZE(rx_int6_spline_mix_switch)),
10664         SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10665
10666         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10667         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10668         SND_SOC_DAPM_MIXER("RX INT7 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10669                         rx_int7_spline_mix_switch,
10670                         ARRAY_SIZE(rx_int7_spline_mix_switch)),
10671
10672         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
10673         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
10674         SND_SOC_DAPM_MIXER("RX INT8 SPLINE MIX", SND_SOC_NOPM, 0, 0,
10675                         rx_int8_spline_mix_switch,
10676                         ARRAY_SIZE(rx_int8_spline_mix_switch)),
10677
10678         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10679         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10680         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10681         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10682         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10683         SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10684         SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10685         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
10686         SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
10687                         NULL, 0, tasha_codec_spk_boost_event,
10688                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10689         SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
10690                         NULL, 0, tasha_codec_spk_boost_event,
10691                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10692
10693         SND_SOC_DAPM_MIXER_E("RX INT5 VBAT", SND_SOC_NOPM, 0, 0,
10694                         rx_int5_vbat_mix_switch,
10695                         ARRAY_SIZE(rx_int5_vbat_mix_switch),
10696                         tasha_codec_vbat_enable_event,
10697                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10698         SND_SOC_DAPM_MIXER_E("RX INT6 VBAT", SND_SOC_NOPM, 0, 0,
10699                         rx_int6_vbat_mix_switch,
10700                         ARRAY_SIZE(rx_int6_vbat_mix_switch),
10701                         tasha_codec_vbat_enable_event,
10702                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10703         SND_SOC_DAPM_MIXER_E("RX INT7 VBAT", SND_SOC_NOPM, 0, 0,
10704                         rx_int7_vbat_mix_switch,
10705                         ARRAY_SIZE(rx_int7_vbat_mix_switch),
10706                         tasha_codec_vbat_enable_event,
10707                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10708         SND_SOC_DAPM_MIXER_E("RX INT8 VBAT", SND_SOC_NOPM, 0, 0,
10709                         rx_int8_vbat_mix_switch,
10710                         ARRAY_SIZE(rx_int8_vbat_mix_switch),
10711                         tasha_codec_vbat_enable_event,
10712                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10713
10714         SND_SOC_DAPM_MUX("RX INT0 MIX2 INP", WCD9335_CDC_RX0_RX_PATH_CFG1, 4,
10715                            0, &rx_int0_mix2_inp_mux),
10716         SND_SOC_DAPM_MUX("RX INT1 MIX2 INP", WCD9335_CDC_RX1_RX_PATH_CFG1, 4,
10717                            0, &rx_int1_mix2_inp_mux),
10718         SND_SOC_DAPM_MUX("RX INT2 MIX2 INP", WCD9335_CDC_RX2_RX_PATH_CFG1, 4,
10719                            0, &rx_int2_mix2_inp_mux),
10720         SND_SOC_DAPM_MUX("RX INT3 MIX2 INP", WCD9335_CDC_RX3_RX_PATH_CFG1, 4,
10721                            0, &rx_int3_mix2_inp_mux),
10722         SND_SOC_DAPM_MUX("RX INT4 MIX2 INP", WCD9335_CDC_RX4_RX_PATH_CFG1, 4,
10723                            0, &rx_int4_mix2_inp_mux),
10724         SND_SOC_DAPM_MUX("RX INT7 MIX2 INP", WCD9335_CDC_RX7_RX_PATH_CFG1, 4,
10725                            0, &rx_int7_mix2_inp_mux),
10726
10727         SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, TASHA_TX0, 0,
10728                 &sb_tx0_mux),
10729         SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, TASHA_TX1, 0,
10730                 &sb_tx1_mux),
10731         SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, TASHA_TX2, 0,
10732                 &sb_tx2_mux),
10733         SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, TASHA_TX3, 0,
10734                 &sb_tx3_mux),
10735         SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, TASHA_TX4, 0,
10736                 &sb_tx4_mux),
10737         SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, TASHA_TX5, 0,
10738                 &sb_tx5_mux),
10739         SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, TASHA_TX6, 0,
10740                 &sb_tx6_mux),
10741         SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, TASHA_TX7, 0,
10742                 &sb_tx7_mux),
10743         SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, TASHA_TX8, 0,
10744                 &sb_tx8_mux),
10745         SND_SOC_DAPM_MUX("SLIM TX9 MUX", SND_SOC_NOPM, TASHA_TX9, 0,
10746                 &sb_tx9_mux),
10747         SND_SOC_DAPM_MUX("SLIM TX10 MUX", SND_SOC_NOPM, TASHA_TX10, 0,
10748                 &sb_tx10_mux),
10749         SND_SOC_DAPM_MUX("SLIM TX11 MUX", SND_SOC_NOPM, TASHA_TX11, 0,
10750                 &sb_tx11_mux),
10751         SND_SOC_DAPM_MUX("SLIM TX11 INP1 MUX", SND_SOC_NOPM, TASHA_TX11, 0,
10752                 &sb_tx11_inp1_mux),
10753         SND_SOC_DAPM_MUX("SLIM TX13 MUX", SND_SOC_NOPM, TASHA_TX13, 0,
10754                 &sb_tx13_mux),
10755         SND_SOC_DAPM_MUX("TX13 INP MUX", SND_SOC_NOPM, 0, 0,
10756                          &tx13_inp_mux),
10757
10758         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
10759                            &tx_adc_mux0, tasha_codec_enable_dec,
10760                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10761                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10762
10763         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
10764                            &tx_adc_mux1, tasha_codec_enable_dec,
10765                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10766                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10767
10768         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
10769                            &tx_adc_mux2, tasha_codec_enable_dec,
10770                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10771                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10772
10773         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
10774                            &tx_adc_mux3, tasha_codec_enable_dec,
10775                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10776                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10777
10778         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
10779                            &tx_adc_mux4, tasha_codec_enable_dec,
10780                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10781                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10782
10783         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
10784                            &tx_adc_mux5, tasha_codec_enable_dec,
10785                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10786                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10787
10788         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
10789                            &tx_adc_mux6, tasha_codec_enable_dec,
10790                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10791                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10792
10793         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
10794                            &tx_adc_mux7, tasha_codec_enable_dec,
10795                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10796                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10797
10798         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
10799                            &tx_adc_mux8, tasha_codec_enable_dec,
10800                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10801                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
10802
10803         SND_SOC_DAPM_MUX_E("ADC MUX10", SND_SOC_NOPM, 10, 0,
10804                          &tx_adc_mux10, tasha_codec_tx_adc_cfg,
10805                          SND_SOC_DAPM_POST_PMU),
10806
10807         SND_SOC_DAPM_MUX_E("ADC MUX11", SND_SOC_NOPM, 11, 0,
10808                          &tx_adc_mux11, tasha_codec_tx_adc_cfg,
10809                          SND_SOC_DAPM_POST_PMU),
10810
10811         SND_SOC_DAPM_MUX_E("ADC MUX12", SND_SOC_NOPM, 12, 0,
10812                          &tx_adc_mux12, tasha_codec_tx_adc_cfg,
10813                          SND_SOC_DAPM_POST_PMU),
10814
10815         SND_SOC_DAPM_MUX_E("ADC MUX13", SND_SOC_NOPM, 13, 0,
10816                          &tx_adc_mux13, tasha_codec_tx_adc_cfg,
10817                          SND_SOC_DAPM_POST_PMU),
10818
10819         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
10820                 &tx_dmic_mux0),
10821         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
10822                 &tx_dmic_mux1),
10823         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
10824                 &tx_dmic_mux2),
10825         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
10826                 &tx_dmic_mux3),
10827         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
10828                 &tx_dmic_mux4),
10829         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
10830                 &tx_dmic_mux5),
10831         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
10832                 &tx_dmic_mux6),
10833         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
10834                 &tx_dmic_mux7),
10835         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
10836                 &tx_dmic_mux8),
10837         SND_SOC_DAPM_MUX("DMIC MUX10", SND_SOC_NOPM, 0, 0,
10838                 &tx_dmic_mux10),
10839         SND_SOC_DAPM_MUX("DMIC MUX11", SND_SOC_NOPM, 0, 0,
10840                 &tx_dmic_mux11),
10841         SND_SOC_DAPM_MUX("DMIC MUX12", SND_SOC_NOPM, 0, 0,
10842                 &tx_dmic_mux12),
10843         SND_SOC_DAPM_MUX("DMIC MUX13", SND_SOC_NOPM, 0, 0,
10844                 &tx_dmic_mux13),
10845
10846         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
10847                 &tx_amic_mux0),
10848         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
10849                 &tx_amic_mux1),
10850         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
10851                 &tx_amic_mux2),
10852         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
10853                 &tx_amic_mux3),
10854         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
10855                 &tx_amic_mux4),
10856         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
10857                 &tx_amic_mux5),
10858         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
10859                 &tx_amic_mux6),
10860         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
10861                 &tx_amic_mux7),
10862         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
10863                 &tx_amic_mux8),
10864         SND_SOC_DAPM_MUX("AMIC MUX10", SND_SOC_NOPM, 0, 0,
10865                 &tx_amic_mux10),
10866         SND_SOC_DAPM_MUX("AMIC MUX11", SND_SOC_NOPM, 0, 0,
10867                 &tx_amic_mux11),
10868         SND_SOC_DAPM_MUX("AMIC MUX12", SND_SOC_NOPM, 0, 0,
10869                 &tx_amic_mux12),
10870         SND_SOC_DAPM_MUX("AMIC MUX13", SND_SOC_NOPM, 0, 0,
10871                 &tx_amic_mux13),
10872
10873         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
10874                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10875         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
10876                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10877         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
10878                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10879         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
10880                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10881         SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
10882                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10883         SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
10884                            tasha_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
10885
10886         SND_SOC_DAPM_SUPPLY("RX INT1 NATIVE SUPPLY", SND_SOC_NOPM,
10887                             INTERP_HPHL, 0, tasha_enable_native_supply,
10888                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
10889
10890         SND_SOC_DAPM_SUPPLY("RX INT2 NATIVE SUPPLY", SND_SOC_NOPM,
10891                             INTERP_HPHR, 0, tasha_enable_native_supply,
10892                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
10893
10894         SND_SOC_DAPM_SUPPLY("RX INT3 NATIVE SUPPLY", SND_SOC_NOPM,
10895                             INTERP_LO1, 0, tasha_enable_native_supply,
10896                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
10897
10898         SND_SOC_DAPM_SUPPLY("RX INT4 NATIVE SUPPLY", SND_SOC_NOPM,
10899                             INTERP_LO2, 0, tasha_enable_native_supply,
10900                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
10901
10902         SND_SOC_DAPM_INPUT("AMIC1"),
10903         SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
10904                                tasha_codec_enable_micbias,
10905                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10906                                SND_SOC_DAPM_POST_PMD),
10907         SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
10908                                tasha_codec_enable_micbias,
10909                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10910                                SND_SOC_DAPM_POST_PMD),
10911         SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
10912                                tasha_codec_enable_micbias,
10913                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10914                                SND_SOC_DAPM_POST_PMD),
10915         SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
10916                                tasha_codec_enable_micbias,
10917                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
10918                                SND_SOC_DAPM_POST_PMD),
10919
10920         SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
10921                                tasha_codec_force_enable_micbias,
10922                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10923         SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
10924                                tasha_codec_force_enable_micbias,
10925                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10926         SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
10927                                tasha_codec_force_enable_micbias,
10928                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10929         SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
10930                                tasha_codec_force_enable_micbias,
10931                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10932         SND_SOC_DAPM_SUPPLY(DAPM_LDO_H_STANDALONE, SND_SOC_NOPM, 0, 0,
10933                             tasha_codec_force_enable_ldo_h,
10934                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
10935
10936         SND_SOC_DAPM_MUX("ANC0 FB MUX", SND_SOC_NOPM, 0, 0, &anc0_fb_mux),
10937         SND_SOC_DAPM_MUX("ANC1 FB MUX", SND_SOC_NOPM, 0, 0, &anc1_fb_mux),
10938
10939         SND_SOC_DAPM_INPUT("AMIC2"),
10940         SND_SOC_DAPM_INPUT("AMIC3"),
10941         SND_SOC_DAPM_INPUT("AMIC4"),
10942         SND_SOC_DAPM_INPUT("AMIC5"),
10943         SND_SOC_DAPM_INPUT("AMIC6"),
10944
10945         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
10946                 AIF1_CAP, 0, tasha_codec_enable_slimtx,
10947                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
10948
10949         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
10950                 AIF2_CAP, 0, tasha_codec_enable_slimtx,
10951                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
10952
10953         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
10954                 AIF3_CAP, 0, tasha_codec_enable_slimtx,
10955                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
10956
10957         SND_SOC_DAPM_AIF_OUT_E("AIF4 VI", "VIfeed", 0, SND_SOC_NOPM,
10958                 AIF4_VIFEED, 0, tasha_codec_enable_slimvi_feedback,
10959                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
10960         SND_SOC_DAPM_MIXER("AIF4_VI Mixer", SND_SOC_NOPM, AIF4_VIFEED, 0,
10961                 aif4_vi_mixer, ARRAY_SIZE(aif4_vi_mixer)),
10962
10963         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
10964                 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
10965
10966         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
10967                 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
10968
10969         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
10970                 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
10971
10972         SND_SOC_DAPM_MIXER("AIF4_MAD Mixer", SND_SOC_NOPM, AIF4_MAD_TX, 0,
10973                 aif4_mad_mixer, ARRAY_SIZE(aif4_mad_mixer)),
10974
10975         SND_SOC_DAPM_INPUT("VIINPUT"),
10976
10977         SND_SOC_DAPM_AIF_OUT("AIF5 CPE", "AIF5 CPE TX", 0, SND_SOC_NOPM,
10978                              AIF5_CPE_TX, 0),
10979
10980         SND_SOC_DAPM_MUX_E("EC BUF MUX INP", SND_SOC_NOPM, 0, 0, &ec_buf_mux,
10981                 tasha_codec_ec_buf_mux_enable,
10982                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
10983
10984         /* Digital Mic Inputs */
10985         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
10986                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
10987                 SND_SOC_DAPM_POST_PMD),
10988
10989         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
10990                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
10991                 SND_SOC_DAPM_POST_PMD),
10992
10993         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
10994                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
10995                 SND_SOC_DAPM_POST_PMD),
10996
10997         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
10998                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
10999                 SND_SOC_DAPM_POST_PMD),
11000
11001         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
11002                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
11003                 SND_SOC_DAPM_POST_PMD),
11004
11005         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
11006                 tasha_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
11007                 SND_SOC_DAPM_POST_PMD),
11008
11009         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
11010         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
11011         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
11012         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
11013         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
11014         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
11015         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
11016         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
11017
11018         SND_SOC_DAPM_MIXER_E("IIR0", WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL,
11019                              4, 0, NULL, 0, tasha_codec_set_iir_gain,
11020                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
11021         SND_SOC_DAPM_MIXER_E("IIR1", WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL,
11022                              4, 0, NULL, 0, tasha_codec_set_iir_gain,
11023                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
11024         SND_SOC_DAPM_MIXER("SRC0", WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
11025                              4, 0, NULL, 0),
11026         SND_SOC_DAPM_MIXER("SRC1", WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
11027                              4, 0, NULL, 0),
11028         SND_SOC_DAPM_MIXER_E("CPE IN Mixer", SND_SOC_NOPM, 0, 0,
11029                                 cpe_in_mix_switch,
11030                                 ARRAY_SIZE(cpe_in_mix_switch),
11031                                 tasha_codec_configure_cpe_input,
11032                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11033
11034         SND_SOC_DAPM_MUX("RX INT1_1 NATIVE MUX", SND_SOC_NOPM, 0, 0,
11035                 &int1_1_native_mux),
11036         SND_SOC_DAPM_MUX("RX INT2_1 NATIVE MUX", SND_SOC_NOPM, 0, 0,
11037                 &int2_1_native_mux),
11038         SND_SOC_DAPM_MUX("RX INT3_1 NATIVE MUX", SND_SOC_NOPM, 0, 0,
11039                 &int3_1_native_mux),
11040         SND_SOC_DAPM_MUX("RX INT4_1 NATIVE MUX", SND_SOC_NOPM, 0, 0,
11041                 &int4_1_native_mux),
11042         SND_SOC_DAPM_MUX("RX MIX TX0 MUX", SND_SOC_NOPM, 0, 0,
11043                 &rx_mix_tx0_mux),
11044         SND_SOC_DAPM_MUX("RX MIX TX1 MUX", SND_SOC_NOPM, 0, 0,
11045                 &rx_mix_tx1_mux),
11046         SND_SOC_DAPM_MUX("RX MIX TX2 MUX", SND_SOC_NOPM, 0, 0,
11047                 &rx_mix_tx2_mux),
11048         SND_SOC_DAPM_MUX("RX MIX TX3 MUX", SND_SOC_NOPM, 0, 0,
11049                 &rx_mix_tx3_mux),
11050         SND_SOC_DAPM_MUX("RX MIX TX4 MUX", SND_SOC_NOPM, 0, 0,
11051                 &rx_mix_tx4_mux),
11052         SND_SOC_DAPM_MUX("RX MIX TX5 MUX", SND_SOC_NOPM, 0, 0,
11053                 &rx_mix_tx5_mux),
11054         SND_SOC_DAPM_MUX("RX MIX TX6 MUX", SND_SOC_NOPM, 0, 0,
11055                 &rx_mix_tx6_mux),
11056         SND_SOC_DAPM_MUX("RX MIX TX7 MUX", SND_SOC_NOPM, 0, 0,
11057                 &rx_mix_tx7_mux),
11058         SND_SOC_DAPM_MUX("RX MIX TX8 MUX", SND_SOC_NOPM, 0, 0,
11059                 &rx_mix_tx8_mux),
11060
11061         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
11062                 &rx_int0_dem_inp_mux),
11063         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
11064                 &rx_int1_dem_inp_mux),
11065         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
11066                 &rx_int2_dem_inp_mux),
11067
11068         SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
11069                 INTERP_EAR, 0, &rx_int0_interp_mux,
11070                 tasha_codec_enable_interpolator,
11071                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11072                 SND_SOC_DAPM_POST_PMD),
11073         SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
11074                 INTERP_HPHL, 0, &rx_int1_interp_mux,
11075                 tasha_codec_enable_interpolator,
11076                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11077                 SND_SOC_DAPM_POST_PMD),
11078         SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
11079                 INTERP_HPHR, 0, &rx_int2_interp_mux,
11080                 tasha_codec_enable_interpolator,
11081                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11082                 SND_SOC_DAPM_POST_PMD),
11083         SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
11084                 INTERP_LO1, 0, &rx_int3_interp_mux,
11085                 tasha_codec_enable_interpolator,
11086                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11087                 SND_SOC_DAPM_POST_PMD),
11088         SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
11089                 INTERP_LO2, 0, &rx_int4_interp_mux,
11090                 tasha_codec_enable_interpolator,
11091                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11092                 SND_SOC_DAPM_POST_PMD),
11093         SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
11094                 INTERP_LO3, 0, &rx_int5_interp_mux,
11095                 tasha_codec_enable_interpolator,
11096                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11097                 SND_SOC_DAPM_POST_PMD),
11098         SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
11099                 INTERP_LO4, 0, &rx_int6_interp_mux,
11100                 tasha_codec_enable_interpolator,
11101                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11102                 SND_SOC_DAPM_POST_PMD),
11103         SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
11104                 INTERP_SPKR1, 0, &rx_int7_interp_mux,
11105                 tasha_codec_enable_interpolator,
11106                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11107                 SND_SOC_DAPM_POST_PMD),
11108         SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
11109                 INTERP_SPKR2, 0, &rx_int8_interp_mux,
11110                 tasha_codec_enable_interpolator,
11111                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11112                 SND_SOC_DAPM_POST_PMD),
11113
11114         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
11115                 0, 0, tasha_codec_ear_dac_event,
11116                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11117                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11118         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, SND_SOC_NOPM,
11119                 0, 0, tasha_codec_hphl_dac_event,
11120                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11121                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11122         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, SND_SOC_NOPM,
11123                 0, 0, tasha_codec_hphr_dac_event,
11124                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11125                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11126         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
11127                 0, 0, tasha_codec_lineout_dac_event,
11128                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11129         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
11130                 0, 0, tasha_codec_lineout_dac_event,
11131                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11132         SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
11133                 0, 0, tasha_codec_lineout_dac_event,
11134                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11135         SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
11136                 0, 0, tasha_codec_lineout_dac_event,
11137                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11138         SND_SOC_DAPM_PGA_E("HPHL PA", SND_SOC_NOPM, 0, 0, NULL, 0,
11139                            tasha_codec_enable_hphl_pa,
11140                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11141                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11142         SND_SOC_DAPM_PGA_E("HPHR PA", SND_SOC_NOPM, 0, 0, NULL, 0,
11143                            tasha_codec_enable_hphr_pa,
11144                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11145                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11146         SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
11147                            tasha_codec_enable_ear_pa,
11148                            SND_SOC_DAPM_POST_PMU |
11149                            SND_SOC_DAPM_POST_PMD),
11150         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
11151                            tasha_codec_enable_lineout_pa,
11152                            SND_SOC_DAPM_POST_PMU |
11153                            SND_SOC_DAPM_POST_PMD),
11154         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
11155                            tasha_codec_enable_lineout_pa,
11156                            SND_SOC_DAPM_POST_PMU |
11157                            SND_SOC_DAPM_POST_PMD),
11158         SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
11159                            tasha_codec_enable_lineout_pa,
11160                            SND_SOC_DAPM_POST_PMU |
11161                            SND_SOC_DAPM_POST_PMD),
11162         SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
11163                            tasha_codec_enable_lineout_pa,
11164                            SND_SOC_DAPM_POST_PMU |
11165                            SND_SOC_DAPM_POST_PMD),
11166         SND_SOC_DAPM_PGA_E("ANC EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
11167                            tasha_codec_enable_ear_pa,
11168                            SND_SOC_DAPM_POST_PMU |
11169                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11170         SND_SOC_DAPM_PGA_E("ANC HPHL PA", SND_SOC_NOPM, 0, 0, NULL, 0,
11171                            tasha_codec_enable_hphl_pa,
11172                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11173                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11174         SND_SOC_DAPM_PGA_E("ANC HPHR PA", SND_SOC_NOPM, 0, 0, NULL, 0,
11175                            tasha_codec_enable_hphr_pa,
11176                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
11177                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11178         SND_SOC_DAPM_PGA_E("ANC LINEOUT1 PA", WCD9335_ANA_LO_1_2,
11179                                 7, 0, NULL, 0,
11180                                 tasha_codec_enable_lineout_pa,
11181                                 SND_SOC_DAPM_POST_PMU |
11182                                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11183         SND_SOC_DAPM_PGA_E("ANC LINEOUT2 PA", WCD9335_ANA_LO_1_2,
11184                                 6, 0, NULL, 0,
11185                                 tasha_codec_enable_lineout_pa,
11186                                 SND_SOC_DAPM_POST_PMU |
11187                                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
11188         SND_SOC_DAPM_PGA_E("ANC SPK1 PA", SND_SOC_NOPM, 0, 0, NULL, 0,
11189                            tasha_codec_enable_spk_anc,
11190                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11191
11192         SND_SOC_DAPM_OUTPUT("HPHL"),
11193         SND_SOC_DAPM_OUTPUT("HPHR"),
11194         SND_SOC_DAPM_OUTPUT("ANC HPHL"),
11195         SND_SOC_DAPM_OUTPUT("ANC HPHR"),
11196         SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
11197                 tasha_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
11198                 SND_SOC_DAPM_POST_PMD),
11199         SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
11200         SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
11201         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
11202         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
11203         SND_SOC_DAPM_OUTPUT("LINEOUT3"),
11204         SND_SOC_DAPM_OUTPUT("LINEOUT4"),
11205         SND_SOC_DAPM_OUTPUT("ANC LINEOUT1"),
11206         SND_SOC_DAPM_OUTPUT("ANC LINEOUT2"),
11207         SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM,
11208                 ON_DEMAND_MICBIAS, 0,
11209                 tasha_codec_enable_on_demand_supply,
11210                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11211
11212         SND_SOC_DAPM_SWITCH("ADC US MUX0", WCD9335_CDC_TX0_TX_PATH_192_CTL, 0,
11213                             0, &adc_us_mux0_switch),
11214         SND_SOC_DAPM_SWITCH("ADC US MUX1", WCD9335_CDC_TX1_TX_PATH_192_CTL, 0,
11215                             0, &adc_us_mux1_switch),
11216         SND_SOC_DAPM_SWITCH("ADC US MUX2", WCD9335_CDC_TX2_TX_PATH_192_CTL, 0,
11217                             0, &adc_us_mux2_switch),
11218         SND_SOC_DAPM_SWITCH("ADC US MUX3", WCD9335_CDC_TX3_TX_PATH_192_CTL, 0,
11219                             0, &adc_us_mux3_switch),
11220         SND_SOC_DAPM_SWITCH("ADC US MUX4", WCD9335_CDC_TX4_TX_PATH_192_CTL, 0,
11221                             0, &adc_us_mux4_switch),
11222         SND_SOC_DAPM_SWITCH("ADC US MUX5", WCD9335_CDC_TX5_TX_PATH_192_CTL, 0,
11223                             0, &adc_us_mux5_switch),
11224         SND_SOC_DAPM_SWITCH("ADC US MUX6", WCD9335_CDC_TX6_TX_PATH_192_CTL, 0,
11225                             0, &adc_us_mux6_switch),
11226         SND_SOC_DAPM_SWITCH("ADC US MUX7", WCD9335_CDC_TX7_TX_PATH_192_CTL, 0,
11227                             0, &adc_us_mux7_switch),
11228         SND_SOC_DAPM_SWITCH("ADC US MUX8", WCD9335_CDC_TX8_TX_PATH_192_CTL, 0,
11229                             0, &adc_us_mux8_switch),
11230         /* MAD related widgets */
11231         SND_SOC_DAPM_AIF_OUT_E("AIF4 MAD", "AIF4 MAD TX", 0,
11232                                SND_SOC_NOPM, 0, 0,
11233                                tasha_codec_enable_mad,
11234                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
11235
11236         SND_SOC_DAPM_MUX("MAD_SEL MUX", SND_SOC_NOPM, 0, 0,
11237                          &mad_sel_mux),
11238         SND_SOC_DAPM_INPUT("MAD_CPE_INPUT"),
11239         SND_SOC_DAPM_INPUT("MADINPUT"),
11240         SND_SOC_DAPM_SWITCH("MADONOFF", SND_SOC_NOPM, 0, 0,
11241                             &aif4_mad_switch),
11242         SND_SOC_DAPM_SWITCH("MAD_BROADCAST", SND_SOC_NOPM, 0, 0,
11243                             &mad_brdcst_switch),
11244         SND_SOC_DAPM_SWITCH("AIF4", SND_SOC_NOPM, 0, 0,
11245                             &aif4_switch_mixer_controls),
11246         SND_SOC_DAPM_SWITCH("ANC HPHL Enable", SND_SOC_NOPM, 0, 0,
11247                         &anc_hphl_switch),
11248         SND_SOC_DAPM_SWITCH("ANC HPHR Enable", SND_SOC_NOPM, 0, 0,
11249                         &anc_hphr_switch),
11250         SND_SOC_DAPM_SWITCH("ANC EAR Enable", SND_SOC_NOPM, 0, 0,
11251                         &anc_ear_switch),
11252         SND_SOC_DAPM_SWITCH("ANC OUT EAR SPKR Enable", SND_SOC_NOPM, 0, 0,
11253                             &anc_ear_spkr_switch),
11254         SND_SOC_DAPM_SWITCH("ANC LINEOUT1 Enable", SND_SOC_NOPM, 0, 0,
11255                         &anc_lineout1_switch),
11256         SND_SOC_DAPM_SWITCH("ANC LINEOUT2 Enable", SND_SOC_NOPM, 0, 0,
11257                         &anc_lineout2_switch),
11258         SND_SOC_DAPM_SWITCH("ANC SPKR PA Enable", SND_SOC_NOPM, 0, 0,
11259                             &anc_spkr_pa_switch),
11260 };
11261
11262 static int tasha_get_channel_map(struct snd_soc_dai *dai,
11263                                  unsigned int *tx_num, unsigned int *tx_slot,
11264                                  unsigned int *rx_num, unsigned int *rx_slot)
11265 {
11266         struct tasha_priv *tasha_p = snd_soc_codec_get_drvdata(dai->codec);
11267         u32 i = 0;
11268         struct wcd9xxx_ch *ch;
11269
11270         switch (dai->id) {
11271         case AIF1_PB:
11272         case AIF2_PB:
11273         case AIF3_PB:
11274         case AIF4_PB:
11275         case AIF_MIX1_PB:
11276                 if (!rx_slot || !rx_num) {
11277                         pr_err("%s: Invalid rx_slot %pK or rx_num %pK\n",
11278                                  __func__, rx_slot, rx_num);
11279                         return -EINVAL;
11280                 }
11281                 list_for_each_entry(ch, &tasha_p->dai[dai->id].wcd9xxx_ch_list,
11282                                     list) {
11283                         pr_debug("%s: slot_num %u ch->ch_num %d\n",
11284                                  __func__, i, ch->ch_num);
11285                         rx_slot[i++] = ch->ch_num;
11286                 }
11287                 pr_debug("%s: rx_num %d\n", __func__, i);
11288                 *rx_num = i;
11289                 break;
11290         case AIF1_CAP:
11291         case AIF2_CAP:
11292         case AIF3_CAP:
11293         case AIF4_MAD_TX:
11294         case AIF4_VIFEED:
11295                 if (!tx_slot || !tx_num) {
11296                         pr_err("%s: Invalid tx_slot %pK or tx_num %pK\n",
11297                                  __func__, tx_slot, tx_num);
11298                         return -EINVAL;
11299                 }
11300                 list_for_each_entry(ch, &tasha_p->dai[dai->id].wcd9xxx_ch_list,
11301                                     list) {
11302                         pr_debug("%s: slot_num %u ch->ch_num %d\n",
11303                                  __func__, i,  ch->ch_num);
11304                         tx_slot[i++] = ch->ch_num;
11305                 }
11306                 pr_debug("%s: tx_num %d\n", __func__, i);
11307                 *tx_num = i;
11308                 break;
11309
11310         default:
11311                 pr_err("%s: Invalid DAI ID %x\n", __func__, dai->id);
11312                 break;
11313         }
11314
11315         return 0;
11316 }
11317
11318 static int tasha_set_channel_map(struct snd_soc_dai *dai,
11319                                  unsigned int tx_num, unsigned int *tx_slot,
11320                                  unsigned int rx_num, unsigned int *rx_slot)
11321 {
11322         struct tasha_priv *tasha;
11323         struct wcd9xxx *core;
11324         struct wcd9xxx_codec_dai_data *dai_data = NULL;
11325
11326         if (!dai) {
11327                 pr_err("%s: dai is empty\n", __func__);
11328                 return -EINVAL;
11329         }
11330         tasha = snd_soc_codec_get_drvdata(dai->codec);
11331         core = dev_get_drvdata(dai->codec->dev->parent);
11332
11333         if (!tx_slot || !rx_slot) {
11334                 pr_err("%s: Invalid tx_slot=%pK, rx_slot=%pK\n",
11335                         __func__, tx_slot, rx_slot);
11336                 return -EINVAL;
11337         }
11338         pr_debug("%s(): dai_name = %s DAI-ID %x tx_ch %d rx_ch %d\n"
11339                  "tasha->intf_type %d\n",
11340                  __func__, dai->name, dai->id, tx_num, rx_num,
11341                  tasha->intf_type);
11342
11343         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
11344                 wcd9xxx_init_slimslave(core, core->slim->laddr,
11345                                            tx_num, tx_slot, rx_num, rx_slot);
11346                 /* Reserve TX12/TX13 for MAD data channel */
11347                 dai_data = &tasha->dai[AIF4_MAD_TX];
11348                 if (dai_data) {
11349                         if (TASHA_IS_2_0(tasha->wcd9xxx))
11350                                 list_add_tail(&core->tx_chs[TASHA_TX13].list,
11351                                               &dai_data->wcd9xxx_ch_list);
11352                         else
11353                                 list_add_tail(&core->tx_chs[TASHA_TX12].list,
11354                                               &dai_data->wcd9xxx_ch_list);
11355                 }
11356         }
11357         return 0;
11358 }
11359
11360 static int tasha_startup(struct snd_pcm_substream *substream,
11361                 struct snd_soc_dai *dai)
11362 {
11363         pr_debug("%s(): substream = %s  stream = %d\n" , __func__,
11364                  substream->name, substream->stream);
11365
11366         return 0;
11367 }
11368
11369 static void tasha_shutdown(struct snd_pcm_substream *substream,
11370                 struct snd_soc_dai *dai)
11371 {
11372         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(dai->codec);
11373
11374         pr_debug("%s(): substream = %s  stream = %d\n" , __func__,
11375                  substream->name, substream->stream);
11376
11377         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
11378                 return;
11379
11380         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
11381                 tasha_codec_vote_max_bw(dai->codec, false);
11382 }
11383
11384 static int tasha_set_decimator_rate(struct snd_soc_dai *dai,
11385                                     u8 tx_fs_rate_reg_val, u32 sample_rate)
11386 {
11387         struct snd_soc_codec *codec = dai->codec;
11388         struct wcd9xxx_ch *ch;
11389         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
11390         u32 tx_port = 0;
11391         u8 shift = 0, shift_val = 0, tx_mux_sel = 0;
11392         int decimator = -1;
11393         u16 tx_port_reg = 0, tx_fs_reg = 0;
11394
11395         list_for_each_entry(ch, &tasha->dai[dai->id].wcd9xxx_ch_list, list) {
11396                 tx_port = ch->port;
11397                 dev_dbg(codec->dev, "%s: dai->id = %d, tx_port = %d",
11398                         __func__, dai->id, tx_port);
11399
11400                 if ((tx_port < 0) || (tx_port == 12) || (tx_port >= 14)) {
11401                         dev_err(codec->dev, "%s: Invalid SLIM TX%u port. DAI ID: %d\n",
11402                                 __func__, tx_port, dai->id);
11403                         return -EINVAL;
11404                 }
11405                 /* Find the SB TX MUX input - which decimator is connected */
11406                 if (tx_port < 4) {
11407                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
11408                         shift = (tx_port << 1);
11409                         shift_val = 0x03;
11410                 } else if ((tx_port >= 4) && (tx_port < 8)) {
11411                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
11412                         shift = ((tx_port - 4) << 1);
11413                         shift_val = 0x03;
11414                 } else if ((tx_port >= 8) && (tx_port < 11)) {
11415                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
11416                         shift = ((tx_port - 8) << 1);
11417                         shift_val = 0x03;
11418                 } else if (tx_port == 11) {
11419                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
11420                         shift = 0;
11421                         shift_val = 0x0F;
11422                 } else if (tx_port == 13) {
11423                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
11424                         shift = 4;
11425                         shift_val = 0x03;
11426                 }
11427                 tx_mux_sel = snd_soc_read(codec, tx_port_reg) &
11428                                           (shift_val << shift);
11429                 tx_mux_sel = tx_mux_sel >> shift;
11430
11431                 if (tx_port <= 8) {
11432                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
11433                                 decimator = tx_port;
11434                 } else if (tx_port <= 10) {
11435                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
11436                                 decimator = ((tx_port == 9) ? 7 : 6);
11437                 } else if (tx_port == 11) {
11438                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
11439                                 decimator = tx_mux_sel - 1;
11440                 } else if (tx_port == 13) {
11441                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
11442                                 decimator = 5;
11443                 }
11444
11445                 if (decimator >= 0) {
11446                         tx_fs_reg = WCD9335_CDC_TX0_TX_PATH_CTL +
11447                                     16 * decimator;
11448                         dev_dbg(codec->dev, "%s: set DEC%u (-> SLIM_TX%u) rate to %u\n",
11449                                 __func__, decimator, tx_port, sample_rate);
11450                         snd_soc_update_bits(codec, tx_fs_reg, 0x0F,
11451                                             tx_fs_rate_reg_val);
11452                 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
11453                         /* Check if the TX Mux input is RX MIX TXn */
11454                         dev_dbg(codec->dev, "%s: RX_MIX_TX%u going to SLIM TX%u\n",
11455                                         __func__, tx_port, tx_port);
11456                 } else {
11457                         dev_err(codec->dev, "%s: ERROR: Invalid decimator: %d\n",
11458                                 __func__, decimator);
11459                         return -EINVAL;
11460                 }
11461         }
11462         return 0;
11463 }
11464
11465 static int tasha_set_mix_interpolator_rate(struct snd_soc_dai *dai,
11466                                            u8 int_mix_fs_rate_reg_val,
11467                                            u32 sample_rate)
11468 {
11469         u8 int_2_inp;
11470         u32 j;
11471         u16 int_mux_cfg1, int_fs_reg;
11472         u8 int_mux_cfg1_val;
11473         struct snd_soc_codec *codec = dai->codec;
11474         struct wcd9xxx_ch *ch;
11475         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
11476
11477         list_for_each_entry(ch, &tasha->dai[dai->id].wcd9xxx_ch_list, list) {
11478                 int_2_inp = ch->port + INTn_2_INP_SEL_RX0 -
11479                                   TASHA_RX_PORT_START_NUMBER;
11480                 if ((int_2_inp < INTn_2_INP_SEL_RX0) ||
11481                    (int_2_inp > INTn_2_INP_SEL_RX7)) {
11482                         pr_err("%s: Invalid RX%u port, Dai ID is %d\n",
11483                                 __func__,
11484                                 (ch->port - TASHA_RX_PORT_START_NUMBER),
11485                                 dai->id);
11486                         return -EINVAL;
11487                 }
11488
11489                 int_mux_cfg1 = WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1;
11490                 for (j = 0; j < TASHA_NUM_INTERPOLATORS; j++) {
11491                         int_mux_cfg1_val = snd_soc_read(codec, int_mux_cfg1) &
11492                                                 0x0F;
11493                         if (int_mux_cfg1_val == int_2_inp) {
11494                                 int_fs_reg = WCD9335_CDC_RX0_RX_PATH_MIX_CTL +
11495                                                 20 * j;
11496                                 pr_debug("%s: AIF_MIX_PB DAI(%d) connected to INT%u_2\n",
11497                                           __func__, dai->id, j);
11498                                 pr_debug("%s: set INT%u_2 sample rate to %u\n",
11499                                         __func__, j, sample_rate);
11500                                 snd_soc_update_bits(codec, int_fs_reg,
11501                                                 0x0F, int_mix_fs_rate_reg_val);
11502                         }
11503                         int_mux_cfg1 += 2;
11504                 }
11505         }
11506         return 0;
11507 }
11508
11509 static int tasha_set_prim_interpolator_rate(struct snd_soc_dai *dai,
11510                                             u8 int_prim_fs_rate_reg_val,
11511                                             u32 sample_rate)
11512 {
11513         u8 int_1_mix1_inp;
11514         u32 j;
11515         u16 int_mux_cfg0, int_mux_cfg1;
11516         u16 int_fs_reg;
11517         u8 int_mux_cfg0_val, int_mux_cfg1_val;
11518         u8 inp0_sel, inp1_sel, inp2_sel;
11519         struct snd_soc_codec *codec = dai->codec;
11520         struct wcd9xxx_ch *ch;
11521         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
11522
11523         list_for_each_entry(ch, &tasha->dai[dai->id].wcd9xxx_ch_list, list) {
11524                 int_1_mix1_inp = ch->port + INTn_1_MIX_INP_SEL_RX0 -
11525                                   TASHA_RX_PORT_START_NUMBER;
11526                 if ((int_1_mix1_inp < INTn_1_MIX_INP_SEL_RX0) ||
11527                    (int_1_mix1_inp > INTn_1_MIX_INP_SEL_RX7)) {
11528                         pr_err("%s: Invalid RX%u port, Dai ID is %d\n",
11529                                 __func__,
11530                                 (ch->port - TASHA_RX_PORT_START_NUMBER),
11531                                 dai->id);
11532                         return -EINVAL;
11533                 }
11534
11535                 int_mux_cfg0 = WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0;
11536
11537                 /*
11538                  * Loop through all interpolator MUX inputs and find out
11539                  * to which interpolator input, the slim rx port
11540                  * is connected
11541                  */
11542                 for (j = 0; j < TASHA_NUM_INTERPOLATORS; j++) {
11543                         int_mux_cfg1 = int_mux_cfg0 + 1;
11544
11545                         int_mux_cfg0_val = snd_soc_read(codec, int_mux_cfg0);
11546                         int_mux_cfg1_val = snd_soc_read(codec, int_mux_cfg1);
11547                         inp0_sel = int_mux_cfg0_val & 0x0F;
11548                         inp1_sel = (int_mux_cfg0_val >> 4) & 0x0F;
11549                         inp2_sel = (int_mux_cfg1_val >> 4) & 0x0F;
11550                         if ((inp0_sel == int_1_mix1_inp) ||
11551                             (inp1_sel == int_1_mix1_inp) ||
11552                             (inp2_sel == int_1_mix1_inp)) {
11553                                 int_fs_reg = WCD9335_CDC_RX0_RX_PATH_CTL +
11554                                              20 * j;
11555                                 pr_debug("%s: AIF_PB DAI(%d) connected to INT%u_1\n",
11556                                           __func__, dai->id, j);
11557                                 pr_debug("%s: set INT%u_1 sample rate to %u\n",
11558                                         __func__, j, sample_rate);
11559                                 /* sample_rate is in Hz */
11560                                 if ((j == 0) && (sample_rate == 44100)) {
11561                                         pr_info("%s: Cannot set 44.1KHz on INT0\n",
11562                                                 __func__);
11563                                 } else
11564                                         snd_soc_update_bits(codec, int_fs_reg,
11565                                                 0x0F, int_prim_fs_rate_reg_val);
11566                         }
11567                         int_mux_cfg0 += 2;
11568                 }
11569         }
11570
11571         return 0;
11572 }
11573
11574
11575 static int tasha_set_interpolator_rate(struct snd_soc_dai *dai,
11576                                        u32 sample_rate)
11577 {
11578         int rate_val = 0;
11579         int i, ret;
11580
11581         /* set mixing path rate */
11582         for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
11583                 if (sample_rate ==
11584                                 int_mix_sample_rate_val[i].sample_rate) {
11585                         rate_val =
11586                                 int_mix_sample_rate_val[i].rate_val;
11587                         break;
11588                 }
11589         }
11590         if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) ||
11591                         (rate_val < 0))
11592                 goto prim_rate;
11593         ret = tasha_set_mix_interpolator_rate(dai,
11594                         (u8) rate_val, sample_rate);
11595 prim_rate:
11596         /* set primary path sample rate */
11597         for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
11598                 if (sample_rate ==
11599                                 int_prim_sample_rate_val[i].sample_rate) {
11600                         rate_val =
11601                                 int_prim_sample_rate_val[i].rate_val;
11602                         break;
11603                 }
11604         }
11605         if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) ||
11606                         (rate_val < 0))
11607                 return -EINVAL;
11608         ret = tasha_set_prim_interpolator_rate(dai,
11609                         (u8) rate_val, sample_rate);
11610         return ret;
11611 }
11612
11613 static int tasha_prepare(struct snd_pcm_substream *substream,
11614                          struct snd_soc_dai *dai)
11615 {
11616         pr_debug("%s(): substream = %s  stream = %d\n" , __func__,
11617                  substream->name, substream->stream);
11618
11619         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
11620                 tasha_codec_vote_max_bw(dai->codec, false);
11621         return 0;
11622 }
11623
11624 static int tasha_hw_params(struct snd_pcm_substream *substream,
11625                            struct snd_pcm_hw_params *params,
11626                            struct snd_soc_dai *dai)
11627 {
11628         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(dai->codec);
11629         int ret;
11630         int tx_fs_rate = -EINVAL;
11631         int rx_fs_rate = -EINVAL;
11632         int i2s_bit_mode;
11633         struct snd_soc_codec *codec = dai->codec;
11634
11635         pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
11636                  dai->name, dai->id, params_rate(params),
11637                  params_channels(params));
11638
11639         switch (substream->stream) {
11640         case SNDRV_PCM_STREAM_PLAYBACK:
11641                 ret = tasha_set_interpolator_rate(dai, params_rate(params));
11642                 if (ret) {
11643                         pr_err("%s: cannot set sample rate: %u\n",
11644                                 __func__, params_rate(params));
11645                         return ret;
11646                 }
11647                 switch (params_width(params)) {
11648                 case 16:
11649                         tasha->dai[dai->id].bit_width = 16;
11650                         i2s_bit_mode = 0x01;
11651                         break;
11652                 case 24:
11653                         tasha->dai[dai->id].bit_width = 24;
11654                         i2s_bit_mode = 0x00;
11655                         break;
11656                 default:
11657                         return -EINVAL;
11658                 }
11659                 tasha->dai[dai->id].rate = params_rate(params);
11660                 if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
11661                         switch (params_rate(params)) {
11662                         case 8000:
11663                                 rx_fs_rate = 0;
11664                                 break;
11665                         case 16000:
11666                                 rx_fs_rate = 1;
11667                                 break;
11668                         case 32000:
11669                                 rx_fs_rate = 2;
11670                                 break;
11671                         case 48000:
11672                                 rx_fs_rate = 3;
11673                                 break;
11674                         case 96000:
11675                                 rx_fs_rate = 4;
11676                                 break;
11677                         case 192000:
11678                                 rx_fs_rate = 5;
11679                                 break;
11680                         default:
11681                                 dev_err(tasha->dev,
11682                                 "%s: Invalid RX sample rate: %d\n",
11683                                 __func__, params_rate(params));
11684                                 return -EINVAL;
11685                         };
11686                         snd_soc_update_bits(codec,
11687                                         WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL,
11688                                         0x20, i2s_bit_mode << 5);
11689                         snd_soc_update_bits(codec,
11690                                         WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL,
11691                                         0x1c, (rx_fs_rate << 2));
11692                 }
11693                 break;
11694         case SNDRV_PCM_STREAM_CAPTURE:
11695                 switch (params_rate(params)) {
11696                 case 8000:
11697                         tx_fs_rate = 0;
11698                         break;
11699                 case 16000:
11700                         tx_fs_rate = 1;
11701                         break;
11702                 case 32000:
11703                         tx_fs_rate = 3;
11704                         break;
11705                 case 48000:
11706                         tx_fs_rate = 4;
11707                         break;
11708                 case 96000:
11709                         tx_fs_rate = 5;
11710                         break;
11711                 case 192000:
11712                         tx_fs_rate = 6;
11713                         break;
11714                 case 384000:
11715                         tx_fs_rate = 7;
11716                         break;
11717                 default:
11718                         dev_err(tasha->dev, "%s: Invalid TX sample rate: %d\n",
11719                                 __func__, params_rate(params));
11720                         return -EINVAL;
11721
11722                 };
11723                 if (dai->id != AIF4_VIFEED &&
11724                     dai->id != AIF4_MAD_TX) {
11725                         ret = tasha_set_decimator_rate(dai, tx_fs_rate,
11726                                         params_rate(params));
11727                         if (ret < 0) {
11728                                 dev_err(tasha->dev, "%s: cannot set TX Decimator rate: %d\n",
11729                                         __func__, tx_fs_rate);
11730                                 return ret;
11731                         }
11732                 }
11733                 tasha->dai[dai->id].rate = params_rate(params);
11734                 switch (params_width(params)) {
11735                 case 16:
11736                         tasha->dai[dai->id].bit_width = 16;
11737                         i2s_bit_mode = 0x01;
11738                         break;
11739                 case 24:
11740                         tasha->dai[dai->id].bit_width = 24;
11741                         i2s_bit_mode = 0x00;
11742                         break;
11743                 case 32:
11744                         tasha->dai[dai->id].bit_width = 32;
11745                         i2s_bit_mode = 0x00;
11746                         break;
11747                 default:
11748                         dev_err(tasha->dev, "%s: Invalid format 0x%x\n",
11749                                 __func__, params_width(params));
11750                         return -EINVAL;
11751                 };
11752                 if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
11753                         snd_soc_update_bits(codec,
11754                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL,
11755                                 0x20, i2s_bit_mode << 5);
11756                         if (tx_fs_rate > 1)
11757                                 tx_fs_rate--;
11758                         snd_soc_update_bits(codec,
11759                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL,
11760                                 0x1c, tx_fs_rate << 2);
11761                         snd_soc_update_bits(codec,
11762                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG,
11763                                 0x05, 0x05);
11764
11765                         snd_soc_update_bits(codec,
11766                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG,
11767                                 0x05, 0x05);
11768
11769                         snd_soc_update_bits(codec,
11770                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG,
11771                                 0x05, 0x05);
11772
11773                         snd_soc_update_bits(codec,
11774                                 WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG,
11775                                 0x05, 0x05);
11776                 }
11777                 break;
11778         default:
11779                 pr_err("%s: Invalid stream type %d\n", __func__,
11780                         substream->stream);
11781                 return -EINVAL;
11782         };
11783         if (dai->id == AIF4_VIFEED)
11784                 tasha->dai[dai->id].bit_width = 32;
11785
11786         return 0;
11787 }
11788
11789 static int tasha_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
11790 {
11791         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(dai->codec);
11792
11793         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
11794         case SND_SOC_DAIFMT_CBS_CFS:
11795                 /* CPU is master */
11796                 if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
11797                         if (dai->id == AIF1_CAP)
11798                                 snd_soc_update_bits(dai->codec,
11799                                         WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL,
11800                                         0x2, 0);
11801                         else if (dai->id == AIF1_PB)
11802                                 snd_soc_update_bits(dai->codec,
11803                                         WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL,
11804                                         0x2, 0);
11805                 }
11806                 break;
11807         case SND_SOC_DAIFMT_CBM_CFM:
11808                 /* CPU is slave */
11809                 if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
11810                         if (dai->id == AIF1_CAP)
11811                                 snd_soc_update_bits(dai->codec,
11812                                         WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL,
11813                                         0x2, 0x2);
11814                         else if (dai->id == AIF1_PB)
11815                                 snd_soc_update_bits(dai->codec,
11816                                         WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL,
11817                                         0x2, 0x2);
11818                 }
11819                 break;
11820         default:
11821                 return -EINVAL;
11822         }
11823         return 0;
11824 }
11825
11826 static int tasha_set_dai_sysclk(struct snd_soc_dai *dai,
11827                 int clk_id, unsigned int freq, int dir)
11828 {
11829         pr_debug("%s\n", __func__);
11830         return 0;
11831 }
11832
11833 static struct snd_soc_dai_ops tasha_dai_ops = {
11834         .startup = tasha_startup,
11835         .shutdown = tasha_shutdown,
11836         .hw_params = tasha_hw_params,
11837         .prepare = tasha_prepare,
11838         .set_sysclk = tasha_set_dai_sysclk,
11839         .set_fmt = tasha_set_dai_fmt,
11840         .set_channel_map = tasha_set_channel_map,
11841         .get_channel_map = tasha_get_channel_map,
11842 };
11843
11844 static struct snd_soc_dai_driver tasha_dai[] = {
11845         {
11846                 .name = "tasha_rx1",
11847                 .id = AIF1_PB,
11848                 .playback = {
11849                         .stream_name = "AIF1 Playback",
11850                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
11851                         .formats = TASHA_FORMATS_S16_S24_LE,
11852                         .rate_max = 192000,
11853                         .rate_min = 8000,
11854                         .channels_min = 1,
11855                         .channels_max = 2,
11856                 },
11857                 .ops = &tasha_dai_ops,
11858         },
11859         {
11860                 .name = "tasha_tx1",
11861                 .id = AIF1_CAP,
11862                 .capture = {
11863                         .stream_name = "AIF1 Capture",
11864                         .rates = WCD9335_RATES_MASK,
11865                         .formats = TASHA_FORMATS_S16_S24_LE,
11866                         .rate_max = 192000,
11867                         .rate_min = 8000,
11868                         .channels_min = 1,
11869                         .channels_max = 4,
11870                 },
11871                 .ops = &tasha_dai_ops,
11872         },
11873         {
11874                 .name = "tasha_rx2",
11875                 .id = AIF2_PB,
11876                 .playback = {
11877                         .stream_name = "AIF2 Playback",
11878                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
11879                         .formats = TASHA_FORMATS_S16_S24_LE,
11880                         .rate_min = 8000,
11881                         .rate_max = 192000,
11882                         .channels_min = 1,
11883                         .channels_max = 2,
11884                 },
11885                 .ops = &tasha_dai_ops,
11886         },
11887         {
11888                 .name = "tasha_tx2",
11889                 .id = AIF2_CAP,
11890                 .capture = {
11891                         .stream_name = "AIF2 Capture",
11892                         .rates = WCD9335_RATES_MASK,
11893                         .formats = TASHA_FORMATS_S16_S24_LE,
11894                         .rate_max = 192000,
11895                         .rate_min = 8000,
11896                         .channels_min = 1,
11897                         .channels_max = 8,
11898                 },
11899                 .ops = &tasha_dai_ops,
11900         },
11901         {
11902                 .name = "tasha_rx3",
11903                 .id = AIF3_PB,
11904                 .playback = {
11905                         .stream_name = "AIF3 Playback",
11906                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
11907                         .formats = TASHA_FORMATS_S16_S24_LE,
11908                         .rate_min = 8000,
11909                         .rate_max = 192000,
11910                         .channels_min = 1,
11911                         .channels_max = 2,
11912                 },
11913                 .ops = &tasha_dai_ops,
11914         },
11915         {
11916                 .name = "tasha_tx3",
11917                 .id = AIF3_CAP,
11918                 .capture = {
11919                         .stream_name = "AIF3 Capture",
11920                         .rates = WCD9335_RATES_MASK,
11921                         .formats = TASHA_FORMATS_S16_S24_LE,
11922                         .rate_max = 48000,
11923                         .rate_min = 8000,
11924                         .channels_min = 1,
11925                         .channels_max = 2,
11926                 },
11927                 .ops = &tasha_dai_ops,
11928         },
11929         {
11930                 .name = "tasha_rx4",
11931                 .id = AIF4_PB,
11932                 .playback = {
11933                         .stream_name = "AIF4 Playback",
11934                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
11935                         .formats = TASHA_FORMATS_S16_S24_LE,
11936                         .rate_min = 8000,
11937                         .rate_max = 192000,
11938                         .channels_min = 1,
11939                         .channels_max = 2,
11940                 },
11941                 .ops = &tasha_dai_ops,
11942         },
11943         {
11944                 .name = "tasha_mix_rx1",
11945                 .id = AIF_MIX1_PB,
11946                 .playback = {
11947                         .stream_name = "AIF Mix Playback",
11948                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
11949                         .formats = TASHA_FORMATS_S16_S24_LE,
11950                         .rate_min = 8000,
11951                         .rate_max = 192000,
11952                         .channels_min = 1,
11953                         .channels_max = 8,
11954                 },
11955                 .ops = &tasha_dai_ops,
11956         },
11957         {
11958                 .name = "tasha_mad1",
11959                 .id = AIF4_MAD_TX,
11960                 .capture = {
11961                         .stream_name = "AIF4 MAD TX",
11962                         .rates = SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_48000 |
11963                                  SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_384000,
11964                         .formats = TASHA_FORMATS_S16_S24_S32_LE,
11965                         .rate_min = 16000,
11966                         .rate_max = 384000,
11967                         .channels_min = 1,
11968                         .channels_max = 1,
11969                 },
11970                 .ops = &tasha_dai_ops,
11971         },
11972         {
11973                 .name = "tasha_vifeedback",
11974                 .id = AIF4_VIFEED,
11975                 .capture = {
11976                         .stream_name = "VIfeed",
11977                         .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
11978                         .formats = TASHA_FORMATS_S16_S24_S32_LE,
11979                         .rate_max = 48000,
11980                         .rate_min = 8000,
11981                         .channels_min = 1,
11982                         .channels_max = 4,
11983                  },
11984                 .ops = &tasha_dai_ops,
11985         },
11986         {
11987                 .name = "tasha_cpe",
11988                 .id = AIF5_CPE_TX,
11989                 .capture = {
11990                         .stream_name = "AIF5 CPE TX",
11991                         .rates = SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_48000,
11992                         .formats = TASHA_FORMATS_S16_S24_S32_LE,
11993                         .rate_min = 16000,
11994                         .rate_max = 48000,
11995                         .channels_min = 1,
11996                         .channels_max = 1,
11997                 },
11998         },
11999 };
12000
12001 static struct snd_soc_dai_driver tasha_i2s_dai[] = {
12002         {
12003                 .name = "tasha_i2s_rx1",
12004                 .id = AIF1_PB,
12005                 .playback = {
12006                         .stream_name = "AIF1 Playback",
12007                         .rates = WCD9335_RATES_MASK,
12008                         .formats = TASHA_FORMATS_S16_S24_LE,
12009                         .rate_max = 192000,
12010                         .rate_min = 8000,
12011                         .channels_min = 1,
12012                         .channels_max = 2,
12013                 },
12014                 .ops = &tasha_dai_ops,
12015         },
12016         {
12017                 .name = "tasha_i2s_tx1",
12018                 .id = AIF1_CAP,
12019                 .capture = {
12020                         .stream_name = "AIF1 Capture",
12021                         .rates = WCD9335_RATES_MASK,
12022                         .formats = TASHA_FORMATS_S16_S24_LE,
12023                         .rate_max = 192000,
12024                         .rate_min = 8000,
12025                         .channels_min = 1,
12026                         .channels_max = 4,
12027                 },
12028                 .ops = &tasha_dai_ops,
12029         },
12030         {
12031                 .name = "tasha_i2s_rx2",
12032                 .id = AIF2_PB,
12033                 .playback = {
12034                         .stream_name = "AIF2 Playback",
12035                         .rates = WCD9335_RATES_MASK,
12036                         .formats = TASHA_FORMATS_S16_S24_LE,
12037                         .rate_max = 192000,
12038                         .rate_min = 8000,
12039                         .channels_min = 1,
12040                         .channels_max = 2,
12041                 },
12042                 .ops = &tasha_dai_ops,
12043         },
12044         {
12045                 .name = "tasha_i2s_tx2",
12046                 .id = AIF2_CAP,
12047                 .capture = {
12048                         .stream_name = "AIF2 Capture",
12049                         .rates = WCD9335_RATES_MASK,
12050                         .formats = TASHA_FORMATS_S16_S24_LE,
12051                         .rate_max = 192000,
12052                         .rate_min = 8000,
12053                         .channels_min = 1,
12054                         .channels_max = 4,
12055                 },
12056                 .ops = &tasha_dai_ops,
12057         },
12058 };
12059
12060 static void tasha_codec_power_gate_digital_core(struct tasha_priv *tasha)
12061 {
12062         struct snd_soc_codec *codec = tasha->codec;
12063
12064         if (!codec)
12065                 return;
12066
12067         mutex_lock(&tasha->power_lock);
12068         dev_dbg(codec->dev, "%s: Entering power gating function, %d\n",
12069                 __func__, tasha->power_active_ref);
12070
12071         if (tasha->power_active_ref > 0)
12072                 goto exit;
12073
12074         wcd9xxx_set_power_state(tasha->wcd9xxx,
12075                         WCD_REGION_POWER_COLLAPSE_BEGIN,
12076                         WCD9XXX_DIG_CORE_REGION_1);
12077         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
12078                         0x04, 0x04);
12079         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
12080                         0x01, 0x00);
12081         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
12082                         0x02, 0x00);
12083         clear_bit(AUDIO_NOMINAL, &tasha->status_mask);
12084         tasha_codec_update_sido_voltage(tasha, sido_buck_svs_voltage);
12085         wcd9xxx_set_power_state(tasha->wcd9xxx, WCD_REGION_POWER_DOWN,
12086                                 WCD9XXX_DIG_CORE_REGION_1);
12087 exit:
12088         dev_dbg(codec->dev, "%s: Exiting power gating function, %d\n",
12089                 __func__, tasha->power_active_ref);
12090         mutex_unlock(&tasha->power_lock);
12091 }
12092
12093 static void tasha_codec_power_gate_work(struct work_struct *work)
12094 {
12095         struct tasha_priv *tasha;
12096         struct delayed_work *dwork;
12097         struct snd_soc_codec *codec;
12098
12099         dwork = to_delayed_work(work);
12100         tasha = container_of(dwork, struct tasha_priv, power_gate_work);
12101         codec = tasha->codec;
12102
12103         if (!codec)
12104                 return;
12105
12106         tasha_codec_power_gate_digital_core(tasha);
12107 }
12108
12109 /* called under power_lock acquisition */
12110 static int tasha_dig_core_remove_power_collapse(struct snd_soc_codec *codec)
12111 {
12112         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12113
12114         tasha_codec_vote_max_bw(codec, true);
12115         snd_soc_write(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
12116         snd_soc_write(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
12117         snd_soc_write(codec, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
12118         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_RST_CTL, 0x02, 0x00);
12119         snd_soc_update_bits(codec, WCD9335_CODEC_RPM_RST_CTL, 0x02, 0x02);
12120
12121         wcd9xxx_set_power_state(tasha->wcd9xxx,
12122                         WCD_REGION_POWER_COLLAPSE_REMOVE,
12123                         WCD9XXX_DIG_CORE_REGION_1);
12124         regcache_mark_dirty(codec->component.regmap);
12125         regcache_sync_region(codec->component.regmap,
12126                              TASHA_DIG_CORE_REG_MIN, TASHA_DIG_CORE_REG_MAX);
12127         tasha_codec_vote_max_bw(codec, false);
12128
12129         return 0;
12130 }
12131
12132 static int tasha_dig_core_power_collapse(struct tasha_priv *tasha,
12133                                          int req_state)
12134 {
12135         struct snd_soc_codec *codec;
12136         int cur_state;
12137
12138         /* Exit if feature is disabled */
12139         if (!dig_core_collapse_enable)
12140                 return 0;
12141
12142         mutex_lock(&tasha->power_lock);
12143         if (req_state == POWER_COLLAPSE)
12144                 tasha->power_active_ref--;
12145         else if (req_state == POWER_RESUME)
12146                 tasha->power_active_ref++;
12147         else
12148                 goto unlock_mutex;
12149
12150         if (tasha->power_active_ref < 0) {
12151                 dev_info(tasha->dev,
12152                         "%s: power_active_ref is negative, resetting it\n",
12153                         __func__);
12154                 tasha->power_active_ref = 0;
12155                 goto unlock_mutex;
12156         }
12157
12158         codec = tasha->codec;
12159         if (!codec)
12160                 goto unlock_mutex;
12161
12162         if (req_state == POWER_COLLAPSE) {
12163                 if (tasha->power_active_ref == 0) {
12164                         queue_delayed_work(system_power_efficient_wq, &tasha->power_gate_work,
12165                         msecs_to_jiffies(dig_core_collapse_timer * 1000));
12166                 }
12167         } else if (req_state == POWER_RESUME) {
12168                 if (tasha->power_active_ref == 1) {
12169                         /*
12170                          * At this point, there can be two cases:
12171                          * 1. Core already in power collapse state
12172                          * 2. Timer kicked in and still did not expire or
12173                          * waiting for the power_lock
12174                          */
12175                         cur_state = wcd9xxx_get_current_power_state(
12176                                                 tasha->wcd9xxx,
12177                                                 WCD9XXX_DIG_CORE_REGION_1);
12178                         if (cur_state == WCD_REGION_POWER_DOWN)
12179                                 tasha_dig_core_remove_power_collapse(codec);
12180                         else {
12181                                 mutex_unlock(&tasha->power_lock);
12182                                 cancel_delayed_work_sync(
12183                                                 &tasha->power_gate_work);
12184                                 mutex_lock(&tasha->power_lock);
12185                         }
12186                 }
12187         }
12188
12189 unlock_mutex:
12190         mutex_unlock(&tasha->power_lock);
12191
12192         return 0;
12193 }
12194
12195 static int __tasha_cdc_mclk_enable_locked(struct tasha_priv *tasha,
12196                                           bool enable)
12197 {
12198         int ret = 0;
12199
12200         if (!tasha->wcd_ext_clk) {
12201                 dev_err(tasha->dev, "%s: wcd ext clock is NULL\n", __func__);
12202                 return -EINVAL;
12203         }
12204
12205         dev_dbg(tasha->dev, "%s: mclk_enable = %u\n", __func__, enable);
12206
12207         if (enable) {
12208                 tasha_dig_core_power_collapse(tasha, POWER_RESUME);
12209                 ret = tasha_cdc_req_mclk_enable(tasha, true);
12210                 if (ret)
12211                         goto err;
12212
12213                 set_bit(AUDIO_NOMINAL, &tasha->status_mask);
12214                 tasha_codec_apply_sido_voltage(tasha,
12215                                 SIDO_VOLTAGE_NOMINAL_MV);
12216         } else {
12217                 if (!dig_core_collapse_enable) {
12218                         clear_bit(AUDIO_NOMINAL, &tasha->status_mask);
12219                         tasha_codec_update_sido_voltage(tasha,
12220                                                 sido_buck_svs_voltage);
12221                 }
12222                 tasha_cdc_req_mclk_enable(tasha, false);
12223                 tasha_dig_core_power_collapse(tasha, POWER_COLLAPSE);
12224         }
12225
12226 err:
12227         return ret;
12228 }
12229
12230 static int __tasha_cdc_mclk_enable(struct tasha_priv *tasha,
12231                                    bool enable)
12232 {
12233         int ret;
12234
12235         WCD9XXX_V2_BG_CLK_LOCK(tasha->resmgr);
12236         ret = __tasha_cdc_mclk_enable_locked(tasha, enable);
12237         WCD9XXX_V2_BG_CLK_UNLOCK(tasha->resmgr);
12238
12239         return ret;
12240 }
12241
12242 int tasha_cdc_mclk_enable(struct snd_soc_codec *codec, int enable, bool dapm)
12243 {
12244         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12245
12246         return __tasha_cdc_mclk_enable(tasha, enable);
12247 }
12248 EXPORT_SYMBOL(tasha_cdc_mclk_enable);
12249
12250 int tasha_cdc_mclk_tx_enable(struct snd_soc_codec *codec, int enable, bool dapm)
12251 {
12252         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12253         int ret = 0;
12254
12255         dev_dbg(tasha->dev, "%s: clk_mode: %d, enable: %d, clk_internal: %d\n",
12256                 __func__, tasha->clk_mode, enable, tasha->clk_internal);
12257         if (tasha->clk_mode || tasha->clk_internal) {
12258                 if (enable) {
12259                         tasha_cdc_sido_ccl_enable(tasha, true);
12260                         wcd_resmgr_enable_master_bias(tasha->resmgr);
12261                         tasha_dig_core_power_collapse(tasha, POWER_RESUME);
12262                         snd_soc_update_bits(codec,
12263                                         WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
12264                                         0x01, 0x01);
12265                         snd_soc_update_bits(codec,
12266                                         WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
12267                                         0x01, 0x01);
12268                         set_bit(CPE_NOMINAL, &tasha->status_mask);
12269                         tasha_codec_update_sido_voltage(tasha,
12270                                                 SIDO_VOLTAGE_NOMINAL_MV);
12271                         tasha->clk_internal = true;
12272                 } else {
12273                         tasha->clk_internal = false;
12274                         clear_bit(CPE_NOMINAL, &tasha->status_mask);
12275                         tasha_codec_update_sido_voltage(tasha,
12276                                                 sido_buck_svs_voltage);
12277                         tasha_dig_core_power_collapse(tasha, POWER_COLLAPSE);
12278                         wcd_resmgr_disable_master_bias(tasha->resmgr);
12279                         tasha_cdc_sido_ccl_enable(tasha, false);
12280                 }
12281         } else {
12282                 ret = __tasha_cdc_mclk_enable(tasha, enable);
12283         }
12284         return ret;
12285 }
12286 EXPORT_SYMBOL(tasha_cdc_mclk_tx_enable);
12287
12288 static ssize_t tasha_codec_version_read(struct snd_info_entry *entry,
12289                                void *file_private_data, struct file *file,
12290                                char __user *buf, size_t count, loff_t pos)
12291 {
12292         struct tasha_priv *tasha;
12293         struct wcd9xxx *wcd9xxx;
12294         char buffer[TASHA_VERSION_ENTRY_SIZE];
12295         int len = 0;
12296
12297         tasha = (struct tasha_priv *) entry->private_data;
12298         if (!tasha) {
12299                 pr_err("%s: tasha priv is null\n", __func__);
12300                 return -EINVAL;
12301         }
12302
12303         wcd9xxx = tasha->wcd9xxx;
12304
12305         if (wcd9xxx->codec_type->id_major == TASHA_MAJOR) {
12306                 if (TASHA_IS_1_0(wcd9xxx))
12307                         len = snprintf(buffer, sizeof(buffer), "WCD9335_1_0\n");
12308                 else if (TASHA_IS_1_1(wcd9xxx))
12309                         len = snprintf(buffer, sizeof(buffer), "WCD9335_1_1\n");
12310                 else
12311                         snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
12312         } else if (wcd9xxx->codec_type->id_major == TASHA2P0_MAJOR) {
12313                         len = snprintf(buffer, sizeof(buffer), "WCD9335_2_0\n");
12314         } else
12315                 len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
12316
12317         return simple_read_from_buffer(buf, count, &pos, buffer, len);
12318 }
12319
12320 static struct snd_info_entry_ops tasha_codec_info_ops = {
12321         .read = tasha_codec_version_read,
12322 };
12323
12324 /*
12325  * tasha_codec_info_create_codec_entry - creates wcd9335 module
12326  * @codec_root: The parent directory
12327  * @codec: Codec instance
12328  *
12329  * Creates wcd9335 module and version entry under the given
12330  * parent directory.
12331  *
12332  * Return: 0 on success or negative error code on failure.
12333  */
12334 int tasha_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
12335                                         struct snd_soc_codec *codec)
12336 {
12337         struct snd_info_entry *version_entry;
12338         struct tasha_priv *tasha;
12339         struct snd_soc_card *card;
12340
12341         if (!codec_root || !codec)
12342                 return -EINVAL;
12343
12344         tasha = snd_soc_codec_get_drvdata(codec);
12345         card = codec->component.card;
12346         tasha->entry = snd_register_module_info(codec_root->module,
12347                                                 "tasha",
12348                                                 codec_root);
12349         if (!tasha->entry) {
12350                 dev_dbg(codec->dev, "%s: failed to create wcd9335 entry\n",
12351                         __func__);
12352                 return -ENOMEM;
12353         }
12354
12355         version_entry = snd_info_create_card_entry(card->snd_card,
12356                                                    "version",
12357                                                    tasha->entry);
12358         if (!version_entry) {
12359                 dev_dbg(codec->dev, "%s: failed to create wcd9335 version entry\n",
12360                         __func__);
12361                 return -ENOMEM;
12362         }
12363
12364         version_entry->private_data = tasha;
12365         version_entry->size = TASHA_VERSION_ENTRY_SIZE;
12366         version_entry->content = SNDRV_INFO_CONTENT_DATA;
12367         version_entry->c.ops = &tasha_codec_info_ops;
12368
12369         if (snd_info_register(version_entry) < 0) {
12370                 snd_info_free_entry(version_entry);
12371                 return -ENOMEM;
12372         }
12373         tasha->version_entry = version_entry;
12374
12375         return 0;
12376 }
12377 EXPORT_SYMBOL(tasha_codec_info_create_codec_entry);
12378
12379 static int __tasha_codec_internal_rco_ctrl(
12380         struct snd_soc_codec *codec, bool enable)
12381 {
12382         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12383         int ret = 0;
12384
12385         if (enable) {
12386                 tasha_cdc_sido_ccl_enable(tasha, true);
12387                 if (wcd_resmgr_get_clk_type(tasha->resmgr) ==
12388                     WCD_CLK_RCO) {
12389                         ret = wcd_resmgr_enable_clk_block(tasha->resmgr,
12390                                                           WCD_CLK_RCO);
12391                 } else {
12392                         ret = tasha_cdc_req_mclk_enable(tasha, true);
12393                         ret |= wcd_resmgr_enable_clk_block(tasha->resmgr,
12394                                                            WCD_CLK_RCO);
12395                         ret |= tasha_cdc_req_mclk_enable(tasha, false);
12396                 }
12397
12398         } else {
12399                 ret = wcd_resmgr_disable_clk_block(tasha->resmgr,
12400                                                    WCD_CLK_RCO);
12401                 tasha_cdc_sido_ccl_enable(tasha, false);
12402         }
12403
12404         if (ret) {
12405                 dev_err(codec->dev, "%s: Error in %s RCO\n",
12406                         __func__, (enable ? "enabling" : "disabling"));
12407                 ret = -EINVAL;
12408         }
12409
12410         return ret;
12411 }
12412
12413 /*
12414  * tasha_codec_internal_rco_ctrl()
12415  * Make sure that the caller does not acquire
12416  * BG_CLK_LOCK.
12417  */
12418 static int tasha_codec_internal_rco_ctrl(struct snd_soc_codec *codec,
12419                                   bool enable)
12420 {
12421         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12422         int ret = 0;
12423
12424         WCD9XXX_V2_BG_CLK_LOCK(tasha->resmgr);
12425         ret = __tasha_codec_internal_rco_ctrl(codec, enable);
12426         WCD9XXX_V2_BG_CLK_UNLOCK(tasha->resmgr);
12427         return ret;
12428 }
12429
12430 /*
12431  * tasha_mbhc_hs_detect: starts mbhc insertion/removal functionality
12432  * @codec: handle to snd_soc_codec *
12433  * @mbhc_cfg: handle to mbhc configuration structure
12434  * return 0 if mbhc_start is success or error code in case of failure
12435  */
12436 int tasha_mbhc_hs_detect(struct snd_soc_codec *codec,
12437                          struct wcd_mbhc_config *mbhc_cfg)
12438 {
12439         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12440
12441         return wcd_mbhc_start(&tasha->mbhc, mbhc_cfg);
12442 }
12443 EXPORT_SYMBOL(tasha_mbhc_hs_detect);
12444
12445 /*
12446  * tasha_mbhc_hs_detect_exit: stop mbhc insertion/removal functionality
12447  * @codec: handle to snd_soc_codec *
12448  */
12449 void tasha_mbhc_hs_detect_exit(struct snd_soc_codec *codec)
12450 {
12451         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
12452
12453         wcd_mbhc_stop(&tasha->mbhc);
12454 }
12455 EXPORT_SYMBOL(tasha_mbhc_hs_detect_exit);
12456
12457 static int wcd9335_get_micb_vout_ctl_val(u32 micb_mv)
12458 {
12459         /* min micbias voltage is 1V and maximum is 2.85V */
12460         if (micb_mv < 1000 || micb_mv > 2850) {
12461                 pr_err("%s: unsupported micbias voltage\n", __func__);
12462                 return -EINVAL;
12463         }
12464
12465         return (micb_mv - 1000) / 50;
12466 }
12467
12468 static const struct tasha_reg_mask_val tasha_reg_update_reset_val_1_1[] = {
12469         {WCD9335_RCO_CTRL_2, 0xFF, 0x47},
12470         {WCD9335_FLYBACK_VNEG_DAC_CTRL_4, 0xFF, 0x60},
12471 };
12472
12473 static const struct tasha_reg_mask_val tasha_codec_reg_init_val_1_1[] = {
12474         {WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0xFF, 0x65},
12475         {WCD9335_FLYBACK_VNEG_DAC_CTRL_2, 0xFF, 0x52},
12476         {WCD9335_FLYBACK_VNEG_DAC_CTRL_3, 0xFF, 0xAF},
12477         {WCD9335_FLYBACK_VNEG_DAC_CTRL_4, 0xFF, 0x60},
12478         {WCD9335_FLYBACK_VNEG_CTRL_3, 0xFF, 0xF4},
12479         {WCD9335_FLYBACK_VNEG_CTRL_9, 0xFF, 0x40},
12480         {WCD9335_FLYBACK_VNEG_CTRL_2, 0xFF, 0x4F},
12481         {WCD9335_FLYBACK_EN, 0xFF, 0x6E},
12482         {WCD9335_CDC_RX2_RX_PATH_SEC0, 0xF8, 0xF8},
12483         {WCD9335_CDC_RX1_RX_PATH_SEC0, 0xF8, 0xF8},
12484 };
12485
12486 static const struct tasha_reg_mask_val tasha_codec_reg_init_val_1_0[] = {
12487         {WCD9335_FLYBACK_VNEG_CTRL_3, 0xFF, 0x54},
12488         {WCD9335_CDC_RX2_RX_PATH_SEC0, 0xFC, 0xFC},
12489         {WCD9335_CDC_RX1_RX_PATH_SEC0, 0xFC, 0xFC},
12490 };
12491
12492 static const struct tasha_reg_mask_val tasha_codec_reg_init_val_2_0[] = {
12493         {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
12494         {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
12495         {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
12496         {WCD9335_HPH_OCP_CTL, 0xFF, 0x7A},
12497         {WCD9335_HPH_L_TEST, 0x01, 0x01},
12498         {WCD9335_HPH_R_TEST, 0x01, 0x01},
12499         {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
12500         {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
12501         {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
12502         {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
12503         {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
12504         {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
12505         {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
12506         {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
12507         {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
12508         {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
12509         {WCD9335_DIFF_LO_CORE_OUT_PROG, 0xFC, 0xA0},
12510         {WCD9335_SE_LO_COM1, 0xFF, 0xC0},
12511         {WCD9335_CDC_RX3_RX_PATH_SEC0, 0xFC, 0xF4},
12512         {WCD9335_CDC_RX4_RX_PATH_SEC0, 0xFC, 0xF4},
12513         {WCD9335_CDC_RX5_RX_PATH_SEC0, 0xFC, 0xF8},
12514         {WCD9335_CDC_RX6_RX_PATH_SEC0, 0xFC, 0xF8},
12515 };
12516
12517 static const struct tasha_reg_mask_val tasha_codec_reg_defaults[] = {
12518         {WCD9335_CODEC_RPM_CLK_GATE, 0x03, 0x00},
12519         {WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x03, 0x01},
12520         {WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x04, 0x04},
12521 };
12522
12523 static const struct tasha_reg_mask_val tasha_codec_reg_i2c_defaults[] = {
12524         {WCD9335_ANA_CLK_TOP, 0x20, 0x20},
12525         {WCD9335_CODEC_RPM_CLK_GATE, 0x03, 0x01},
12526         {WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x03, 0x00},
12527         {WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x05, 0x05},
12528         {WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x01, 0x01},
12529         {WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x01, 0x01},
12530         {WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x01, 0x01},
12531         {WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x01, 0x01},
12532         {WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG, 0x05, 0x05},
12533         {WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG, 0x05, 0x05},
12534         {WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG, 0x05, 0x05},
12535         {WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG, 0x05, 0x05},
12536 };
12537
12538 static const struct tasha_reg_mask_val tasha_codec_reg_init_common_val[] = {
12539         /* Rbuckfly/R_EAR(32) */
12540         {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
12541         {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
12542         {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
12543         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
12544         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
12545         {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
12546         {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
12547         {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
12548         {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
12549         {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
12550         {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
12551         {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
12552         {WCD9335_EAR_CMBUFF, 0x08, 0x00},
12553         {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
12554         {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
12555         {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
12556         {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
12557         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
12558         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
12559         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
12560         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
12561         {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
12562         {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
12563         {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
12564         {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
12565         {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
12566         {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
12567         {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
12568         {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
12569         {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
12570         {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
12571         {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
12572         {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
12573         {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
12574         {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
12575         {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
12576         {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
12577         {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
12578         {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
12579         {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
12580 };
12581
12582 static const struct tasha_reg_mask_val tasha_codec_reg_init_1_x_val[] = {
12583         /* Enable TX HPF Filter & Linear Phase */
12584         {WCD9335_CDC_TX0_TX_PATH_CFG0, 0x11, 0x11},
12585         {WCD9335_CDC_TX1_TX_PATH_CFG0, 0x11, 0x11},
12586         {WCD9335_CDC_TX2_TX_PATH_CFG0, 0x11, 0x11},
12587         {WCD9335_CDC_TX3_TX_PATH_CFG0, 0x11, 0x11},
12588         {WCD9335_CDC_TX4_TX_PATH_CFG0, 0x11, 0x11},
12589         {WCD9335_CDC_TX5_TX_PATH_CFG0, 0x11, 0x11},
12590         {WCD9335_CDC_TX6_TX_PATH_CFG0, 0x11, 0x11},
12591         {WCD9335_CDC_TX7_TX_PATH_CFG0, 0x11, 0x11},
12592         {WCD9335_CDC_TX8_TX_PATH_CFG0, 0x11, 0x11},
12593         {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xF8, 0xF8},
12594         {WCD9335_CDC_RX0_RX_PATH_SEC1, 0x08, 0x08},
12595         {WCD9335_CDC_RX1_RX_PATH_SEC1, 0x08, 0x08},
12596         {WCD9335_CDC_RX2_RX_PATH_SEC1, 0x08, 0x08},
12597         {WCD9335_CDC_RX3_RX_PATH_SEC1, 0x08, 0x08},
12598         {WCD9335_CDC_RX4_RX_PATH_SEC1, 0x08, 0x08},
12599         {WCD9335_CDC_RX5_RX_PATH_SEC1, 0x08, 0x08},
12600         {WCD9335_CDC_RX6_RX_PATH_SEC1, 0x08, 0x08},
12601         {WCD9335_CDC_RX7_RX_PATH_SEC1, 0x08, 0x08},
12602         {WCD9335_CDC_RX8_RX_PATH_SEC1, 0x08, 0x08},
12603         {WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x08, 0x08},
12604         {WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x08, 0x08},
12605         {WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x08, 0x08},
12606         {WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x08, 0x08},
12607         {WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x08, 0x08},
12608         {WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x08, 0x08},
12609         {WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x08, 0x08},
12610         {WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x08, 0x08},
12611         {WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x08, 0x08},
12612         {WCD9335_CDC_TX0_TX_PATH_SEC2, 0x01, 0x01},
12613         {WCD9335_CDC_TX1_TX_PATH_SEC2, 0x01, 0x01},
12614         {WCD9335_CDC_TX2_TX_PATH_SEC2, 0x01, 0x01},
12615         {WCD9335_CDC_TX3_TX_PATH_SEC2, 0x01, 0x01},
12616         {WCD9335_CDC_TX4_TX_PATH_SEC2, 0x01, 0x01},
12617         {WCD9335_CDC_TX5_TX_PATH_SEC2, 0x01, 0x01},
12618         {WCD9335_CDC_TX6_TX_PATH_SEC2, 0x01, 0x01},
12619         {WCD9335_CDC_TX7_TX_PATH_SEC2, 0x01, 0x01},
12620         {WCD9335_CDC_TX8_TX_PATH_SEC2, 0x01, 0x01},
12621         {WCD9335_CDC_RX3_RX_PATH_SEC0, 0xF8, 0xF0},
12622         {WCD9335_CDC_RX4_RX_PATH_SEC0, 0xF8, 0xF0},
12623         {WCD9335_CDC_RX5_RX_PATH_SEC0, 0xF8, 0xF8},
12624         {WCD9335_CDC_RX6_RX_PATH_SEC0, 0xF8, 0xF8},
12625         {WCD9335_RX_OCP_COUNT, 0xFF, 0xFF},
12626         {WCD9335_HPH_OCP_CTL, 0xF0, 0x70},
12627         {WCD9335_CPE_SS_CPAR_CFG, 0xFF, 0x00},
12628         {WCD9335_FLYBACK_VNEG_CTRL_1, 0xFF, 0x63},
12629         {WCD9335_FLYBACK_VNEG_CTRL_4, 0xFF, 0x7F},
12630         {WCD9335_CLASSH_CTRL_VCL_1, 0xFF, 0x60},
12631         {WCD9335_CLASSH_CTRL_CCL_5, 0xFF, 0x40},
12632         {WCD9335_RX_TIMER_DIV, 0xFF, 0x32},
12633         {WCD9335_SE_LO_COM2, 0xFF, 0x01},
12634         {WCD9335_MBHC_ZDET_ANA_CTL, 0x0F, 0x07},
12635         {WCD9335_RX_BIAS_HPH_PA, 0xF0, 0x60},
12636         {WCD9335_HPH_RDAC_LDO_CTL, 0x88, 0x88},
12637         {WCD9335_HPH_L_EN, 0x20, 0x20},
12638         {WCD9335_HPH_R_EN, 0x20, 0x20},
12639         {WCD9335_DIFF_LO_CORE_OUT_PROG, 0xFC, 0xD8},
12640         {WCD9335_CDC_RX5_RX_PATH_SEC3, 0xBD, 0xBD},
12641         {WCD9335_CDC_RX6_RX_PATH_SEC3, 0xBD, 0xBD},
12642         {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
12643 };
12644
12645 static void tasha_update_reg_reset_values(struct snd_soc_codec *codec)
12646 {
12647         u32 i;
12648         struct wcd9xxx *tasha_core = dev_get_drvdata(codec->dev->parent);
12649
12650         if (TASHA_IS_1_1(tasha_core)) {
12651                 for (i = 0; i < ARRAY_SIZE(tasha_reg_update_reset_val_1_1);
12652                      i++)
12653                         snd_soc_write(codec,
12654                                       tasha_reg_update_reset_val_1_1[i].reg,
12655                                       tasha_reg_update_reset_val_1_1[i].val);
12656         }
12657 }
12658
12659 static void tasha_codec_init_reg(struct snd_soc_codec *codec)
12660 {
12661         u32 i;
12662         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
12663
12664         for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_init_common_val); i++)
12665                 snd_soc_update_bits(codec,
12666                                 tasha_codec_reg_init_common_val[i].reg,
12667                                 tasha_codec_reg_init_common_val[i].mask,
12668                                 tasha_codec_reg_init_common_val[i].val);
12669
12670         if (TASHA_IS_1_1(wcd9xxx) ||
12671             TASHA_IS_1_0(wcd9xxx))
12672                 for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_init_1_x_val); i++)
12673                         snd_soc_update_bits(codec,
12674                                         tasha_codec_reg_init_1_x_val[i].reg,
12675                                         tasha_codec_reg_init_1_x_val[i].mask,
12676                                         tasha_codec_reg_init_1_x_val[i].val);
12677
12678         if (TASHA_IS_1_1(wcd9xxx)) {
12679                 for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_init_val_1_1); i++)
12680                         snd_soc_update_bits(codec,
12681                                         tasha_codec_reg_init_val_1_1[i].reg,
12682                                         tasha_codec_reg_init_val_1_1[i].mask,
12683                                         tasha_codec_reg_init_val_1_1[i].val);
12684         } else if (TASHA_IS_1_0(wcd9xxx)) {
12685                 for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_init_val_1_0); i++)
12686                         snd_soc_update_bits(codec,
12687                                         tasha_codec_reg_init_val_1_0[i].reg,
12688                                         tasha_codec_reg_init_val_1_0[i].mask,
12689                                         tasha_codec_reg_init_val_1_0[i].val);
12690         } else if (TASHA_IS_2_0(wcd9xxx)) {
12691                 for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_init_val_2_0); i++)
12692                         snd_soc_update_bits(codec,
12693                                         tasha_codec_reg_init_val_2_0[i].reg,
12694                                         tasha_codec_reg_init_val_2_0[i].mask,
12695                                         tasha_codec_reg_init_val_2_0[i].val);
12696         }
12697 }
12698
12699 static void tasha_update_reg_defaults(struct tasha_priv *tasha)
12700 {
12701         u32 i;
12702         struct wcd9xxx *wcd9xxx;
12703
12704         wcd9xxx = tasha->wcd9xxx;
12705         for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_defaults); i++)
12706                 regmap_update_bits(wcd9xxx->regmap,
12707                                    tasha_codec_reg_defaults[i].reg,
12708                                    tasha_codec_reg_defaults[i].mask,
12709                                    tasha_codec_reg_defaults[i].val);
12710
12711         tasha->intf_type = wcd9xxx_get_intf_type();
12712         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
12713                 for (i = 0; i < ARRAY_SIZE(tasha_codec_reg_i2c_defaults); i++)
12714                         regmap_update_bits(wcd9xxx->regmap,
12715                                            tasha_codec_reg_i2c_defaults[i].reg,
12716                                            tasha_codec_reg_i2c_defaults[i].mask,
12717                                            tasha_codec_reg_i2c_defaults[i].val);
12718
12719         return;
12720 }
12721
12722 static void tasha_slim_interface_init_reg(struct snd_soc_codec *codec)
12723 {
12724         int i;
12725         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
12726
12727         for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++)
12728                 wcd9xxx_interface_reg_write(priv->wcd9xxx,
12729                                             TASHA_SLIM_PGD_PORT_INT_EN0 + i,
12730                                             0xFF);
12731 }
12732
12733 static irqreturn_t tasha_slimbus_irq(int irq, void *data)
12734 {
12735         struct tasha_priv *priv = data;
12736         unsigned long status = 0;
12737         int i, j, port_id, k;
12738         u32 bit;
12739         u8 val, int_val = 0;
12740         bool tx, cleared;
12741         unsigned short reg = 0;
12742
12743         for (i = TASHA_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
12744              i <= TASHA_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
12745                 val = wcd9xxx_interface_reg_read(priv->wcd9xxx, i);
12746                 status |= ((u32)val << (8 * j));
12747         }
12748
12749         for_each_set_bit(j, &status, 32) {
12750                 tx = (j >= 16 ? true : false);
12751                 port_id = (tx ? j - 16 : j);
12752                 val = wcd9xxx_interface_reg_read(priv->wcd9xxx,
12753                                 TASHA_SLIM_PGD_PORT_INT_RX_SOURCE0 + j);
12754                 if (val) {
12755                         if (!tx)
12756                                 reg = TASHA_SLIM_PGD_PORT_INT_EN0 +
12757                                         (port_id / 8);
12758                         else
12759                                 reg = TASHA_SLIM_PGD_PORT_INT_TX_EN0 +
12760                                         (port_id / 8);
12761                         int_val = wcd9xxx_interface_reg_read(
12762                                 priv->wcd9xxx, reg);
12763                         /*
12764                          * Ignore interrupts for ports for which the
12765                          * interrupts are not specifically enabled.
12766                          */
12767                         if (!(int_val & (1 << (port_id % 8))))
12768                                 continue;
12769                 }
12770                 if (val & TASHA_SLIM_IRQ_OVERFLOW)
12771                         pr_err_ratelimited(
12772                            "%s: overflow error on %s port %d, value %x\n",
12773                            __func__, (tx ? "TX" : "RX"), port_id, val);
12774                 if (val & TASHA_SLIM_IRQ_UNDERFLOW)
12775                         pr_err_ratelimited(
12776                            "%s: underflow error on %s port %d, value %x\n",
12777                            __func__, (tx ? "TX" : "RX"), port_id, val);
12778                 if ((val & TASHA_SLIM_IRQ_OVERFLOW) ||
12779                         (val & TASHA_SLIM_IRQ_UNDERFLOW)) {
12780                         if (!tx)
12781                                 reg = TASHA_SLIM_PGD_PORT_INT_EN0 +
12782                                         (port_id / 8);
12783                         else
12784                                 reg = TASHA_SLIM_PGD_PORT_INT_TX_EN0 +
12785                                         (port_id / 8);
12786                         int_val = wcd9xxx_interface_reg_read(
12787                                 priv->wcd9xxx, reg);
12788                         if (int_val & (1 << (port_id % 8))) {
12789                                 int_val = int_val ^ (1 << (port_id % 8));
12790                                 wcd9xxx_interface_reg_write(priv->wcd9xxx,
12791                                         reg, int_val);
12792                         }
12793                 }
12794                 if (val & TASHA_SLIM_IRQ_PORT_CLOSED) {
12795                         /*
12796                          * INT SOURCE register starts from RX to TX
12797                          * but port number in the ch_mask is in opposite way
12798                          */
12799                         bit = (tx ? j - 16 : j + 16);
12800                         pr_debug("%s: %s port %d closed value %x, bit %u\n",
12801                                  __func__, (tx ? "TX" : "RX"), port_id, val,
12802                                  bit);
12803                         for (k = 0, cleared = false; k < NUM_CODEC_DAIS; k++) {
12804                                 pr_debug("%s: priv->dai[%d].ch_mask = 0x%lx\n",
12805                                          __func__, k, priv->dai[k].ch_mask);
12806                                 if (test_and_clear_bit(bit,
12807                                                        &priv->dai[k].ch_mask)) {
12808                                         cleared = true;
12809                                         if (!priv->dai[k].ch_mask)
12810                                                 wake_up(&priv->dai[k].dai_wait);
12811                                         /*
12812                                          * There are cases when multiple DAIs
12813                                          * might be using the same slimbus
12814                                          * channel. Hence don't break here.
12815                                          */
12816                                 }
12817                         }
12818                         WARN(!cleared,
12819                              "Couldn't find slimbus %s port %d for closing\n",
12820                              (tx ? "TX" : "RX"), port_id);
12821                 }
12822                 wcd9xxx_interface_reg_write(priv->wcd9xxx,
12823                                             TASHA_SLIM_PGD_PORT_INT_CLR_RX_0 +
12824                                             (j / 8),
12825                                             1 << (j % 8));
12826         }
12827
12828         return IRQ_HANDLED;
12829 }
12830
12831 static int tasha_setup_irqs(struct tasha_priv *tasha)
12832 {
12833         int ret = 0;
12834         struct snd_soc_codec *codec = tasha->codec;
12835         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
12836         struct wcd9xxx_core_resource *core_res =
12837                                 &wcd9xxx->core_res;
12838
12839         ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_SLIMBUS,
12840                                   tasha_slimbus_irq, "SLIMBUS Slave", tasha);
12841         if (ret)
12842                 pr_err("%s: Failed to request irq %d\n", __func__,
12843                        WCD9XXX_IRQ_SLIMBUS);
12844         else
12845                 tasha_slim_interface_init_reg(codec);
12846
12847         return ret;
12848 }
12849
12850 static void tasha_init_slim_slave_cfg(struct snd_soc_codec *codec)
12851 {
12852         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
12853         struct afe_param_cdc_slimbus_slave_cfg *cfg;
12854         struct wcd9xxx *wcd9xxx = priv->wcd9xxx;
12855         uint64_t eaddr = 0;
12856
12857         cfg = &priv->slimbus_slave_cfg;
12858         cfg->minor_version = 1;
12859         cfg->tx_slave_port_offset = 0;
12860         cfg->rx_slave_port_offset = 16;
12861
12862         memcpy(&eaddr, &wcd9xxx->slim->e_addr, sizeof(wcd9xxx->slim->e_addr));
12863         WARN_ON(sizeof(wcd9xxx->slim->e_addr) != 6);
12864         cfg->device_enum_addr_lsw = eaddr & 0xFFFFFFFF;
12865         cfg->device_enum_addr_msw = eaddr >> 32;
12866
12867         dev_dbg(codec->dev, "%s: slimbus logical address 0x%llx\n",
12868                 __func__, eaddr);
12869 }
12870
12871 static void tasha_cleanup_irqs(struct tasha_priv *tasha)
12872 {
12873         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
12874         struct wcd9xxx_core_resource *core_res =
12875                                 &wcd9xxx->core_res;
12876
12877         wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_SLIMBUS, tasha);
12878 }
12879
12880 static int tasha_handle_pdata(struct tasha_priv *tasha,
12881                               struct wcd9xxx_pdata *pdata)
12882 {
12883         struct snd_soc_codec *codec = tasha->codec;
12884         u8 dmic_ctl_val, mad_dmic_ctl_val;
12885         u8 anc_ctl_value;
12886         u32 def_dmic_rate, dmic_clk_drv;
12887         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
12888         int rc = 0;
12889
12890         if (!pdata) {
12891                 dev_err(codec->dev, "%s: NULL pdata\n", __func__);
12892                 return -ENODEV;
12893         }
12894
12895         /* set micbias voltage */
12896         vout_ctl_1 = wcd9335_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
12897         vout_ctl_2 = wcd9335_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
12898         vout_ctl_3 = wcd9335_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
12899         vout_ctl_4 = wcd9335_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
12900
12901         if (IS_ERR_VALUE(vout_ctl_1) || IS_ERR_VALUE(vout_ctl_2) ||
12902             IS_ERR_VALUE(vout_ctl_3) || IS_ERR_VALUE(vout_ctl_4)) {
12903                 rc = -EINVAL;
12904                 goto done;
12905         }
12906         snd_soc_update_bits(codec, WCD9335_ANA_MICB1, 0x3F, vout_ctl_1);
12907         snd_soc_update_bits(codec, WCD9335_ANA_MICB2, 0x3F, vout_ctl_2);
12908         snd_soc_update_bits(codec, WCD9335_ANA_MICB3, 0x3F, vout_ctl_3);
12909         snd_soc_update_bits(codec, WCD9335_ANA_MICB4, 0x3F, vout_ctl_4);
12910
12911         /* Set the DMIC sample rate */
12912         switch (pdata->mclk_rate) {
12913         case TASHA_MCLK_CLK_9P6MHZ:
12914                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
12915                 break;
12916         case TASHA_MCLK_CLK_12P288MHZ:
12917                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
12918                 break;
12919         default:
12920                 /* should never happen */
12921                 dev_err(codec->dev, "%s: Invalid mclk_rate %d\n",
12922                         __func__, pdata->mclk_rate);
12923                 rc = -EINVAL;
12924                 goto done;
12925         };
12926
12927         if (pdata->dmic_sample_rate ==
12928             WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED) {
12929                 dev_info(codec->dev, "%s: dmic_rate invalid default = %d\n",
12930                         __func__, def_dmic_rate);
12931                 pdata->dmic_sample_rate = def_dmic_rate;
12932         }
12933         if (pdata->mad_dmic_sample_rate ==
12934             WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED) {
12935                 dev_info(codec->dev, "%s: mad_dmic_rate invalid default = %d\n",
12936                         __func__, def_dmic_rate);
12937                 /*
12938                  * use dmic_sample_rate as the default for MAD
12939                  * if mad dmic sample rate is undefined
12940                  */
12941                 pdata->mad_dmic_sample_rate = pdata->dmic_sample_rate;
12942         }
12943         if (pdata->ecpp_dmic_sample_rate ==
12944             WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED) {
12945                 dev_info(codec->dev,
12946                          "%s: ecpp_dmic_rate invalid default = %d\n",
12947                          __func__, def_dmic_rate);
12948                 /*
12949                  * use dmic_sample_rate as the default for ECPP DMIC
12950                  * if ecpp dmic sample rate is undefined
12951                  */
12952                 pdata->ecpp_dmic_sample_rate = pdata->dmic_sample_rate;
12953         }
12954
12955         if (pdata->dmic_clk_drv ==
12956             WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED) {
12957                 pdata->dmic_clk_drv = WCD9335_DMIC_CLK_DRIVE_DEFAULT;
12958                 dev_info(codec->dev,
12959                          "%s: dmic_clk_strength invalid, default = %d\n",
12960                          __func__, pdata->dmic_clk_drv);
12961         }
12962
12963         switch (pdata->dmic_clk_drv) {
12964         case 2:
12965                 dmic_clk_drv = 0;
12966                 break;
12967         case 4:
12968                 dmic_clk_drv = 1;
12969                 break;
12970         case 8:
12971                 dmic_clk_drv = 2;
12972                 break;
12973         case 16:
12974                 dmic_clk_drv = 3;
12975                 break;
12976         default:
12977                 dev_err(codec->dev,
12978                         "%s: invalid dmic_clk_drv %d, using default\n",
12979                         __func__, pdata->dmic_clk_drv);
12980                 dmic_clk_drv = 0;
12981                 break;
12982         }
12983
12984         snd_soc_update_bits(codec, WCD9335_TEST_DEBUG_PAD_DRVCTL,
12985                             0x0C, dmic_clk_drv << 2);
12986
12987         /*
12988          * Default the DMIC clk rates to mad_dmic_sample_rate,
12989          * whereas, the anc/txfe dmic rates to dmic_sample_rate
12990          * since the anc/txfe are independent of mad block.
12991          */
12992         mad_dmic_ctl_val = tasha_get_dmic_clk_val(tasha->codec,
12993                                 pdata->mclk_rate,
12994                                 pdata->mad_dmic_sample_rate);
12995         snd_soc_update_bits(codec, WCD9335_CPE_SS_DMIC0_CTL,
12996                 0x0E, mad_dmic_ctl_val << 1);
12997         snd_soc_update_bits(codec, WCD9335_CPE_SS_DMIC1_CTL,
12998                 0x0E, mad_dmic_ctl_val << 1);
12999         snd_soc_update_bits(codec, WCD9335_CPE_SS_DMIC2_CTL,
13000                 0x0E, mad_dmic_ctl_val << 1);
13001
13002         dmic_ctl_val = tasha_get_dmic_clk_val(tasha->codec,
13003                                 pdata->mclk_rate,
13004                                 pdata->dmic_sample_rate);
13005
13006         if (dmic_ctl_val == WCD9335_DMIC_CLK_DIV_2)
13007                 anc_ctl_value = WCD9335_ANC_DMIC_X2_FULL_RATE;
13008         else
13009                 anc_ctl_value = WCD9335_ANC_DMIC_X2_HALF_RATE;
13010
13011         snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
13012                             0x40, anc_ctl_value << 6);
13013         snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
13014                             0x20, anc_ctl_value << 5);
13015         snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
13016                             0x40, anc_ctl_value << 6);
13017         snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
13018                             0x20, anc_ctl_value << 5);
13019 done:
13020         return rc;
13021 }
13022
13023 static struct wcd_cpe_core *tasha_codec_get_cpe_core(
13024                 struct snd_soc_codec *codec)
13025 {
13026         struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
13027         return priv->cpe_core;
13028 }
13029
13030 static int tasha_codec_cpe_fll_update_divider(
13031         struct snd_soc_codec *codec, u32 cpe_fll_rate)
13032 {
13033         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
13034         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13035         u32 div_val = 0, l_val = 0;
13036         u32 computed_cpe_fll;
13037
13038         if (cpe_fll_rate != CPE_FLL_CLK_75MHZ &&
13039             cpe_fll_rate != CPE_FLL_CLK_150MHZ) {
13040                 dev_err(codec->dev,
13041                         "%s: Invalid CPE fll rate request %u\n",
13042                         __func__, cpe_fll_rate);
13043                 return -EINVAL;
13044         }
13045
13046         if (wcd9xxx->mclk_rate == TASHA_MCLK_CLK_12P288MHZ) {
13047                 /* update divider to 10 and enable 5x divider */
13048                 snd_soc_write(codec, WCD9335_CPE_FLL_USER_CTL_1,
13049                               0x55);
13050                 div_val = 10;
13051         } else if (wcd9xxx->mclk_rate == TASHA_MCLK_CLK_9P6MHZ) {
13052                 /* update divider to 8 and enable 2x divider */
13053                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_USER_CTL_0,
13054                                     0x7C, 0x70);
13055                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_USER_CTL_1,
13056                                     0xE0, 0x20);
13057                 div_val = 8;
13058         } else {
13059                 dev_err(codec->dev,
13060                         "%s: Invalid MCLK rate %u\n",
13061                         __func__, wcd9xxx->mclk_rate);
13062                 return -EINVAL;
13063         }
13064
13065         l_val = ((cpe_fll_rate / 1000) * div_val) /
13066                  (wcd9xxx->mclk_rate / 1000);
13067
13068         /* If l_val was integer truncated, increment l_val once */
13069         computed_cpe_fll = (wcd9xxx->mclk_rate / div_val) * l_val;
13070         if (computed_cpe_fll < cpe_fll_rate)
13071                 l_val++;
13072
13073
13074         /* update L value LSB and MSB */
13075         snd_soc_write(codec, WCD9335_CPE_FLL_L_VAL_CTL_0,
13076                       (l_val & 0xFF));
13077         snd_soc_write(codec, WCD9335_CPE_FLL_L_VAL_CTL_1,
13078                       ((l_val >> 8) & 0xFF));
13079
13080         tasha->current_cpe_clk_freq = cpe_fll_rate;
13081         dev_dbg(codec->dev,
13082                 "%s: updated l_val to %u for cpe_clk %u and mclk %u\n",
13083                 __func__, l_val, cpe_fll_rate, wcd9xxx->mclk_rate);
13084
13085         return 0;
13086 }
13087
13088 static int __tasha_cdc_change_cpe_clk(struct snd_soc_codec *codec,
13089                 u32 clk_freq)
13090 {
13091         int ret = 0;
13092         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13093
13094         if (!tasha_cdc_is_svs_enabled(tasha)) {
13095                 dev_dbg(codec->dev,
13096                         "%s: SVS not enabled or tasha is not 2p0, return\n",
13097                         __func__);
13098                 return 0;
13099         }
13100         dev_dbg(codec->dev, "%s: clk_freq = %u\n", __func__, clk_freq);
13101
13102         if (clk_freq == CPE_FLL_CLK_75MHZ) {
13103                 /* Change to SVS */
13104                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13105                                     0x08, 0x08);
13106                 if (tasha_codec_cpe_fll_update_divider(codec, clk_freq)) {
13107                         ret = -EINVAL;
13108                         goto done;
13109                 }
13110
13111                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13112                                     0x10, 0x10);
13113
13114                 clear_bit(CPE_NOMINAL, &tasha->status_mask);
13115                 tasha_codec_update_sido_voltage(tasha, sido_buck_svs_voltage);
13116
13117         } else if (clk_freq == CPE_FLL_CLK_150MHZ) {
13118                 /* change to nominal */
13119                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13120                                     0x08, 0x08);
13121
13122                 set_bit(CPE_NOMINAL, &tasha->status_mask);
13123                 tasha_codec_update_sido_voltage(tasha, SIDO_VOLTAGE_NOMINAL_MV);
13124
13125                 if (tasha_codec_cpe_fll_update_divider(codec, clk_freq)) {
13126                         ret = -EINVAL;
13127                         goto done;
13128                 }
13129                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13130                                     0x10, 0x10);
13131         } else {
13132                 dev_err(codec->dev,
13133                         "%s: Invalid clk_freq request %d for CPE FLL\n",
13134                         __func__, clk_freq);
13135                 ret = -EINVAL;
13136         }
13137
13138 done:
13139         snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13140                             0x10, 0x00);
13141         snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13142                             0x08, 0x00);
13143         return ret;
13144 }
13145
13146
13147 static int tasha_codec_cpe_fll_enable(struct snd_soc_codec *codec,
13148                                    bool enable)
13149 {
13150         struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
13151         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13152         u8 clk_sel_reg_val = 0x00;
13153
13154         dev_dbg(codec->dev, "%s: enable = %s\n",
13155                         __func__, enable ? "true" : "false");
13156
13157         if (enable) {
13158                 if (tasha_cdc_is_svs_enabled(tasha)) {
13159                         /* FLL enable is always at SVS */
13160                         if (__tasha_cdc_change_cpe_clk(codec,
13161                                         CPE_FLL_CLK_75MHZ)) {
13162                                 dev_err(codec->dev,
13163                                         "%s: clk change to %d failed\n",
13164                                         __func__, CPE_FLL_CLK_75MHZ);
13165                                 return -EINVAL;
13166                         }
13167                 } else {
13168                         if (tasha_codec_cpe_fll_update_divider(codec,
13169                                                         CPE_FLL_CLK_75MHZ)) {
13170                                 dev_err(codec->dev,
13171                                         "%s: clk change to %d failed\n",
13172                                         __func__, CPE_FLL_CLK_75MHZ);
13173                                 return -EINVAL;
13174                         }
13175                 }
13176
13177                 if (TASHA_IS_1_0(wcd9xxx)) {
13178                         tasha_cdc_mclk_enable(codec, true, false);
13179                         clk_sel_reg_val = 0x02;
13180                 }
13181
13182                 /* Setup CPE reference clk */
13183                 snd_soc_update_bits(codec, WCD9335_ANA_CLK_TOP,
13184                                     0x02, clk_sel_reg_val);
13185
13186                 /* enable CPE FLL reference clk */
13187                 snd_soc_update_bits(codec, WCD9335_ANA_CLK_TOP,
13188                                     0x01, 0x01);
13189
13190                 /* program the PLL */
13191                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_USER_CTL_0,
13192                                     0x01, 0x01);
13193
13194                 /* TEST clk setting */
13195                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_TEST_CTL_0,
13196                                     0x80, 0x80);
13197                 /* set FLL mode to HW controlled */
13198                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13199                                     0x60, 0x00);
13200                 snd_soc_write(codec, WCD9335_CPE_FLL_FLL_MODE, 0x80);
13201         } else {
13202                 /* disable CPE FLL reference clk */
13203                 snd_soc_update_bits(codec, WCD9335_ANA_CLK_TOP,
13204                                     0x01, 0x00);
13205                 /* undo TEST clk setting */
13206                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_TEST_CTL_0,
13207                                     0x80, 0x00);
13208                 /* undo FLL mode to HW control */
13209                 snd_soc_write(codec, WCD9335_CPE_FLL_FLL_MODE, 0x00);
13210                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_FLL_MODE,
13211                                     0x60, 0x20);
13212                 /* undo the PLL */
13213                 snd_soc_update_bits(codec, WCD9335_CPE_FLL_USER_CTL_0,
13214                                     0x01, 0x00);
13215
13216                 if (TASHA_IS_1_0(wcd9xxx))
13217                         tasha_cdc_mclk_enable(codec, false, false);
13218
13219                 /*
13220                  * FLL could get disabled while at nominal,
13221                  * scale it back to SVS
13222                  */
13223                 if (tasha_cdc_is_svs_enabled(tasha))
13224                         __tasha_cdc_change_cpe_clk(codec,
13225                                                 CPE_FLL_CLK_75MHZ);
13226         }
13227
13228         return 0;
13229
13230 }
13231
13232 static void tasha_cdc_query_cpe_clk_plan(void *data,
13233                 struct cpe_svc_cfg_clk_plan *clk_freq)
13234 {
13235         struct snd_soc_codec *codec = data;
13236         struct tasha_priv *tasha;
13237         u32 cpe_clk_khz;
13238
13239         if (!codec) {
13240                 pr_err("%s: Invalid codec handle\n",
13241                         __func__);
13242                 return;
13243         }
13244
13245         tasha = snd_soc_codec_get_drvdata(codec);
13246         cpe_clk_khz = tasha->current_cpe_clk_freq / 1000;
13247
13248         dev_dbg(codec->dev,
13249                 "%s: current_clk_freq = %u\n",
13250                 __func__, tasha->current_cpe_clk_freq);
13251
13252         clk_freq->current_clk_feq = cpe_clk_khz;
13253         clk_freq->num_clk_freqs = 2;
13254
13255         if (tasha_cdc_is_svs_enabled(tasha)) {
13256                 clk_freq->clk_freqs[0] = CPE_FLL_CLK_75MHZ / 1000;
13257                 clk_freq->clk_freqs[1] = CPE_FLL_CLK_150MHZ / 1000;
13258         } else {
13259                 clk_freq->clk_freqs[0] = CPE_FLL_CLK_75MHZ;
13260                 clk_freq->clk_freqs[1] = CPE_FLL_CLK_150MHZ;
13261         }
13262 }
13263
13264 static void tasha_cdc_change_cpe_clk(void *data,
13265                 u32 clk_freq)
13266 {
13267         struct snd_soc_codec *codec = data;
13268         struct tasha_priv *tasha;
13269         u32 cpe_clk_khz, req_freq = 0;
13270
13271         if (!codec) {
13272                 pr_err("%s: Invalid codec handle\n",
13273                         __func__);
13274                 return;
13275         }
13276
13277         tasha = snd_soc_codec_get_drvdata(codec);
13278         cpe_clk_khz = tasha->current_cpe_clk_freq / 1000;
13279
13280         if (tasha_cdc_is_svs_enabled(tasha)) {
13281                 if ((clk_freq * 1000) <= CPE_FLL_CLK_75MHZ)
13282                         req_freq = CPE_FLL_CLK_75MHZ;
13283                 else
13284                         req_freq = CPE_FLL_CLK_150MHZ;
13285         }
13286
13287         dev_dbg(codec->dev,
13288                 "%s: requested clk_freq = %u, current clk_freq = %u\n",
13289                 __func__, clk_freq * 1000,
13290                 tasha->current_cpe_clk_freq);
13291
13292         if (tasha_cdc_is_svs_enabled(tasha)) {
13293                 if (__tasha_cdc_change_cpe_clk(codec, req_freq))
13294                         dev_err(codec->dev,
13295                                 "%s: clock/voltage scaling failed\n",
13296                                 __func__);
13297         }
13298 }
13299
13300 static int tasha_codec_slim_reserve_bw(struct snd_soc_codec *codec,
13301                 u32 bw_ops, bool commit)
13302 {
13303         struct wcd9xxx *wcd9xxx;
13304         if (!codec) {
13305                 pr_err("%s: Invalid handle to codec\n",
13306                         __func__);
13307                 return -EINVAL;
13308         }
13309
13310         wcd9xxx = dev_get_drvdata(codec->dev->parent);
13311
13312         if (!wcd9xxx) {
13313                 dev_err(codec->dev, "%s: Invalid parent drv_data\n",
13314                         __func__);
13315                 return -EINVAL;
13316         }
13317
13318         return wcd9xxx_slim_reserve_bw(wcd9xxx, bw_ops, commit);
13319 }
13320
13321 static int tasha_codec_vote_max_bw(struct snd_soc_codec *codec,
13322                         bool vote)
13323 {
13324         u32 bw_ops;
13325         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13326
13327         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
13328                 return 0;
13329
13330         mutex_lock(&tasha->sb_clk_gear_lock);
13331         if (vote) {
13332                 tasha->ref_count++;
13333                 if (tasha->ref_count == 1) {
13334                         bw_ops = SLIM_BW_CLK_GEAR_9;
13335                         tasha_codec_slim_reserve_bw(codec,
13336                                 bw_ops, true);
13337                 }
13338         } else if (!vote && tasha->ref_count > 0) {
13339                 tasha->ref_count--;
13340                 if (tasha->ref_count == 0) {
13341                         bw_ops = SLIM_BW_UNVOTE;
13342                         tasha_codec_slim_reserve_bw(codec,
13343                                 bw_ops, true);
13344                 }
13345         };
13346
13347         dev_dbg(codec->dev, "%s Value of counter after vote or un-vote is %d\n",
13348                 __func__, tasha->ref_count);
13349
13350         mutex_unlock(&tasha->sb_clk_gear_lock);
13351
13352         return 0;
13353 }
13354
13355 static int tasha_cpe_err_irq_control(struct snd_soc_codec *codec,
13356         enum cpe_err_irq_cntl_type cntl_type, u8 *status)
13357 {
13358         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13359         u8 irq_bits;
13360
13361         if (TASHA_IS_2_0(tasha->wcd9xxx))
13362                 irq_bits = 0xFF;
13363         else
13364                 irq_bits = 0x3F;
13365
13366         if (status)
13367                 irq_bits = (*status) & irq_bits;
13368
13369         switch (cntl_type) {
13370         case CPE_ERR_IRQ_MASK:
13371                 snd_soc_update_bits(codec,
13372                                     WCD9335_CPE_SS_SS_ERROR_INT_MASK,
13373                                     irq_bits, irq_bits);
13374                 break;
13375         case CPE_ERR_IRQ_UNMASK:
13376                 snd_soc_update_bits(codec,
13377                                     WCD9335_CPE_SS_SS_ERROR_INT_MASK,
13378                                     irq_bits, 0x00);
13379                 break;
13380         case CPE_ERR_IRQ_CLEAR:
13381                 snd_soc_write(codec, WCD9335_CPE_SS_SS_ERROR_INT_CLEAR,
13382                               irq_bits);
13383                 break;
13384         case CPE_ERR_IRQ_STATUS:
13385                 if (!status)
13386                         return -EINVAL;
13387                 *status = snd_soc_read(codec,
13388                                        WCD9335_CPE_SS_SS_ERROR_INT_STATUS);
13389                 break;
13390         }
13391
13392         return 0;
13393 }
13394
13395 static const struct wcd_cpe_cdc_cb cpe_cb = {
13396         .cdc_clk_en = tasha_codec_internal_rco_ctrl,
13397         .cpe_clk_en = tasha_codec_cpe_fll_enable,
13398         .get_afe_out_port_id = tasha_codec_get_mad_port_id,
13399         .lab_cdc_ch_ctl = tasha_codec_enable_slimtx_mad,
13400         .cdc_ext_clk = tasha_cdc_mclk_enable,
13401         .bus_vote_bw = tasha_codec_vote_max_bw,
13402         .cpe_err_irq_control = tasha_cpe_err_irq_control,
13403 };
13404
13405 static struct cpe_svc_init_param cpe_svc_params = {
13406         .version = CPE_SVC_INIT_PARAM_V1,
13407         .query_freq_plans_cb = tasha_cdc_query_cpe_clk_plan,
13408         .change_freq_plan_cb = tasha_cdc_change_cpe_clk,
13409 };
13410
13411 static int tasha_cpe_initialize(struct snd_soc_codec *codec)
13412 {
13413         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13414         struct wcd_cpe_params cpe_params;
13415
13416         memset(&cpe_params, 0,
13417                sizeof(struct wcd_cpe_params));
13418         cpe_params.codec = codec;
13419         cpe_params.get_cpe_core = tasha_codec_get_cpe_core;
13420         cpe_params.cdc_cb = &cpe_cb;
13421         cpe_params.dbg_mode = cpe_debug_mode;
13422         cpe_params.cdc_major_ver = CPE_SVC_CODEC_WCD9335;
13423         cpe_params.cdc_minor_ver = CPE_SVC_CODEC_V1P0;
13424         cpe_params.cdc_id = CPE_SVC_CODEC_WCD9335;
13425
13426         cpe_params.cdc_irq_info.cpe_engine_irq =
13427                         WCD9335_IRQ_SVA_OUTBOX1;
13428         cpe_params.cdc_irq_info.cpe_err_irq =
13429                         WCD9335_IRQ_SVA_ERROR;
13430         cpe_params.cdc_irq_info.cpe_fatal_irqs =
13431                         TASHA_CPE_FATAL_IRQS;
13432
13433         cpe_svc_params.context = codec;
13434         cpe_params.cpe_svc_params = &cpe_svc_params;
13435
13436         tasha->cpe_core = wcd_cpe_init("cpe_9335", codec,
13437                                         &cpe_params);
13438         if (IS_ERR_OR_NULL(tasha->cpe_core)) {
13439                 dev_err(codec->dev,
13440                         "%s: Failed to enable CPE\n",
13441                         __func__);
13442                 return -EINVAL;
13443         }
13444
13445         return 0;
13446 }
13447
13448 static const struct wcd_resmgr_cb tasha_resmgr_cb = {
13449         .cdc_rco_ctrl = __tasha_codec_internal_rco_ctrl,
13450 };
13451
13452 static int tasha_device_down(struct wcd9xxx *wcd9xxx)
13453 {
13454         struct snd_soc_codec *codec;
13455         struct tasha_priv *priv;
13456         int count;
13457         int i = 0;
13458
13459         codec = (struct snd_soc_codec *)(wcd9xxx->ssr_priv);
13460         priv = snd_soc_codec_get_drvdata(codec);
13461         wcd_cpe_ssr_event(priv->cpe_core, WCD_CPE_BUS_DOWN_EVENT);
13462         for (i = 0; i < priv->nr; i++)
13463                 swrm_wcd_notify(priv->swr_ctrl_data[i].swr_pdev,
13464                                 SWR_DEVICE_DOWN, NULL);
13465         snd_soc_card_change_online_state(codec->component.card, 0);
13466         for (count = 0; count < NUM_CODEC_DAIS; count++)
13467                 priv->dai[count].bus_down_in_recovery = true;
13468
13469         priv->resmgr->sido_input_src = SIDO_SOURCE_INTERNAL;
13470
13471         return 0;
13472 }
13473
13474 static int tasha_post_reset_cb(struct wcd9xxx *wcd9xxx)
13475 {
13476         int i, ret = 0;
13477         struct wcd9xxx *control;
13478         struct snd_soc_codec *codec;
13479         struct tasha_priv *tasha;
13480         struct wcd9xxx_pdata *pdata;
13481
13482         codec = (struct snd_soc_codec *)(wcd9xxx->ssr_priv);
13483         tasha = snd_soc_codec_get_drvdata(codec);
13484         control = dev_get_drvdata(codec->dev->parent);
13485
13486         wcd9xxx_set_power_state(tasha->wcd9xxx,
13487                                 WCD_REGION_POWER_COLLAPSE_REMOVE,
13488                                 WCD9XXX_DIG_CORE_REGION_1);
13489
13490         mutex_lock(&tasha->codec_mutex);
13491
13492         tasha_slimbus_slave_port_cfg.slave_dev_intfdev_la =
13493                 control->slim_slave->laddr;
13494         tasha_slimbus_slave_port_cfg.slave_dev_pgd_la =
13495                 control->slim->laddr;
13496         tasha_init_slim_slave_cfg(codec);
13497         if (tasha->machine_codec_event_cb)
13498                 tasha->machine_codec_event_cb(codec,
13499                                 WCD9335_CODEC_EVENT_CODEC_UP);
13500         snd_soc_card_change_online_state(codec->component.card, 1);
13501
13502         /* Class-H Init*/
13503         wcd_clsh_init(&tasha->clsh_d);
13504
13505         for (i = 0; i < TASHA_MAX_MICBIAS; i++)
13506                 tasha->micb_ref[i] = 0;
13507
13508         tasha_update_reg_defaults(tasha);
13509
13510         tasha->codec = codec;
13511
13512         dev_dbg(codec->dev, "%s: MCLK Rate = %x\n",
13513                 __func__, control->mclk_rate);
13514
13515         if (control->mclk_rate == TASHA_MCLK_CLK_12P288MHZ)
13516                 snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
13517                                     0x03, 0x00);
13518         else if (control->mclk_rate == TASHA_MCLK_CLK_9P6MHZ)
13519                 snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
13520                                     0x03, 0x01);
13521         tasha_codec_init_reg(codec);
13522
13523         wcd_resmgr_post_ssr_v2(tasha->resmgr);
13524
13525         tasha_enable_efuse_sensing(codec);
13526
13527         regcache_mark_dirty(codec->component.regmap);
13528         regcache_sync(codec->component.regmap);
13529
13530         pdata = dev_get_platdata(codec->dev->parent);
13531         ret = tasha_handle_pdata(tasha, pdata);
13532         if (IS_ERR_VALUE(ret))
13533                 dev_err(codec->dev, "%s: invalid pdata\n", __func__);
13534
13535         /* Reset reference counter for voting for max bw */
13536         tasha->ref_count = 0;
13537         /* MBHC Init */
13538         wcd_mbhc_deinit(&tasha->mbhc);
13539         tasha->mbhc_started = false;
13540
13541         /* Initialize MBHC module */
13542         ret = wcd_mbhc_init(&tasha->mbhc, codec, &mbhc_cb, &intr_ids,
13543                       wcd_mbhc_registers, TASHA_ZDET_SUPPORTED);
13544         if (ret)
13545                 dev_err(codec->dev, "%s: mbhc initialization failed\n",
13546                         __func__);
13547         else
13548                 tasha_mbhc_hs_detect(codec, tasha->mbhc.mbhc_cfg);
13549
13550         tasha_cleanup_irqs(tasha);
13551         ret = tasha_setup_irqs(tasha);
13552         if (ret) {
13553                 dev_err(codec->dev, "%s: tasha irq setup failed %d\n",
13554                         __func__, ret);
13555                 goto err;
13556         }
13557
13558         tasha_set_spkr_mode(codec, tasha->spkr_mode);
13559         wcd_cpe_ssr_event(tasha->cpe_core, WCD_CPE_BUS_UP_EVENT);
13560
13561 err:
13562         mutex_unlock(&tasha->codec_mutex);
13563         return ret;
13564 }
13565
13566 static struct regulator *tasha_codec_find_ondemand_regulator(
13567                 struct snd_soc_codec *codec, const char *name)
13568 {
13569         int i;
13570         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13571         struct wcd9xxx *wcd9xxx = tasha->wcd9xxx;
13572         struct wcd9xxx_pdata *pdata = dev_get_platdata(codec->dev->parent);
13573
13574         for (i = 0; i < wcd9xxx->num_of_supplies; ++i) {
13575                 if (pdata->regulator[i].ondemand &&
13576                         wcd9xxx->supplies[i].supply &&
13577                         !strcmp(wcd9xxx->supplies[i].supply, name))
13578                         return wcd9xxx->supplies[i].consumer;
13579         }
13580
13581         dev_dbg(tasha->dev, "Warning: regulator not found:%s\n",
13582                 name);
13583         return NULL;
13584 }
13585
13586 static int tasha_codec_probe(struct snd_soc_codec *codec)
13587 {
13588         struct wcd9xxx *control;
13589         struct tasha_priv *tasha;
13590         struct wcd9xxx_pdata *pdata;
13591         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
13592         int i, ret;
13593         void *ptr = NULL;
13594         struct regulator *supply;
13595
13596         control = dev_get_drvdata(codec->dev->parent);
13597
13598         dev_info(codec->dev, "%s()\n", __func__);
13599         tasha = snd_soc_codec_get_drvdata(codec);
13600         tasha->intf_type = wcd9xxx_get_intf_type();
13601
13602         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
13603                 control->dev_down = tasha_device_down;
13604                 control->post_reset = tasha_post_reset_cb;
13605                 control->ssr_priv = (void *)codec;
13606         }
13607
13608         /* Resource Manager post Init */
13609         ret = wcd_resmgr_post_init(tasha->resmgr, &tasha_resmgr_cb, codec);
13610         if (ret) {
13611                 dev_err(codec->dev, "%s: wcd resmgr post init failed\n",
13612                         __func__);
13613                 goto err;
13614         }
13615         /* Class-H Init*/
13616         wcd_clsh_init(&tasha->clsh_d);
13617         /* Default HPH Mode to Class-H HiFi */
13618         tasha->hph_mode = CLS_H_HIFI;
13619
13620         tasha->codec = codec;
13621         for (i = 0; i < COMPANDER_MAX; i++)
13622                 tasha->comp_enabled[i] = 0;
13623
13624         tasha->spkr_gain_offset = RX_GAIN_OFFSET_0_DB;
13625         tasha->intf_type = wcd9xxx_get_intf_type();
13626         tasha_update_reg_reset_values(codec);
13627         pr_debug("%s: MCLK Rate = %x\n", __func__, control->mclk_rate);
13628         if (control->mclk_rate == TASHA_MCLK_CLK_12P288MHZ)
13629                 snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
13630                                     0x03, 0x00);
13631         else if (control->mclk_rate == TASHA_MCLK_CLK_9P6MHZ)
13632                 snd_soc_update_bits(codec, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
13633                                     0x03, 0x01);
13634         tasha_codec_init_reg(codec);
13635
13636         tasha_enable_efuse_sensing(codec);
13637
13638         pdata = dev_get_platdata(codec->dev->parent);
13639         ret = tasha_handle_pdata(tasha, pdata);
13640         if (IS_ERR_VALUE(ret)) {
13641                 pr_err("%s: bad pdata\n", __func__);
13642                 goto err;
13643         }
13644
13645         supply = tasha_codec_find_ondemand_regulator(codec,
13646                 on_demand_supply_name[ON_DEMAND_MICBIAS]);
13647         if (supply) {
13648                 tasha->on_demand_list[ON_DEMAND_MICBIAS].supply = supply;
13649                 tasha->on_demand_list[ON_DEMAND_MICBIAS].ondemand_supply_count =
13650                                 0;
13651         }
13652
13653         tasha->fw_data = devm_kzalloc(codec->dev,
13654                                       sizeof(*(tasha->fw_data)), GFP_KERNEL);
13655         if (!tasha->fw_data) {
13656                 dev_err(codec->dev, "Failed to allocate fw_data\n");
13657                 goto err;
13658         }
13659         set_bit(WCD9XXX_ANC_CAL, tasha->fw_data->cal_bit);
13660         set_bit(WCD9XXX_MBHC_CAL, tasha->fw_data->cal_bit);
13661         set_bit(WCD9XXX_MAD_CAL, tasha->fw_data->cal_bit);
13662         set_bit(WCD9XXX_VBAT_CAL, tasha->fw_data->cal_bit);
13663
13664         ret = wcd_cal_create_hwdep(tasha->fw_data,
13665                                    WCD9XXX_CODEC_HWDEP_NODE, codec);
13666         if (ret < 0) {
13667                 dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret);
13668                 goto err_hwdep;
13669         }
13670
13671         /* Initialize MBHC module */
13672         if (TASHA_IS_2_0(tasha->wcd9xxx)) {
13673                 wcd_mbhc_registers[WCD_MBHC_FSM_STATUS].reg =
13674                         WCD9335_MBHC_FSM_STATUS;
13675                 wcd_mbhc_registers[WCD_MBHC_FSM_STATUS].mask = 0x01;
13676         }
13677         ret = wcd_mbhc_init(&tasha->mbhc, codec, &mbhc_cb, &intr_ids,
13678                       wcd_mbhc_registers, TASHA_ZDET_SUPPORTED);
13679         if (ret) {
13680                 pr_err("%s: mbhc initialization failed\n", __func__);
13681                 goto err_hwdep;
13682         }
13683
13684         ptr = devm_kzalloc(codec->dev, (sizeof(tasha_rx_chs) +
13685                            sizeof(tasha_tx_chs)), GFP_KERNEL);
13686         if (!ptr) {
13687                 pr_err("%s: no mem for slim chan ctl data\n", __func__);
13688                 ret = -ENOMEM;
13689                 goto err_hwdep;
13690         }
13691
13692         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
13693                 snd_soc_dapm_new_controls(dapm, tasha_dapm_i2s_widgets,
13694                         ARRAY_SIZE(tasha_dapm_i2s_widgets));
13695                 snd_soc_dapm_add_routes(dapm, audio_i2s_map,
13696                         ARRAY_SIZE(audio_i2s_map));
13697                 for (i = 0; i < ARRAY_SIZE(tasha_i2s_dai); i++) {
13698                         INIT_LIST_HEAD(&tasha->dai[i].wcd9xxx_ch_list);
13699                         init_waitqueue_head(&tasha->dai[i].dai_wait);
13700                 }
13701         } else if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
13702                 for (i = 0; i < NUM_CODEC_DAIS; i++) {
13703                         INIT_LIST_HEAD(&tasha->dai[i].wcd9xxx_ch_list);
13704                         init_waitqueue_head(&tasha->dai[i].dai_wait);
13705                 }
13706                 tasha_slimbus_slave_port_cfg.slave_dev_intfdev_la =
13707                                         control->slim_slave->laddr;
13708                 tasha_slimbus_slave_port_cfg.slave_dev_pgd_la =
13709                                         control->slim->laddr;
13710                 tasha_slimbus_slave_port_cfg.slave_port_mapping[0] =
13711                                         TASHA_TX13;
13712                 tasha_init_slim_slave_cfg(codec);
13713         }
13714
13715         snd_soc_add_codec_controls(codec, impedance_detect_controls,
13716                                    ARRAY_SIZE(impedance_detect_controls));
13717         snd_soc_add_codec_controls(codec, hph_type_detect_controls,
13718                                    ARRAY_SIZE(hph_type_detect_controls));
13719
13720         snd_soc_add_codec_controls(codec,
13721                         tasha_analog_gain_controls,
13722                         ARRAY_SIZE(tasha_analog_gain_controls));
13723         control->num_rx_port = TASHA_RX_MAX;
13724         control->rx_chs = ptr;
13725         memcpy(control->rx_chs, tasha_rx_chs, sizeof(tasha_rx_chs));
13726         control->num_tx_port = TASHA_TX_MAX;
13727         control->tx_chs = ptr + sizeof(tasha_rx_chs);
13728         memcpy(control->tx_chs, tasha_tx_chs, sizeof(tasha_tx_chs));
13729
13730         snd_soc_dapm_ignore_suspend(dapm, "AIF1 Playback");
13731         snd_soc_dapm_ignore_suspend(dapm, "AIF1 Capture");
13732         snd_soc_dapm_ignore_suspend(dapm, "AIF2 Playback");
13733         snd_soc_dapm_ignore_suspend(dapm, "AIF2 Capture");
13734
13735         if (tasha->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
13736                 snd_soc_dapm_ignore_suspend(dapm, "AIF3 Playback");
13737                 snd_soc_dapm_ignore_suspend(dapm, "AIF3 Capture");
13738                 snd_soc_dapm_ignore_suspend(dapm, "AIF4 Playback");
13739                 snd_soc_dapm_ignore_suspend(dapm, "AIF Mix Playback");
13740                 snd_soc_dapm_ignore_suspend(dapm, "AIF4 MAD TX");
13741                 snd_soc_dapm_ignore_suspend(dapm, "VIfeed");
13742                 snd_soc_dapm_ignore_suspend(dapm, "AIF5 CPE TX");
13743         }
13744
13745         snd_soc_dapm_sync(dapm);
13746
13747         ret = tasha_setup_irqs(tasha);
13748         if (ret) {
13749                 pr_err("%s: tasha irq setup failed %d\n", __func__, ret);
13750                 goto err_pdata;
13751         }
13752
13753         ret = tasha_cpe_initialize(codec);
13754         if (ret) {
13755                 dev_err(codec->dev,
13756                         "%s: cpe initialization failed, err = %d\n",
13757                         __func__, ret);
13758                 /* Do not fail probe if CPE failed */
13759                 ret = 0;
13760         }
13761
13762         for (i = 0; i < TASHA_NUM_DECIMATORS; i++) {
13763                 tasha->tx_hpf_work[i].tasha = tasha;
13764                 tasha->tx_hpf_work[i].decimator = i;
13765                 INIT_DELAYED_WORK(&tasha->tx_hpf_work[i].dwork,
13766                         tasha_tx_hpf_corner_freq_callback);
13767         }
13768
13769         for (i = 0; i < TASHA_NUM_DECIMATORS; i++) {
13770                 tasha->tx_mute_dwork[i].tasha = tasha;
13771                 tasha->tx_mute_dwork[i].decimator = i;
13772                 INIT_DELAYED_WORK(&tasha->tx_mute_dwork[i].dwork,
13773                           tasha_tx_mute_update_callback);
13774         }
13775
13776         tasha->spk_anc_dwork.tasha = tasha;
13777         INIT_DELAYED_WORK(&tasha->spk_anc_dwork.dwork,
13778                           tasha_spk_anc_update_callback);
13779
13780         mutex_lock(&tasha->codec_mutex);
13781         snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT1");
13782         snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT2");
13783         snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT1 PA");
13784         snd_soc_dapm_disable_pin(dapm, "ANC LINEOUT2 PA");
13785         snd_soc_dapm_disable_pin(dapm, "ANC HPHL");
13786         snd_soc_dapm_disable_pin(dapm, "ANC HPHR");
13787         snd_soc_dapm_disable_pin(dapm, "ANC HPHL PA");
13788         snd_soc_dapm_disable_pin(dapm, "ANC HPHR PA");
13789         snd_soc_dapm_disable_pin(dapm, "ANC EAR PA");
13790         snd_soc_dapm_disable_pin(dapm, "ANC EAR");
13791         snd_soc_dapm_disable_pin(dapm, "ANC SPK1 PA");
13792         mutex_unlock(&tasha->codec_mutex);
13793         snd_soc_dapm_sync(dapm);
13794
13795         return ret;
13796
13797 err_pdata:
13798         devm_kfree(codec->dev, ptr);
13799         control->rx_chs = NULL;
13800         control->tx_chs = NULL;
13801 err_hwdep:
13802         devm_kfree(codec->dev, tasha->fw_data);
13803         tasha->fw_data = NULL;
13804 err:
13805         return ret;
13806 }
13807
13808 static int tasha_codec_remove(struct snd_soc_codec *codec)
13809 {
13810         struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
13811         struct wcd9xxx *control;
13812
13813         control = dev_get_drvdata(codec->dev->parent);
13814         control->rx_chs = NULL;
13815         control->tx_chs = NULL;
13816
13817         tasha_cleanup_irqs(tasha);
13818         /* Cleanup MBHC */
13819         /* Cleanup resmgr */
13820
13821         return 0;
13822 }
13823
13824 static struct regmap *tasha_get_regmap(struct device *dev)
13825 {
13826         struct wcd9xxx *control = dev_get_drvdata(dev->parent);
13827
13828         return control->regmap;
13829 }
13830
13831 static struct snd_soc_codec_driver soc_codec_dev_tasha = {
13832         .probe = tasha_codec_probe,
13833         .remove = tasha_codec_remove,
13834         .controls = tasha_snd_controls,
13835         .num_controls = ARRAY_SIZE(tasha_snd_controls),
13836         .dapm_widgets = tasha_dapm_widgets,
13837         .num_dapm_widgets = ARRAY_SIZE(tasha_dapm_widgets),
13838         .dapm_routes = audio_map,
13839         .num_dapm_routes = ARRAY_SIZE(audio_map),
13840         .get_regmap = tasha_get_regmap,
13841 };
13842
13843 #ifdef CONFIG_PM
13844 static int tasha_suspend(struct device *dev)
13845 {
13846         struct platform_device *pdev = to_platform_device(dev);
13847         struct tasha_priv *tasha = platform_get_drvdata(pdev);
13848
13849         dev_dbg(dev, "%s: system suspend\n", __func__);
13850         if (cancel_delayed_work_sync(&tasha->power_gate_work))
13851                 tasha_codec_power_gate_digital_core(tasha);
13852
13853         return 0;
13854 }
13855
13856 static int tasha_resume(struct device *dev)
13857 {
13858         struct platform_device *pdev = to_platform_device(dev);
13859         struct tasha_priv *tasha = platform_get_drvdata(pdev);
13860
13861         if (!tasha) {
13862                 dev_err(dev, "%s: tasha private data is NULL\n", __func__);
13863                 return -EINVAL;
13864         }
13865         dev_dbg(dev, "%s: system resume\n", __func__);
13866         return 0;
13867 }
13868
13869 static const struct dev_pm_ops tasha_pm_ops = {
13870         .suspend = tasha_suspend,
13871         .resume = tasha_resume,
13872 };
13873 #endif
13874
13875 static int tasha_swrm_read(void *handle, int reg)
13876 {
13877         struct tasha_priv *tasha;
13878         struct wcd9xxx *wcd9xxx;
13879         unsigned short swr_rd_addr_base;
13880         unsigned short swr_rd_data_base;
13881         int val, ret;
13882
13883         if (!handle) {
13884                 pr_err("%s: NULL handle\n", __func__);
13885                 return -EINVAL;
13886         }
13887         tasha = (struct tasha_priv *)handle;
13888         wcd9xxx = tasha->wcd9xxx;
13889
13890         dev_dbg(tasha->dev, "%s: Reading soundwire register, 0x%x\n",
13891                 __func__, reg);
13892         swr_rd_addr_base = WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0;
13893         swr_rd_data_base = WCD9335_SWR_AHB_BRIDGE_RD_DATA_0;
13894         /* read_lock */
13895         mutex_lock(&tasha->swr_read_lock);
13896         ret = regmap_bulk_write(wcd9xxx->regmap, swr_rd_addr_base,
13897                                 (u8 *)&reg, 4);
13898         if (ret < 0) {
13899                 pr_err("%s: RD Addr Failure\n", __func__);
13900                 goto err;
13901         }
13902         /* Check for RD status */
13903         ret = regmap_bulk_read(wcd9xxx->regmap, swr_rd_data_base,
13904                                (u8 *)&val, 4);
13905         if (ret < 0) {
13906                 pr_err("%s: RD Data Failure\n", __func__);
13907                 goto err;
13908         }
13909         ret = val;
13910 err:
13911         /* read_unlock */
13912         mutex_unlock(&tasha->swr_read_lock);
13913         return ret;
13914 }
13915
13916 static int tasha_swrm_i2s_bulk_write(struct wcd9xxx *wcd9xxx,
13917                                 struct wcd9xxx_reg_val *bulk_reg,
13918                                 size_t len)
13919 {
13920         int i, ret = 0;
13921         unsigned short swr_wr_addr_base;
13922         unsigned short swr_wr_data_base;
13923
13924         swr_wr_addr_base = WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0;
13925         swr_wr_data_base = WCD9335_SWR_AHB_BRIDGE_WR_DATA_0;
13926
13927         for (i = 0; i < (len * 2); i += 2) {
13928                 /* First Write the Data to register */
13929                 ret = regmap_bulk_write(wcd9xxx->regmap,
13930                         swr_wr_data_base, bulk_reg[i].buf, 4);
13931                 if (ret < 0) {
13932                         dev_err(wcd9xxx->dev, "%s: WR Data Failure\n",
13933                                 __func__);
13934                         break;
13935                 }
13936                 /* Next Write Address */
13937                 ret = regmap_bulk_write(wcd9xxx->regmap,
13938                         swr_wr_addr_base, bulk_reg[i+1].buf, 4);
13939                 if (ret < 0) {
13940                         dev_err(wcd9xxx->dev, "%s: WR Addr Failure\n",
13941                                 __func__);
13942                         break;
13943                 }
13944         }
13945         return ret;
13946 }
13947
13948 static int tasha_swrm_bulk_write(void *handle, u32 *reg, u32 *val, size_t len)
13949 {
13950         struct tasha_priv *tasha;
13951         struct wcd9xxx *wcd9xxx;
13952         struct wcd9xxx_reg_val *bulk_reg;
13953         unsigned short swr_wr_addr_base;
13954         unsigned short swr_wr_data_base;
13955         int i, j, ret;
13956
13957         if (!handle) {
13958                 pr_err("%s: NULL handle\n", __func__);
13959                 return -EINVAL;
13960         }
13961         if (len <= 0) {
13962                 pr_err("%s: Invalid size: %zu\n", __func__, len);
13963                 return -EINVAL;
13964         }
13965         tasha = (struct tasha_priv *)handle;
13966         wcd9xxx = tasha->wcd9xxx;
13967
13968         swr_wr_addr_base = WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0;
13969         swr_wr_data_base = WCD9335_SWR_AHB_BRIDGE_WR_DATA_0;
13970
13971         bulk_reg = kzalloc((2 * len * sizeof(struct wcd9xxx_reg_val)),
13972                            GFP_KERNEL);
13973         if (!bulk_reg)
13974                 return -ENOMEM;
13975
13976         for (i = 0, j = 0; i < (len * 2); i += 2, j++) {
13977                 bulk_reg[i].reg = swr_wr_data_base;
13978                 bulk_reg[i].buf = (u8 *)(&val[j]);
13979                 bulk_reg[i].bytes = 4;
13980                 bulk_reg[i+1].reg = swr_wr_addr_base;
13981                 bulk_reg[i+1].buf = (u8 *)(&reg[j]);
13982                 bulk_reg[i+1].bytes = 4;
13983         }
13984         mutex_lock(&tasha->swr_write_lock);
13985
13986         if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C) {
13987                 ret = tasha_swrm_i2s_bulk_write(wcd9xxx, bulk_reg, len);
13988                 if (ret) {
13989                         dev_err(tasha->dev, "%s: i2s bulk write failed, ret: %d\n",
13990                                 __func__, ret);
13991                 }
13992         } else {
13993                 ret = wcd9xxx_slim_bulk_write(wcd9xxx, bulk_reg,
13994                                  (len * 2), false);
13995                 if (ret) {
13996                         dev_err(tasha->dev, "%s: swrm bulk write failed, ret: %d\n",
13997                                 __func__, ret);
13998                 }
13999         }
14000
14001         mutex_unlock(&tasha->swr_write_lock);
14002         kfree(bulk_reg);
14003
14004         return ret;
14005 }
14006
14007 static int tasha_swrm_write(void *handle, int reg, int val)
14008 {
14009         struct tasha_priv *tasha;
14010         struct wcd9xxx *wcd9xxx;
14011         unsigned short swr_wr_addr_base;
14012         unsigned short swr_wr_data_base;
14013         struct wcd9xxx_reg_val bulk_reg[2];
14014         int ret;
14015
14016         if (!handle) {
14017                 pr_err("%s: NULL handle\n", __func__);
14018                 return -EINVAL;
14019         }
14020         tasha = (struct tasha_priv *)handle;
14021         wcd9xxx = tasha->wcd9xxx;
14022
14023         swr_wr_addr_base = WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0;
14024         swr_wr_data_base = WCD9335_SWR_AHB_BRIDGE_WR_DATA_0;
14025
14026         /* First Write the Data to register */
14027         bulk_reg[0].reg = swr_wr_data_base;
14028         bulk_reg[0].buf = (u8 *)(&val);
14029         bulk_reg[0].bytes = 4;
14030         bulk_reg[1].reg = swr_wr_addr_base;
14031         bulk_reg[1].buf = (u8 *)(&reg);
14032         bulk_reg[1].bytes = 4;
14033
14034         mutex_lock(&tasha->swr_write_lock);
14035
14036         if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C) {
14037                 ret = tasha_swrm_i2s_bulk_write(wcd9xxx, bulk_reg, 1);
14038                 if (ret) {
14039                         dev_err(tasha->dev, "%s: i2s swrm write failed, ret: %d\n",
14040                                 __func__, ret);
14041                 }
14042         } else {
14043                 ret = wcd9xxx_slim_bulk_write(wcd9xxx, bulk_reg, 2, false);
14044                 if (ret < 0)
14045                         pr_err("%s: WR Data Failure\n", __func__);
14046         }
14047
14048         mutex_unlock(&tasha->swr_write_lock);
14049         return ret;
14050 }
14051
14052 static int tasha_swrm_clock(void *handle, bool enable)
14053 {
14054         struct tasha_priv *tasha = (struct tasha_priv *) handle;
14055
14056         mutex_lock(&tasha->swr_clk_lock);
14057
14058         dev_dbg(tasha->dev, "%s: swrm clock %s\n",
14059                 __func__, (enable?"enable" : "disable"));
14060         if (enable) {
14061                 tasha->swr_clk_users++;
14062                 if (tasha->swr_clk_users == 1) {
14063                         if (TASHA_IS_2_0(tasha->wcd9xxx))
14064                                 regmap_update_bits(
14065                                         tasha->wcd9xxx->regmap,
14066                                         WCD9335_TEST_DEBUG_NPL_DLY_TEST_1,
14067                                         0x10, 0x00);
14068                         __tasha_cdc_mclk_enable(tasha, true);
14069                         regmap_update_bits(tasha->wcd9xxx->regmap,
14070                                 WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL,
14071                                 0x01, 0x01);
14072                 }
14073         } else {
14074                 tasha->swr_clk_users--;
14075                 if (tasha->swr_clk_users == 0) {
14076                         regmap_update_bits(tasha->wcd9xxx->regmap,
14077                                 WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL,
14078                                 0x01, 0x00);
14079                         __tasha_cdc_mclk_enable(tasha, false);
14080                         if (TASHA_IS_2_0(tasha->wcd9xxx))
14081                                 regmap_update_bits(
14082                                         tasha->wcd9xxx->regmap,
14083                                         WCD9335_TEST_DEBUG_NPL_DLY_TEST_1,
14084                                         0x10, 0x10);
14085                 }
14086         }
14087         dev_dbg(tasha->dev, "%s: swrm clock users %d\n",
14088                 __func__, tasha->swr_clk_users);
14089         mutex_unlock(&tasha->swr_clk_lock);
14090         return 0;
14091 }
14092
14093 static int tasha_swrm_handle_irq(void *handle,
14094                                    irqreturn_t (*swrm_irq_handler)(int irq,
14095                                                                    void *data),
14096                                     void *swrm_handle,
14097                                     int action)
14098 {
14099         struct tasha_priv *tasha;
14100         int ret = 0;
14101         struct wcd9xxx *wcd9xxx;
14102
14103         if (!handle) {
14104                 pr_err("%s: null handle received\n", __func__);
14105                 return -EINVAL;
14106         }
14107         tasha = (struct tasha_priv *) handle;
14108         wcd9xxx = tasha->wcd9xxx;
14109
14110         if (action) {
14111                 ret = wcd9xxx_request_irq(&wcd9xxx->core_res,
14112                                           WCD9335_IRQ_SOUNDWIRE,
14113                                           swrm_irq_handler,
14114                                           "Tasha SWR Master", swrm_handle);
14115                 if (ret)
14116                         dev_err(tasha->dev, "%s: Failed to request irq %d\n",
14117                                 __func__, WCD9335_IRQ_SOUNDWIRE);
14118         } else
14119                 wcd9xxx_free_irq(&wcd9xxx->core_res, WCD9335_IRQ_SOUNDWIRE,
14120                                  swrm_handle);
14121
14122         return ret;
14123 }
14124
14125 static void tasha_add_child_devices(struct work_struct *work)
14126 {
14127         struct tasha_priv *tasha;
14128         struct platform_device *pdev;
14129         struct device_node *node;
14130         struct wcd9xxx *wcd9xxx;
14131         struct tasha_swr_ctrl_data *swr_ctrl_data = NULL, *temp;
14132         int ret, ctrl_num = 0;
14133         struct wcd_swr_ctrl_platform_data *platdata;
14134         char plat_dev_name[WCD9335_STRING_LEN];
14135
14136         tasha = container_of(work, struct tasha_priv,
14137                              tasha_add_child_devices_work);
14138         if (!tasha) {
14139                 pr_err("%s: Memory for WCD9335 does not exist\n",
14140                         __func__);
14141                 return;
14142         }
14143         wcd9xxx = tasha->wcd9xxx;
14144         if (!wcd9xxx) {
14145                 pr_err("%s: Memory for WCD9XXX does not exist\n",
14146                         __func__);
14147                 return;
14148         }
14149         if (!wcd9xxx->dev->of_node) {
14150                 pr_err("%s: DT node for wcd9xxx does not exist\n",
14151                         __func__);
14152                 return;
14153         }
14154
14155         platdata = &tasha->swr_plat_data;
14156
14157         for_each_child_of_node(wcd9xxx->dev->of_node, node) {
14158                 if (!strcmp(node->name, "swr_master"))
14159                         strlcpy(plat_dev_name, "tasha_swr_ctrl",
14160                                 (WCD9335_STRING_LEN - 1));
14161                 else if (strnstr(node->name, "msm_cdc_pinctrl",
14162                                  strlen("msm_cdc_pinctrl")) != NULL)
14163                         strlcpy(plat_dev_name, node->name,
14164                                 (WCD9335_STRING_LEN - 1));
14165                 else
14166                         continue;
14167
14168                 pdev = platform_device_alloc(plat_dev_name, -1);
14169                 if (!pdev) {
14170                         dev_err(wcd9xxx->dev, "%s: pdev memory alloc failed\n",
14171                                 __func__);
14172                         ret = -ENOMEM;
14173                         goto err;
14174                 }
14175                 pdev->dev.parent = tasha->dev;
14176                 pdev->dev.of_node = node;
14177
14178                 if (!strcmp(node->name, "swr_master")) {
14179                         ret = platform_device_add_data(pdev, platdata,
14180                                                        sizeof(*platdata));
14181                         if (ret) {
14182                                 dev_err(&pdev->dev,
14183                                         "%s: cannot add plat data ctrl:%d\n",
14184                                         __func__, ctrl_num);
14185                                 goto fail_pdev_add;
14186                         }
14187                 }
14188
14189                 ret = platform_device_add(pdev);
14190                 if (ret) {
14191                         dev_err(&pdev->dev,
14192                                 "%s: Cannot add platform device\n",
14193                                 __func__);
14194                         goto fail_pdev_add;
14195                 }
14196
14197                 if (!strcmp(node->name, "swr_master")) {
14198                         temp = krealloc(swr_ctrl_data,
14199                                         (ctrl_num + 1) * sizeof(
14200                                         struct tasha_swr_ctrl_data),
14201                                         GFP_KERNEL);
14202                         if (!temp) {
14203                                 dev_err(wcd9xxx->dev, "out of memory\n");
14204                                 ret = -ENOMEM;
14205                                 goto err;
14206                         }
14207                         swr_ctrl_data = temp;
14208                         swr_ctrl_data[ctrl_num].swr_pdev = pdev;
14209                         ctrl_num++;
14210                         dev_dbg(&pdev->dev,
14211                                 "%s: Added soundwire ctrl device(s)\n",
14212                                 __func__);
14213                         tasha->nr = ctrl_num;
14214                         tasha->swr_ctrl_data = swr_ctrl_data;
14215                 }
14216         }
14217
14218         return;
14219 fail_pdev_add:
14220         platform_device_put(pdev);
14221 err:
14222         return;
14223 }
14224
14225 /*
14226  * tasha_codec_ver: to get tasha codec version
14227  * @codec: handle to snd_soc_codec *
14228  * return enum codec_variant - version
14229  */
14230 enum codec_variant tasha_codec_ver(void)
14231 {
14232         return codec_ver;
14233 }
14234 EXPORT_SYMBOL(tasha_codec_ver);
14235
14236 static int __tasha_enable_efuse_sensing(struct tasha_priv *tasha)
14237 {
14238         int val, rc;
14239
14240         __tasha_cdc_mclk_enable(tasha, true);
14241
14242         regmap_update_bits(tasha->wcd9xxx->regmap,
14243                            WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x1E, 0x20);
14244         regmap_update_bits(tasha->wcd9xxx->regmap,
14245                            WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x01, 0x01);
14246
14247         /*
14248          * 5ms sleep required after enabling efuse control
14249          * before checking the status.
14250          */
14251         usleep_range(5000, 5500);
14252         rc = regmap_read(tasha->wcd9xxx->regmap,
14253                          WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
14254
14255         if (rc || (!(val & 0x01)))
14256                 WARN(1, "%s: Efuse sense is not complete\n", __func__);
14257
14258         __tasha_cdc_mclk_enable(tasha, false);
14259
14260         return rc;
14261 }
14262
14263 void tasha_get_codec_ver(struct tasha_priv *tasha)
14264 {
14265         int i;
14266         int val;
14267         struct tasha_reg_mask_val codec_reg[] = {
14268                 {WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10, 0xFF, 0xFF},
14269                 {WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11, 0xFF, 0x83},
14270                 {WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12, 0xFF, 0x0A},
14271         };
14272
14273         __tasha_enable_efuse_sensing(tasha);
14274         for (i = 0; i < ARRAY_SIZE(codec_reg); i++) {
14275                 regmap_read(tasha->wcd9xxx->regmap, codec_reg[i].reg, &val);
14276                 if (!(val && codec_reg[i].val)) {
14277                         codec_ver = WCD9335;
14278                         goto ret;
14279                 }
14280         }
14281         codec_ver = WCD9326;
14282 ret:
14283         pr_debug("%s: codec is %d\n", __func__, codec_ver);
14284 }
14285 EXPORT_SYMBOL(tasha_get_codec_ver);
14286
14287 static int tasha_probe(struct platform_device *pdev)
14288 {
14289         int ret = 0;
14290         struct tasha_priv *tasha;
14291         struct clk *wcd_ext_clk, *wcd_native_clk;
14292         struct wcd9xxx_resmgr_v2 *resmgr;
14293         struct wcd9xxx_power_region *cdc_pwr;
14294
14295         if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C) {
14296                 if (apr_get_subsys_state() == APR_SUBSYS_DOWN) {
14297                         dev_err(&pdev->dev, "%s: dsp down\n", __func__);
14298                         return -EPROBE_DEFER;
14299                 }
14300         }
14301
14302         tasha = devm_kzalloc(&pdev->dev, sizeof(struct tasha_priv),
14303                             GFP_KERNEL);
14304         if (!tasha) {
14305                 dev_err(&pdev->dev, "%s: cannot create memory for wcd9335\n",
14306                         __func__);
14307                 return -ENOMEM;
14308         }
14309         platform_set_drvdata(pdev, tasha);
14310
14311         tasha->wcd9xxx = dev_get_drvdata(pdev->dev.parent);
14312         tasha->dev = &pdev->dev;
14313         INIT_DELAYED_WORK(&tasha->power_gate_work, tasha_codec_power_gate_work);
14314         mutex_init(&tasha->power_lock);
14315         mutex_init(&tasha->sido_lock);
14316         INIT_WORK(&tasha->tasha_add_child_devices_work,
14317                   tasha_add_child_devices);
14318         BLOCKING_INIT_NOTIFIER_HEAD(&tasha->notifier);
14319         mutex_init(&tasha->micb_lock);
14320         mutex_init(&tasha->swr_read_lock);
14321         mutex_init(&tasha->swr_write_lock);
14322         mutex_init(&tasha->swr_clk_lock);
14323         mutex_init(&tasha->sb_clk_gear_lock);
14324         mutex_init(&tasha->mclk_lock);
14325
14326         cdc_pwr = devm_kzalloc(&pdev->dev, sizeof(struct wcd9xxx_power_region),
14327                                GFP_KERNEL);
14328         if (!cdc_pwr) {
14329                 ret = -ENOMEM;
14330                 goto err_cdc_pwr;
14331         }
14332         tasha->wcd9xxx->wcd9xxx_pwr[WCD9XXX_DIG_CORE_REGION_1] = cdc_pwr;
14333         cdc_pwr->pwr_collapse_reg_min = TASHA_DIG_CORE_REG_MIN;
14334         cdc_pwr->pwr_collapse_reg_max = TASHA_DIG_CORE_REG_MAX;
14335         wcd9xxx_set_power_state(tasha->wcd9xxx,
14336                                 WCD_REGION_POWER_COLLAPSE_REMOVE,
14337                                 WCD9XXX_DIG_CORE_REGION_1);
14338
14339         mutex_init(&tasha->codec_mutex);
14340         /*
14341          * Init resource manager so that if child nodes such as SoundWire
14342          * requests for clock, resource manager can honor the request
14343          */
14344         resmgr = wcd_resmgr_init(&tasha->wcd9xxx->core_res, NULL);
14345         if (IS_ERR(resmgr)) {
14346                 ret = PTR_ERR(resmgr);
14347                 dev_err(&pdev->dev, "%s: Failed to initialize wcd resmgr\n",
14348                         __func__);
14349                 goto err_resmgr;
14350         }
14351         tasha->resmgr = resmgr;
14352         tasha->swr_plat_data.handle = (void *) tasha;
14353         tasha->swr_plat_data.read = tasha_swrm_read;
14354         tasha->swr_plat_data.write = tasha_swrm_write;
14355         tasha->swr_plat_data.bulk_write = tasha_swrm_bulk_write;
14356         tasha->swr_plat_data.clk = tasha_swrm_clock;
14357         tasha->swr_plat_data.handle_irq = tasha_swrm_handle_irq;
14358
14359         /* Register for Clock */
14360         wcd_ext_clk = clk_get(tasha->wcd9xxx->dev, "wcd_clk");
14361         if (IS_ERR(wcd_ext_clk)) {
14362                 dev_err(tasha->wcd9xxx->dev, "%s: clk get %s failed\n",
14363                         __func__, "wcd_ext_clk");
14364                 goto err_clk;
14365         }
14366         tasha->wcd_ext_clk = wcd_ext_clk;
14367         tasha->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
14368         set_bit(AUDIO_NOMINAL, &tasha->status_mask);
14369         tasha->sido_ccl_cnt = 0;
14370
14371         /* Register native clk for 44.1 playback */
14372         wcd_native_clk = clk_get(tasha->wcd9xxx->dev, "wcd_native_clk");
14373         if (IS_ERR(wcd_native_clk))
14374                 dev_dbg(tasha->wcd9xxx->dev, "%s: clk get %s failed\n",
14375                         __func__, "wcd_native_clk");
14376         else
14377                 tasha->wcd_native_clk = wcd_native_clk;
14378
14379         if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
14380                 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tasha,
14381                                              tasha_dai, ARRAY_SIZE(tasha_dai));
14382         else if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
14383                 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tasha,
14384                                              tasha_i2s_dai,
14385                                              ARRAY_SIZE(tasha_i2s_dai));
14386         else
14387                 ret = -EINVAL;
14388         if (ret) {
14389                 dev_err(&pdev->dev, "%s: Codec registration failed, ret = %d\n",
14390                         __func__, ret);
14391                 goto err_cdc_reg;
14392         }
14393         /* Update codec register default values */
14394         tasha_update_reg_defaults(tasha);
14395         schedule_work(&tasha->tasha_add_child_devices_work);
14396         tasha_get_codec_ver(tasha);
14397
14398         dev_info(&pdev->dev, "%s: Tasha driver probe done\n", __func__);
14399         return ret;
14400
14401 err_cdc_reg:
14402         clk_put(tasha->wcd_ext_clk);
14403         if (tasha->wcd_native_clk)
14404                 clk_put(tasha->wcd_native_clk);
14405 err_clk:
14406         wcd_resmgr_remove(tasha->resmgr);
14407 err_resmgr:
14408         devm_kfree(&pdev->dev, cdc_pwr);
14409 err_cdc_pwr:
14410         mutex_destroy(&tasha->mclk_lock);
14411         devm_kfree(&pdev->dev, tasha);
14412         return ret;
14413 }
14414
14415 static int tasha_remove(struct platform_device *pdev)
14416 {
14417         struct tasha_priv *tasha;
14418
14419         tasha = platform_get_drvdata(pdev);
14420
14421         mutex_destroy(&tasha->codec_mutex);
14422         clk_put(tasha->wcd_ext_clk);
14423         if (tasha->wcd_native_clk)
14424                 clk_put(tasha->wcd_native_clk);
14425         mutex_destroy(&tasha->mclk_lock);
14426         devm_kfree(&pdev->dev, tasha);
14427         snd_soc_unregister_codec(&pdev->dev);
14428         mutex_destroy(&tasha->sb_clk_gear_lock);
14429         return 0;
14430 }
14431
14432 static struct platform_driver tasha_codec_driver = {
14433         .probe = tasha_probe,
14434         .remove = tasha_remove,
14435         .driver = {
14436                 .name = "tasha_codec",
14437                 .owner = THIS_MODULE,
14438 #ifdef CONFIG_PM
14439                 .pm = &tasha_pm_ops,
14440 #endif
14441         },
14442 };
14443
14444 module_platform_driver(tasha_codec_driver);
14445
14446 MODULE_DESCRIPTION("Tasha Codec driver");
14447 MODULE_LICENSE("GPL v2");