sound/soc/mediatek/mt8192/mt8192-dai-adda.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // MediaTek ALSA SoC Audio DAI ADDA Control
   4 //
   5 // Copyright (c) 2020 MediaTek Inc.
   6 // Author: Shane Chien <shane.chien@mediatek.com>
   7 //
   8
   9 #include <linux/delay.h>
  10 #include <linux/regmap.h>
  11
  12 #include "mt8192-afe-clk.h"
  13 #include "mt8192-afe-common.h"
  14 #include "mt8192-afe-gpio.h"
  15 #include "mt8192-interconnection.h"
  16
  17 enum {
  18         UL_IIR_SW = 0,
  19         UL_IIR_5HZ,
  20         UL_IIR_10HZ,
  21         UL_IIR_25HZ,
  22         UL_IIR_50HZ,
  23         UL_IIR_75HZ,
  24 };
  25
  26 enum {
  27         AUDIO_SDM_LEVEL_MUTE = 0,
  28         AUDIO_SDM_LEVEL_NORMAL = 0x1d,
  29         /* if you change level normal */
  30         /* you need to change formula of hp impedance and dc trim too */
  31 };
  32
  33 enum {
  34         AUDIO_SDM_2ND = 0,
  35         AUDIO_SDM_3RD,
  36 };
  37
  38 enum {
  39         DELAY_DATA_MISO1 = 0,
  40         DELAY_DATA_MISO2,
  41 };
  42
  43 enum {
  44         MTK_AFE_ADDA_DL_RATE_8K = 0,
  45         MTK_AFE_ADDA_DL_RATE_11K = 1,
  46         MTK_AFE_ADDA_DL_RATE_12K = 2,
  47         MTK_AFE_ADDA_DL_RATE_16K = 3,
  48         MTK_AFE_ADDA_DL_RATE_22K = 4,
  49         MTK_AFE_ADDA_DL_RATE_24K = 5,
  50         MTK_AFE_ADDA_DL_RATE_32K = 6,
  51         MTK_AFE_ADDA_DL_RATE_44K = 7,
  52         MTK_AFE_ADDA_DL_RATE_48K = 8,
  53         MTK_AFE_ADDA_DL_RATE_96K = 9,
  54         MTK_AFE_ADDA_DL_RATE_192K = 10,
  55 };
  56
  57 enum {
  58         MTK_AFE_ADDA_UL_RATE_8K = 0,
  59         MTK_AFE_ADDA_UL_RATE_16K = 1,
  60         MTK_AFE_ADDA_UL_RATE_32K = 2,
  61         MTK_AFE_ADDA_UL_RATE_48K = 3,
  62         MTK_AFE_ADDA_UL_RATE_96K = 4,
  63         MTK_AFE_ADDA_UL_RATE_192K = 5,
  64         MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
  65 };
  66
  67 #define SDM_AUTO_RESET_THRESHOLD 0x190000
  68
  69 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
  70                                            unsigned int rate)
  71 {
  72         switch (rate) {
  73         case 8000:
  74                 return MTK_AFE_ADDA_DL_RATE_8K;
  75         case 11025:
  76                 return MTK_AFE_ADDA_DL_RATE_11K;
  77         case 12000:
  78                 return MTK_AFE_ADDA_DL_RATE_12K;
  79         case 16000:
  80                 return MTK_AFE_ADDA_DL_RATE_16K;
  81         case 22050:
  82                 return MTK_AFE_ADDA_DL_RATE_22K;
  83         case 24000:
  84                 return MTK_AFE_ADDA_DL_RATE_24K;
  85         case 32000:
  86                 return MTK_AFE_ADDA_DL_RATE_32K;
  87         case 44100:
  88                 return MTK_AFE_ADDA_DL_RATE_44K;
  89         case 48000:
  90                 return MTK_AFE_ADDA_DL_RATE_48K;
  91         case 96000:
  92                 return MTK_AFE_ADDA_DL_RATE_96K;
  93         case 192000:
  94                 return MTK_AFE_ADDA_DL_RATE_192K;
  95         default:
  96                 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
  97                          __func__, rate);
  98                 return MTK_AFE_ADDA_DL_RATE_48K;
  99         }
 100 }
 101
 102 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
 103                                            unsigned int rate)
 104 {
 105         switch (rate) {
 106         case 8000:
 107                 return MTK_AFE_ADDA_UL_RATE_8K;
 108         case 16000:
 109                 return MTK_AFE_ADDA_UL_RATE_16K;
 110         case 32000:
 111                 return MTK_AFE_ADDA_UL_RATE_32K;
 112         case 48000:
 113                 return MTK_AFE_ADDA_UL_RATE_48K;
 114         case 96000:
 115                 return MTK_AFE_ADDA_UL_RATE_96K;
 116         case 192000:
 117                 return MTK_AFE_ADDA_UL_RATE_192K;
 118         default:
 119                 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 120                          __func__, rate);
 121                 return MTK_AFE_ADDA_UL_RATE_48K;
 122         }
 123 }
 124
 125 /* dai component */
 126 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
 127         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
 128         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
 129         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
 130         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
 131         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
 132         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0),
 133         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0),
 134         SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0),
 135         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3,
 136                                     I_ADDA_UL_CH3, 1, 0),
 137         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
 138                                     I_ADDA_UL_CH2, 1, 0),
 139         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
 140                                     I_ADDA_UL_CH1, 1, 0),
 141         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3,
 142                                     I_GAIN1_OUT_CH1, 1, 0),
 143         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
 144                                     I_PCM_1_CAP_CH1, 1, 0),
 145         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
 146                                     I_PCM_2_CAP_CH1, 1, 0),
 147         SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1,
 148                                     I_SRC_1_OUT_CH1, 1, 0),
 149         SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1,
 150                                     I_SRC_2_OUT_CH1, 1, 0),
 151 };
 152
 153 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
 154         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
 155         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
 156         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0),
 157         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
 158         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
 159         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
 160         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
 161         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0),
 162         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0),
 163         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0),
 164         SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0),
 165         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4,
 166                                     I_ADDA_UL_CH3, 1, 0),
 167         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
 168                                     I_ADDA_UL_CH2, 1, 0),
 169         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
 170                                     I_ADDA_UL_CH1, 1, 0),
 171         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4,
 172                                     I_GAIN1_OUT_CH2, 1, 0),
 173         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
 174                                     I_PCM_1_CAP_CH1, 1, 0),
 175         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
 176                                     I_PCM_2_CAP_CH1, 1, 0),
 177         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
 178                                     I_PCM_1_CAP_CH2, 1, 0),
 179         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
 180                                     I_PCM_2_CAP_CH2, 1, 0),
 181         SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1,
 182                                     I_SRC_1_OUT_CH2, 1, 0),
 183         SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1,
 184                                     I_SRC_2_OUT_CH2, 1, 0),
 185 };
 186
 187 static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
 188         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0),
 189         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0),
 190         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0),
 191         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0),
 192         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0),
 193         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0),
 194         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0),
 195         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52,
 196                                     I_ADDA_UL_CH3, 1, 0),
 197         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52,
 198                                     I_ADDA_UL_CH2, 1, 0),
 199         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52,
 200                                     I_ADDA_UL_CH1, 1, 0),
 201         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52,
 202                                     I_GAIN1_OUT_CH1, 1, 0),
 203         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52,
 204                                     I_PCM_1_CAP_CH1, 1, 0),
 205         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52,
 206                                     I_PCM_2_CAP_CH1, 1, 0),
 207 };
 208
 209 static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
 210         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0),
 211         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0),
 212         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0),
 213         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0),
 214         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0),
 215         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0),
 216         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0),
 217         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0),
 218         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0),
 219         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0),
 220         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53,
 221                                     I_ADDA_UL_CH3, 1, 0),
 222         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53,
 223                                     I_ADDA_UL_CH2, 1, 0),
 224         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53,
 225                                     I_ADDA_UL_CH1, 1, 0),
 226         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53,
 227                                     I_GAIN1_OUT_CH2, 1, 0),
 228         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53,
 229                                     I_PCM_1_CAP_CH1, 1, 0),
 230         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53,
 231                                     I_PCM_2_CAP_CH1, 1, 0),
 232         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53,
 233                                     I_PCM_1_CAP_CH2, 1, 0),
 234         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53,
 235                                     I_PCM_2_CAP_CH2, 1, 0),
 236 };
 237
 238 static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = {
 239         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19,
 240                                     I_ADDA_UL_CH1, 1, 0),
 241 };
 242
 243 static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = {
 244         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20,
 245                                     I_ADDA_UL_CH2, 1, 0),
 246 };
 247
 248 enum {
 249         SUPPLY_SEQ_ADDA_AFE_ON,
 250         SUPPLY_SEQ_ADDA_DL_ON,
 251         SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
 252         SUPPLY_SEQ_ADDA_MTKAIF_CFG,
 253         SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
 254         SUPPLY_SEQ_ADDA_FIFO,
 255         SUPPLY_SEQ_ADDA_AP_DMIC,
 256         SUPPLY_SEQ_ADDA_UL_ON,
 257 };
 258
 259 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
 260 {
 261         unsigned int reg;
 262
 263         switch (id) {
 264         case MT8192_DAI_ADDA:
 265         case MT8192_DAI_AP_DMIC:
 266                 reg = AFE_ADDA_UL_SRC_CON0;
 267                 break;
 268         case MT8192_DAI_ADDA_CH34:
 269         case MT8192_DAI_AP_DMIC_CH34:
 270                 reg = AFE_ADDA6_UL_SRC_CON0;
 271                 break;
 272         default:
 273                 return -EINVAL;
 274         }
 275
 276         /* dmic mode, 3.25M*/
 277         regmap_update_bits(afe->regmap, reg,
 278                            DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
 279                            0x0);
 280         regmap_update_bits(afe->regmap, reg,
 281                            DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
 282                            0x0);
 283
 284         /* turn on dmic, ch1, ch2 */
 285         regmap_update_bits(afe->regmap, reg,
 286                            UL_SDM_3_LEVEL_CTL_MASK_SFT,
 287                            0x1 << UL_SDM_3_LEVEL_CTL_SFT);
 288         regmap_update_bits(afe->regmap, reg,
 289                            UL_MODE_3P25M_CH1_CTL_MASK_SFT,
 290                            0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
 291         regmap_update_bits(afe->regmap, reg,
 292                            UL_MODE_3P25M_CH2_CTL_MASK_SFT,
 293                            0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
 294         return 0;
 295 }
 296
 297 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
 298                              struct snd_kcontrol *kcontrol,
 299                              int event)
 300 {
 301         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 302         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 303         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 304         int mtkaif_dmic = afe_priv->mtkaif_dmic;
 305
 306         dev_info(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
 307                  __func__, w->name, event, mtkaif_dmic);
 308
 309         switch (event) {
 310         case SND_SOC_DAPM_PRE_PMU:
 311                 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
 312
 313                 /* update setting to dmic */
 314                 if (mtkaif_dmic) {
 315                         /* mtkaif_rxif_data_mode = 1, dmic */
 316                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 317                                            0x1, 0x1);
 318
 319                         /* dmic mode, 3.25M*/
 320                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 321                                            MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
 322                                            0x0);
 323                         mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA);
 324                 }
 325                 break;
 326         case SND_SOC_DAPM_POST_PMD:
 327                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 328                 usleep_range(125, 135);
 329                 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
 330                 break;
 331         default:
 332                 break;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
 339                                   struct snd_kcontrol *kcontrol,
 340                                   int event)
 341 {
 342         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 343         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 344         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 345         int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34;
 346         int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only;
 347
 348         dev_info(afe->dev,
 349                  "%s(), name %s, event 0x%x, mtkaif_dmic %d, mtkaif_adda6_only %d\n",
 350                  __func__, w->name, event, mtkaif_dmic, mtkaif_adda6_only);
 351
 352         switch (event) {
 353         case SND_SOC_DAPM_PRE_PMU:
 354                 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
 355                                         1);
 356
 357                 /* update setting to dmic */
 358                 if (mtkaif_dmic) {
 359                         /* mtkaif_rxif_data_mode = 1, dmic */
 360                         regmap_update_bits(afe->regmap,
 361                                            AFE_ADDA6_MTKAIF_RX_CFG0,
 362                                            0x1, 0x1);
 363
 364                         /* dmic mode, 3.25M*/
 365                         regmap_update_bits(afe->regmap,
 366                                            AFE_ADDA6_MTKAIF_RX_CFG0,
 367                                            MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
 368                                            0x0);
 369                         mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34);
 370                 }
 371
 372                 /* when using adda6 without adda enabled,
 373                  * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or
 374                  * data cannot be received.
 375                  */
 376                 if (mtkaif_adda6_only) {
 377                         regmap_update_bits(afe->regmap,
 378                                            AFE_ADDA_MTKAIF_SYNCWORD_CFG,
 379                                            0x1 << 23, 0x1 << 23);
 380                 }
 381                 break;
 382         case SND_SOC_DAPM_POST_PMD:
 383                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 384                 usleep_range(125, 135);
 385                 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
 386                                         1);
 387
 388                 /* reset dmic */
 389                 afe_priv->mtkaif_dmic_ch34 = 0;
 390
 391                 if (mtkaif_adda6_only) {
 392                         regmap_update_bits(afe->regmap,
 393                                            AFE_ADDA_MTKAIF_SYNCWORD_CFG,
 394                                            0x1 << 23, 0x0 << 23);
 395                 }
 396                 break;
 397         default:
 398                 break;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
 405                                   struct snd_kcontrol *kcontrol,
 406                                   int event)
 407 {
 408         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 409         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 410         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 411
 412         switch (event) {
 413         case SND_SOC_DAPM_PRE_PMU:
 414                 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
 415                         regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
 416                 else
 417                         regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30);
 418                 break;
 419         default:
 420                 break;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
 427                                      struct snd_kcontrol *kcontrol,
 428                                      int event)
 429 {
 430         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 431         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 432         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 433         int delay_data;
 434         int delay_cycle;
 435
 436         switch (event) {
 437         case SND_SOC_DAPM_PRE_PMU:
 438                 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
 439                         /* set protocol 2 */
 440                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 441                                      0x00010000);
 442                         regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
 443                                      0x00010000);
 444
 445                         if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
 446                             (afe_priv->mtkaif_chosen_phase[0] < 0 ||
 447                              afe_priv->mtkaif_chosen_phase[1] < 0)) {
 448                                 dev_warn(afe->dev,
 449                                          "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n",
 450                                          __func__,
 451                                          afe_priv->mtkaif_chosen_phase[0],
 452                                          afe_priv->mtkaif_chosen_phase[1]);
 453                                 break;
 454                         } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
 455                                    afe_priv->mtkaif_chosen_phase[2] < 0) {
 456                                 dev_warn(afe->dev,
 457                                          "%s(), mtkaif_chosen_phase[2]:%d\n",
 458                                          __func__,
 459                                          afe_priv->mtkaif_chosen_phase[2]);
 460                                 break;
 461                         }
 462
 463                         /* mtkaif_rxif_clkinv_adc inverse for calibration */
 464                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 465                                            MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
 466                                            0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
 467                         regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
 468                                            MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
 469                                            0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
 470
 471                         /* set delay for ch12 */
 472                         if (afe_priv->mtkaif_phase_cycle[0] >=
 473                             afe_priv->mtkaif_phase_cycle[1]) {
 474                                 delay_data = DELAY_DATA_MISO1;
 475                                 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
 476                                               afe_priv->mtkaif_phase_cycle[1];
 477                         } else {
 478                                 delay_data = DELAY_DATA_MISO2;
 479                                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 480                                               afe_priv->mtkaif_phase_cycle[0];
 481                         }
 482
 483                         regmap_update_bits(afe->regmap,
 484                                            AFE_ADDA_MTKAIF_RX_CFG2,
 485                                            MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
 486                                            delay_data <<
 487                                            MTKAIF_RXIF_DELAY_DATA_SFT);
 488
 489                         regmap_update_bits(afe->regmap,
 490                                            AFE_ADDA_MTKAIF_RX_CFG2,
 491                                            MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
 492                                            delay_cycle <<
 493                                            MTKAIF_RXIF_DELAY_CYCLE_SFT);
 494
 495                         /* set delay between ch3 and ch2 */
 496                         if (afe_priv->mtkaif_phase_cycle[2] >=
 497                             afe_priv->mtkaif_phase_cycle[1]) {
 498                                 delay_data = DELAY_DATA_MISO1;  /* ch3 */
 499                                 delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
 500                                               afe_priv->mtkaif_phase_cycle[1];
 501                         } else {
 502                                 delay_data = DELAY_DATA_MISO2;  /* ch2 */
 503                                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 504                                               afe_priv->mtkaif_phase_cycle[2];
 505                         }
 506
 507                         regmap_update_bits(afe->regmap,
 508                                            AFE_ADDA6_MTKAIF_RX_CFG2,
 509                                            MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
 510                                            delay_data <<
 511                                            MTKAIF_RXIF_DELAY_DATA_SFT);
 512                         regmap_update_bits(afe->regmap,
 513                                            AFE_ADDA6_MTKAIF_RX_CFG2,
 514                                            MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
 515                                            delay_cycle <<
 516                                            MTKAIF_RXIF_DELAY_CYCLE_SFT);
 517                 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
 518                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 519                                      0x00010000);
 520                         regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
 521                                      0x00010000);
 522                 } else {
 523                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
 524                         regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0);
 525                 }
 526                 break;
 527         default:
 528                 break;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
 535                              struct snd_kcontrol *kcontrol,
 536                              int event)
 537 {
 538         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 539         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 540
 541         dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
 542                  __func__, w->name, event);
 543
 544         switch (event) {
 545         case SND_SOC_DAPM_PRE_PMU:
 546                 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
 547                 break;
 548         case SND_SOC_DAPM_POST_PMD:
 549                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 550                 usleep_range(125, 135);
 551                 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
 552                 break;
 553         default:
 554                 break;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w,
 561                                   struct snd_kcontrol *kcontrol,
 562                                   int event)
 563 {
 564         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 565         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 566
 567         dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
 568                  __func__, w->name, event);
 569
 570         switch (event) {
 571         case SND_SOC_DAPM_PRE_PMU:
 572                 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
 573                                         0);
 574                 break;
 575         case SND_SOC_DAPM_POST_PMD:
 576                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 577                 usleep_range(125, 135);
 578                 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
 579                                         0);
 580                 break;
 581         default:
 582                 break;
 583         }
 584
 585         return 0;
 586 }
 587
 588 /* stf */
 589 static int stf_positive_gain_get(struct snd_kcontrol *kcontrol,
 590                                  struct snd_ctl_elem_value *ucontrol)
 591 {
 592         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 593         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 594         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 595
 596         ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db;
 597         return 0;
 598 }
 599
 600 static int stf_positive_gain_set(struct snd_kcontrol *kcontrol,
 601                                  struct snd_ctl_elem_value *ucontrol)
 602 {
 603         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 604         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 605         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 606         int gain_db = ucontrol->value.integer.value[0];
 607
 608         afe_priv->stf_positive_gain_db = gain_db;
 609
 610         if (gain_db >= 0 && gain_db <= 24) {
 611                 regmap_update_bits(afe->regmap,
 612                                    AFE_SIDETONE_GAIN,
 613                                    POSITIVE_GAIN_MASK_SFT,
 614                                    (gain_db / 6) << POSITIVE_GAIN_SFT);
 615         } else {
 616                 dev_warn(afe->dev, "%s(), gain_db %d invalid\n",
 617                          __func__, gain_db);
 618         }
 619         return 0;
 620 }
 621
 622 static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol,
 623                                 struct snd_ctl_elem_value *ucontrol)
 624 {
 625         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 626         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 627         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 628
 629         ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
 630         return 0;
 631 }
 632
 633 static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol,
 634                                 struct snd_ctl_elem_value *ucontrol)
 635 {
 636         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 637         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 638         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 639         int dmic_on;
 640
 641         dmic_on = ucontrol->value.integer.value[0];
 642
 643         dev_info(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
 644                  __func__, kcontrol->id.name, dmic_on);
 645
 646         afe_priv->mtkaif_dmic = dmic_on;
 647         afe_priv->mtkaif_dmic_ch34 = dmic_on;
 648         return 0;
 649 }
 650
 651 static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol,
 652                                  struct snd_ctl_elem_value *ucontrol)
 653 {
 654         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 655         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 656         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 657
 658         ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only;
 659         return 0;
 660 }
 661
 662 static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol,
 663                                  struct snd_ctl_elem_value *ucontrol)
 664 {
 665         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 666         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 667         struct mt8192_afe_private *afe_priv = afe->platform_priv;
 668         int mtkaif_adda6_only;
 669
 670         mtkaif_adda6_only = ucontrol->value.integer.value[0];
 671
 672         dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
 673                  __func__, kcontrol->id.name, mtkaif_adda6_only);
 674
 675         afe_priv->mtkaif_adda6_only = mtkaif_adda6_only;
 676         return 0;
 677 }
 678
 679 static const struct snd_kcontrol_new mtk_adda_controls[] = {
 680         SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN,
 681                    SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0),
 682         SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 100, 0,
 683                        stf_positive_gain_get, stf_positive_gain_set),
 684         SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
 685                    DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
 686         SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
 687                             mt8192_adda_dmic_get, mt8192_adda_dmic_set),
 688         SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0,
 689                             mt8192_adda6_only_get, mt8192_adda6_only_set),
 690 };
 691
 692 static const struct snd_kcontrol_new stf_ctl =
 693         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
 694
 695 static const u16 stf_coeff_table_16k[] = {
 696         0x049C, 0x09E8, 0x09E0, 0x089C,
 697         0xFF54, 0xF488, 0xEAFC, 0xEBAC,
 698         0xfA40, 0x17AC, 0x3D1C, 0x6028,
 699         0x7538
 700 };
 701
 702 static const u16 stf_coeff_table_32k[] = {
 703         0xFE52, 0x0042, 0x00C5, 0x0194,
 704         0x029A, 0x03B7, 0x04BF, 0x057D,
 705         0x05BE, 0x0555, 0x0426, 0x0230,
 706         0xFF92, 0xFC89, 0xF973, 0xF6C6,
 707         0xF500, 0xF49D, 0xF603, 0xF970,
 708         0xFEF3, 0x065F, 0x0F4F, 0x1928,
 709         0x2329, 0x2C80, 0x345E, 0x3A0D,
 710         0x3D08
 711 };
 712
 713 static const u16 stf_coeff_table_48k[] = {
 714         0x0401, 0xFFB0, 0xFF5A, 0xFECE,
 715         0xFE10, 0xFD28, 0xFC21, 0xFB08,
 716         0xF9EF, 0xF8E8, 0xF80A, 0xF76C,
 717         0xF724, 0xF746, 0xF7E6, 0xF90F,
 718         0xFACC, 0xFD1E, 0xFFFF, 0x0364,
 719         0x0737, 0x0B62, 0x0FC1, 0x1431,
 720         0x188A, 0x1CA4, 0x2056, 0x237D,
 721         0x25F9, 0x27B0, 0x2890
 722 };
 723
 724 static int mtk_stf_event(struct snd_soc_dapm_widget *w,
 725                          struct snd_kcontrol *kcontrol,
 726                          int event)
 727 {
 728         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 729         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 730
 731         size_t half_tap_num;
 732         const u16 *stf_coeff_table;
 733         unsigned int ul_rate, reg_value;
 734         size_t coef_addr;
 735
 736         regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate);
 737         ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT;
 738         ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK;
 739
 740         if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) {
 741                 half_tap_num = ARRAY_SIZE(stf_coeff_table_48k);
 742                 stf_coeff_table = stf_coeff_table_48k;
 743         } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) {
 744                 half_tap_num = ARRAY_SIZE(stf_coeff_table_32k);
 745                 stf_coeff_table = stf_coeff_table_32k;
 746         } else {
 747                 half_tap_num = ARRAY_SIZE(stf_coeff_table_16k);
 748                 stf_coeff_table = stf_coeff_table_16k;
 749         }
 750
 751         regmap_read(afe->regmap, AFE_SIDETONE_CON1, &reg_value);
 752
 753         dev_info(afe->dev, "%s(), name %s, event 0x%x, ul_rate 0x%x, AFE_SIDETONE_CON1 0x%x\n",
 754                  __func__, w->name, event, ul_rate, reg_value);
 755
 756         switch (event) {
 757         case SND_SOC_DAPM_PRE_PMU:
 758                 /* set side tone gain = 0 */
 759                 regmap_update_bits(afe->regmap,
 760                                    AFE_SIDETONE_GAIN,
 761                                    SIDE_TONE_GAIN_MASK_SFT,
 762                                    0);
 763                 regmap_update_bits(afe->regmap,
 764                                    AFE_SIDETONE_GAIN,
 765                                    POSITIVE_GAIN_MASK_SFT,
 766                                    0);
 767                 /* don't bypass stf */
 768                 regmap_update_bits(afe->regmap,
 769                                    AFE_SIDETONE_CON1,
 770                                    0x1f << 27,
 771                                    0x0);
 772                 /* set stf half tap num */
 773                 regmap_update_bits(afe->regmap,
 774                                    AFE_SIDETONE_CON1,
 775                                    SIDE_TONE_HALF_TAP_NUM_MASK_SFT,
 776                                    half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT);
 777
 778                 /* set side tone coefficient */
 779                 regmap_read(afe->regmap, AFE_SIDETONE_CON0, &reg_value);
 780                 for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) {
 781                         bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
 782                         bool new_w_ready = 0;
 783                         int try_cnt = 0;
 784
 785                         regmap_update_bits(afe->regmap,
 786                                            AFE_SIDETONE_CON0,
 787                                            0x39FFFFF,
 788                                            (1 << R_W_EN_SFT) |
 789                                            (1 << R_W_SEL_SFT) |
 790                                            (0 << SEL_CH2_SFT) |
 791                                            (coef_addr <<
 792                                            SIDE_TONE_COEFFICIENT_ADDR_SFT) |
 793                                            stf_coeff_table[coef_addr]);
 794
 795                         /* wait until flag write_ready changed */
 796                         for (try_cnt = 0; try_cnt < 10; try_cnt++) {
 797                                 regmap_read(afe->regmap,
 798                                             AFE_SIDETONE_CON0, &reg_value);
 799                                 new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
 800
 801                                 /* flip => ok */
 802                                 if (new_w_ready == old_w_ready) {
 803                                         udelay(3);
 804                                         if (try_cnt == 9) {
 805                                                 dev_warn(afe->dev,
 806                                                          "%s(), write coeff not ready",
 807                                                          __func__);
 808                                         }
 809                                 } else {
 810                                         break;
 811                                 }
 812                         }
 813                         /* need write -> read -> write to write next coeff */
 814                         regmap_update_bits(afe->regmap,
 815                                            AFE_SIDETONE_CON0,
 816                                            R_W_SEL_MASK_SFT,
 817                                            0x0);
 818                 }
 819                 break;
 820         case SND_SOC_DAPM_POST_PMD:
 821                 /* bypass stf */
 822                 regmap_update_bits(afe->regmap,
 823                                    AFE_SIDETONE_CON1,
 824                                    0x1f << 27,
 825                                    0x1f << 27);
 826
 827                 /* set side tone gain = 0 */
 828                 regmap_update_bits(afe->regmap,
 829                                    AFE_SIDETONE_GAIN,
 830                                    SIDE_TONE_GAIN_MASK_SFT,
 831                                    0);
 832                 regmap_update_bits(afe->regmap,
 833                                    AFE_SIDETONE_GAIN,
 834                                    POSITIVE_GAIN_MASK_SFT,
 835                                    0);
 836                 break;
 837         default:
 838                 break;
 839         }
 840
 841         return 0;
 842 }
 843
 844 /* stf mux */
 845 enum {
 846         STF_SRC_ADDA_ADDA6 = 0,
 847         STF_SRC_O19O20,
 848 };
 849
 850 static const char *const stf_o19o20_mux_map[] = {
 851         "ADDA_ADDA6",
 852         "O19O20",
 853 };
 854
 855 static int stf_o19o20_mux_map_value[] = {
 856         STF_SRC_ADDA_ADDA6,
 857         STF_SRC_O19O20,
 858 };
 859
 860 static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum,
 861                                   AFE_SIDETONE_CON1,
 862                                   STF_SOURCE_FROM_O19O20_SFT,
 863                                   STF_SOURCE_FROM_O19O20_MASK,
 864                                   stf_o19o20_mux_map,
 865                                   stf_o19o20_mux_map_value);
 866
 867 static const struct snd_kcontrol_new stf_o19O20_mux_control =
 868         SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum);
 869
 870 enum {
 871         STF_SRC_ADDA = 0,
 872         STF_SRC_ADDA6,
 873 };
 874
 875 static const char *const stf_adda_mux_map[] = {
 876         "ADDA",
 877         "ADDA6",
 878 };
 879
 880 static int stf_adda_mux_map_value[] = {
 881         STF_SRC_ADDA,
 882         STF_SRC_ADDA6,
 883 };
 884
 885 static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum,
 886                                   AFE_SIDETONE_CON1,
 887                                   STF_O19O20_OUT_EN_SEL_SFT,
 888                                   STF_O19O20_OUT_EN_SEL_MASK,
 889                                   stf_adda_mux_map,
 890                                   stf_adda_mux_map_value);
 891
 892 static const struct snd_kcontrol_new stf_adda_mux_control =
 893         SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum);
 894
 895 /* ADDA UL MUX */
 896 enum {
 897         ADDA_UL_MUX_MTKAIF = 0,
 898         ADDA_UL_MUX_AP_DMIC,
 899         ADDA_UL_MUX_MASK = 0x1,
 900 };
 901
 902 static const char * const adda_ul_mux_map[] = {
 903         "MTKAIF", "AP_DMIC"
 904 };
 905
 906 static int adda_ul_map_value[] = {
 907         ADDA_UL_MUX_MTKAIF,
 908         ADDA_UL_MUX_AP_DMIC,
 909 };
 910
 911 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
 912                                   SND_SOC_NOPM,
 913                                   0,
 914                                   ADDA_UL_MUX_MASK,
 915                                   adda_ul_mux_map,
 916                                   adda_ul_map_value);
 917
 918 static const struct snd_kcontrol_new adda_ul_mux_control =
 919         SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
 920
 921 static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
 922         SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
 923
 924 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
 925         /* inter-connections */
 926         SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
 927                            mtk_adda_dl_ch1_mix,
 928                            ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
 929         SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
 930                            mtk_adda_dl_ch2_mix,
 931                            ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
 932
 933         SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
 934                            mtk_adda_dl_ch3_mix,
 935                            ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
 936         SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
 937                            mtk_adda_dl_ch4_mix,
 938                            ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
 939
 940         SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
 941                               AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
 942                               NULL, 0),
 943
 944         SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
 945                               AFE_ADDA_DL_SRC2_CON0,
 946                               DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
 947                               mtk_adda_dl_event,
 948                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 949         SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable",
 950                               SUPPLY_SEQ_ADDA_DL_ON,
 951                               AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
 952                               DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
 953                               mtk_adda_ch34_dl_event,
 954                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 955
 956         SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 957                               AFE_ADDA_UL_SRC_CON0,
 958                               UL_SRC_ON_TMP_CTL_SFT, 0,
 959                               mtk_adda_ul_event,
 960                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 961         SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 962                               AFE_ADDA6_UL_SRC_CON0,
 963                               UL_SRC_ON_TMP_CTL_SFT, 0,
 964                               mtk_adda_ch34_ul_event,
 965                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 966
 967         SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
 968                               AFE_AUD_PAD_TOP,
 969                               RG_RX_FIFO_ON_SFT, 0,
 970                               mtk_adda_pad_top_event,
 971                               SND_SOC_DAPM_PRE_PMU),
 972         SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
 973                               SND_SOC_NOPM, 0, 0,
 974                               mtk_adda_mtkaif_cfg_event,
 975                               SND_SOC_DAPM_PRE_PMU),
 976         SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
 977                               SND_SOC_NOPM, 0, 0,
 978                               mtk_adda_mtkaif_cfg_event,
 979                               SND_SOC_DAPM_PRE_PMU),
 980
 981         SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
 982                               AFE_ADDA_UL_SRC_CON0,
 983                               UL_AP_DMIC_ON_SFT, 0,
 984                               NULL, 0),
 985         SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
 986                               AFE_ADDA6_UL_SRC_CON0,
 987                               UL_AP_DMIC_ON_SFT, 0,
 988                               NULL, 0),
 989
 990         SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 991                               AFE_ADDA_UL_DL_CON0,
 992                               AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
 993                               NULL, 0),
 994         SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 995                               AFE_ADDA_UL_DL_CON0,
 996                               AFE_ADDA6_FIFO_AUTO_RST_SFT, 1,
 997                               NULL, 0),
 998
 999         SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
1000                          &adda_ul_mux_control),
1001         SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
1002                          &adda_ch34_ul_mux_control),
1003
1004         SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
1005         SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
1006
1007         /* stf */
1008         SND_SOC_DAPM_SWITCH_E("Sidetone Filter",
1009                               AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0,
1010                               &stf_ctl,
1011                               mtk_stf_event,
1012                               SND_SOC_DAPM_PRE_PMU |
1013                               SND_SOC_DAPM_POST_PMD),
1014         SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0,
1015                          &stf_o19O20_mux_control),
1016         SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0,
1017                          &stf_adda_mux_control),
1018         SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0,
1019                            mtk_stf_ch1_mix,
1020                            ARRAY_SIZE(mtk_stf_ch1_mix)),
1021         SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0,
1022                            mtk_stf_ch2_mix,
1023                            ARRAY_SIZE(mtk_stf_ch2_mix)),
1024         SND_SOC_DAPM_OUTPUT("STF_OUTPUT"),
1025
1026         /* clock */
1027         SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
1028
1029         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
1030         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
1031         SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"),
1032         SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"),
1033
1034         SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
1035         SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"),
1036 };
1037
1038 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
1039         /* playback */
1040         {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
1041         {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
1042         {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
1043
1044         {"ADDA_DL_CH1", "DL12_CH1", "DL12"},
1045         {"ADDA_DL_CH2", "DL12_CH2", "DL12"},
1046
1047         {"ADDA_DL_CH1", "DL6_CH1", "DL6"},
1048         {"ADDA_DL_CH2", "DL6_CH2", "DL6"},
1049
1050         {"ADDA_DL_CH1", "DL8_CH1", "DL8"},
1051         {"ADDA_DL_CH2", "DL8_CH2", "DL8"},
1052
1053         {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
1054         {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
1055         {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
1056
1057         {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
1058         {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
1059         {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
1060
1061         {"ADDA_DL_CH1", "DL4_CH1", "DL4"},
1062         {"ADDA_DL_CH2", "DL4_CH2", "DL4"},
1063
1064         {"ADDA_DL_CH1", "DL5_CH1", "DL5"},
1065         {"ADDA_DL_CH2", "DL5_CH2", "DL5"},
1066
1067         {"ADDA Playback", NULL, "ADDA_DL_CH1"},
1068         {"ADDA Playback", NULL, "ADDA_DL_CH2"},
1069
1070         {"ADDA Playback", NULL, "ADDA Enable"},
1071         {"ADDA Playback", NULL, "ADDA Playback Enable"},
1072
1073         {"ADDA_DL_CH3", "DL1_CH1", "DL1"},
1074         {"ADDA_DL_CH4", "DL1_CH1", "DL1"},
1075         {"ADDA_DL_CH4", "DL1_CH2", "DL1"},
1076
1077         {"ADDA_DL_CH3", "DL12_CH1", "DL12"},
1078         {"ADDA_DL_CH4", "DL12_CH2", "DL12"},
1079
1080         {"ADDA_DL_CH3", "DL6_CH1", "DL6"},
1081         {"ADDA_DL_CH4", "DL6_CH2", "DL6"},
1082
1083         {"ADDA_DL_CH3", "DL2_CH1", "DL2"},
1084         {"ADDA_DL_CH4", "DL2_CH1", "DL2"},
1085         {"ADDA_DL_CH4", "DL2_CH2", "DL2"},
1086
1087         {"ADDA_DL_CH3", "DL3_CH1", "DL3"},
1088         {"ADDA_DL_CH4", "DL3_CH1", "DL3"},
1089         {"ADDA_DL_CH4", "DL3_CH2", "DL3"},
1090
1091         {"ADDA_DL_CH3", "DL4_CH1", "DL4"},
1092         {"ADDA_DL_CH4", "DL4_CH2", "DL4"},
1093
1094         {"ADDA_DL_CH3", "DL5_CH1", "DL5"},
1095         {"ADDA_DL_CH4", "DL5_CH2", "DL5"},
1096
1097         {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"},
1098         {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"},
1099
1100         {"ADDA CH34 Playback", NULL, "ADDA Enable"},
1101         {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"},
1102
1103         /* capture */
1104         {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
1105         {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
1106
1107         {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
1108         {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
1109
1110         {"ADDA Capture", NULL, "ADDA Enable"},
1111         {"ADDA Capture", NULL, "ADDA Capture Enable"},
1112         {"ADDA Capture", NULL, "AUD_PAD_TOP"},
1113         {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
1114
1115         {"AP DMIC Capture", NULL, "ADDA Enable"},
1116         {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
1117         {"AP DMIC Capture", NULL, "ADDA_FIFO"},
1118         {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
1119
1120         {"ADDA CH34 Capture", NULL, "ADDA Enable"},
1121         {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1122         {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"},
1123         {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"},
1124
1125         {"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
1126         {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1127         {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
1128         {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
1129
1130         {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
1131         {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
1132
1133         /* sidetone filter */
1134         {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"},
1135         {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"},
1136
1137         {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"},
1138         {"STF_O19O20_MUX", "O19O20", "STF_CH1"},
1139         {"STF_O19O20_MUX", "O19O20", "STF_CH2"},
1140
1141         {"Sidetone Filter", "Switch", "STF_O19O20_MUX"},
1142         {"STF_OUTPUT", NULL, "Sidetone Filter"},
1143         {"ADDA Playback", NULL, "Sidetone Filter"},
1144         {"ADDA CH34 Playback", NULL, "Sidetone Filter"},
1145
1146         /* clk */
1147         {"ADDA Playback", NULL, "aud_dac_clk"},
1148         {"ADDA Playback", NULL, "aud_dac_predis_clk"},
1149
1150         {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"},
1151         {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"},
1152
1153         {"ADDA Capture Enable", NULL, "aud_adc_clk"},
1154         {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"},
1155 };
1156
1157 /* dai ops */
1158 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
1159                                   struct snd_pcm_hw_params *params,
1160                                   struct snd_soc_dai *dai)
1161 {
1162         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1163         unsigned int rate = params_rate(params);
1164         int id = dai->id;
1165
1166         dev_info(afe->dev, "%s(), id %d, stream %d, rate %d\n",
1167                  __func__,
1168                  id,
1169                  substream->stream,
1170                  rate);
1171
1172         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1173                 unsigned int dl_src2_con0 = 0;
1174                 unsigned int dl_src2_con1 = 0;
1175
1176                 /* set sampling rate */
1177                 dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
1178                                DL_2_INPUT_MODE_CTL_SFT;
1179
1180                 /* set output mode, UP_SAMPLING_RATE_X8 */
1181                 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
1182
1183                 /* turn off mute function */
1184                 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
1185                 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
1186
1187                 /* set voice input data if input sample rate is 8k or 16k */
1188                 if (rate == 8000 || rate == 16000)
1189                         dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT;
1190
1191                 /* SA suggest apply -0.3db to audio/speech path */
1192                 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
1193                                DL_2_GAIN_CTL_PRE_SFT;
1194
1195                 /* turn on down-link gain */
1196                 dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT);
1197
1198                 if (id == MT8192_DAI_ADDA) {
1199                         /* clean predistortion */
1200                         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
1201                         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
1202
1203                         regmap_write(afe->regmap,
1204                                      AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
1205                         regmap_write(afe->regmap,
1206                                      AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
1207
1208                         /* set sdm gain */
1209                         regmap_update_bits(afe->regmap,
1210                                            AFE_ADDA_DL_SDM_DCCOMP_CON,
1211                                            ATTGAIN_CTL_MASK_SFT,
1212                                            AUDIO_SDM_LEVEL_NORMAL <<
1213                                            ATTGAIN_CTL_SFT);
1214
1215                         /* 2nd sdm */
1216                         regmap_update_bits(afe->regmap,
1217                                            AFE_ADDA_DL_SDM_DCCOMP_CON,
1218                                            USE_3RD_SDM_MASK_SFT,
1219                                            AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1220
1221                         /* sdm auto reset */
1222                         regmap_write(afe->regmap,
1223                                      AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1224                                      SDM_AUTO_RESET_THRESHOLD);
1225                         regmap_update_bits(afe->regmap,
1226                                            AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1227                                            ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1228                                            0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT);
1229                 } else {
1230                         /* clean predistortion */
1231                         regmap_write(afe->regmap,
1232                                      AFE_ADDA_3RD_DAC_PREDIS_CON0, 0);
1233                         regmap_write(afe->regmap,
1234                                      AFE_ADDA_3RD_DAC_PREDIS_CON1, 0);
1235
1236                         regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
1237                                      dl_src2_con0);
1238                         regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1,
1239                                      dl_src2_con1);
1240
1241                         /* set sdm gain */
1242                         regmap_update_bits(afe->regmap,
1243                                            AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1244                                            ATTGAIN_CTL_MASK_SFT,
1245                                            AUDIO_SDM_LEVEL_NORMAL <<
1246                                            ATTGAIN_CTL_SFT);
1247
1248                         /* 2nd sdm */
1249                         regmap_update_bits(afe->regmap,
1250                                            AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1251                                            USE_3RD_SDM_MASK_SFT,
1252                                            AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1253
1254                         /* sdm auto reset */
1255                         regmap_write(afe->regmap,
1256                                      AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1257                                      SDM_AUTO_RESET_THRESHOLD);
1258                         regmap_update_bits(afe->regmap,
1259                                            AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1260                                            ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1261                                            0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT);
1262                 }
1263         } else {
1264                 unsigned int voice_mode = 0;
1265                 unsigned int ul_src_con0 = 0;   /* default value */
1266
1267                 voice_mode = adda_ul_rate_transform(afe, rate);
1268
1269                 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
1270
1271                 /* enable iir */
1272                 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
1273                                UL_IIR_ON_TMP_CTL_MASK_SFT;
1274                 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
1275                                UL_IIRMODE_CTL_MASK_SFT;
1276
1277                 switch (id) {
1278                 case MT8192_DAI_ADDA:
1279                 case MT8192_DAI_AP_DMIC:
1280                         /* 35Hz @ 48k */
1281                         regmap_write(afe->regmap,
1282                                      AFE_ADDA_IIR_COEF_02_01, 0x00000000);
1283                         regmap_write(afe->regmap,
1284                                      AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
1285                         regmap_write(afe->regmap,
1286                                      AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
1287                         regmap_write(afe->regmap,
1288                                      AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
1289                         regmap_write(afe->regmap,
1290                                      AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
1291
1292                         regmap_write(afe->regmap,
1293                                      AFE_ADDA_UL_SRC_CON0, ul_src_con0);
1294
1295                         /* Using Internal ADC */
1296                         regmap_update_bits(afe->regmap,
1297                                            AFE_ADDA_TOP_CON0,
1298                                            0x1 << 0,
1299                                            0x0 << 0);
1300
1301                         /* mtkaif_rxif_data_mode = 0, amic */
1302                         regmap_update_bits(afe->regmap,
1303                                            AFE_ADDA_MTKAIF_RX_CFG0,
1304                                            0x1 << 0,
1305                                            0x0 << 0);
1306                         break;
1307                 case MT8192_DAI_ADDA_CH34:
1308                 case MT8192_DAI_AP_DMIC_CH34:
1309                         /* 35Hz @ 48k */
1310                         regmap_write(afe->regmap,
1311                                      AFE_ADDA6_IIR_COEF_02_01, 0x00000000);
1312                         regmap_write(afe->regmap,
1313                                      AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8);
1314                         regmap_write(afe->regmap,
1315                                      AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000);
1316                         regmap_write(afe->regmap,
1317                                      AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000);
1318                         regmap_write(afe->regmap,
1319                                      AFE_ADDA6_IIR_COEF_10_09, 0x0000C048);
1320
1321                         regmap_write(afe->regmap,
1322                                      AFE_ADDA6_UL_SRC_CON0, ul_src_con0);
1323
1324                         /* Using Internal ADC */
1325                         regmap_update_bits(afe->regmap,
1326                                            AFE_ADDA6_TOP_CON0,
1327                                            0x1 << 0,
1328                                            0x0 << 0);
1329
1330                         /* mtkaif_rxif_data_mode = 0, amic */
1331                         regmap_update_bits(afe->regmap,
1332                                            AFE_ADDA6_MTKAIF_RX_CFG0,
1333                                            0x1 << 0,
1334                                            0x0 << 0);
1335                         break;
1336                 default:
1337                         break;
1338                 }
1339
1340                 /* ap dmic */
1341                 switch (id) {
1342                 case MT8192_DAI_AP_DMIC:
1343                 case MT8192_DAI_AP_DMIC_CH34:
1344                         mtk_adda_ul_src_dmic(afe, id);
1345                         break;
1346                 default:
1347                         break;
1348                 }
1349         }
1350
1351         return 0;
1352 }
1353
1354 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
1355         .hw_params = mtk_dai_adda_hw_params,
1356 };
1357
1358 /* dai driver */
1359 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
1360                                  SNDRV_PCM_RATE_96000 |\
1361                                  SNDRV_PCM_RATE_192000)
1362
1363 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1364                                 SNDRV_PCM_RATE_16000 |\
1365                                 SNDRV_PCM_RATE_32000 |\
1366                                 SNDRV_PCM_RATE_48000 |\
1367                                 SNDRV_PCM_RATE_96000 |\
1368                                 SNDRV_PCM_RATE_192000)
1369
1370 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1371                           SNDRV_PCM_FMTBIT_S24_LE |\
1372                           SNDRV_PCM_FMTBIT_S32_LE)
1373
1374 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
1375         {
1376                 .name = "ADDA",
1377                 .id = MT8192_DAI_ADDA,
1378                 .playback = {
1379                         .stream_name = "ADDA Playback",
1380                         .channels_min = 1,
1381                         .channels_max = 2,
1382                         .rates = MTK_ADDA_PLAYBACK_RATES,
1383                         .formats = MTK_ADDA_FORMATS,
1384                 },
1385                 .capture = {
1386                         .stream_name = "ADDA Capture",
1387                         .channels_min = 1,
1388                         .channels_max = 2,
1389                         .rates = MTK_ADDA_CAPTURE_RATES,
1390                         .formats = MTK_ADDA_FORMATS,
1391                 },
1392                 .ops = &mtk_dai_adda_ops,
1393         },
1394         {
1395                 .name = "ADDA_CH34",
1396                 .id = MT8192_DAI_ADDA_CH34,
1397                 .playback = {
1398                         .stream_name = "ADDA CH34 Playback",
1399                         .channels_min = 1,
1400                         .channels_max = 2,
1401                         .rates = MTK_ADDA_PLAYBACK_RATES,
1402                         .formats = MTK_ADDA_FORMATS,
1403                 },
1404                 .capture = {
1405                         .stream_name = "ADDA CH34 Capture",
1406                         .channels_min = 1,
1407                         .channels_max = 2,
1408                         .rates = MTK_ADDA_CAPTURE_RATES,
1409                         .formats = MTK_ADDA_FORMATS,
1410                 },
1411                 .ops = &mtk_dai_adda_ops,
1412         },
1413         {
1414                 .name = "AP_DMIC",
1415                 .id = MT8192_DAI_AP_DMIC,
1416                 .capture = {
1417                         .stream_name = "AP DMIC Capture",
1418                         .channels_min = 1,
1419                         .channels_max = 2,
1420                         .rates = MTK_ADDA_CAPTURE_RATES,
1421                         .formats = MTK_ADDA_FORMATS,
1422                 },
1423                 .ops = &mtk_dai_adda_ops,
1424         },
1425         {
1426                 .name = "AP_DMIC_CH34",
1427                 .id = MT8192_DAI_AP_DMIC_CH34,
1428                 .capture = {
1429                         .stream_name = "AP DMIC CH34 Capture",
1430                         .channels_min = 1,
1431                         .channels_max = 2,
1432                         .rates = MTK_ADDA_CAPTURE_RATES,
1433                         .formats = MTK_ADDA_FORMATS,
1434                 },
1435                 .ops = &mtk_dai_adda_ops,
1436         },
1437 };
1438
1439 int mt8192_dai_adda_register(struct mtk_base_afe *afe)
1440 {
1441         struct mtk_base_afe_dai *dai;
1442         struct mt8192_afe_private *afe_priv = afe->platform_priv;
1443
1444         dev_info(afe->dev, "%s()\n", __func__);
1445
1446         dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1447         if (!dai)
1448                 return -ENOMEM;
1449
1450         list_add(&dai->list, &afe->sub_dais);
1451
1452         dai->dai_drivers = mtk_dai_adda_driver;
1453         dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
1454
1455         dai->controls = mtk_adda_controls;
1456         dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
1457         dai->dapm_widgets = mtk_dai_adda_widgets;
1458         dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
1459         dai->dapm_routes = mtk_dai_adda_routes;
1460         dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
1461
1462         /* ap dmic priv share with adda */
1463         afe_priv->dai_priv[MT8192_DAI_AP_DMIC] =
1464                 afe_priv->dai_priv[MT8192_DAI_ADDA];
1465         afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] =
1466                 afe_priv->dai_priv[MT8192_DAI_ADDA_CH34];
1467
1468         return 0;
1469 }