1 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 #ifndef _MSM_PCM_ROUTING_H
13 #define _MSM_PCM_ROUTING_H
14 #include <sound/apr_audio-v2.h>
15 #include <sound/q6adm-v2.h>
18 * These names are used by HAL to specify the BE. If any changes are
19 * made to the string names or the max name length corresponding
20 * changes need to be made in the HAL to ensure they still match.
22 #define LPASS_BE_NAME_MAX_LENGTH 24
23 #define LPASS_BE_PRI_I2S_RX "PRIMARY_I2S_RX"
24 #define LPASS_BE_PRI_I2S_TX "PRIMARY_I2S_TX"
25 #define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
26 #define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
27 #define LPASS_BE_HDMI "HDMI"
28 #define LPASS_BE_DISPLAY_PORT "DISPLAY_PORT"
29 #define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
30 #define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
31 #define LPASS_BE_INT_BT_A2DP_RX "INT_BT_A2DP_RX"
32 #define LPASS_BE_INT_FM_RX "INT_FM_RX"
33 #define LPASS_BE_INT_FM_TX "INT_FM_TX"
34 #define LPASS_BE_AFE_PCM_RX "RT_PROXY_DAI_001_RX"
35 #define LPASS_BE_AFE_PCM_TX "RT_PROXY_DAI_002_TX"
36 #define LPASS_BE_AUXPCM_RX "AUX_PCM_RX"
37 #define LPASS_BE_AUXPCM_TX "AUX_PCM_TX"
38 #define LPASS_BE_SEC_AUXPCM_RX "SEC_AUX_PCM_RX"
39 #define LPASS_BE_SEC_AUXPCM_TX "SEC_AUX_PCM_TX"
40 #define LPASS_BE_TERT_AUXPCM_RX "TERT_AUX_PCM_RX"
41 #define LPASS_BE_TERT_AUXPCM_TX "TERT_AUX_PCM_TX"
42 #define LPASS_BE_QUAT_AUXPCM_RX "QUAT_AUX_PCM_RX"
43 #define LPASS_BE_QUAT_AUXPCM_TX "QUAT_AUX_PCM_TX"
44 #define LPASS_BE_VOICE_PLAYBACK_TX "VOICE_PLAYBACK_TX"
45 #define LPASS_BE_VOICE2_PLAYBACK_TX "VOICE2_PLAYBACK_TX"
46 #define LPASS_BE_INCALL_RECORD_RX "INCALL_RECORD_RX"
47 #define LPASS_BE_INCALL_RECORD_TX "INCALL_RECORD_TX"
48 #define LPASS_BE_SEC_I2S_RX "SECONDARY_I2S_RX"
49 #define LPASS_BE_SPDIF_RX "SPDIF_RX"
51 #define LPASS_BE_MI2S_RX "MI2S_RX"
52 #define LPASS_BE_MI2S_TX "MI2S_TX"
53 #define LPASS_BE_QUAT_MI2S_RX "QUAT_MI2S_RX"
54 #define LPASS_BE_QUAT_MI2S_TX "QUAT_MI2S_TX"
55 #define LPASS_BE_SEC_MI2S_RX "SEC_MI2S_RX"
56 #define LPASS_BE_SEC_MI2S_RX_SD1 "SEC_MI2S_RX_SD1"
57 #define LPASS_BE_SEC_MI2S_TX "SEC_MI2S_TX"
58 #define LPASS_BE_PRI_MI2S_RX "PRI_MI2S_RX"
59 #define LPASS_BE_PRI_MI2S_TX "PRI_MI2S_TX"
60 #define LPASS_BE_TERT_MI2S_RX "TERT_MI2S_RX"
61 #define LPASS_BE_TERT_MI2S_TX "TERT_MI2S_TX"
62 #define LPASS_BE_AUDIO_I2S_RX "AUDIO_I2S_RX"
63 #define LPASS_BE_STUB_RX "STUB_RX"
64 #define LPASS_BE_STUB_TX "STUB_TX"
65 #define LPASS_BE_SLIMBUS_1_RX "SLIMBUS_1_RX"
66 #define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
67 #define LPASS_BE_STUB_1_TX "STUB_1_TX"
68 #define LPASS_BE_SLIMBUS_2_RX "SLIMBUS_2_RX"
69 #define LPASS_BE_SLIMBUS_2_TX "SLIMBUS_2_TX"
70 #define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
71 #define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
72 #define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
73 #define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
74 #define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI"
75 #define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX"
76 #define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX"
77 #define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX"
78 #define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX"
79 #define LPASS_BE_QUIN_MI2S_RX "QUIN_MI2S_RX"
80 #define LPASS_BE_QUIN_MI2S_TX "QUIN_MI2S_TX"
81 #define LPASS_BE_SENARY_MI2S_TX "SENARY_MI2S_TX"
83 #define LPASS_BE_PRI_TDM_RX_0 "PRI_TDM_RX_0"
84 #define LPASS_BE_PRI_TDM_TX_0 "PRI_TDM_TX_0"
85 #define LPASS_BE_PRI_TDM_RX_1 "PRI_TDM_RX_1"
86 #define LPASS_BE_PRI_TDM_TX_1 "PRI_TDM_TX_1"
87 #define LPASS_BE_PRI_TDM_RX_2 "PRI_TDM_RX_2"
88 #define LPASS_BE_PRI_TDM_TX_2 "PRI_TDM_TX_2"
89 #define LPASS_BE_PRI_TDM_RX_3 "PRI_TDM_RX_3"
90 #define LPASS_BE_PRI_TDM_TX_3 "PRI_TDM_TX_3"
91 #define LPASS_BE_PRI_TDM_RX_4 "PRI_TDM_RX_4"
92 #define LPASS_BE_PRI_TDM_TX_4 "PRI_TDM_TX_4"
93 #define LPASS_BE_PRI_TDM_RX_5 "PRI_TDM_RX_5"
94 #define LPASS_BE_PRI_TDM_TX_5 "PRI_TDM_TX_5"
95 #define LPASS_BE_PRI_TDM_RX_6 "PRI_TDM_RX_6"
96 #define LPASS_BE_PRI_TDM_TX_6 "PRI_TDM_TX_6"
97 #define LPASS_BE_PRI_TDM_RX_7 "PRI_TDM_RX_7"
98 #define LPASS_BE_PRI_TDM_TX_7 "PRI_TDM_TX_7"
99 #define LPASS_BE_SEC_TDM_RX_0 "SEC_TDM_RX_0"
100 #define LPASS_BE_SEC_TDM_TX_0 "SEC_TDM_TX_0"
101 #define LPASS_BE_SEC_TDM_RX_1 "SEC_TDM_RX_1"
102 #define LPASS_BE_SEC_TDM_TX_1 "SEC_TDM_TX_1"
103 #define LPASS_BE_SEC_TDM_RX_2 "SEC_TDM_RX_2"
104 #define LPASS_BE_SEC_TDM_TX_2 "SEC_TDM_TX_2"
105 #define LPASS_BE_SEC_TDM_RX_3 "SEC_TDM_RX_3"
106 #define LPASS_BE_SEC_TDM_TX_3 "SEC_TDM_TX_3"
107 #define LPASS_BE_SEC_TDM_RX_4 "SEC_TDM_RX_4"
108 #define LPASS_BE_SEC_TDM_TX_4 "SEC_TDM_TX_4"
109 #define LPASS_BE_SEC_TDM_RX_5 "SEC_TDM_RX_5"
110 #define LPASS_BE_SEC_TDM_TX_5 "SEC_TDM_TX_5"
111 #define LPASS_BE_SEC_TDM_RX_6 "SEC_TDM_RX_6"
112 #define LPASS_BE_SEC_TDM_TX_6 "SEC_TDM_TX_6"
113 #define LPASS_BE_SEC_TDM_RX_7 "SEC_TDM_RX_7"
114 #define LPASS_BE_SEC_TDM_TX_7 "SEC_TDM_TX_7"
115 #define LPASS_BE_TERT_TDM_RX_0 "TERT_TDM_RX_0"
116 #define LPASS_BE_TERT_TDM_TX_0 "TERT_TDM_TX_0"
117 #define LPASS_BE_TERT_TDM_RX_1 "TERT_TDM_RX_1"
118 #define LPASS_BE_TERT_TDM_TX_1 "TERT_TDM_TX_1"
119 #define LPASS_BE_TERT_TDM_RX_2 "TERT_TDM_RX_2"
120 #define LPASS_BE_TERT_TDM_TX_2 "TERT_TDM_TX_2"
121 #define LPASS_BE_TERT_TDM_RX_3 "TERT_TDM_RX_3"
122 #define LPASS_BE_TERT_TDM_TX_3 "TERT_TDM_TX_3"
123 #define LPASS_BE_TERT_TDM_RX_4 "TERT_TDM_RX_4"
124 #define LPASS_BE_TERT_TDM_TX_4 "TERT_TDM_TX_4"
125 #define LPASS_BE_TERT_TDM_RX_5 "TERT_TDM_RX_5"
126 #define LPASS_BE_TERT_TDM_TX_5 "TERT_TDM_TX_5"
127 #define LPASS_BE_TERT_TDM_RX_6 "TERT_TDM_RX_6"
128 #define LPASS_BE_TERT_TDM_TX_6 "TERT_TDM_TX_6"
129 #define LPASS_BE_TERT_TDM_RX_7 "TERT_TDM_RX_7"
130 #define LPASS_BE_TERT_TDM_TX_7 "TERT_TDM_TX_7"
131 #define LPASS_BE_QUAT_TDM_RX_0 "QUAT_TDM_RX_0"
132 #define LPASS_BE_QUAT_TDM_TX_0 "QUAT_TDM_TX_0"
133 #define LPASS_BE_QUAT_TDM_RX_1 "QUAT_TDM_RX_1"
134 #define LPASS_BE_QUAT_TDM_TX_1 "QUAT_TDM_TX_1"
135 #define LPASS_BE_QUAT_TDM_RX_2 "QUAT_TDM_RX_2"
136 #define LPASS_BE_QUAT_TDM_TX_2 "QUAT_TDM_TX_2"
137 #define LPASS_BE_QUAT_TDM_RX_3 "QUAT_TDM_RX_3"
138 #define LPASS_BE_QUAT_TDM_TX_3 "QUAT_TDM_TX_3"
139 #define LPASS_BE_QUAT_TDM_RX_4 "QUAT_TDM_RX_4"
140 #define LPASS_BE_QUAT_TDM_TX_4 "QUAT_TDM_TX_4"
141 #define LPASS_BE_QUAT_TDM_RX_5 "QUAT_TDM_RX_5"
142 #define LPASS_BE_QUAT_TDM_TX_5 "QUAT_TDM_TX_5"
143 #define LPASS_BE_QUAT_TDM_RX_6 "QUAT_TDM_RX_6"
144 #define LPASS_BE_QUAT_TDM_TX_6 "QUAT_TDM_TX_6"
145 #define LPASS_BE_QUAT_TDM_RX_7 "QUAT_TDM_RX_7"
146 #define LPASS_BE_QUAT_TDM_TX_7 "QUAT_TDM_TX_7"
148 #define LPASS_BE_SLIMBUS_7_RX "SLIMBUS_7_RX"
149 #define LPASS_BE_SLIMBUS_7_TX "SLIMBUS_7_TX"
150 #define LPASS_BE_SLIMBUS_8_RX "SLIMBUS_8_RX"
151 #define LPASS_BE_SLIMBUS_8_TX "SLIMBUS_8_TX"
153 #define LPASS_BE_USB_AUDIO_RX "USB_AUDIO_RX"
154 #define LPASS_BE_USB_AUDIO_TX "USB_AUDIO_TX"
156 #define LPASS_BE_INT0_MI2S_RX "INT0_MI2S_RX"
157 #define LPASS_BE_INT0_MI2S_TX "INT0_MI2S_TX"
158 #define LPASS_BE_INT1_MI2S_RX "INT1_MI2S_RX"
159 #define LPASS_BE_INT1_MI2S_TX "INT1_MI2S_TX"
160 #define LPASS_BE_INT2_MI2S_RX "INT2_MI2S_RX"
161 #define LPASS_BE_INT2_MI2S_TX "INT2_MI2S_TX"
162 #define LPASS_BE_INT3_MI2S_RX "INT3_MI2S_RX"
163 #define LPASS_BE_INT3_MI2S_TX "INT3_MI2S_TX"
164 #define LPASS_BE_INT4_MI2S_RX "INT4_MI2S_RX"
165 #define LPASS_BE_INT4_MI2S_TX "INT4_MI2S_TX"
166 #define LPASS_BE_INT5_MI2S_RX "INT5_MI2S_RX"
167 #define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
168 #define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
169 #define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
170 /* For multimedia front-ends, asm session is allocated dynamically.
171 * Hence, asm session/multimedia front-end mapping has to be maintained.
172 * Due to this reason, additional multimedia front-end must be placed before
173 * non-multimedia front-ends.
177 MSM_FRONTEND_DAI_MULTIMEDIA1 = 0,
178 MSM_FRONTEND_DAI_MULTIMEDIA2,
179 MSM_FRONTEND_DAI_MULTIMEDIA3,
180 MSM_FRONTEND_DAI_MULTIMEDIA4,
181 MSM_FRONTEND_DAI_MULTIMEDIA5,
182 MSM_FRONTEND_DAI_MULTIMEDIA6,
183 MSM_FRONTEND_DAI_MULTIMEDIA7,
184 MSM_FRONTEND_DAI_MULTIMEDIA8,
185 MSM_FRONTEND_DAI_MULTIMEDIA9,
186 MSM_FRONTEND_DAI_MULTIMEDIA10,
187 MSM_FRONTEND_DAI_MULTIMEDIA11,
188 MSM_FRONTEND_DAI_MULTIMEDIA12,
189 MSM_FRONTEND_DAI_MULTIMEDIA13,
190 MSM_FRONTEND_DAI_MULTIMEDIA14,
191 MSM_FRONTEND_DAI_MULTIMEDIA15,
192 MSM_FRONTEND_DAI_MULTIMEDIA16,
193 MSM_FRONTEND_DAI_MULTIMEDIA17,
194 MSM_FRONTEND_DAI_MULTIMEDIA18,
195 MSM_FRONTEND_DAI_MULTIMEDIA19,
196 MSM_FRONTEND_DAI_MULTIMEDIA20,
197 MSM_FRONTEND_DAI_MULTIMEDIA21,
198 MSM_FRONTEND_DAI_MULTIMEDIA22,
199 MSM_FRONTEND_DAI_MULTIMEDIA23,
200 MSM_FRONTEND_DAI_MULTIMEDIA24,
201 MSM_FRONTEND_DAI_MULTIMEDIA25,
202 MSM_FRONTEND_DAI_MULTIMEDIA26,
203 MSM_FRONTEND_DAI_MULTIMEDIA27,
204 MSM_FRONTEND_DAI_MULTIMEDIA28,
205 MSM_FRONTEND_DAI_MULTIMEDIA29,
206 MSM_FRONTEND_DAI_CS_VOICE,
207 MSM_FRONTEND_DAI_VOIP,
208 MSM_FRONTEND_DAI_AFE_RX,
209 MSM_FRONTEND_DAI_AFE_TX,
210 MSM_FRONTEND_DAI_VOICE_STUB,
211 MSM_FRONTEND_DAI_VOLTE,
212 MSM_FRONTEND_DAI_DTMF_RX,
213 MSM_FRONTEND_DAI_VOICE2,
214 MSM_FRONTEND_DAI_QCHAT,
215 MSM_FRONTEND_DAI_VOLTE_STUB,
216 MSM_FRONTEND_DAI_LSM1,
217 MSM_FRONTEND_DAI_LSM2,
218 MSM_FRONTEND_DAI_LSM3,
219 MSM_FRONTEND_DAI_LSM4,
220 MSM_FRONTEND_DAI_LSM5,
221 MSM_FRONTEND_DAI_LSM6,
222 MSM_FRONTEND_DAI_LSM7,
223 MSM_FRONTEND_DAI_LSM8,
224 MSM_FRONTEND_DAI_VOICE2_STUB,
225 MSM_FRONTEND_DAI_VOWLAN,
226 MSM_FRONTEND_DAI_VOICEMMODE1,
227 MSM_FRONTEND_DAI_VOICEMMODE2,
228 MSM_FRONTEND_DAI_MAX,
231 #define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA29 + 1)
232 #define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA29
235 MSM_BACKEND_DAI_PRI_I2S_RX = 0,
236 MSM_BACKEND_DAI_PRI_I2S_TX,
237 MSM_BACKEND_DAI_SLIMBUS_0_RX,
238 MSM_BACKEND_DAI_SLIMBUS_0_TX,
239 MSM_BACKEND_DAI_HDMI_RX,
240 MSM_BACKEND_DAI_INT_BT_SCO_RX,
241 MSM_BACKEND_DAI_INT_BT_SCO_TX,
242 MSM_BACKEND_DAI_INT_FM_RX,
243 MSM_BACKEND_DAI_INT_FM_TX,
244 MSM_BACKEND_DAI_AFE_PCM_RX,
245 MSM_BACKEND_DAI_AFE_PCM_TX,
246 MSM_BACKEND_DAI_AUXPCM_RX,
247 MSM_BACKEND_DAI_AUXPCM_TX,
248 MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
249 MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
250 MSM_BACKEND_DAI_INCALL_RECORD_RX,
251 MSM_BACKEND_DAI_INCALL_RECORD_TX,
252 MSM_BACKEND_DAI_MI2S_RX,
253 MSM_BACKEND_DAI_MI2S_TX,
254 MSM_BACKEND_DAI_SEC_I2S_RX,
255 MSM_BACKEND_DAI_SLIMBUS_1_RX,
256 MSM_BACKEND_DAI_SLIMBUS_1_TX,
257 MSM_BACKEND_DAI_SLIMBUS_2_RX,
258 MSM_BACKEND_DAI_SLIMBUS_2_TX,
259 MSM_BACKEND_DAI_SLIMBUS_3_RX,
260 MSM_BACKEND_DAI_SLIMBUS_3_TX,
261 MSM_BACKEND_DAI_SLIMBUS_4_RX,
262 MSM_BACKEND_DAI_SLIMBUS_4_TX,
263 MSM_BACKEND_DAI_SLIMBUS_5_RX,
264 MSM_BACKEND_DAI_SLIMBUS_5_TX,
265 MSM_BACKEND_DAI_SLIMBUS_6_RX,
266 MSM_BACKEND_DAI_SLIMBUS_6_TX,
267 MSM_BACKEND_DAI_SLIMBUS_7_RX,
268 MSM_BACKEND_DAI_SLIMBUS_7_TX,
269 MSM_BACKEND_DAI_SLIMBUS_8_RX,
270 MSM_BACKEND_DAI_SLIMBUS_8_TX,
271 MSM_BACKEND_DAI_EXTPROC_RX,
272 MSM_BACKEND_DAI_EXTPROC_TX,
273 MSM_BACKEND_DAI_EXTPROC_EC_TX,
274 MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
275 MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
276 MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
277 MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
278 MSM_BACKEND_DAI_PRI_MI2S_RX,
279 MSM_BACKEND_DAI_PRI_MI2S_TX,
280 MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
281 MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
282 MSM_BACKEND_DAI_AUDIO_I2S_RX,
283 MSM_BACKEND_DAI_SEC_AUXPCM_RX,
284 MSM_BACKEND_DAI_SEC_AUXPCM_TX,
285 MSM_BACKEND_DAI_SPDIF_RX,
286 MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1,
287 MSM_BACKEND_DAI_QUINARY_MI2S_RX,
288 MSM_BACKEND_DAI_QUINARY_MI2S_TX,
289 MSM_BACKEND_DAI_SENARY_MI2S_TX,
290 MSM_BACKEND_DAI_PRI_TDM_RX_0,
291 MSM_BACKEND_DAI_PRI_TDM_TX_0,
292 MSM_BACKEND_DAI_PRI_TDM_RX_1,
293 MSM_BACKEND_DAI_PRI_TDM_TX_1,
294 MSM_BACKEND_DAI_PRI_TDM_RX_2,
295 MSM_BACKEND_DAI_PRI_TDM_TX_2,
296 MSM_BACKEND_DAI_PRI_TDM_RX_3,
297 MSM_BACKEND_DAI_PRI_TDM_TX_3,
298 MSM_BACKEND_DAI_PRI_TDM_RX_4,
299 MSM_BACKEND_DAI_PRI_TDM_TX_4,
300 MSM_BACKEND_DAI_PRI_TDM_RX_5,
301 MSM_BACKEND_DAI_PRI_TDM_TX_5,
302 MSM_BACKEND_DAI_PRI_TDM_RX_6,
303 MSM_BACKEND_DAI_PRI_TDM_TX_6,
304 MSM_BACKEND_DAI_PRI_TDM_RX_7,
305 MSM_BACKEND_DAI_PRI_TDM_TX_7,
306 MSM_BACKEND_DAI_SEC_TDM_RX_0,
307 MSM_BACKEND_DAI_SEC_TDM_TX_0,
308 MSM_BACKEND_DAI_SEC_TDM_RX_1,
309 MSM_BACKEND_DAI_SEC_TDM_TX_1,
310 MSM_BACKEND_DAI_SEC_TDM_RX_2,
311 MSM_BACKEND_DAI_SEC_TDM_TX_2,
312 MSM_BACKEND_DAI_SEC_TDM_RX_3,
313 MSM_BACKEND_DAI_SEC_TDM_TX_3,
314 MSM_BACKEND_DAI_SEC_TDM_RX_4,
315 MSM_BACKEND_DAI_SEC_TDM_TX_4,
316 MSM_BACKEND_DAI_SEC_TDM_RX_5,
317 MSM_BACKEND_DAI_SEC_TDM_TX_5,
318 MSM_BACKEND_DAI_SEC_TDM_RX_6,
319 MSM_BACKEND_DAI_SEC_TDM_TX_6,
320 MSM_BACKEND_DAI_SEC_TDM_RX_7,
321 MSM_BACKEND_DAI_SEC_TDM_TX_7,
322 MSM_BACKEND_DAI_TERT_TDM_RX_0,
323 MSM_BACKEND_DAI_TERT_TDM_TX_0,
324 MSM_BACKEND_DAI_TERT_TDM_RX_1,
325 MSM_BACKEND_DAI_TERT_TDM_TX_1,
326 MSM_BACKEND_DAI_TERT_TDM_RX_2,
327 MSM_BACKEND_DAI_TERT_TDM_TX_2,
328 MSM_BACKEND_DAI_TERT_TDM_RX_3,
329 MSM_BACKEND_DAI_TERT_TDM_TX_3,
330 MSM_BACKEND_DAI_TERT_TDM_RX_4,
331 MSM_BACKEND_DAI_TERT_TDM_TX_4,
332 MSM_BACKEND_DAI_TERT_TDM_RX_5,
333 MSM_BACKEND_DAI_TERT_TDM_TX_5,
334 MSM_BACKEND_DAI_TERT_TDM_RX_6,
335 MSM_BACKEND_DAI_TERT_TDM_TX_6,
336 MSM_BACKEND_DAI_TERT_TDM_RX_7,
337 MSM_BACKEND_DAI_TERT_TDM_TX_7,
338 MSM_BACKEND_DAI_QUAT_TDM_RX_0,
339 MSM_BACKEND_DAI_QUAT_TDM_TX_0,
340 MSM_BACKEND_DAI_QUAT_TDM_RX_1,
341 MSM_BACKEND_DAI_QUAT_TDM_TX_1,
342 MSM_BACKEND_DAI_QUAT_TDM_RX_2,
343 MSM_BACKEND_DAI_QUAT_TDM_TX_2,
344 MSM_BACKEND_DAI_QUAT_TDM_RX_3,
345 MSM_BACKEND_DAI_QUAT_TDM_TX_3,
346 MSM_BACKEND_DAI_QUAT_TDM_RX_4,
347 MSM_BACKEND_DAI_QUAT_TDM_TX_4,
348 MSM_BACKEND_DAI_QUAT_TDM_RX_5,
349 MSM_BACKEND_DAI_QUAT_TDM_TX_5,
350 MSM_BACKEND_DAI_QUAT_TDM_RX_6,
351 MSM_BACKEND_DAI_QUAT_TDM_TX_6,
352 MSM_BACKEND_DAI_QUAT_TDM_RX_7,
353 MSM_BACKEND_DAI_QUAT_TDM_TX_7,
354 MSM_BACKEND_DAI_INT_BT_A2DP_RX,
355 MSM_BACKEND_DAI_USB_RX,
356 MSM_BACKEND_DAI_USB_TX,
357 MSM_BACKEND_DAI_DISPLAY_PORT_RX,
358 MSM_BACKEND_DAI_TERT_AUXPCM_RX,
359 MSM_BACKEND_DAI_TERT_AUXPCM_TX,
360 MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
361 MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
362 MSM_BACKEND_DAI_INT0_MI2S_RX,
363 MSM_BACKEND_DAI_INT0_MI2S_TX,
364 MSM_BACKEND_DAI_INT1_MI2S_RX,
365 MSM_BACKEND_DAI_INT1_MI2S_TX,
366 MSM_BACKEND_DAI_INT2_MI2S_RX,
367 MSM_BACKEND_DAI_INT2_MI2S_TX,
368 MSM_BACKEND_DAI_INT3_MI2S_RX,
369 MSM_BACKEND_DAI_INT3_MI2S_TX,
370 MSM_BACKEND_DAI_INT4_MI2S_RX,
371 MSM_BACKEND_DAI_INT4_MI2S_TX,
372 MSM_BACKEND_DAI_INT5_MI2S_RX,
373 MSM_BACKEND_DAI_INT5_MI2S_TX,
374 MSM_BACKEND_DAI_INT6_MI2S_RX,
375 MSM_BACKEND_DAI_INT6_MI2S_TX,
379 enum msm_pcm_routing_event {
380 MSM_PCM_RT_EVT_BUF_RECFG,
381 MSM_PCM_RT_EVT_DEVSWITCH,
387 EXT_EC_REF_PRI_MI2S_TX,
388 EXT_EC_REF_SEC_MI2S_TX,
389 EXT_EC_REF_TERT_MI2S_TX,
390 EXT_EC_REF_QUAT_MI2S_TX,
391 EXT_EC_REF_QUIN_MI2S_TX,
392 EXT_EC_REF_SLIM_1_TX,
395 #define INVALID_SESSION -1
396 #define SESSION_TYPE_RX 0
397 #define SESSION_TYPE_TX 1
398 #define MAX_SESSION_TYPES 2
399 #define INT_RX_VOL_MAX_STEPS 0x2000
400 #define INT_RX_VOL_GAIN 0x2000
402 #define RELEASE_LOCK 0
403 #define ACQUIRE_LOCK 1
405 #define HDMI_RX_ID 0x8001
408 ADM_PP_PARAM_MUTE_ID,
409 ADM_PP_PARAM_LATENCY_ID,
410 ADM_PP_PARAM_LIMITER_ID
414 ADM_PP_PARAM_MUTE_BIT = 0x1,
415 ADM_PP_PARAM_LATENCY_BIT = 0x2,
416 ADM_PP_PARAM_LIMITER_BIT = 0x4
419 #define BE_DAI_PORT_SESSIONS_IDX_MAX 4
420 #define BE_DAI_FE_SESSIONS_IDX_MAX 2
422 struct msm_pcm_routing_evt {
423 void (*event_func)(enum msm_pcm_routing_event, void *);
427 struct msm_pcm_routing_bdai_data {
428 u16 port_id; /* AFE port ID */
429 u8 active; /* track if this backend is enabled */
431 /* Front-end sessions */
432 unsigned long fe_sessions[BE_DAI_FE_SESSIONS_IDX_MAX];
434 * Track Tx BE ports -> Rx BE ports.
435 * port_sessions[0] used to track BE 0 to BE 63.
436 * port_sessions[1] used to track BE 64 to BE 127.
437 * port_sessions[2] used to track BE 128 to BE 191.
438 * port_sessions[3] used to track BE 192 to BE 255.
440 u64 port_sessions[BE_DAI_PORT_SESSIONS_IDX_MAX];
442 unsigned int sample_rate;
443 unsigned int channel;
445 unsigned int adm_override_ch;
446 u32 passthr_mode[MSM_FRONTEND_DAI_MAX];
450 struct msm_pcm_routing_fdai_data {
451 u16 be_srate; /* track prior backend sample rate for flushing purpose */
452 int strm_id; /* ASM stream ID */
454 struct msm_pcm_routing_evt event_info;
457 #define MAX_APP_TYPES 16
458 struct msm_pcm_routing_app_type_data {
464 struct msm_pcm_stream_app_type_cfg {
470 /* dai_id: front-end ID,
471 * dspst_id: DSP audio stream ID
472 * stream_type: playback or capture
474 int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, int dspst_id,
476 void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
478 int msm_pcm_routing_reg_phy_compr_stream(int fedai_id, int perf_mode,
479 int dspst_id, int stream_type,
480 uint32_t compr_passthr);
482 int msm_pcm_routing_reg_phy_stream_v2(int fedai_id, int perf_mode,
483 int dspst_id, int stream_type,
484 struct msm_pcm_routing_evt event_info);
486 void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
488 int msm_routing_check_backend_enabled(int fedai_id);
491 void msm_pcm_routing_get_bedai_info(int be_idx,
492 struct msm_pcm_routing_bdai_data *bedai);
493 void msm_pcm_routing_get_fedai_info(int fe_idx, int sess_type,
494 struct msm_pcm_routing_fdai_data *fe_dai);
495 void msm_pcm_routing_acquire_lock(void);
496 void msm_pcm_routing_release_lock(void);
498 int msm_pcm_routing_reg_stream_app_type_cfg(
499 int fedai_id, int session_type, int be_id,
500 struct msm_pcm_stream_app_type_cfg *cfg_data);
501 int msm_pcm_routing_get_stream_app_type_cfg(
502 int fedai_id, int session_type, int *be_id,
503 struct msm_pcm_stream_app_type_cfg *cfg_data);
504 int msm_routing_set_downmix_control_data(int be_id, int session_id,
505 struct asm_stream_pan_ctrl_params *pan_param);
506 int msm_pcm_routing_set_channel_mixer_runtime(
507 int be_id, int session_id,
509 struct msm_pcm_channel_mixer *params);
511 int msm_pcm_routing_set_channel_mixer_cfg(
512 int fe_id, int session_type,
513 struct msm_pcm_channel_mixer *params);
514 #endif /*_MSM_PCM_H*/