sound/soc/omap/mcbsp.c

   1 /*
   2  * sound/soc/omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Multichannel mode not supported.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27 #include <linux/pm_runtime.h>
  28
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30
  31 #include <plat/cpu.h>
  32
  33 #include "mcbsp.h"
  34
  35 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  36 {
  37         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  38
  39         if (mcbsp->pdata->reg_size == 2) {
  40                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  41                 __raw_writew((u16)val, addr);
  42         } else {
  43                 ((u32 *)mcbsp->reg_cache)[reg] = val;
  44                 __raw_writel(val, addr);
  45         }
  46 }
  47
  48 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  49 {
  50         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  51
  52         if (mcbsp->pdata->reg_size == 2) {
  53                 return !from_cache ? __raw_readw(addr) :
  54                                      ((u16 *)mcbsp->reg_cache)[reg];
  55         } else {
  56                 return !from_cache ? __raw_readl(addr) :
  57                                      ((u32 *)mcbsp->reg_cache)[reg];
  58         }
  59 }
  60
  61 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  62 {
  63         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  64 }
  65
  66 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  67 {
  68         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  69 }
  70
  71 #define MCBSP_READ(mcbsp, reg) \
  72                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  73 #define MCBSP_WRITE(mcbsp, reg, val) \
  74                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  75 #define MCBSP_READ_CACHE(mcbsp, reg) \
  76                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  77
  78 #define MCBSP_ST_READ(mcbsp, reg) \
  79                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  80 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  81                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  82
  83 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  84 {
  85         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  86         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  87                         MCBSP_READ(mcbsp, DRR2));
  88         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  89                         MCBSP_READ(mcbsp, DRR1));
  90         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  91                         MCBSP_READ(mcbsp, DXR2));
  92         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  93                         MCBSP_READ(mcbsp, DXR1));
  94         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  95                         MCBSP_READ(mcbsp, SPCR2));
  96         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  97                         MCBSP_READ(mcbsp, SPCR1));
  98         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  99                         MCBSP_READ(mcbsp, RCR2));
 100         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 101                         MCBSP_READ(mcbsp, RCR1));
 102         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 103                         MCBSP_READ(mcbsp, XCR2));
 104         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 105                         MCBSP_READ(mcbsp, XCR1));
 106         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 107                         MCBSP_READ(mcbsp, SRGR2));
 108         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 109                         MCBSP_READ(mcbsp, SRGR1));
 110         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 111                         MCBSP_READ(mcbsp, PCR0));
 112         dev_dbg(mcbsp->dev, "***********************\n");
 113 }
 114
 115 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
 116 {
 117         struct omap_mcbsp *mcbsp = dev_id;
 118         u16 irqst;
 119
 120         irqst = MCBSP_READ(mcbsp, IRQST);
 121         dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
 122
 123         if (irqst & RSYNCERREN)
 124                 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 125         if (irqst & RFSREN)
 126                 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 127         if (irqst & REOFEN)
 128                 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 129         if (irqst & RRDYEN)
 130                 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 131         if (irqst & RUNDFLEN)
 132                 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 133         if (irqst & ROVFLEN)
 134                 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 135
 136         if (irqst & XSYNCERREN)
 137                 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 138         if (irqst & XFSXEN)
 139                 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 140         if (irqst & XEOFEN)
 141                 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 142         if (irqst & XRDYEN)
 143                 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 144         if (irqst & XUNDFLEN)
 145                 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 146         if (irqst & XOVFLEN)
 147                 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 148         if (irqst & XEMPTYEOFEN)
 149                 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 150
 151         MCBSP_WRITE(mcbsp, IRQST, irqst);
 152
 153         return IRQ_HANDLED;
 154 }
 155
 156 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 157 {
 158         struct omap_mcbsp *mcbsp_tx = dev_id;
 159         u16 irqst_spcr2;
 160
 161         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 162         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 163
 164         if (irqst_spcr2 & XSYNC_ERR) {
 165                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 166                         irqst_spcr2);
 167                 /* Writing zero to XSYNC_ERR clears the IRQ */
 168                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 169         }
 170
 171         return IRQ_HANDLED;
 172 }
 173
 174 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 175 {
 176         struct omap_mcbsp *mcbsp_rx = dev_id;
 177         u16 irqst_spcr1;
 178
 179         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 180         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 181
 182         if (irqst_spcr1 & RSYNC_ERR) {
 183                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 184                         irqst_spcr1);
 185                 /* Writing zero to RSYNC_ERR clears the IRQ */
 186                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 187         }
 188
 189         return IRQ_HANDLED;
 190 }
 191
 192 /*
 193  * omap_mcbsp_config simply write a config to the
 194  * appropriate McBSP.
 195  * You either call this function or set the McBSP registers
 196  * by yourself before calling omap_mcbsp_start().
 197  */
 198 void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 199                        const struct omap_mcbsp_reg_cfg *config)
 200 {
 201         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 202                         mcbsp->id, mcbsp->phys_base);
 203
 204         /* We write the given config */
 205         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 206         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 207         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 208         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 209         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 210         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 211         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 212         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 213         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 214         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 215         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 216         if (mcbsp->pdata->has_ccr) {
 217                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 218                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 219         }
 220         /* Enable wakeup behavior */
 221         if (mcbsp->pdata->has_wakeup)
 222                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 223
 224         /* Enable TX/RX sync error interrupts by default */
 225         if (mcbsp->irq)
 226                 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
 227 }
 228
 229 /**
 230  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 231  * @id - mcbsp id
 232  * @stream - indicates the direction of data flow (rx or tx)
 233  *
 234  * Returns the address of mcbsp data transmit register or data receive register
 235  * to be used by DMA for transferring/receiving data based on the value of
 236  * @stream for the requested mcbsp given by @id
 237  */
 238 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 239                                      unsigned int stream)
 240 {
 241         int data_reg;
 242
 243         if (mcbsp->pdata->reg_size == 2) {
 244                 if (stream)
 245                         data_reg = OMAP_MCBSP_REG_DRR1;
 246                 else
 247                         data_reg = OMAP_MCBSP_REG_DXR1;
 248         } else {
 249                 if (stream)
 250                         data_reg = OMAP_MCBSP_REG_DRR;
 251                 else
 252                         data_reg = OMAP_MCBSP_REG_DXR;
 253         }
 254
 255         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 256 }
 257
 258 static void omap_st_on(struct omap_mcbsp *mcbsp)
 259 {
 260         unsigned int w;
 261
 262         if (mcbsp->pdata->enable_st_clock)
 263                 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
 264
 265         /* Enable McBSP Sidetone */
 266         w = MCBSP_READ(mcbsp, SSELCR);
 267         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 268
 269         /* Enable Sidetone from Sidetone Core */
 270         w = MCBSP_ST_READ(mcbsp, SSELCR);
 271         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 272 }
 273
 274 static void omap_st_off(struct omap_mcbsp *mcbsp)
 275 {
 276         unsigned int w;
 277
 278         w = MCBSP_ST_READ(mcbsp, SSELCR);
 279         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 280
 281         w = MCBSP_READ(mcbsp, SSELCR);
 282         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 283
 284         if (mcbsp->pdata->enable_st_clock)
 285                 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
 286 }
 287
 288 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 289 {
 290         u16 val, i;
 291
 292         val = MCBSP_ST_READ(mcbsp, SSELCR);
 293
 294         if (val & ST_COEFFWREN)
 295                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 296
 297         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 298
 299         for (i = 0; i < 128; i++)
 300                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 301
 302         i = 0;
 303
 304         val = MCBSP_ST_READ(mcbsp, SSELCR);
 305         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 306                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 307
 308         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 309
 310         if (i == 1000)
 311                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 312 }
 313
 314 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 315 {
 316         u16 w;
 317         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 318
 319         w = MCBSP_ST_READ(mcbsp, SSELCR);
 320
 321         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 322                       ST_CH1GAIN(st_data->ch1gain));
 323 }
 324
 325 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
 326 {
 327         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 328         int ret = 0;
 329
 330         if (!st_data)
 331                 return -ENOENT;
 332
 333         spin_lock_irq(&mcbsp->lock);
 334         if (channel == 0)
 335                 st_data->ch0gain = chgain;
 336         else if (channel == 1)
 337                 st_data->ch1gain = chgain;
 338         else
 339                 ret = -EINVAL;
 340
 341         if (st_data->enabled)
 342                 omap_st_chgain(mcbsp);
 343         spin_unlock_irq(&mcbsp->lock);
 344
 345         return ret;
 346 }
 347
 348 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
 349 {
 350         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 351         int ret = 0;
 352
 353         if (!st_data)
 354                 return -ENOENT;
 355
 356         spin_lock_irq(&mcbsp->lock);
 357         if (channel == 0)
 358                 *chgain = st_data->ch0gain;
 359         else if (channel == 1)
 360                 *chgain = st_data->ch1gain;
 361         else
 362                 ret = -EINVAL;
 363         spin_unlock_irq(&mcbsp->lock);
 364
 365         return ret;
 366 }
 367
 368 static int omap_st_start(struct omap_mcbsp *mcbsp)
 369 {
 370         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 371
 372         if (st_data->enabled && !st_data->running) {
 373                 omap_st_fir_write(mcbsp, st_data->taps);
 374                 omap_st_chgain(mcbsp);
 375
 376                 if (!mcbsp->free) {
 377                         omap_st_on(mcbsp);
 378                         st_data->running = 1;
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 int omap_st_enable(struct omap_mcbsp *mcbsp)
 386 {
 387         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 388
 389         if (!st_data)
 390                 return -ENODEV;
 391
 392         spin_lock_irq(&mcbsp->lock);
 393         st_data->enabled = 1;
 394         omap_st_start(mcbsp);
 395         spin_unlock_irq(&mcbsp->lock);
 396
 397         return 0;
 398 }
 399
 400 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 401 {
 402         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 403
 404         if (st_data->running) {
 405                 if (!mcbsp->free) {
 406                         omap_st_off(mcbsp);
 407                         st_data->running = 0;
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int omap_st_disable(struct omap_mcbsp *mcbsp)
 415 {
 416         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 417         int ret = 0;
 418
 419         if (!st_data)
 420                 return -ENODEV;
 421
 422         spin_lock_irq(&mcbsp->lock);
 423         omap_st_stop(mcbsp);
 424         st_data->enabled = 0;
 425         spin_unlock_irq(&mcbsp->lock);
 426
 427         return ret;
 428 }
 429
 430 int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
 431 {
 432         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 433
 434         if (!st_data)
 435                 return -ENODEV;
 436
 437         return st_data->enabled;
 438 }
 439
 440 /*
 441  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 442  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 443  * for the THRSH2 register.
 444  */
 445 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 446 {
 447         if (mcbsp->pdata->buffer_size == 0)
 448                 return;
 449
 450         if (threshold && threshold <= mcbsp->max_tx_thres)
 451                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 452 }
 453
 454 /*
 455  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 456  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 457  * for the THRSH1 register.
 458  */
 459 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 460 {
 461         if (mcbsp->pdata->buffer_size == 0)
 462                 return;
 463
 464         if (threshold && threshold <= mcbsp->max_rx_thres)
 465                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 466 }
 467
 468 /*
 469  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 470  */
 471 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 472 {
 473         u16 buffstat;
 474
 475         if (mcbsp->pdata->buffer_size == 0)
 476                 return 0;
 477
 478         /* Returns the number of free locations in the buffer */
 479         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 480
 481         /* Number of slots are different in McBSP ports */
 482         return mcbsp->pdata->buffer_size - buffstat;
 483 }
 484
 485 /*
 486  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 487  * to reach the threshold value (when the DMA will be triggered to read it)
 488  */
 489 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 490 {
 491         u16 buffstat, threshold;
 492
 493         if (mcbsp->pdata->buffer_size == 0)
 494                 return 0;
 495
 496         /* Returns the number of used locations in the buffer */
 497         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 498         /* RX threshold */
 499         threshold = MCBSP_READ(mcbsp, THRSH1);
 500
 501         /* Return the number of location till we reach the threshold limit */
 502         if (threshold <= buffstat)
 503                 return 0;
 504         else
 505                 return threshold - buffstat;
 506 }
 507
 508 int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 509 {
 510         void *reg_cache;
 511         int err;
 512
 513         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 514         if (!reg_cache) {
 515                 return -ENOMEM;
 516         }
 517
 518         spin_lock(&mcbsp->lock);
 519         if (!mcbsp->free) {
 520                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 521                         mcbsp->id);
 522                 err = -EBUSY;
 523                 goto err_kfree;
 524         }
 525
 526         mcbsp->free = false;
 527         mcbsp->reg_cache = reg_cache;
 528         spin_unlock(&mcbsp->lock);
 529
 530         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 531                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 532
 533         /*
 534          * Make sure that transmitter, receiver and sample-rate generator are
 535          * not running before activating IRQs.
 536          */
 537         MCBSP_WRITE(mcbsp, SPCR1, 0);
 538         MCBSP_WRITE(mcbsp, SPCR2, 0);
 539
 540         if (mcbsp->irq) {
 541                 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 542                                   "McBSP", (void *)mcbsp);
 543                 if (err != 0) {
 544                         dev_err(mcbsp->dev, "Unable to request IRQ\n");
 545                         goto err_clk_disable;
 546                 }
 547         } else {
 548                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 549                                   "McBSP TX", (void *)mcbsp);
 550                 if (err != 0) {
 551                         dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 552                         goto err_clk_disable;
 553                 }
 554
 555                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 556                                   "McBSP RX", (void *)mcbsp);
 557                 if (err != 0) {
 558                         dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 559                         goto err_free_irq;
 560                 }
 561         }
 562
 563         return 0;
 564 err_free_irq:
 565         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 566 err_clk_disable:
 567         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 568                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 569
 570         /* Disable wakeup behavior */
 571         if (mcbsp->pdata->has_wakeup)
 572                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 573
 574         spin_lock(&mcbsp->lock);
 575         mcbsp->free = true;
 576         mcbsp->reg_cache = NULL;
 577 err_kfree:
 578         spin_unlock(&mcbsp->lock);
 579         kfree(reg_cache);
 580
 581         return err;
 582 }
 583
 584 void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 585 {
 586         void *reg_cache;
 587
 588         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 589                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 590
 591         /* Disable wakeup behavior */
 592         if (mcbsp->pdata->has_wakeup)
 593                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 594
 595         /* Disable interrupt requests */
 596         if (mcbsp->irq)
 597                 MCBSP_WRITE(mcbsp, IRQEN, 0);
 598
 599         if (mcbsp->irq) {
 600                 free_irq(mcbsp->irq, (void *)mcbsp);
 601         } else {
 602                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 603                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 604         }
 605
 606         reg_cache = mcbsp->reg_cache;
 607
 608         /*
 609          * Select CLKS source from internal source unconditionally before
 610          * marking the McBSP port as free.
 611          * If the external clock source via MCBSP_CLKS pin has been selected the
 612          * system will refuse to enter idle if the CLKS pin source is not reset
 613          * back to internal source.
 614          */
 615         if (!cpu_class_is_omap1())
 616                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 617
 618         spin_lock(&mcbsp->lock);
 619         if (mcbsp->free)
 620                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 621         else
 622                 mcbsp->free = true;
 623         mcbsp->reg_cache = NULL;
 624         spin_unlock(&mcbsp->lock);
 625
 626         if (reg_cache)
 627                 kfree(reg_cache);
 628 }
 629
 630 /*
 631  * Here we start the McBSP, by enabling transmitter, receiver or both.
 632  * If no transmitter or receiver is active prior calling, then sample-rate
 633  * generator and frame sync are started.
 634  */
 635 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
 636 {
 637         int enable_srg = 0;
 638         u16 w;
 639
 640         if (mcbsp->st_data)
 641                 omap_st_start(mcbsp);
 642
 643         /* Only enable SRG, if McBSP is master */
 644         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 645         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 646                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 647                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 648
 649         if (enable_srg) {
 650                 /* Start the sample generator */
 651                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 652                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 653         }
 654
 655         /* Enable transmitter and receiver */
 656         tx &= 1;
 657         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 658         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 659
 660         rx &= 1;
 661         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 662         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 663
 664         /*
 665          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 666          * REVISIT: 100us may give enough time for two CLKSRG, however
 667          * due to some unknown PM related, clock gating etc. reason it
 668          * is now at 500us.
 669          */
 670         udelay(500);
 671
 672         if (enable_srg) {
 673                 /* Start frame sync */
 674                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 675                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 676         }
 677
 678         if (mcbsp->pdata->has_ccr) {
 679                 /* Release the transmitter and receiver */
 680                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 681                 w &= ~(tx ? XDISABLE : 0);
 682                 MCBSP_WRITE(mcbsp, XCCR, w);
 683                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 684                 w &= ~(rx ? RDISABLE : 0);
 685                 MCBSP_WRITE(mcbsp, RCCR, w);
 686         }
 687
 688         /* Dump McBSP Regs */
 689         omap_mcbsp_dump_reg(mcbsp);
 690 }
 691
 692 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 693 {
 694         int idle;
 695         u16 w;
 696
 697         /* Reset transmitter */
 698         tx &= 1;
 699         if (mcbsp->pdata->has_ccr) {
 700                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 701                 w |= (tx ? XDISABLE : 0);
 702                 MCBSP_WRITE(mcbsp, XCCR, w);
 703         }
 704         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 705         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 706
 707         /* Reset receiver */
 708         rx &= 1;
 709         if (mcbsp->pdata->has_ccr) {
 710                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 711                 w |= (rx ? RDISABLE : 0);
 712                 MCBSP_WRITE(mcbsp, RCCR, w);
 713         }
 714         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 715         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 716
 717         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 718                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 719
 720         if (idle) {
 721                 /* Reset the sample rate generator */
 722                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 723                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 724         }
 725
 726         if (mcbsp->st_data)
 727                 omap_st_stop(mcbsp);
 728 }
 729
 730 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 731 {
 732         struct clk *fck_src;
 733         const char *src;
 734         int r;
 735
 736         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
 737                 src = "pad_fck";
 738         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
 739                 src = "prcm_fck";
 740         else
 741                 return -EINVAL;
 742
 743         fck_src = clk_get(mcbsp->dev, src);
 744         if (IS_ERR(fck_src)) {
 745                 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
 746                 return -EINVAL;
 747         }
 748
 749         pm_runtime_put_sync(mcbsp->dev);
 750
 751         r = clk_set_parent(mcbsp->fclk, fck_src);
 752         if (r) {
 753                 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
 754                         src);
 755                 clk_put(fck_src);
 756                 return r;
 757         }
 758
 759         pm_runtime_get_sync(mcbsp->dev);
 760
 761         clk_put(fck_src);
 762
 763         return 0;
 764
 765 }
 766
 767 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 768 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 769 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 770 static ssize_t prop##_show(struct device *dev,                          \
 771                         struct device_attribute *attr, char *buf)       \
 772 {                                                                       \
 773         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 774                                                                         \
 775         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 776 }                                                                       \
 777                                                                         \
 778 static ssize_t prop##_store(struct device *dev,                         \
 779                                 struct device_attribute *attr,          \
 780                                 const char *buf, size_t size)           \
 781 {                                                                       \
 782         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 783         unsigned long val;                                              \
 784         int status;                                                     \
 785                                                                         \
 786         status = strict_strtoul(buf, 0, &val);                          \
 787         if (status)                                                     \
 788                 return status;                                          \
 789                                                                         \
 790         if (!valid_threshold(mcbsp, val))                               \
 791                 return -EDOM;                                           \
 792                                                                         \
 793         mcbsp->prop = val;                                              \
 794         return size;                                                    \
 795 }                                                                       \
 796                                                                         \
 797 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
 798
 799 THRESHOLD_PROP_BUILDER(max_tx_thres);
 800 THRESHOLD_PROP_BUILDER(max_rx_thres);
 801
 802 static const char *dma_op_modes[] = {
 803         "element", "threshold",
 804 };
 805
 806 static ssize_t dma_op_mode_show(struct device *dev,
 807                         struct device_attribute *attr, char *buf)
 808 {
 809         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 810         int dma_op_mode, i = 0;
 811         ssize_t len = 0;
 812         const char * const *s;
 813
 814         dma_op_mode = mcbsp->dma_op_mode;
 815
 816         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 817                 if (dma_op_mode == i)
 818                         len += sprintf(buf + len, "[%s] ", *s);
 819                 else
 820                         len += sprintf(buf + len, "%s ", *s);
 821         }
 822         len += sprintf(buf + len, "\n");
 823
 824         return len;
 825 }
 826
 827 static ssize_t dma_op_mode_store(struct device *dev,
 828                                 struct device_attribute *attr,
 829                                 const char *buf, size_t size)
 830 {
 831         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 832         const char * const *s;
 833         int i = 0;
 834
 835         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
 836                 if (sysfs_streq(buf, *s))
 837                         break;
 838
 839         if (i == ARRAY_SIZE(dma_op_modes))
 840                 return -EINVAL;
 841
 842         spin_lock_irq(&mcbsp->lock);
 843         if (!mcbsp->free) {
 844                 size = -EBUSY;
 845                 goto unlock;
 846         }
 847         mcbsp->dma_op_mode = i;
 848
 849 unlock:
 850         spin_unlock_irq(&mcbsp->lock);
 851
 852         return size;
 853 }
 854
 855 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 856
 857 static const struct attribute *additional_attrs[] = {
 858         &dev_attr_max_tx_thres.attr,
 859         &dev_attr_max_rx_thres.attr,
 860         &dev_attr_dma_op_mode.attr,
 861         NULL,
 862 };
 863
 864 static const struct attribute_group additional_attr_group = {
 865         .attrs = (struct attribute **)additional_attrs,
 866 };
 867
 868 static ssize_t st_taps_show(struct device *dev,
 869                             struct device_attribute *attr, char *buf)
 870 {
 871         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 872         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 873         ssize_t status = 0;
 874         int i;
 875
 876         spin_lock_irq(&mcbsp->lock);
 877         for (i = 0; i < st_data->nr_taps; i++)
 878                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
 879                                   st_data->taps[i]);
 880         if (i)
 881                 status += sprintf(&buf[status], "\n");
 882         spin_unlock_irq(&mcbsp->lock);
 883
 884         return status;
 885 }
 886
 887 static ssize_t st_taps_store(struct device *dev,
 888                              struct device_attribute *attr,
 889                              const char *buf, size_t size)
 890 {
 891         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 892         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 893         int val, tmp, status, i = 0;
 894
 895         spin_lock_irq(&mcbsp->lock);
 896         memset(st_data->taps, 0, sizeof(st_data->taps));
 897         st_data->nr_taps = 0;
 898
 899         do {
 900                 status = sscanf(buf, "%d%n", &val, &tmp);
 901                 if (status < 0 || status == 0) {
 902                         size = -EINVAL;
 903                         goto out;
 904                 }
 905                 if (val < -32768 || val > 32767) {
 906                         size = -EINVAL;
 907                         goto out;
 908                 }
 909                 st_data->taps[i++] = val;
 910                 buf += tmp;
 911                 if (*buf != ',')
 912                         break;
 913                 buf++;
 914         } while (1);
 915
 916         st_data->nr_taps = i;
 917
 918 out:
 919         spin_unlock_irq(&mcbsp->lock);
 920
 921         return size;
 922 }
 923
 924 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
 925
 926 static const struct attribute *sidetone_attrs[] = {
 927         &dev_attr_st_taps.attr,
 928         NULL,
 929 };
 930
 931 static const struct attribute_group sidetone_attr_group = {
 932         .attrs = (struct attribute **)sidetone_attrs,
 933 };
 934
 935 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
 936                                  struct resource *res)
 937 {
 938         struct omap_mcbsp_st_data *st_data;
 939         int err;
 940
 941         st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
 942         if (!st_data)
 943                 return -ENOMEM;
 944
 945         st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
 946                                            resource_size(res));
 947         if (!st_data->io_base_st)
 948                 return -ENOMEM;
 949
 950         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
 951         if (err)
 952                 return err;
 953
 954         mcbsp->st_data = st_data;
 955         return 0;
 956 }
 957
 958 /*
 959  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 960  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 961  */
 962 int __devinit omap_mcbsp_init(struct platform_device *pdev)
 963 {
 964         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 965         struct resource *res;
 966         int ret = 0;
 967
 968         spin_lock_init(&mcbsp->lock);
 969         mcbsp->free = true;
 970
 971         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 972         if (!res) {
 973                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 974                 if (!res) {
 975                         dev_err(mcbsp->dev, "invalid memory resource\n");
 976                         return -ENOMEM;
 977                 }
 978         }
 979         if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
 980                                      dev_name(&pdev->dev))) {
 981                 dev_err(mcbsp->dev, "memory region already claimed\n");
 982                 return -ENODEV;
 983         }
 984
 985         mcbsp->phys_base = res->start;
 986         mcbsp->reg_cache_size = resource_size(res);
 987         mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
 988                                       resource_size(res));
 989         if (!mcbsp->io_base)
 990                 return -ENOMEM;
 991
 992         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 993         if (!res)
 994                 mcbsp->phys_dma_base = mcbsp->phys_base;
 995         else
 996                 mcbsp->phys_dma_base = res->start;
 997
 998         /*
 999          * OMAP1, 2 uses two interrupt lines: TX, RX
1000          * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1001          * OMAP4 and newer SoC only have the combined IRQ line.
1002          * Use the combined IRQ if available since it gives better debugging
1003          * possibilities.
1004          */
1005         mcbsp->irq = platform_get_irq_byname(pdev, "common");
1006         if (mcbsp->irq == -ENXIO) {
1007                 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1008
1009                 if (mcbsp->tx_irq == -ENXIO) {
1010                         mcbsp->irq = platform_get_irq(pdev, 0);
1011                         mcbsp->tx_irq = 0;
1012                 } else {
1013                         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1014                         mcbsp->irq = 0;
1015                 }
1016         }
1017
1018         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1019         if (!res) {
1020                 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1021                 return -ENODEV;
1022         }
1023         /* RX DMA request number, and port address configuration */
1024         mcbsp->dma_data[1].name = "Audio Capture";
1025         mcbsp->dma_data[1].dma_req = res->start;
1026         mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1027
1028         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1029         if (!res) {
1030                 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1031                 return -ENODEV;
1032         }
1033         /* TX DMA request number, and port address configuration */
1034         mcbsp->dma_data[0].name = "Audio Playback";
1035         mcbsp->dma_data[0].dma_req = res->start;
1036         mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1037
1038         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1039         if (IS_ERR(mcbsp->fclk)) {
1040                 ret = PTR_ERR(mcbsp->fclk);
1041                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1042                 return ret;
1043         }
1044
1045         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1046         if (mcbsp->pdata->buffer_size) {
1047                 /*
1048                  * Initially configure the maximum thresholds to a safe value.
1049                  * The McBSP FIFO usage with these values should not go under
1050                  * 16 locations.
1051                  * If the whole FIFO without safety buffer is used, than there
1052                  * is a possibility that the DMA will be not able to push the
1053                  * new data on time, causing channel shifts in runtime.
1054                  */
1055                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1056                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1057
1058                 ret = sysfs_create_group(&mcbsp->dev->kobj,
1059                                          &additional_attr_group);
1060                 if (ret) {
1061                         dev_err(mcbsp->dev,
1062                                 "Unable to create additional controls\n");
1063                         goto err_thres;
1064                 }
1065         } else {
1066                 mcbsp->max_tx_thres = -EINVAL;
1067                 mcbsp->max_rx_thres = -EINVAL;
1068         }
1069
1070         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1071         if (res) {
1072                 ret = omap_st_add(mcbsp, res);
1073                 if (ret) {
1074                         dev_err(mcbsp->dev,
1075                                 "Unable to create sidetone controls\n");
1076                         goto err_st;
1077                 }
1078         }
1079
1080         return 0;
1081
1082 err_st:
1083         if (mcbsp->pdata->buffer_size)
1084                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1085 err_thres:
1086         clk_put(mcbsp->fclk);
1087         return ret;
1088 }
1089
1090 void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
1091 {
1092         if (mcbsp->pdata->buffer_size)
1093                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1094
1095         if (mcbsp->st_data)
1096                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1097 }