sound/soc/stm/stm32_i2s.c

   1 /*
   2  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   3  *
   4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   5  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   6  *
   7  * License terms: GPL V2.0.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16  * details.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset.h>
  26 #include <linux/spinlock.h>
  27
  28 #include <sound/dmaengine_pcm.h>
  29 #include <sound/pcm_params.h>
  30
  31 #define STM32_I2S_CR1_REG       0x0
  32 #define STM32_I2S_CFG1_REG      0x08
  33 #define STM32_I2S_CFG2_REG      0x0C
  34 #define STM32_I2S_IER_REG       0x10
  35 #define STM32_I2S_SR_REG        0x14
  36 #define STM32_I2S_IFCR_REG      0x18
  37 #define STM32_I2S_TXDR_REG      0X20
  38 #define STM32_I2S_RXDR_REG      0x30
  39 #define STM32_I2S_CGFR_REG      0X50
  40
  41 /* Bit definition for SPI2S_CR1 register */
  42 #define I2S_CR1_SPE             BIT(0)
  43 #define I2S_CR1_CSTART          BIT(9)
  44 #define I2S_CR1_CSUSP           BIT(10)
  45 #define I2S_CR1_HDDIR           BIT(11)
  46 #define I2S_CR1_SSI             BIT(12)
  47 #define I2S_CR1_CRC33_17        BIT(13)
  48 #define I2S_CR1_RCRCI           BIT(14)
  49 #define I2S_CR1_TCRCI           BIT(15)
  50
  51 /* Bit definition for SPI_CFG2 register */
  52 #define I2S_CFG2_IOSWP_SHIFT    15
  53 #define I2S_CFG2_IOSWP          BIT(I2S_CFG2_IOSWP_SHIFT)
  54 #define I2S_CFG2_LSBFRST        BIT(23)
  55 #define I2S_CFG2_AFCNTR         BIT(31)
  56
  57 /* Bit definition for SPI_CFG1 register */
  58 #define I2S_CFG1_FTHVL_SHIFT    5
  59 #define I2S_CFG1_FTHVL_MASK     GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  60 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
  61
  62 #define I2S_CFG1_TXDMAEN        BIT(15)
  63 #define I2S_CFG1_RXDMAEN        BIT(14)
  64
  65 /* Bit definition for SPI2S_IER register */
  66 #define I2S_IER_RXPIE           BIT(0)
  67 #define I2S_IER_TXPIE           BIT(1)
  68 #define I2S_IER_DPXPIE          BIT(2)
  69 #define I2S_IER_EOTIE           BIT(3)
  70 #define I2S_IER_TXTFIE          BIT(4)
  71 #define I2S_IER_UDRIE           BIT(5)
  72 #define I2S_IER_OVRIE           BIT(6)
  73 #define I2S_IER_CRCEIE          BIT(7)
  74 #define I2S_IER_TIFREIE         BIT(8)
  75 #define I2S_IER_MODFIE          BIT(9)
  76 #define I2S_IER_TSERFIE         BIT(10)
  77
  78 /* Bit definition for SPI2S_SR register */
  79 #define I2S_SR_RXP              BIT(0)
  80 #define I2S_SR_TXP              BIT(1)
  81 #define I2S_SR_DPXP             BIT(2)
  82 #define I2S_SR_EOT              BIT(3)
  83 #define I2S_SR_TXTF             BIT(4)
  84 #define I2S_SR_UDR              BIT(5)
  85 #define I2S_SR_OVR              BIT(6)
  86 #define I2S_SR_CRCERR           BIT(7)
  87 #define I2S_SR_TIFRE            BIT(8)
  88 #define I2S_SR_MODF             BIT(9)
  89 #define I2S_SR_TSERF            BIT(10)
  90 #define I2S_SR_SUSP             BIT(11)
  91 #define I2S_SR_TXC              BIT(12)
  92 #define I2S_SR_RXPLVL           GENMASK(14, 13)
  93 #define I2S_SR_RXWNE            BIT(15)
  94
  95 #define I2S_SR_MASK             GENMASK(15, 0)
  96
  97 /* Bit definition for SPI_IFCR register */
  98 #define I2S_IFCR_EOTC           BIT(3)
  99 #define I2S_IFCR_TXTFC          BIT(4)
 100 #define I2S_IFCR_UDRC           BIT(5)
 101 #define I2S_IFCR_OVRC           BIT(6)
 102 #define I2S_IFCR_CRCEC          BIT(7)
 103 #define I2S_IFCR_TIFREC         BIT(8)
 104 #define I2S_IFCR_MODFC          BIT(9)
 105 #define I2S_IFCR_TSERFC         BIT(10)
 106 #define I2S_IFCR_SUSPC          BIT(11)
 107
 108 #define I2S_IFCR_MASK           GENMASK(11, 3)
 109
 110 /* Bit definition for SPI_I2SCGFR register */
 111 #define I2S_CGFR_I2SMOD         BIT(0)
 112
 113 #define I2S_CGFR_I2SCFG_SHIFT   1
 114 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 115 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
 116
 117 #define I2S_CGFR_I2SSTD_SHIFT   4
 118 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 119 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
 120
 121 #define I2S_CGFR_PCMSYNC        BIT(7)
 122
 123 #define I2S_CGFR_DATLEN_SHIFT   8
 124 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 125 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
 126
 127 #define I2S_CGFR_CHLEN_SHIFT    10
 128 #define I2S_CGFR_CHLEN          BIT(I2S_CGFR_CHLEN_SHIFT)
 129 #define I2S_CGFR_CKPOL          BIT(11)
 130 #define I2S_CGFR_FIXCH          BIT(12)
 131 #define I2S_CGFR_WSINV          BIT(13)
 132 #define I2S_CGFR_DATFMT         BIT(14)
 133
 134 #define I2S_CGFR_I2SDIV_SHIFT   16
 135 #define I2S_CGFR_I2SDIV_BIT_H   23
 136 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 137                                 I2S_CGFR_I2SDIV_SHIFT)
 138 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
 139 #define I2S_CGFR_I2SDIV_MAX     ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 140                                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
 141
 142 #define I2S_CGFR_ODD_SHIFT      24
 143 #define I2S_CGFR_ODD            BIT(I2S_CGFR_ODD_SHIFT)
 144 #define I2S_CGFR_MCKOE          BIT(25)
 145
 146 enum i2s_master_mode {
 147         I2S_MS_NOT_SET,
 148         I2S_MS_MASTER,
 149         I2S_MS_SLAVE,
 150 };
 151
 152 enum i2s_mode {
 153         I2S_I2SMOD_TX_SLAVE,
 154         I2S_I2SMOD_RX_SLAVE,
 155         I2S_I2SMOD_TX_MASTER,
 156         I2S_I2SMOD_RX_MASTER,
 157         I2S_I2SMOD_FD_SLAVE,
 158         I2S_I2SMOD_FD_MASTER,
 159 };
 160
 161 enum i2s_fifo_th {
 162         I2S_FIFO_TH_NONE,
 163         I2S_FIFO_TH_ONE_QUARTER,
 164         I2S_FIFO_TH_HALF,
 165         I2S_FIFO_TH_THREE_QUARTER,
 166         I2S_FIFO_TH_FULL,
 167 };
 168
 169 enum i2s_std {
 170         I2S_STD_I2S,
 171         I2S_STD_LEFT_J,
 172         I2S_STD_RIGHT_J,
 173         I2S_STD_DSP,
 174 };
 175
 176 enum i2s_datlen {
 177         I2S_I2SMOD_DATLEN_16,
 178         I2S_I2SMOD_DATLEN_24,
 179         I2S_I2SMOD_DATLEN_32,
 180 };
 181
 182 #define STM32_I2S_DAI_NAME_SIZE         20
 183 #define STM32_I2S_FIFO_SIZE             16
 184
 185 #define STM32_I2S_IS_MASTER(x)          ((x)->ms_flg == I2S_MS_MASTER)
 186 #define STM32_I2S_IS_SLAVE(x)           ((x)->ms_flg == I2S_MS_SLAVE)
 187
 188 /**
 189  * struct stm32_i2s_data - private data of I2S
 190  * @regmap_conf: I2S register map configuration pointer
 191  * @regmap: I2S register map pointer
 192  * @pdev: device data pointer
 193  * @dai_drv: DAI driver pointer
 194  * @dma_data_tx: dma configuration data for tx channel
 195  * @dma_data_rx: dma configuration data for tx channel
 196  * @substream: PCM substream data pointer
 197  * @i2sclk: kernel clock feeding the I2S clock generator
 198  * @pclk: peripheral clock driving bus interface
 199  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 200  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 201  * @base:  mmio register base virtual address
 202  * @phys_addr: I2S registers physical base address
 203  * @lock_fd: lock to manage race conditions in full duplex mode
 204  * @irq_lock: prevent race condition with IRQ
 205  * @dais_name: DAI name
 206  * @mclk_rate: master clock frequency (Hz)
 207  * @fmt: DAI protocol
 208  * @refcount: keep count of opened streams on I2S
 209  * @ms_flg: master mode flag.
 210  */
 211 struct stm32_i2s_data {
 212         const struct regmap_config *regmap_conf;
 213         struct regmap *regmap;
 214         struct platform_device *pdev;
 215         struct snd_soc_dai_driver *dai_drv;
 216         struct snd_dmaengine_dai_dma_data dma_data_tx;
 217         struct snd_dmaengine_dai_dma_data dma_data_rx;
 218         struct snd_pcm_substream *substream;
 219         struct clk *i2sclk;
 220         struct clk *pclk;
 221         struct clk *x8kclk;
 222         struct clk *x11kclk;
 223         void __iomem *base;
 224         dma_addr_t phys_addr;
 225         spinlock_t lock_fd; /* Manage race conditions for full duplex */
 226         spinlock_t irq_lock; /* used to prevent race condition with IRQ */
 227         char dais_name[STM32_I2S_DAI_NAME_SIZE];
 228         unsigned int mclk_rate;
 229         unsigned int fmt;
 230         int refcount;
 231         int ms_flg;
 232 };
 233
 234 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 235 {
 236         struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 237         struct platform_device *pdev = i2s->pdev;
 238         u32 sr, ier;
 239         unsigned long flags;
 240         int err = 0;
 241
 242         regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 243         regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 244
 245         flags = sr & ier;
 246         if (!flags) {
 247                 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 248                         sr, ier);
 249                 return IRQ_NONE;
 250         }
 251
 252         regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 253                           I2S_IFCR_MASK, flags);
 254
 255         if (flags & I2S_SR_OVR) {
 256                 dev_dbg(&pdev->dev, "Overrun\n");
 257                 err = 1;
 258         }
 259
 260         if (flags & I2S_SR_UDR) {
 261                 dev_dbg(&pdev->dev, "Underrun\n");
 262                 err = 1;
 263         }
 264
 265         if (flags & I2S_SR_TIFRE)
 266                 dev_dbg(&pdev->dev, "Frame error\n");
 267
 268         spin_lock(&i2s->irq_lock);
 269         if (err && i2s->substream)
 270                 snd_pcm_stop_xrun(i2s->substream);
 271         spin_unlock(&i2s->irq_lock);
 272
 273         return IRQ_HANDLED;
 274 }
 275
 276 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 277 {
 278         switch (reg) {
 279         case STM32_I2S_CR1_REG:
 280         case STM32_I2S_CFG1_REG:
 281         case STM32_I2S_CFG2_REG:
 282         case STM32_I2S_IER_REG:
 283         case STM32_I2S_SR_REG:
 284         case STM32_I2S_RXDR_REG:
 285         case STM32_I2S_CGFR_REG:
 286                 return true;
 287         default:
 288                 return false;
 289         }
 290 }
 291
 292 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 293 {
 294         switch (reg) {
 295         case STM32_I2S_SR_REG:
 296         case STM32_I2S_RXDR_REG:
 297                 return true;
 298         default:
 299                 return false;
 300         }
 301 }
 302
 303 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 304 {
 305         switch (reg) {
 306         case STM32_I2S_CR1_REG:
 307         case STM32_I2S_CFG1_REG:
 308         case STM32_I2S_CFG2_REG:
 309         case STM32_I2S_IER_REG:
 310         case STM32_I2S_IFCR_REG:
 311         case STM32_I2S_TXDR_REG:
 312         case STM32_I2S_CGFR_REG:
 313                 return true;
 314         default:
 315                 return false;
 316         }
 317 }
 318
 319 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 320 {
 321         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 322         u32 cgfr;
 323         u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 324                          I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 325
 326         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 327
 328         /*
 329          * winv = 0 : default behavior (high/low) for all standards
 330          * ckpol = 0 for all standards.
 331          */
 332         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 333         case SND_SOC_DAIFMT_I2S:
 334                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 335                 break;
 336         case SND_SOC_DAIFMT_MSB:
 337                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 338                 break;
 339         case SND_SOC_DAIFMT_LSB:
 340                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 341                 break;
 342         case SND_SOC_DAIFMT_DSP_A:
 343                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 344                 break;
 345         /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 346         default:
 347                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 348                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 349                 return -EINVAL;
 350         }
 351
 352         /* DAI clock strobing */
 353         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 354         case SND_SOC_DAIFMT_NB_NF:
 355                 break;
 356         case SND_SOC_DAIFMT_IB_NF:
 357                 cgfr |= I2S_CGFR_CKPOL;
 358                 break;
 359         case SND_SOC_DAIFMT_NB_IF:
 360                 cgfr |= I2S_CGFR_WSINV;
 361                 break;
 362         case SND_SOC_DAIFMT_IB_IF:
 363                 cgfr |= I2S_CGFR_CKPOL;
 364                 cgfr |= I2S_CGFR_WSINV;
 365                 break;
 366         default:
 367                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 368                         fmt & SND_SOC_DAIFMT_INV_MASK);
 369                 return -EINVAL;
 370         }
 371
 372         /* DAI clock master masks */
 373         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 374         case SND_SOC_DAIFMT_CBM_CFM:
 375                 i2s->ms_flg = I2S_MS_SLAVE;
 376                 break;
 377         case SND_SOC_DAIFMT_CBS_CFS:
 378                 i2s->ms_flg = I2S_MS_MASTER;
 379                 break;
 380         default:
 381                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 382                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
 383                 return -EINVAL;
 384         }
 385
 386         i2s->fmt = fmt;
 387         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 388                                   cgfr_mask, cgfr);
 389 }
 390
 391 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 392                                 int clk_id, unsigned int freq, int dir)
 393 {
 394         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 395
 396         dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
 397
 398         if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
 399                 i2s->mclk_rate = freq;
 400
 401                 /* Enable master clock if master mode and mclk-fs are set */
 402                 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 403                                           I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 410                                      struct snd_pcm_hw_params *params)
 411 {
 412         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 413         unsigned long i2s_clock_rate;
 414         unsigned int tmp, div, real_div, nb_bits, frame_len;
 415         unsigned int rate = params_rate(params);
 416         int ret;
 417         u32 cgfr, cgfr_mask;
 418         bool odd;
 419
 420         if (!(rate % 11025))
 421                 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
 422         else
 423                 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
 424         i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 425
 426         /*
 427          * mckl = mclk_ratio x ws
 428          *   i2s mode : mclk_ratio = 256
 429          *   dsp mode : mclk_ratio = 128
 430          *
 431          * mclk on
 432          *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 433          *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 434          * mclk off
 435          *   i2s mode : div = i2s_clk / (nb_bits x ws)
 436          *   dsp mode : div = i2s_clk / (nb_bits x ws)
 437          */
 438         if (i2s->mclk_rate) {
 439                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
 440         } else {
 441                 frame_len = 32;
 442                 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 443                     SND_SOC_DAIFMT_DSP_A)
 444                         frame_len = 16;
 445
 446                 /* master clock not enabled */
 447                 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 448                 if (ret < 0)
 449                         return ret;
 450
 451                 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
 452                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
 453         }
 454
 455         /* Check the parity of the divider */
 456         odd = tmp & 0x1;
 457
 458         /* Compute the div prescaler */
 459         div = tmp >> 1;
 460
 461         cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
 462         cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 463
 464         real_div = ((2 * div) + odd);
 465         dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
 466                 i2s_clock_rate, rate);
 467         dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 468                 div, odd, real_div);
 469
 470         if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
 471                 dev_err(cpu_dai->dev, "Wrong divider setting\n");
 472                 return -EINVAL;
 473         }
 474
 475         if (!div && !odd)
 476                 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
 477
 478         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 479                                  cgfr_mask, cgfr);
 480         if (ret < 0)
 481                 return ret;
 482
 483         /* Set bitclock and frameclock to their inactive state */
 484         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 485                                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 486 }
 487
 488 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 489                                struct snd_pcm_hw_params *params,
 490                                struct snd_pcm_substream *substream)
 491 {
 492         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 493         int format = params_width(params);
 494         u32 cfgr, cfgr_mask, cfg1;
 495         unsigned int fthlv;
 496         int ret;
 497
 498         if ((params_channels(params) == 1) &&
 499             ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)) {
 500                 dev_err(cpu_dai->dev, "Mono mode supported only by DSP_A\n");
 501                 return -EINVAL;
 502         }
 503
 504         switch (format) {
 505         case 16:
 506                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 507                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 508                 break;
 509         case 32:
 510                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 511                                            I2S_CGFR_CHLEN;
 512                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 513                 break;
 514         default:
 515                 dev_err(cpu_dai->dev, "Unexpected format %d", format);
 516                 return -EINVAL;
 517         }
 518
 519         if (STM32_I2S_IS_SLAVE(i2s)) {
 520                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 521
 522                 /* As data length is either 16 or 32 bits, fixch always set */
 523                 cfgr |= I2S_CGFR_FIXCH;
 524                 cfgr_mask |= I2S_CGFR_FIXCH;
 525         } else {
 526                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 527         }
 528         cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 529
 530         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 531                                  cfgr_mask, cfgr);
 532         if (ret < 0)
 533                 return ret;
 534
 535         fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 536         cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
 537
 538         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 539                                   I2S_CFG1_FTHVL_MASK, cfg1);
 540 }
 541
 542 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 543                              struct snd_soc_dai *cpu_dai)
 544 {
 545         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 546         unsigned long flags;
 547         int ret;
 548
 549         spin_lock_irqsave(&i2s->irq_lock, flags);
 550         i2s->substream = substream;
 551         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 552
 553         ret = clk_prepare_enable(i2s->i2sclk);
 554         if (ret < 0) {
 555                 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
 556                 return ret;
 557         }
 558
 559         return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 560                                  I2S_IFCR_MASK, I2S_IFCR_MASK);
 561 }
 562
 563 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 564                                struct snd_pcm_hw_params *params,
 565                                struct snd_soc_dai *cpu_dai)
 566 {
 567         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 568         int ret;
 569
 570         ret = stm32_i2s_configure(cpu_dai, params, substream);
 571         if (ret < 0) {
 572                 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 573                 return ret;
 574         }
 575
 576         if (STM32_I2S_IS_MASTER(i2s))
 577                 ret = stm32_i2s_configure_clock(cpu_dai, params);
 578
 579         return ret;
 580 }
 581
 582 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 583                              struct snd_soc_dai *cpu_dai)
 584 {
 585         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 586         bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 587         u32 cfg1_mask, ier;
 588         int ret;
 589
 590         switch (cmd) {
 591         case SNDRV_PCM_TRIGGER_START:
 592         case SNDRV_PCM_TRIGGER_RESUME:
 593         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 594                 /* Enable i2s */
 595                 dev_dbg(cpu_dai->dev, "start I2S\n");
 596
 597                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 598                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 599                                    cfg1_mask, cfg1_mask);
 600
 601                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 602                                          I2S_CR1_SPE, I2S_CR1_SPE);
 603                 if (ret < 0) {
 604                         dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 605                         return ret;
 606                 }
 607
 608                 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
 609                                         I2S_CR1_CSTART, I2S_CR1_CSTART);
 610                 if (ret < 0) {
 611                         dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 612                         return ret;
 613                 }
 614
 615                 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 616                                   I2S_IFCR_MASK, I2S_IFCR_MASK);
 617
 618                 spin_lock(&i2s->lock_fd);
 619                 i2s->refcount++;
 620                 if (playback_flg) {
 621                         ier = I2S_IER_UDRIE;
 622                 } else {
 623                         ier = I2S_IER_OVRIE;
 624
 625                         if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
 626                                 /* dummy write to gate bus clocks */
 627                                 regmap_write(i2s->regmap,
 628                                              STM32_I2S_TXDR_REG, 0);
 629                 }
 630                 spin_unlock(&i2s->lock_fd);
 631
 632                 if (STM32_I2S_IS_SLAVE(i2s))
 633                         ier |= I2S_IER_TIFREIE;
 634
 635                 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
 636                 break;
 637         case SNDRV_PCM_TRIGGER_STOP:
 638         case SNDRV_PCM_TRIGGER_SUSPEND:
 639         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 640                 if (playback_flg)
 641                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 642                                            I2S_IER_UDRIE,
 643                                            (unsigned int)~I2S_IER_UDRIE);
 644                 else
 645                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 646                                            I2S_IER_OVRIE,
 647                                            (unsigned int)~I2S_IER_OVRIE);
 648
 649                 spin_lock(&i2s->lock_fd);
 650                 i2s->refcount--;
 651                 if (i2s->refcount) {
 652                         spin_unlock(&i2s->lock_fd);
 653                         break;
 654                 }
 655
 656                 dev_dbg(cpu_dai->dev, "stop I2S\n");
 657
 658                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 659                                          I2S_CR1_SPE, 0);
 660                 if (ret < 0) {
 661                         dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
 662                         spin_unlock(&i2s->lock_fd);
 663                         return ret;
 664                 }
 665                 spin_unlock(&i2s->lock_fd);
 666
 667                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 668                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 669                                    cfg1_mask, 0);
 670                 break;
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         return 0;
 676 }
 677
 678 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
 679                                struct snd_soc_dai *cpu_dai)
 680 {
 681         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 682         unsigned long flags;
 683
 684         regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 685                            I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
 686
 687         clk_disable_unprepare(i2s->i2sclk);
 688
 689         spin_lock_irqsave(&i2s->irq_lock, flags);
 690         i2s->substream = NULL;
 691         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 692 }
 693
 694 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
 695 {
 696         struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
 697         struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
 698         struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
 699
 700         /* Buswidth will be set by framework */
 701         dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 702         dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
 703         dma_data_tx->maxburst = 1;
 704         dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 705         dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
 706         dma_data_rx->maxburst = 1;
 707
 708         snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
 709
 710         return 0;
 711 }
 712
 713 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
 714         .reg_bits = 32,
 715         .reg_stride = 4,
 716         .val_bits = 32,
 717         .max_register = STM32_I2S_CGFR_REG,
 718         .readable_reg = stm32_i2s_readable_reg,
 719         .volatile_reg = stm32_i2s_volatile_reg,
 720         .writeable_reg = stm32_i2s_writeable_reg,
 721         .fast_io = true,
 722         .cache_type = REGCACHE_FLAT,
 723 };
 724
 725 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
 726         .set_sysclk     = stm32_i2s_set_sysclk,
 727         .set_fmt        = stm32_i2s_set_dai_fmt,
 728         .startup        = stm32_i2s_startup,
 729         .hw_params      = stm32_i2s_hw_params,
 730         .trigger        = stm32_i2s_trigger,
 731         .shutdown       = stm32_i2s_shutdown,
 732 };
 733
 734 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
 735         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 736         .buffer_bytes_max = 8 * PAGE_SIZE,
 737         .period_bytes_max = 2048,
 738         .periods_min = 2,
 739         .periods_max = 8,
 740 };
 741
 742 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
 743         .pcm_hardware   = &stm32_i2s_pcm_hw,
 744         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 745         .prealloc_buffer_size = PAGE_SIZE * 8,
 746 };
 747
 748 static const struct snd_soc_component_driver stm32_i2s_component = {
 749         .name = "stm32-i2s",
 750 };
 751
 752 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
 753                                char *stream_name)
 754 {
 755         stream->stream_name = stream_name;
 756         stream->channels_min = 1;
 757         stream->channels_max = 2;
 758         stream->rates = SNDRV_PCM_RATE_8000_192000;
 759         stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
 760                                    SNDRV_PCM_FMTBIT_S32_LE;
 761 }
 762
 763 static int stm32_i2s_dais_init(struct platform_device *pdev,
 764                                struct stm32_i2s_data *i2s)
 765 {
 766         struct snd_soc_dai_driver *dai_ptr;
 767
 768         dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
 769                                GFP_KERNEL);
 770         if (!dai_ptr)
 771                 return -ENOMEM;
 772
 773         snprintf(i2s->dais_name, STM32_I2S_DAI_NAME_SIZE,
 774                  "%s", dev_name(&pdev->dev));
 775
 776         dai_ptr->probe = stm32_i2s_dai_probe;
 777         dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
 778         dai_ptr->name = i2s->dais_name;
 779         dai_ptr->id = 1;
 780         stm32_i2s_dai_init(&dai_ptr->playback, "playback");
 781         stm32_i2s_dai_init(&dai_ptr->capture, "capture");
 782         i2s->dai_drv = dai_ptr;
 783
 784         return 0;
 785 }
 786
 787 static const struct of_device_id stm32_i2s_ids[] = {
 788         {
 789                 .compatible = "st,stm32h7-i2s",
 790                 .data = &stm32_h7_i2s_regmap_conf
 791         },
 792         {},
 793 };
 794
 795 static int stm32_i2s_parse_dt(struct platform_device *pdev,
 796                               struct stm32_i2s_data *i2s)
 797 {
 798         struct device_node *np = pdev->dev.of_node;
 799         const struct of_device_id *of_id;
 800         struct reset_control *rst;
 801         struct resource *res;
 802         int irq, ret;
 803
 804         if (!np)
 805                 return -ENODEV;
 806
 807         of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
 808         if (of_id)
 809                 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
 810         else
 811                 return -EINVAL;
 812
 813         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 814         i2s->base = devm_ioremap_resource(&pdev->dev, res);
 815         if (IS_ERR(i2s->base))
 816                 return PTR_ERR(i2s->base);
 817
 818         i2s->phys_addr = res->start;
 819
 820         /* Get clocks */
 821         i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
 822         if (IS_ERR(i2s->pclk)) {
 823                 dev_err(&pdev->dev, "Could not get pclk\n");
 824                 return PTR_ERR(i2s->pclk);
 825         }
 826
 827         i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
 828         if (IS_ERR(i2s->i2sclk)) {
 829                 dev_err(&pdev->dev, "Could not get i2sclk\n");
 830                 return PTR_ERR(i2s->i2sclk);
 831         }
 832
 833         i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
 834         if (IS_ERR(i2s->x8kclk)) {
 835                 dev_err(&pdev->dev, "missing x8k parent clock\n");
 836                 return PTR_ERR(i2s->x8kclk);
 837         }
 838
 839         i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
 840         if (IS_ERR(i2s->x11kclk)) {
 841                 dev_err(&pdev->dev, "missing x11k parent clock\n");
 842                 return PTR_ERR(i2s->x11kclk);
 843         }
 844
 845         /* Get irqs */
 846         irq = platform_get_irq(pdev, 0);
 847         if (irq < 0) {
 848                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
 849                 return -ENOENT;
 850         }
 851
 852         ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
 853                                dev_name(&pdev->dev), i2s);
 854         if (ret) {
 855                 dev_err(&pdev->dev, "irq request returned %d\n", ret);
 856                 return ret;
 857         }
 858
 859         /* Reset */
 860         rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 861         if (!IS_ERR(rst)) {
 862                 reset_control_assert(rst);
 863                 udelay(2);
 864                 reset_control_deassert(rst);
 865         }
 866
 867         return 0;
 868 }
 869
 870 static int stm32_i2s_probe(struct platform_device *pdev)
 871 {
 872         struct stm32_i2s_data *i2s;
 873         int ret;
 874
 875         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 876         if (!i2s)
 877                 return -ENOMEM;
 878
 879         ret = stm32_i2s_parse_dt(pdev, i2s);
 880         if (ret)
 881                 return ret;
 882
 883         i2s->pdev = pdev;
 884         i2s->ms_flg = I2S_MS_NOT_SET;
 885         spin_lock_init(&i2s->lock_fd);
 886         spin_lock_init(&i2s->irq_lock);
 887         platform_set_drvdata(pdev, i2s);
 888
 889         ret = stm32_i2s_dais_init(pdev, i2s);
 890         if (ret)
 891                 return ret;
 892
 893         i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
 894                                                 i2s->base, i2s->regmap_conf);
 895         if (IS_ERR(i2s->regmap)) {
 896                 dev_err(&pdev->dev, "regmap init failed\n");
 897                 return PTR_ERR(i2s->regmap);
 898         }
 899
 900         ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
 901                                               i2s->dai_drv, 1);
 902         if (ret)
 903                 return ret;
 904
 905         ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
 906                                               &stm32_i2s_pcm_config, 0);
 907         if (ret)
 908                 return ret;
 909
 910         /* Set SPI/I2S in i2s mode */
 911         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 912                                   I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
 913 }
 914
 915 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
 916
 917 #ifdef CONFIG_PM_SLEEP
 918 static int stm32_i2s_suspend(struct device *dev)
 919 {
 920         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 921
 922         regcache_cache_only(i2s->regmap, true);
 923         regcache_mark_dirty(i2s->regmap);
 924
 925         return 0;
 926 }
 927
 928 static int stm32_i2s_resume(struct device *dev)
 929 {
 930         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 931
 932         regcache_cache_only(i2s->regmap, false);
 933         return regcache_sync(i2s->regmap);
 934 }
 935 #endif /* CONFIG_PM_SLEEP */
 936
 937 static const struct dev_pm_ops stm32_i2s_pm_ops = {
 938         SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
 939 };
 940
 941 static struct platform_driver stm32_i2s_driver = {
 942         .driver = {
 943                 .name = "st,stm32-i2s",
 944                 .of_match_table = stm32_i2s_ids,
 945                 .pm = &stm32_i2s_pm_ops,
 946         },
 947         .probe = stm32_i2s_probe,
 948 };
 949
 950 module_platform_driver(stm32_i2s_driver);
 951
 952 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
 953 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
 954 MODULE_ALIAS("platform:stm32-i2s");
 955 MODULE_LICENSE("GPL v2");