source/src/vm/fm7/display.cpp

   1 /*
   2  * Common source code project -> FM-7 -> Display
   3  * (C) 2015 K.Ohta <whatisthis.sowhat _at_ gmail.com>
   4  * History:
   5  *  Feb 10, 2015 : Initial.
   6  */
   7
   8 #include "vm.h"
   9 #include "emu.h"
  10 #include "../../fileio.h"
  11 #include "fm7_display.h"
  12 #if defined(_FM77AV_VARIANTS)
  13 # include "mb61vh010.h"
  14 #endif
  15 #if defined(_FM77L4)
  16 #include "hd46505.h"
  17 #endif
  18
  19 #include "fm7_mainio.h"
  20 #include "./fm7_keyboard.h"
  21 #include "./kanjirom.h"
  22 #include "../../statesub.h"
  23
  24 DISPLAY::DISPLAY(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
  25 {
  26         ins_led = NULL;
  27         kana_led = NULL;
  28         caps_led = NULL;
  29 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
  30         kanjiclass1 = NULL;
  31         kanjiclass2 = NULL;
  32 #elif defined(_FM77_VARIANTS)
  33         kanjiclass1 = NULL;
  34 #endif
  35 #if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
  36         kanjisub = false;       // fix by Ryu Takegami
  37 #endif
  38 #if defined(_FM77AV_VARIANTS)
  39         alu = NULL;
  40 #endif
  41         mainio = NULL;
  42         subcpu = NULL;
  43         keyboard = NULL;
  44         for(int i = 0; i < 256; i++) {
  45                 uint16_t n = (uint16_t)i;
  46                 for(int j = 0; j < 8; j++) {
  47                         bit_trans_table_0[i][j] = n & 0x80;
  48                         bit_trans_table_1[i][j] = ((n & 0x80) != 0) ? 0x40 : 0;
  49                         bit_trans_table_2[i][j] = ((n & 0x80) != 0) ? 0x20 : 0;
  50                         bit_trans_table_3[i][j] = ((n & 0x80) != 0) ? 0x10 : 0;
  51 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
  52                         bit_trans_table_4[i][j] = ((n & 0x80) != 0) ? 0x08 : 0;
  53                         bit_trans_table_5[i][j] = ((n & 0x80) != 0) ? 0x04 : 0;
  54 #endif
  55                         n <<= 1;
  56                 }
  57         }
  58         displine = 0;
  59         active_page = 0;
  60 #if defined(USE_GREEN_DISPLAY)
  61         use_green_monitor = false;
  62 #endif
  63         force_update = true;
  64         set_device_name(_T("DISPLAY SUBSYSTEM"));
  65 }
  66
  67 DISPLAY::~DISPLAY()
  68 {
  69
  70 }
  71
  72 void DISPLAY::reset_some_devices()
  73 {
  74         int i;
  75         double usec;
  76         call_write_signal(keyboard, SIG_FM7KEY_SET_INSLED, 0x00, 0x01);
  77         call_write_signal(mainio, SIG_FM7_SUB_HALT, 0x00, 0xff);
  78         sub_busy = true;
  79
  80         palette_changed = true;
  81         multimode_accessmask = 0;
  82         multimode_dispmask = 0;
  83         for(i = 0; i < 4; i++) {
  84                 multimode_accessflags[i] = ((multimode_accessmask & (1 << i)) != 0) ? true : false;
  85                 multimode_dispflags[i] = ((multimode_dispmask & (1 << i)) != 0) ? true : false;
  86         }
  87         //firq_mask = false; // 20180215 Thanks to Ryu takegami.
  88         //cancel_request = false;
  89         is_cyclesteal = ((config.dipswitch & FM7_DIPSW_CYCLESTEAL) != 0) ? true : false;
  90         switch(config.cpu_type){
  91                 case 0:
  92                         clock_fast = true;
  93                         break;
  94                 case 1:
  95                         clock_fast = false;
  96                         break;
  97         }
  98         if(clock_fast) {
  99                 prev_clock = SUBCLOCK_NORMAL;
 100         } else {
 101                 prev_clock = SUBCLOCK_SLOW;
 102         }
 103         enter_display();
 104
 105         offset_point = 0;
 106         for(i = 0; i < 2; i++) {
 107                 offset_changed[i] = true;
 108                 tmp_offset_point[i].d = 0;
 109         }
 110
 111         vram_wrote_shadow = true;
 112         for(i = 0; i < 411 * 5; i++) vram_wrote_table[i] = true;
 113         for(i = 0; i < 411; i++) vram_draw_table[i] = true;
 114         displine = 0;
 115         active_page = 0;
 116
 117 //#if defined(_FM77AV_VARIANTS) || defined(_FM77L4)
 118 #if 1
 119         vsync = true;
 120         vblank = true;
 121         hblank = false;
 122         vblank_count = 0;
 123
 124         if(hblank_event_id >= 0) cancel_event(this, hblank_event_id);
 125         if(hdisp_event_id >= 0) cancel_event(this, hdisp_event_id);
 126
 127         if(vsync_event_id >= 0) cancel_event(this, vsync_event_id);
 128         if(vstart_event_id >= 0) cancel_event(this, vstart_event_id);
 129         hblank_event_id = -1;
 130         hdisp_event_id = -1;
 131         vsync_event_id = -1;
 132         vstart_event_id = -1;
 133 #endif
 134         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
 135                 usec = 0.33 * 1000.0;
 136                 vm->set_vm_frame_rate(55.40);
 137         } else {
 138                 usec = 0.51 * 1000.0;
 139                 vm->set_vm_frame_rate(FRAMES_PER_SEC);
 140         }
 141         //usec = 16.0;
 142         //register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
 143         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x00, 0xff);
 144         call_write_signal(mainio, SIG_DISPLAY_VSYNC, 0xff, 0xff);
 145 //#endif
 146         display_page = 0;
 147         display_page_bak = 0;
 148
 149 #if defined(_FM77AV_VARIANTS)
 150         offset_77av = false;
 151         offset_point_bank1 = 0;
 152
 153         subcpu_resetreq = false;
 154         subrom_bank_using = subrom_bank;
 155
 156         nmi_enable = true;
 157         use_alu = false;
 158
 159 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
 160         vram_bank = 0;
 161         vram_display_block = 0;
 162         vram_active_block = 0;
 163
 164 #  if defined(_FM77AV40EX) || defined(_FM77AV40SX)
 165         window_low = 0;
 166         window_high = 0;
 167         window_xbegin = 0;
 168         window_xend = 0;
 169         window_opened = false;
 170 #  endif
 171 # endif
 172
 173         alu->reset();
 174 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
 175         call_write_signal(alu, SIG_ALU_X_WIDTH, (mode320 || mode256k) ? 40 : 80, 0xffff);
 176         call_write_signal(alu, SIG_ALU_Y_HEIGHT, (display_mode == DISPLAY_MODE_8_400L) ? 400: 200, 0xffff);
 177         call_write_signal(alu, SIG_ALU_400LINE, (display_mode == DISPLAY_MODE_8_400L) ? 0xffffffff : 0, 0xffffffff);
 178 # else
 179         call_write_signal(alu, SIG_ALU_X_WIDTH, (mode320) ? 40 : 80, 0xffff);
 180         call_write_signal(alu, SIG_ALU_Y_HEIGHT, 200, 0xffff);
 181         call_write_signal(alu, SIG_ALU_400LINE, 0, 0xffffffff);
 182 # endif
 183         call_write_signal(alu, SIG_ALU_MULTIPAGE, multimode_accessmask, 0x07);
 184         call_write_signal(alu, SIG_ALU_PLANES, 3, 3);
 185 #endif
 186         for(i = 0; i < 8; i++) set_dpalette(i, i);
 187 #if defined(USE_GREEN_DISPLAY)
 188         memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
 189 #endif
 190         memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
 191         //do_firq(!firq_mask && key_firq_req);
 192
 193 #if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
 194         //kanjisub = false; // Fixed by Ryu takegami
 195         kanjiaddr.d = 0x00000000;
 196 # if defined(_FM77L4)
 197         mode400line = false;
 198         stat_400linecard = false;
 199 # endif
 200 #endif
 201         vram_wrote = true;
 202         clr_count = 0;
 203         frame_skip_count_draw = 3;
 204         frame_skip_count_transfer = 3;
 205         need_transfer_line = true;
 206         setup_display_mode();
 207
 208 }
 209
 210
 211 void DISPLAY::reset()
 212 {
 213         int i;
 214         //printf("RESET\n");
 215         halt_flag = false;
 216         vram_accessflag = true;
 217         display_mode = DISPLAY_MODE_8_200L;
 218         //crt_flag = true;
 219         crt_flag = false; // Fixed by Ryu Takegami
 220         screen_update_flag = true;
 221         crt_flag_bak = false;
 222         cancel_request = false;
 223 #if defined(_FM77AV_VARIANTS)
 224         mode320 = false;
 225         apalette_index.d = 0;
 226         for(i = 0; i < 4096; i++) {
 227                 analog_palette_r[i] = i & 0x0f0;
 228                 analog_palette_g[i] = (i & 0xf00) >> 4;
 229                 analog_palette_b[i] = (i & 0x00f) << 4;
 230                 calc_apalette(i);
 231                 memcpy(analog_palette_pixel, analog_palette_pixel_tmp, sizeof(analog_palette_pixel));
 232         }
 233         subrom_bank = 0;
 234         cgrom_bank = 0;
 235 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
 236         monitor_ram = false;
 237         ram_protect = true;
 238
 239         mode400line = false;
 240         mode256k = false;
 241 # endif
 242 #elif defined(_FM77L4)
 243         mode400line = false;
 244         stat_400linecard = false;
 245
 246         workram_l4 = false;
 247         cursor_lsb = false;
 248     text_width40 = false;
 249
 250         text_blink = true;
 251         cursor_blink = true;
 252
 253         text_start_addr.d = 0x0000;
 254         text_lines = 64;
 255         text_xmax = 80;
 256
 257         cursor_addr.d = 0;
 258         cursor_start = 0;
 259         cursor_end = 0;
 260         cursor_type = 0;
 261         text_scroll_count = 0;
 262
 263         cursor_blink = true;
 264         {
 265                 // OK?
 266                 double usec;
 267                 uint8_t *regs = l4crtc->get_regs();
 268                 display_mode = DISPLAY_MODE_1_400L;
 269                 if(event_id_l4_cursor_blink >= 0) {
 270                         cancel_event(this, event_id_l4_cursor_blink);
 271                 }
 272                 if(event_id_l4_text_blink >= 0) {
 273                         cancel_event(this, event_id_l4_text_blink);
 274                 }
 275                 event_id_l4_cursor_blink = -1;
 276                 event_id_l4_text_blink = -1;
 277                 if(regs != NULL) {
 278                         usec = ((regs[10] & 0x20) == 0) ? 160.0 : 320.0;
 279                         usec = usec * 1000.0;
 280                         register_event(this, EVENT_FM7SUB_CURSOR_BLINK, true, usec, &event_id_l4_cursor_blink);
 281                         usec = 160.0 * 1000.0;
 282                         register_event(this, EVENT_FM7SUB_TEXT_BLINK, true, usec, &event_id_l4_cursor_blink);
 283                 }
 284         }
 285         //memset(crtc_regs, 0x00, sizeof(crtc_regs));
 286 #endif
 287
 288 #if !defined(FIXED_FRAMEBUFFER_SIZE)
 289         emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
 290 #else
 291         emu->set_vm_screen_size(640, 400, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
 292 #endif
 293         emu->set_vm_screen_lines(200);
 294
 295         reset_some_devices();
 296
 297 #if defined(_FM77AV_VARIANTS)
 298         power_on_reset = false;
 299         for(i = 0; i < 411 * 5; i++) vram_wrote_table[i] = false;
 300         nmi_enable = true;
 301 #else
 302 # if defined(_FM8)
 303         for(i = 0; i < 8; i++) set_dpalette(i, i);
 304 # endif
 305 #endif
 306 #if defined(USE_GREEN_DISPLAY) && defined(USE_MONITOR_TYPE)
 307         memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
 308         switch(config.monitor_type) {
 309         case FM7_MONITOR_GREEN:
 310                 use_green_monitor = true;
 311                 break;
 312         case FM7_MONITOR_STANDARD:
 313         default:
 314                 use_green_monitor = false;
 315                 break;
 316         }
 317 #else
 318         //use_green_monitor = false;
 319 #endif
 320         force_update = true;
 321
 322         memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
 323         //enter_display();
 324
 325         if(nmi_event_id >= 0) cancel_event(this, nmi_event_id);
 326         register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
 327
 328         firq_mask = false;
 329         key_firq_req = false;
 330         do_firq(false);
 331         reset_subcpu(true);
 332 }
 333
 334 void DISPLAY::reset_subcpu(bool _check_firq)
 335 {
 336         call_write_signal(subcpu, SIG_CPU_HALTREQ, 0, 1);
 337         call_write_signal(subcpu, SIG_CPU_BUSREQ, 0, 1);
 338         subcpu->reset();
 339         if(_check_firq) {
 340                 do_firq(!firq_mask && key_firq_req);
 341         }
 342 }
 343 void DISPLAY::setup_display_mode(void)
 344 {
 345 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
 346         if(display_mode == DISPLAY_MODE_8_400L) {
 347                 page_offset = 0x0000;
 348                 pagemod_mask = 0x18000;
 349                 page_mask = 0x7fff;
 350         } else if(display_mode == DISPLAY_MODE_256k) {
 351                 if(active_page != 0) {
 352                         page_offset = 0xc000;
 353                 } else {
 354                         page_offset = 0x0000;
 355                 }
 356                 pagemod_mask = 0xe000;
 357                 page_mask = 0x1fff;
 358         } else if(display_mode == DISPLAY_MODE_4096) {
 359                 if(active_page != 0) {
 360                         page_offset = 0xc000;
 361                 } else {
 362                         page_offset = 0x0000;
 363                 }
 364                 pagemod_mask = 0xe000;
 365                 page_mask = 0x1fff;
 366         } else { // 200Line
 367                 if(active_page != 0) {
 368                         page_offset = 0xc000;
 369                 } else {
 370                         page_offset = 0x0000;
 371                 }
 372                 pagemod_mask = 0xc000;
 373                 page_mask = 0x3fff;
 374         }
 375 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
 376         if(vram_active_block != 0) page_offset += 0x18000;
 377 # endif
 378 #elif defined(_FM77AV_VARIANTS)
 379         if(mode320) {
 380                 page_mask = 0x1fff;
 381                 pagemod_mask = 0xe000;
 382         } else { // 640x200, 8colors
 383                 page_mask = 0x3fff;
 384                 pagemod_mask = 0xc000;
 385         }
 386         if(active_page != 0) {
 387                 page_offset = 0xc000;
 388         } else {
 389                 page_offset = 0x0000;
 390         }
 391 #elif defined(_FM77L4)
 392         if(display_mode == DISPLAY_MODE_1_400L) {
 393                 page_mask = 0x7fff;
 394                 pagemod_mask = 0x0000;
 395                 page_offset = 0x0000;
 396         } else { // 640x200, 8colors
 397                 page_mask = 0x3fff;
 398                 pagemod_mask = 0xc000;
 399                 page_offset = 0x0000;
 400         }
 401         page_offset = 0x0000;
 402 #else
 403         page_offset = 0x0000;
 404         pagemod_mask = 0xc000;
 405         page_mask = 0x3fff;
 406 #endif
 407 }
 408
 409 void DISPLAY::update_config()
 410 {
 411         vram_wrote = true;
 412
 413
 414 #if !defined(_FM8)
 415         is_cyclesteal = ((config.dipswitch & FM7_DIPSW_CYCLESTEAL) != 0) ? true : false;
 416 #endif
 417         enter_display();
 418 }
 419
 420 /*
 421  * Vram accessing functions moved to vram.cpp .
 422  */
 423
 424 void DISPLAY::do_irq(bool flag)
 425 {
 426         call_write_signal(subcpu, SIG_CPU_IRQ, flag ? 1: 0, 1);
 427 }
 428
 429 void DISPLAY::do_firq(bool flag)
 430 {
 431         call_write_signal(subcpu, SIG_CPU_FIRQ, flag ? 1: 0, 1);
 432 }
 433
 434 void DISPLAY::do_nmi(bool flag)
 435 {
 436 #if defined(_FM77AV_VARIANTS)
 437         if(!nmi_enable) flag = false;
 438 #endif
 439         call_write_signal(subcpu, SIG_CPU_NMI, flag ? 1 : 0, 1);
 440 }
 441
 442 void DISPLAY::set_multimode(uint8_t val)
 443 {
 444 #if !defined(_FM8)
 445         multimode_accessmask = val & 0x07;
 446         multimode_dispmask = (val & 0x70) >> 4;
 447         for(int i = 0; i < 4; i++) {
 448                 multimode_accessflags[i] = ((multimode_accessmask & (1 << i)) != 0) ? true : false;
 449                 multimode_dispflags[i] = ((multimode_dispmask & (1 << i)) != 0) ? true : false;
 450         }
 451         vram_wrote = true;
 452 # if defined(_FM77AV_VARIANTS)
 453         call_write_signal(alu, SIG_ALU_MULTIPAGE, multimode_accessmask, 0x07);
 454 # endif
 455 #endif
 456 }
 457
 458 uint8_t DISPLAY::get_multimode(void)
 459 {
 460 #if defined(_FM8)
 461         return 0xff;
 462 #else
 463         uint8_t val;
 464         val = multimode_accessmask & 0x07;
 465         val |= ((multimode_dispmask << 4) & 0x70);
 466         val |= 0x80;
 467         return val;
 468 #endif
 469 }
 470
 471 uint8_t DISPLAY::get_cpuaccessmask(void)
 472 {
 473         return multimode_accessmask & 0x07;
 474 }
 475
 476 void DISPLAY::set_dpalette(uint32_t addr, uint8_t val)
 477 {
 478         scrntype_t r, g, b;
 479         addr &= 7;
 480         dpalette_data[addr] = val | 0xf8; //0b11111000;
 481         b =  ((val & 0x01) != 0x00)? 255 : 0x00;
 482         r =  ((val & 0x02) != 0x00)? 255 : 0x00;
 483         g =  ((val & 0x04) != 0x00)? 255 : 0x00;
 484
 485         dpalette_pixel_tmp[addr] = RGB_COLOR(r, g, b);
 486 #if defined(USE_GREEN_DISPLAY)
 487         static const scrntype_t colortable[8] = {0, 48, 70, 100, 140, 175, 202, 255};
 488         g = colortable[val & 0x07];
 489         b = r = ((val & 0x07) > 4) ? 48 : 0;
 490         dpalette_green_tmp[addr] = RGB_COLOR(r, g, b);
 491 #endif
 492         palette_changed = true;
 493 }
 494
 495 uint8_t DISPLAY::get_dpalette(uint32_t addr)
 496 {
 497 #if defined(_FM8)
 498         return 0xff;
 499 #else
 500         uint8_t data;
 501         addr = addr & 7;
 502
 503         data = dpalette_data[addr];
 504         return data;
 505 #endif
 506 }
 507
 508 void DISPLAY::halt_subcpu(void)
 509 {
 510         //call_write_signal(subcpu, SIG_CPU_BUSREQ, 0x01, 0x01);
 511         call_write_signal(subcpu, SIG_CPU_HALTREQ, 0x01, 0x01);
 512 }
 513
 514 void DISPLAY::go_subcpu(void)
 515 {
 516         call_write_signal(subcpu, SIG_CPU_HALTREQ, 0x00, 0x01);
 517 }
 518
 519 void DISPLAY::enter_display(void)
 520 {
 521         uint32_t subclock;
 522
 523         if(clock_fast) {
 524                 subclock = SUBCLOCK_NORMAL;
 525         } else {
 526                 subclock = SUBCLOCK_SLOW;
 527         }
 528         if(!(is_cyclesteal) && (vram_accessflag)) {
 529                 subclock = subclock / 3;
 530         }
 531         if(prev_clock != subclock) {
 532                 vm->set_cpu_clock(subcpu, subclock);
 533         }
 534         prev_clock = subclock;
 535 }
 536
 537
 538 void DISPLAY::leave_display(void)
 539 {
 540 }
 541
 542 void DISPLAY::halt_subsystem(void)
 543 {
 544         //halt_flag = false;
 545         halt_subcpu();
 546 }
 547
 548 void DISPLAY::restart_subsystem(void)
 549 {
 550         //halt_flag = false;
 551 #if defined(_FM77AV_VARIANTS)
 552         if(subcpu_resetreq) {
 553                 //firq_mask = (mainio->read_signal(FM7_MAINIO_KEYBOARDIRQ_MASK) != 0) ? false : true;
 554                 reset_some_devices();
 555                 power_on_reset = true;
 556                 reset_subcpu(true);
 557         }
 558 #endif
 559         go_subcpu();
 560 }
 561
 562 //SUB:D408:R
 563 void DISPLAY::set_crtflag(void)
 564 {
 565         crt_flag = true;
 566         vram_wrote = true;
 567 }
 568
 569 //SUB:D408:W
 570 void DISPLAY::reset_crtflag(void)
 571 {
 572         crt_flag = false;
 573         vram_wrote = true;
 574 }
 575
 576 //SUB:D402:R
 577 uint8_t DISPLAY::acknowledge_irq(void)
 578 {
 579         cancel_request = false;
 580         do_irq(false);
 581         return 0xff;
 582 }
 583
 584 //SUB:D403:R
 585 uint8_t DISPLAY::beep(void)
 586 {
 587         call_write_signal(mainio, FM7_MAINIO_BEEP, 0x01, 0x01);
 588         return 0xff; // True?
 589 }
 590
 591
 592 // SUB:D404 : R
 593 uint8_t DISPLAY::attention_irq(void)
 594 {
 595         call_write_signal(mainio, FM7_MAINIO_SUB_ATTENTION, 0x01, 0x01);
 596         return 0xff;
 597 }
 598
 599 // SUB:D405:W
 600 void DISPLAY::set_cyclesteal(uint8_t val)
 601 {
 602 #if !defined(_FM8)
 603 # if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
 604         vram_wrote = true;
 605         val &= 0x01;
 606         if(val == 0) {
 607                 is_cyclesteal = true;
 608         } else {
 609                 is_cyclesteal = false;
 610         }
 611    enter_display();
 612 # endif
 613 #endif
 614 }
 615
 616 void DISPLAY::setup_400linemode(uint8_t val)
 617 {
 618 #if defined(_FM77L4)
 619         // 400Line board.
 620         cursor_lsb = ((val & 0x10) != 0);
 621         text_width40 = ((val & 0x08) != 0);
 622         workram_l4 = ((val & 0x04) != 0);
 623         bool tmpmode = ((val & 0x02) != 0);
 624         if(tmpmode != mode400line) {
 625                 int oldmode = display_mode;
 626                 mode400line = tmpmode;
 627                 if(mode400line && stat_400linecard) {
 628                         display_mode = DISPLAY_MODE_1_400L;
 629                 } else {
 630                         display_mode = DISPLAY_MODE_8_200L;
 631                 }
 632                 if(oldmode != display_mode) {
 633                         scrntype_t *pp;
 634                         if(display_mode == DISPLAY_MODE_1_400L) {
 635                                 emu->set_vm_screen_size(640, 400, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
 636                                 for(int y = 0; y < 400; y++) {
 637                                         pp = emu->get_screen_buffer(y);
 638                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
 639                                 }
 640                         } else { // 200Line
 641
 642                                 vm->set_vm_frame_rate(FRAMES_PER_SEC);
 643 #if !defined(FIXED_FRAMEBUFFER_SIZE)
 644                                 emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
 645                                 for(int y = 0; y < 200; y++) {
 646                                         pp = emu->get_screen_buffer(y);
 647                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
 648                                 }
 649 #else
 650                                 for(int y = 0; y < 400; y++) {
 651                                         pp = emu->get_screen_buffer(y);
 652                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
 653                                 }
 654 #endif
 655                         }
 656                         vram_wrote = true;
 657                         setup_display_mode();
 658
 659                 }
 660         }
 661 #endif
 662 }
 663
 664 //SUB:D409:R
 665 uint8_t DISPLAY::set_vramaccess(void)
 666 {
 667         vram_accessflag = true;
 668         //enter_display();
 669         return 0xff;
 670 }
 671
 672 //SUB:D409:W
 673 void DISPLAY::reset_vramaccess(void)
 674 {
 675         vram_accessflag = false;
 676         //enter_display();
 677 }
 678
 679 //SUB:D40A:R
 680 uint8_t DISPLAY::reset_subbusy(void)
 681 {
 682         sub_busy = false;
 683         return 0xff;
 684 }
 685
 686 //SUB:D40A:W
 687 void DISPLAY::set_subbusy(void)
 688 {
 689         sub_busy = true;
 690 }
 691
 692
 693 #if defined(_FM77AV_VARIANTS)
 694 // D410
 695 void DISPLAY::alu_write_cmdreg(uint32_t val)
 696 {
 697         call_write_data8(alu, ALU_CMDREG, val);
 698         if((val & 0x80) != 0) {
 699                 use_alu = true;
 700         } else {
 701                 use_alu = false;
 702         }
 703 }
 704
 705 // D411
 706 void DISPLAY::alu_write_logical_color(uint8_t val)
 707 {
 708         uint32_t data = (uint32_t)val;
 709         call_write_data8(alu, ALU_LOGICAL_COLOR, data);
 710 }
 711
 712 // D412
 713 void DISPLAY::alu_write_mask_reg(uint8_t val)
 714 {
 715         uint32_t data = (uint32_t)val;
 716         call_write_data8(alu, ALU_WRITE_MASKREG, data);
 717 }
 718
 719 // D413 - D41A
 720 void DISPLAY::alu_write_cmpdata_reg(int addr, uint8_t val)
 721 {
 722         uint32_t data = (uint32_t)val;
 723         addr = addr & 7;
 724         call_write_data8(alu, ALU_CMPDATA_REG + addr, data);
 725 }
 726
 727 // D41B
 728 void DISPLAY::alu_write_disable_reg(uint8_t val)
 729 {
 730         uint32_t data = (uint32_t)val;
 731         call_write_data8(alu, ALU_BANK_DISABLE, data);
 732 }
 733
 734 // D41C - D41F
 735 void DISPLAY::alu_write_tilepaint_data(uint32_t addr, uint8_t val)
 736 {
 737         uint32_t data = (uint32_t)val;
 738         switch(addr & 3) {
 739                 case 0: // $D41C
 740                         call_write_data8(alu, ALU_TILEPAINT_B, data);
 741                         break;
 742                 case 1: // $D41D
 743                         call_write_data8(alu, ALU_TILEPAINT_R, data);
 744                         break;
 745                 case 2: // $D41E
 746                         call_write_data8(alu, ALU_TILEPAINT_G, data);
 747                         break;
 748                 case 3: // xxxx
 749                         //call_write_data8(alu, ALU_TILEPAINT_L, 0xff);
 750                         break;
 751         }
 752 }
 753
 754 // D420
 755 void DISPLAY::alu_write_offsetreg_hi(uint8_t val)
 756 {
 757         call_write_data8(alu, ALU_OFFSET_REG_HIGH, val & 0x7f);
 758 }
 759
 760 // D421
 761 void DISPLAY::alu_write_offsetreg_lo(uint8_t val)
 762 {
 763         call_write_data8(alu, ALU_OFFSET_REG_LO, val);
 764 }
 765
 766 // D422
 767 void DISPLAY::alu_write_linepattern_hi(uint8_t val)
 768 {
 769         call_write_data8(alu, ALU_LINEPATTERN_REG_HIGH, val);
 770 }
 771
 772 // D423
 773 void DISPLAY::alu_write_linepattern_lo(uint8_t val)
 774 {
 775         call_write_data8(alu, ALU_LINEPATTERN_REG_LO, val);
 776 }
 777
 778 // D424-D42B
 779 void DISPLAY::alu_write_line_position(int addr, uint8_t val)
 780 {
 781         uint32_t data = (uint32_t)val;
 782         switch(addr) {
 783                 case 0:
 784                         call_write_data8(alu, ALU_LINEPOS_START_X_HIGH, data & 0x03);
 785                         break;
 786                 case 1:
 787                         call_write_data8(alu, ALU_LINEPOS_START_X_LOW, data);
 788                         break;
 789                 case 2:
 790                         call_write_data8(alu, ALU_LINEPOS_START_Y_HIGH, data & 0x01);
 791                         break;
 792                 case 3:
 793                         call_write_data8(alu, ALU_LINEPOS_START_Y_LOW, data);
 794                         break;
 795                 case 4:
 796                         call_write_data8(alu, ALU_LINEPOS_END_X_HIGH, data & 0x03);
 797                         break;
 798                 case 5:
 799                         call_write_data8(alu, ALU_LINEPOS_END_X_LOW, data);
 800                         break;
 801                 case 6:
 802                         call_write_data8(alu, ALU_LINEPOS_END_Y_HIGH, data & 0x01);
 803                         break;
 804                 case 7:
 805                         call_write_data8(alu, ALU_LINEPOS_END_Y_LOW, data);
 806                         break;
 807         }
 808 }
 809
 810 //SUB:D430:R
 811 uint8_t DISPLAY::get_miscreg(void)
 812 {
 813         uint8_t ret;
 814
 815         ret = 0x6a;
 816         if(!hblank) ret |= 0x80;
 817         if(vsync) ret |= 0x04;
 818         if(alu->read_signal(SIG_ALU_BUSYSTAT) == 0) ret |= 0x10;
 819         if(power_on_reset) ret |= 0x01;
 820         return ret;
 821 }
 822
 823 //SUB:D430:W
 824 void DISPLAY::set_miscreg(uint8_t val)
 825 {
 826         int old_display_page = display_page;
 827
 828         nmi_enable = ((val & 0x80) == 0) ? true : false;
 829         if(!nmi_enable) do_nmi(false);
 830
 831         if((val & 0x40) == 0) {
 832                 display_page = 0;
 833         } else {
 834                 display_page = 1;
 835         }
 836         if(display_page != old_display_page) {
 837                 vram_wrote = true;
 838         }
 839         active_page = ((val & 0x20) == 0) ? 0 : 1;
 840         if((val & 0x04) == 0) {
 841                 offset_77av = false;
 842         } else {
 843                 offset_77av = true;
 844         }
 845         cgrom_bank = val & 0x03;
 846         setup_display_mode();
 847 }
 848
 849 // Main: FD13
 850 void DISPLAY::set_monitor_bank(uint8_t var)
 851 {
 852 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
 853         if((var & 0x04) != 0){
 854                 monitor_ram = true;
 855         } else {
 856                 monitor_ram = false;
 857         }
 858 # endif
 859         subrom_bank = var & 0x03;
 860         vram_wrote = true;
 861         if(!halt_flag) {
 862                 subcpu_resetreq = false;
 863                 power_on_reset = true;
 864                 //firq_mask = (mainio->read_signal(FM7_MAINIO_KEYBOARDIRQ_MASK) != 0) ? false : true;
 865                 reset_some_devices();
 866                 reset_subcpu(true);
 867         } else {
 868                 subcpu_resetreq = true;
 869         }
 870 }
 871
 872
 873 // FD30
 874 void DISPLAY::set_apalette_index_hi(uint8_t val)
 875 {
 876         apalette_index.b.h = val & 0x0f;
 877 }
 878
 879 // FD31
 880 void DISPLAY::set_apalette_index_lo(uint8_t val)
 881 {
 882         apalette_index.b.l = val;
 883 }
 884
 885 void DISPLAY::calc_apalette(uint16_t idx)
 886 {
 887         uint8_t r, g, b;
 888         idx = idx & 4095;
 889         g = analog_palette_g[idx];
 890         r = analog_palette_r[idx];
 891         b = analog_palette_b[idx];
 892         if(g != 0) g |= 0x0f;
 893         if(r != 0) r |= 0x0f;
 894         if(b != 0) b |= 0x0f;
 895         analog_palette_pixel_tmp[idx] = RGB_COLOR(r, g, b);
 896 }
 897
 898 // FD32
 899 void DISPLAY::set_apalette_b(uint8_t val)
 900 {
 901         uint16_t index;
 902         uint8_t tmp;
 903         index = apalette_index.w.l;
 904         tmp = (val & 0x0f) << 4;
 905         if(analog_palette_b[index] != tmp) {
 906                 analog_palette_b[index] = tmp;
 907                 calc_apalette(index);
 908                 palette_changed = true;
 909         }
 910 }
 911
 912 // FD33
 913 void DISPLAY::set_apalette_r(uint8_t val)
 914 {
 915         uint16_t index;
 916         uint8_t tmp;
 917         index = apalette_index.w.l;
 918         tmp = (val & 0x0f) << 4;
 919         if(analog_palette_r[index] != tmp) {
 920                 analog_palette_r[index] = tmp;
 921                 calc_apalette(index);
 922                 palette_changed = true;
 923         }
 924 }
 925
 926 // FD34
 927 void DISPLAY::set_apalette_g(uint8_t val)
 928 {
 929         uint16_t index;
 930         uint8_t tmp;
 931         index = apalette_index.w.l;
 932         tmp = (val & 0x0f) << 4;
 933         if(analog_palette_g[index] != tmp) {
 934                 analog_palette_g[index] = tmp;
 935                 calc_apalette(index);
 936                 palette_changed = true;
 937         }
 938 }
 939
 940 #endif // _FM77AV_VARIANTS
 941
 942
 943 void DISPLAY::copy_vram_blank_area(void)
 944 {
 945 }
 946
 947 void DISPLAY::copy_vram_per_line(int begin, int end)
 948 {
 949         uint32_t src_offset;
 950         uint32_t yoff_d1;
 951         uint32_t yoff_d2;
 952         uint32_t yoff_d;
 953         uint32_t poff = 0;
 954         uint32_t src_base;
 955         int pages = 1;
 956         uint32_t src_offset_d1;
 957         uint32_t src_offset_d2;
 958         uint32_t src_offset_d;
 959         uint32_t bytes_d1;
 960         uint32_t bytes_d2;
 961         uint32_t bytes_d;
 962
 963         uint32_t addr_d1, addr_d2;
 964         int sectors;
 965
 966         int i, j, k;
 967         //int dline = (int)displine - 1;
 968         int dline = (int)displine;
 969
 970         if((begin  < 0) || (begin > 4)) return;
 971         if((end  < 0) || (end > 4)) return;
 972         if(begin > end) return;
 973         if(dline < 0) return;
 974
 975         sectors = end - begin + 1;
 976
 977         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)){
 978                 if(dline >= 400) return;
 979         } else {
 980                 if(dline >= 200) return;
 981         }
 982 #if defined(_FM77AV_VARIANTS)
 983         yoff_d1 = offset_point;
 984         yoff_d2 = offset_point_bank1;
 985         if(display_mode == DISPLAY_MODE_4096) {
 986                 src_offset = dline * 40 + begin * 8;
 987                 sectors = sectors * 8;
 988 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
 989                 pages = 2;
 990 #endif
 991                 addr_d1 = (src_offset + yoff_d1) & 0x1fff;
 992                 addr_d2 = (src_offset + yoff_d2) & 0x1fff;
 993                 bytes_d1 = 0x2000 - addr_d1;
 994                 bytes_d2 = 0x2000 - addr_d2;
 995                 for(k = 0; k < pages; k++) {
 996                         src_base = 0;
 997                         for(i = 0; i < 3; i++) {
 998                                 for(j = 0; j < 2; j++) {
 999                                         uint32_t _addr_base = src_base + src_offset + poff;
1000                                         if(bytes_d1 < sectors) {
1001                                                 my_memcpy(&gvram_shadow[_addr_base],
1002                                                            &gvram[addr_d1 + src_base + poff],
1003                                                            bytes_d1);
1004                                                 my_memcpy(&gvram_shadow[_addr_base + bytes_d1],
1005                                                            &gvram[src_base + poff],
1006                                                            sectors - bytes_d1);
1007                                         } else {
1008                                                 my_memcpy(&gvram_shadow[_addr_base],
1009                                                            &gvram[addr_d1 + src_base + poff],
1010                                                            sectors);
1011                                         }
1012                                         _addr_base += 0xc000;
1013                                         if(bytes_d2 < sectors) {
1014                                                 my_memcpy(&gvram_shadow[_addr_base],
1015                                                            &gvram[addr_d2 + src_base + poff + 0xc000],
1016                                                            bytes_d2);
1017                                                 my_memcpy(&gvram_shadow[_addr_base + bytes_d2],
1018                                                            &gvram[src_base + poff + 0xc000],
1019                                                            sectors - bytes_d2);
1020                                         } else {
1021                                                 my_memcpy(&gvram_shadow[_addr_base],
1022                                                            &gvram[addr_d2 + src_base + poff + 0xc000],
1023                                                            sectors);
1024                                         }
1025                                         src_base += 0x2000;
1026                                 }
1027                                 src_base = (i + 1) * 0x4000;
1028                         }
1029                         poff += 0x18000;
1030                 }
1031                 vram_draw_table[dline] = true;
1032                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1033         }
1034 # if defined(_FM77AV40EX) || defined(_FM77AV40SX) || defined(_FM77AV40)
1035         else if(display_mode == DISPLAY_MODE_256k) {
1036                 src_offset = dline * 40 + begin * 8;
1037                 sectors = sectors * 8;
1038
1039 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1040                 pages = 4;
1041 #elif defined(_FM77AV40)
1042                 pages = 3;
1043 #else
1044                 pages = 0;
1045 #endif
1046                 src_offset_d1 = (src_offset + yoff_d1) & 0x1fff;
1047                 src_offset_d2 = (src_offset + yoff_d2) & 0x1fff;
1048                 bytes_d1 = 0x2000 - ((src_offset + yoff_d1) & 0x1fff);
1049                 bytes_d2 = 0x2000 - ((src_offset + yoff_d2) & 0x1fff);
1050                 for(k = 0; k < pages; k++) {
1051                         for(i = 0; i < 3; i++) {
1052                                 for(j = 0; j < 2; j++) {
1053                                         if((k & 1) == 0) {
1054                                                 src_base = i * 0x4000 + j * 0x2000 + k *  0xc000;
1055                                                 src_offset_d = src_offset_d1;
1056                                                 bytes_d = bytes_d1;
1057                                         } else {
1058                                                 src_base = i * 0x4000 + j * 0x2000 + k *  0xc000;
1059                                                 src_offset_d = src_offset_d2;
1060                                                 bytes_d = bytes_d2;
1061                                         }
1062                                         if(bytes_d < sectors) {
1063                                                 my_memcpy(&gvram_shadow[src_offset + src_base],
1064                                                            &gvram[src_offset_d + src_base],
1065                                                            bytes_d);
1066                                                 my_memcpy(&gvram_shadow[src_offset + bytes_d + src_base],
1067                                                            &gvram[src_base],
1068                                                            sectors - bytes_d);
1069                                         } else {
1070                                                 my_memcpy(&gvram_shadow[src_offset + src_base],
1071                                                            &gvram[src_offset_d + src_base],
1072                                                            sectors);
1073                                         }
1074                                 }
1075                         }
1076                 }
1077                 vram_draw_table[dline] = true;
1078                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1079         }
1080         else if(display_mode == DISPLAY_MODE_8_400L) {
1081                 src_offset = dline * 80 + begin * 16;
1082                 sectors = sectors * 16;
1083 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1084                 pages = 2;
1085 #endif
1086                 if(display_page_bak == 1) { // Is this dirty?
1087                         yoff_d = yoff_d2;
1088                 } else {
1089                         yoff_d = yoff_d1;
1090                 }
1091                 yoff_d = (yoff_d << 1) & 0x7fff;
1092                 src_offset_d = (src_offset + yoff_d) & 0x7fff;
1093                 bytes_d = 0x8000 - ((src_offset + yoff_d) & 0x7fff);
1094                 for(i = 0; i < pages; i++) {
1095                         for(j = 0; j < 3; j++) {
1096                                 src_base = i * 0x18000 + j * 0x8000;
1097                                 if(bytes_d < sectors) {
1098                                         if(bytes_d > 0) {
1099                                                 my_memcpy(&gvram_shadow[src_offset + src_base],
1100                                                            &gvram[src_offset_d + src_base],
1101                                                            bytes_d);
1102                                         }
1103                                         my_memcpy(&gvram_shadow[src_offset + bytes_d + src_base],
1104                                                    &gvram[src_base],
1105                                                    sectors - bytes_d);
1106                                 } else {
1107                                         my_memcpy(&gvram_shadow[src_offset + src_base + poff],
1108                                                    &gvram[src_offset_d + src_base],
1109                                                    sectors);
1110                                 }
1111                         }
1112                 }
1113                 vram_draw_table[dline] = true;
1114                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1115         }
1116 #endif
1117         else { // 200line
1118                 src_offset = dline * 80 + begin * 16;
1119                 sectors = sectors * 16;
1120 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1121                 pages = 4;
1122 #elif defined(_FM77AV40)
1123                 pages = 3;
1124 #elif defined(_FM77AV_VARIANTS)
1125                 pages = 2;
1126 #else
1127                 pages = 1;
1128 #endif
1129                 poff = 0;
1130                 src_offset_d1 = (src_offset + yoff_d1) & 0x3fff;
1131                 src_offset_d2 = (src_offset + yoff_d2) & 0x3fff;
1132                 bytes_d1 = 0x4000 - ((src_offset + yoff_d1) & 0x3fff);
1133                 bytes_d2 = 0x4000 - ((src_offset + yoff_d2) & 0x3fff);
1134                 for(i = 0; i < pages; i++) {
1135                         if((i & 1) == 0) {
1136                                 src_offset_d = src_offset_d1;
1137                                 bytes_d = bytes_d1;
1138                         } else {
1139                                 src_offset_d = src_offset_d2;
1140                                 bytes_d = bytes_d2;
1141                         }
1142                         src_base = 0;
1143                         for(j = 0; j < 3; j++) {
1144                                 if(bytes_d < sectors) {
1145                                         my_memcpy(&gvram_shadow[src_offset + src_base + poff],
1146                                                    &gvram[src_offset_d + src_base + poff],
1147                                                    bytes_d);
1148                                         my_memcpy(&gvram_shadow[src_offset + bytes_d + src_base + poff],
1149                                                    &gvram[src_base + poff],
1150                                                    sectors - bytes_d);
1151                                 } else {
1152                                         my_memcpy(&gvram_shadow[src_offset + src_base + poff],
1153                                                    &gvram[src_offset_d + src_base + poff],
1154                                                    sectors);
1155                                 }
1156                                 src_base += 0x4000;
1157                         }
1158                         poff += 0xc000;
1159                 }
1160                 vram_draw_table[dline] = true;
1161                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1162                 //vram_wrote_table[dline] = false;
1163         }
1164 #else // FM-8/7/77
1165 #if defined(_FM77L4)
1166         if(display_mode == DISPLAY_MODE_1_400L) {
1167                 src_offset = dline * 80 + begin * 16;
1168                 sectors = sectors * 16;
1169                 yoff_d = (yoff_d1 << 1) & 0x7fff;
1170                 src_offset_d = (src_offset + yoff_d) & 0x7fff;
1171                 bytes_d = 0x8000 - ((src_offset + yoff_d) & 0x7fff);
1172                 if(bytes_d < sectors) {
1173                         if(bytes_d > 0) {
1174                                 my_memcpy(&gvram_shadow[src_offset],
1175                                                   &gvram[src_offset_d],
1176                                                   bytes_d);
1177                         }
1178                         my_memcpy(&gvram_shadow[src_offset + bytes_d + src_base],
1179                                           &gvram[0],
1180                                           sectors - bytes_d);
1181                 } else {
1182                         my_memcpy(&gvram_shadow[src_offset +  poff],
1183                                           &gvram[src_offset_d ],
1184                                           sectors);
1185                 }
1186                 vram_draw_table[dline] = true;
1187                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1188                 return;
1189         }
1190 #endif
1191         { // 200line
1192                 src_offset = dline * 80 + begin * 16;
1193                 sectors = sectors * 16;
1194                 pages = 1;
1195                 poff = 0;
1196                 yoff_d = offset_point;
1197                 src_offset_d = (src_offset + yoff_d) & 0x3fff;
1198                 bytes_d = 0x4000 - ((src_offset + yoff_d) & 0x3fff);
1199                 for(j = 0; j < 3; j++) {
1200                         src_base = j * 0x4000;
1201                         if(bytes_d < sectors) {
1202                                 my_memcpy(&gvram_shadow[src_offset + src_base + poff],
1203                                            &gvram[src_offset_d + src_base + poff],
1204                                            bytes_d);
1205                                 my_memcpy(&gvram_shadow[src_offset + bytes_d + src_base + poff],
1206                                            &gvram[src_base + poff],
1207                                            sectors - bytes_d);
1208                         } else {
1209                                 my_memcpy(&gvram_shadow[src_offset + src_base + poff],
1210                                            &gvram[src_offset_d + src_base + poff],
1211                                            sectors);
1212                         }
1213                 }
1214                 vram_draw_table[dline] = true;
1215                 for(int ii = begin; ii <= end; ii++) vram_wrote_table[(dline * 5) + ii] = false;
1216                 //vram_wrote_table[dline] = false;
1217         }
1218
1219 #endif
1220 }
1221
1222 void DISPLAY::copy_vram_all()
1223 {
1224 #if defined(_FM77AV_VARIANTS)
1225         uint32_t yoff_d1 = offset_point;
1226         uint32_t yoff_d2 = offset_point_bank1;
1227         uint32_t src_offset_1, src_offset_2;
1228         uint32_t poff = 0;
1229         if(display_mode == DISPLAY_MODE_4096) {
1230 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1231                 int pages = 2;
1232 #else
1233                 int pages = 1;
1234 #endif
1235                 uint32_t bytes_d1 = 0x2000 - (yoff_d1 & 0x1fff);
1236                 uint32_t bytes_d2 = 0x2000 - (yoff_d2 & 0x1fff);
1237                 for(int k = 0; k < pages; k++) {
1238                         for(int i = 0; i < 3; i++) {
1239                                 for(int j = 0; j < 2; j++) {
1240                                         src_offset_1 = i * 0x4000 + j * 0x2000;
1241                                         src_offset_2 = src_offset_1 + 0xc000;
1242                                         my_memcpy(&gvram_shadow[src_offset_1 + poff], &gvram[src_offset_1 + (yoff_d1 & 0x1fff) + poff], bytes_d1);
1243                                         my_memcpy(&gvram_shadow[src_offset_1 + bytes_d1 + poff], &gvram[src_offset_1 + poff], 0x2000 - bytes_d1);
1244                                         my_memcpy(&gvram_shadow[src_offset_2 + poff], &gvram[src_offset_2 + (yoff_d2 & 0x1fff) + poff], bytes_d2);
1245                                         my_memcpy(&gvram_shadow[src_offset_2 + bytes_d2 + poff], &gvram[src_offset_2 + poff], 0x2000 - bytes_d2);
1246                                 }
1247                         }
1248                         poff += 0x18000;
1249                 }
1250         }
1251 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
1252         else if(display_mode == DISPLAY_MODE_256k) {
1253                 uint32_t bytes_d1 = 0x2000 - (yoff_d1 & 0x1fff);
1254                 uint32_t bytes_d2 = 0x2000 - (yoff_d2 & 0x1fff);
1255                 for(int i = 0; i < 3; i++) {
1256                         for(int j = 0; j < 2; j++) {
1257                                 src_offset_1 = i * 0x4000 + j * 0x2000;
1258                                 src_offset_2 = src_offset_1 + 0xc000;
1259                                 my_memcpy(&gvram_shadow[src_offset_1 + poff], &gvram[src_offset_1 + (yoff_d1 & 0x1fff) + poff], bytes_d1);
1260                                 my_memcpy(&gvram_shadow[src_offset_1 + bytes_d1 + poff], &gvram[src_offset_1 + poff], 0x2000 - bytes_d1);
1261                                 my_memcpy(&gvram_shadow[src_offset_2 + poff], &gvram[src_offset_2 + (yoff_d2 & 0x1fff) + poff], bytes_d2);
1262                                 my_memcpy(&gvram_shadow[src_offset_2 + bytes_d2 + poff], &gvram[src_offset_2 + poff], 0x2000 - bytes_d2);
1263                         }
1264                 }
1265                 poff += 0x18000;
1266                 for(int i = 0; i < 3; i++) {
1267                         for(int j = 0; j < 2; j++) {
1268                                 src_offset_1 = i * 0x4000 + j * 0x2000;
1269                                 my_memcpy(&gvram_shadow[src_offset_1 + poff], &gvram[src_offset_1 + (yoff_d1 & 0x1fff) + poff], bytes_d1);
1270                                 my_memcpy(&gvram_shadow[src_offset_1 + bytes_d1 + poff], &gvram[src_offset_1 + poff], 0x2000 - bytes_d1);
1271                         }
1272                 }
1273         } else if(display_mode == DISPLAY_MODE_8_400L) {
1274                 int pages = 1;
1275                 uint32_t yoff_d, bytes_d;
1276 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1277                 pages = 2;
1278 #endif
1279                 if(display_page_bak == 1) { // Is this dirty?
1280                         yoff_d = yoff_d2;
1281                 } else {
1282                         yoff_d = yoff_d1;
1283                 }
1284                 yoff_d = (yoff_d << 1) & 0x7fff;
1285                 bytes_d = 0x8000 - yoff_d;
1286                 for(int i = 0; i < pages; i++) {
1287                         for(int j = 0; j < 3; j++) {
1288                                 uint32_t src_base = i * 0x18000 + j * 0x8000;
1289                                 my_memcpy(&gvram_shadow[src_base],
1290                                            &gvram[yoff_d + src_base],
1291                                            bytes_d);
1292                                 if(bytes_d < 0x8000) {
1293                                         my_memcpy(&gvram_shadow[bytes_d + src_base],
1294                                                    &gvram[src_base],
1295                                                    0x8000 - bytes_d);
1296                                 }
1297                         }
1298                 }
1299         }
1300 #endif
1301     else { // 200line
1302 #if defined(_FM77AV40EX) || defined(_FM77AV40SX)
1303                 int pages = 4;
1304 #elif defined(_FM77AV40)
1305                 int pages = 3;
1306 #else
1307                 int pages = 2;
1308 #endif
1309                 uint32_t bytes_d1 = 0x4000 - (yoff_d1 & 0x3fff);
1310                 uint32_t bytes_d2 = 0x4000 - (yoff_d2 & 0x3fff);
1311                 uint32_t yoff_d, bytes_d;
1312                 for(int k = 0; k < pages; k++) {
1313                         yoff_d = ((k & 1) == 0) ? (yoff_d1 & 0x3fff) : (yoff_d2 & 0x3fff);
1314                         bytes_d = ((k & 1) == 0) ? bytes_d1 : bytes_d2;
1315                         for(int j = 0; j < 3; j++) {
1316                                 src_offset_1 = k * 0xc000 + j * 0x4000;
1317                                 my_memcpy(&gvram_shadow[src_offset_1], &gvram[src_offset_1 + yoff_d], bytes_d);
1318                                 my_memcpy(&gvram_shadow[src_offset_1 + bytes_d], &gvram[src_offset_1], 0x4000 - bytes_d);
1319                         }
1320                 }
1321         }
1322 #else // FM-8/7/77
1323 #  if defined(_FM77L4)
1324         if(display_mode == DISPLAY_MODE_1_400L) {
1325                 uint32_t yoff_d = offset_point & 0x7fff;
1326                 uint32_t bytes_d = 0x8000 - (offset_point & 0x7fff);
1327                 my_memcpy(&gvram_shadow[0], &gvram[0 + yoff_d], bytes_d);
1328                 my_memcpy(&gvram_shadow[0 + bytes_d], &gvram[0], 0x8000 - bytes_d);
1329                 return;
1330         }
1331 #  endif
1332     { // 200line
1333                 uint32_t yoff_d = offset_point & 0x3fff;
1334                 uint32_t bytes_d = 0x4000 - (offset_point & 0x3fff);
1335                 uint32_t src_offset_1;
1336                 for(int j = 0; j < 3; j++) {
1337                         src_offset_1 = j * 0x4000;
1338                         my_memcpy(&gvram_shadow[src_offset_1], &gvram[src_offset_1 + yoff_d], bytes_d);
1339                         my_memcpy(&gvram_shadow[src_offset_1 + bytes_d], &gvram[src_offset_1], 0x4000 - bytes_d);
1340                 }
1341         }
1342 #endif
1343 }
1344
1345 // Timing values from XM7 . Thanks Ryu.
1346 //#if defined(_FM77AV_VARIANTS) || defined(_FM77L4)
1347 void DISPLAY::event_callback_hdisp(void)
1348 {
1349         bool f = false;
1350         double usec;
1351         hblank = false;
1352         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x02, 0xff);
1353         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1354                 if(displine < 400) f = true;
1355         } else {
1356                 if(displine < 200) f = true;
1357         }
1358
1359         hdisp_event_id = -1;
1360         if(f) {
1361                 // DO ONLY WHEN SYNC-TO-HSYNC.
1362                 if((config.dipswitch & FM7_DIPSW_SYNC_TO_HSYNC) != 0) {
1363                         if(vram_wrote) {
1364                                 //copy_vram_per_line(0, 4);
1365                         } else if(need_transfer_line) { // Not frame skip.
1366                                 int begin = -1;
1367                                 int end = -1;
1368                                 for(int iii = 0; iii < 5 ; iii++) {
1369                                         if(vram_wrote_table[iii + displine * 5]) {
1370                                                 if(begin < 0) begin = iii; // Check first.
1371                                         } else {
1372                                                 // Check end.
1373                                                 if(begin >= 0) {
1374                                                         end = iii - 1;
1375                                                         if(end < begin) end = begin;
1376                                                         // Do transfer.
1377                                                         copy_vram_per_line(begin, end);
1378                                                         // Prepare to next block.
1379                                                         begin = -1;
1380                                                         end = -1;
1381                                                 }
1382                                         }
1383                                 }
1384                                 // Tail of this line.
1385                                 if(begin >= 0) {
1386                                         end = 4;
1387                                         copy_vram_per_line(begin, end);
1388                                 }
1389                         }
1390                 }
1391                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1392                         register_event(this, EVENT_FM7SUB_HBLANK, 30.0, false, &hblank_event_id); // NEXT CYCLE_
1393                 } else {
1394                         register_event(this, EVENT_FM7SUB_HBLANK, 39.5, false, &hblank_event_id); // NEXT CYCLE_
1395                 }
1396                 vsync = false;
1397                 vblank = false;
1398                 enter_display();
1399         }
1400         f = false;
1401 }
1402 void DISPLAY::event_callback_hblank(void)
1403 {
1404         bool f = false;
1405         bool ff = false;
1406         double usec;
1407
1408         hblank = true;
1409         hblank_event_id = -1;
1410
1411         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x00, 0xff);
1412         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1413                 if((displine < 400)) f = true;
1414                 usec = 11.0;
1415         } else {
1416                 if((displine < 200)) f = true;
1417                 usec = 24.0;
1418         }
1419         if(f) {
1420                 register_event(this, EVENT_FM7SUB_HDISP, usec, false, &hdisp_event_id);
1421         }
1422         displine++;
1423 }
1424
1425 void DISPLAY::event_callback_vstart(void)
1426 {
1427         double usec;
1428         vblank = true;
1429         vsync = false;
1430         hblank = false;
1431         displine = 0;
1432         display_page_bak = display_page;
1433
1434         // Parameter from XM7/VM/display.c , thanks, Ryu.
1435         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x00, 0xff);
1436         call_write_signal(mainio, SIG_DISPLAY_VSYNC, 0x00, 0xff);
1437
1438         if(vblank_count != 0) {
1439                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1440                         usec = (0.98 + 16.4) * 1000.0;
1441                 } else {
1442                         usec = (1.91 + 12.7) * 1000.0;
1443                 }
1444                 register_event(this, EVENT_FM7SUB_VSYNC, usec, false, &vsync_event_id);
1445
1446                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1447                         usec = 930.0; // 939.0
1448                 } else {
1449                         usec = 1840.0; // 1846.5
1450                 }
1451                 vstart_event_id = -1;
1452                 register_event(this, EVENT_FM7SUB_HDISP, usec, false, &hdisp_event_id); // NEXT CYCLE_
1453                 //register_event(this, EVENT_FM7SUB_HBLANK, usec, false, &hdisp_event_id); // NEXT CYCLE_
1454                 vblank_count = 0;
1455         } else {
1456                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1457                         usec = 0.34 * 1000.0;
1458                 } else {
1459                         usec = 1.52 * 1000.0;
1460                 }
1461                 vsync_event_id = -1;
1462                 hblank_event_id = -1;
1463                 hdisp_event_id = -1;
1464                 register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
1465                 vblank_count++;
1466         }
1467 }
1468 void DISPLAY::event_callback_vsync(void)
1469 {
1470         double usec;
1471         vblank = true;
1472         hblank = false;
1473         vsync = true;
1474         //write_access_page = (write_access_page + 1) & 1;
1475         //displine = 0;
1476
1477         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1478                 usec = 0.33 * 1000.0;
1479         } else {
1480                 usec = 0.51 * 1000.0;
1481         }
1482         call_write_signal(mainio, SIG_DISPLAY_VSYNC, 0x01, 0xff);
1483         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x00, 0xff);
1484         //register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
1485
1486         if(palette_changed) {
1487 #if defined(_FM77AV_VARIANTS)
1488                 memcpy(analog_palette_pixel, analog_palette_pixel_tmp, sizeof(analog_palette_pixel));
1489 #endif
1490 #if defined(USE_GREEN_DISPLAY)
1491                 memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
1492 #endif
1493                 memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
1494                 vram_wrote_shadow = true;
1495                 for(int yy = 0; yy < 400; yy++) {
1496                         vram_draw_table[yy] = true;
1497                 }
1498                 palette_changed = false;
1499         }
1500         // Transfer on VSYNC
1501         if((config.dipswitch & FM7_DIPSW_SYNC_TO_HSYNC) == 0) {
1502                 bool ff = false;
1503                 int lines = 200;
1504
1505                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L))lines = 400;
1506                 if(need_transfer_line) {
1507                         if(vram_wrote) { // transfer all line
1508                                 for(displine = 0; displine < lines; displine++) {
1509                                         //if(!vram_draw_table[displine]) {
1510                                         copy_vram_per_line(0, 4);
1511                                                 //}
1512                                 }
1513                                 vram_wrote = false;
1514                         } else { // transfer wrote line
1515                                 int begin = -1;
1516                                 int end = -1;
1517                                 for(displine = 0; displine < lines; displine++) {
1518                                         //if(!vram_draw_table[displine]) {
1519                                         for(int iii = 0; iii < 5 ; iii++) {
1520                                                 if(vram_wrote_table[iii + displine * 5]) {
1521                                                         if(begin < 0) {
1522                                                                 begin = iii;
1523                                                         }
1524                                                 } else {
1525                                                         if(begin >= 0) {
1526                                                                 end = iii - 1;
1527                                                                 if(end < begin) end = begin;
1528                                                                 copy_vram_per_line(begin, end);
1529                                                                 begin = -1;
1530                                                                 end = -1;
1531                                                         }
1532                                                 }
1533                                         }
1534                                         if(begin >= 0) {
1535                                                 if(end < 0) end = 4;
1536                                                 copy_vram_per_line(begin, end);
1537                                         }
1538                                         begin = -1;
1539                                         end = -1;
1540                                 //}
1541                                 }
1542                         }
1543                 }
1544                 for(int yy = 0; yy < lines; yy++) {
1545                         if(vram_draw_table[yy]) {
1546                                 vram_wrote_shadow = true;
1547                                 screen_update_flag = true;
1548                                 break;
1549                         }
1550                 }
1551         } else {
1552                 // TRANSFER per HSYNC a.k.a SYNC-TO-HSYNC.
1553                 int lines = 200;
1554                 if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) lines = 400;
1555
1556                 if(need_transfer_line) {
1557                         if(vram_wrote) { // Transfer all line.
1558                                 for(int yy = 0; yy < lines; yy++) {
1559                                         displine = yy;
1560                                         copy_vram_per_line(0, 4);
1561                                 }
1562                                 //displine = 0;
1563                                 vram_wrote = false;
1564                         }
1565                 }
1566                 for(int yy = 0; yy < lines; yy++) {
1567                         if(vram_draw_table[yy]) {
1568                                 vram_wrote_shadow = true;
1569                                 screen_update_flag = true;
1570                                 break;
1571                         }
1572                 }
1573                 //vram_wrote = false;
1574         }
1575         frame_skip_count_transfer++;
1576         {
1577                 // Check frame skip for next frame.
1578                 uint32_t factor = ((config.dipswitch & FM7_DIPSW_FRAMESKIP) >> 28) & 3;
1579                 if((frame_skip_count_transfer > factor) /* || (vram_wrote) */) {
1580                         frame_skip_count_transfer = 0;
1581                         need_transfer_line = true;
1582                 } else {
1583                         need_transfer_line = false;
1584                 }
1585         }
1586 }
1587
1588 //#endif
1589 #if defined(_FM77L4)
1590 void DISPLAY::cursor_blink_77l4()
1591 {
1592         if(!(mode400line && stat_400linecard)) return;
1593         uint8_t *regs = l4crtc->get_regs();
1594         uint32_t naddr;
1595         if(regs != NULL) {
1596                 int x, y;
1597                 if((regs[10] & 0x40) != 0) {
1598                         cursor_blink = !cursor_blink;
1599                         uint16_t addr = cursor_addr.w.l;
1600                         if(text_width40) {
1601                                 x = ((addr / 2) % 40) / 8;
1602                                 y = (addr / 2) / 40;
1603                         } else { // Width 80
1604                                 x = ((addr / 2) % 80) / 8;
1605                                 y = (addr / 2) / 80;
1606                         }
1607                         for(int yy = 0; yy < 8; yy++) {
1608                                 naddr = (y + yy) * 5 + x;
1609                                 vram_wrote_table[naddr] = true;
1610                         }
1611                 }
1612         }
1613 }
1614
1615 void DISPLAY::text_blink_77l4()
1616 {
1617         uint16_t addr;
1618         uint16_t offset = text_start_addr.w.l;
1619         uint32_t naddr;
1620         int x, y;
1621         if(!(mode400line && stat_400linecard)) return;
1622         text_blink = !text_blink;
1623         for(addr = 0; addr < (80 * 50); addr++) {
1624                 naddr = ((addr + offset) & 0x0ffe) + 1;
1625                 if((text_vram[naddr] & 0x10) != 0) { // ATTR BLINK
1626                         if(text_width40) {
1627                                 x = ((naddr / 2) % 40) / 8;
1628                                 y = (naddr / 2) / 40;
1629                         } else { // Width 80
1630                                 x = ((naddr / 2) % 80) / 8;
1631                                 y = (naddr / 2) / 80;
1632                         }
1633                         for(int yy = 0; yy < 8; yy++) {
1634                                 naddr = (y + yy) * 5 + x;
1635                                 vram_wrote_table[naddr] = true;
1636                         }
1637                 }
1638         }
1639 }
1640 #endif //#if defined(_FM77L4)
1641
1642 void DISPLAY::event_callback(int event_id, int err)
1643 {
1644         double usec;
1645         bool f;
1646         switch(event_id) {
1647                 case EVENT_FM7SUB_DISPLAY_NMI: // per 20.00ms
1648 #if defined(_FM77AV_VARIANTS)
1649                         if(nmi_enable) {
1650                                 do_nmi(true);
1651                         }
1652 #else
1653                         do_nmi(true);
1654 #endif
1655                         break;
1656                 case EVENT_FM7SUB_DISPLAY_NMI_OFF: // per 20.00ms
1657                         do_nmi(false);
1658                         break;
1659 //#if defined(_FM77AV_VARIANTS) || defined(_FM77L4)
1660                 case EVENT_FM7SUB_HDISP:
1661                         event_callback_hdisp();
1662                         break;
1663                 case EVENT_FM7SUB_HBLANK:
1664                         event_callback_hblank();
1665                         break;
1666                 case EVENT_FM7SUB_VSTART: // Call first.
1667                         event_callback_vstart();
1668                         break;
1669                 case EVENT_FM7SUB_VSYNC:
1670                         event_callback_vsync();
1671                         break;
1672 //#endif
1673                 case EVENT_FM7SUB_CLR_BUSY:
1674                         set_subbusy();
1675                         break;
1676                 case EVENT_FM7SUB_CLR_CRTFLAG:
1677                         reset_crtflag();
1678                         break;
1679 #if defined(_FM77L4)
1680                 case EVENT_FM7SUB_CURSOR_BLINK:
1681                         cursor_blink_77l4();
1682                         break;
1683                 case EVENT_FM7SUB_TEXT_BLINK:
1684                         text_blink_77l4();
1685                         break;
1686 #endif
1687         }
1688 }
1689
1690 void DISPLAY::event_frame()
1691 {
1692 #if 1
1693         double usec;
1694         vblank = true;
1695         hblank = false;
1696         vsync = true;
1697         //write_access_page = (write_access_page + 1) & 1;
1698         //out_debug_log(_T("DISPLINE=%d"), displine);
1699         displine = 0;
1700         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) {
1701                 usec = 0.34 * 1000.0;
1702         } else {
1703                 usec = 1.52 * 1000.0;
1704         }
1705         call_write_signal(mainio, SIG_DISPLAY_VSYNC, 0x01, 0xff);
1706         call_write_signal(mainio, SIG_DISPLAY_DISPLAY, 0x00, 0xff);
1707         register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
1708         vblank_count = 1;
1709 #endif
1710 #if 0
1711 #if !defined(_FM77AV_VARIANTS) && !defined(_FM77L4)
1712         int yy;
1713         bool f = false;
1714         int lines = 200;
1715         if((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) lines = 400;
1716 #if 0
1717         if(need_transfer_line && vram_wrote) {
1718                 for(yy = 0; yy < lines; yy++) {
1719                         //if(!vram_draw_table[yy]) {
1720                                 displine = yy;
1721                                 copy_vram_per_line(0, 4);
1722                         //}
1723                 }
1724                 vram_wrote = false;
1725                 displine = 0;
1726         }
1727 #endif
1728         {
1729                 for(yy = 0; yy < lines; yy++) {
1730                         if(vram_draw_table[yy]) {
1731                                 f = true;
1732                                 break;
1733                         }
1734                 }
1735                 if(f) {
1736                         screen_update_flag = true;
1737                         vram_wrote_shadow = true;
1738                 }
1739         }
1740         enter_display();
1741         frame_skip_count_transfer++;
1742         {
1743                 uint32_t factor = (config.dipswitch & FM7_DIPSW_FRAMESKIP) >> 28;
1744                 if(frame_skip_count_transfer > factor) {
1745                         frame_skip_count_transfer = 0;
1746                         need_transfer_line = true;
1747                 } else {
1748                         need_transfer_line = false;
1749                         displine = 0;
1750                         //vram_wrote = false;
1751                 }
1752         }
1753
1754 #endif
1755 #endif
1756 }
1757
1758 void DISPLAY::event_vline(int v, int clock)
1759 {
1760 #if !defined(_FM77AV_VARIANTS) && !defined(_FM77L4)
1761         bool ff = false;
1762         if(need_transfer_line == false) return;
1763         displine = v;
1764         if(vram_wrote) {
1765                 // Not transfer, will transfer at event_frame.
1766                 copy_vram_per_line(0, 4);
1767         } else {
1768                 int begin = -1;
1769                 int end = -1;
1770                 for(int iii = 0; iii < 5 ; iii++) {
1771                         if(vram_wrote_table[displine * 5 + iii]) {
1772                                 if(begin < 0) begin = iii;
1773                         } else {
1774                                 if(begin >= 0) {
1775                                         end = iii - 1;
1776                                         if(end < begin) end = begin;
1777                                         copy_vram_per_line(begin, end);
1778                                         begin = -1;
1779                                         end = -1;
1780                                 }
1781                         }
1782                 }
1783                 if(begin >= 0) {
1784                         end = 4;
1785                         copy_vram_per_line(begin, end);
1786                 }
1787         }
1788         enter_display();
1789 #endif
1790 }
1791
1792
1793 uint32_t DISPLAY::read_signal(int id)
1794 {
1795         uint32_t retval = 0;
1796         switch(id) {
1797                 case SIG_FM7_SUB_HALT:
1798                 case SIG_DISPLAY_HALT:
1799                         retval = (halt_flag) ? 0xffffffff : 0;
1800                         break;
1801                 case SIG_DISPLAY_BUSY:
1802                         retval =  (sub_busy) ? 0x80 : 0;
1803                         break;
1804                 case SIG_DISPLAY_MULTIPAGE:
1805                         retval =  multimode_accessmask;
1806                         break;
1807                 case SIG_DISPLAY_PLANES:
1808                         retval = 3;
1809                         break;
1810 #if defined(_FM77AV_VARIANTS)
1811                 case SIG_DISPLAY_VSYNC:
1812                         retval = (vsync) ? 0x01 : 0x00;
1813                         break;
1814                 case SIG_DISPLAY_DISPLAY:
1815                         retval = (!hblank) ? 0x02: 0x00;
1816                         break;
1817                 case SIG_FM7_SUB_BANK: // Main: FD13
1818                         retval = subrom_bank & 0x03;
1819 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
1820                         if(monitor_ram) retval |= 0x04;
1821 #endif
1822                         break;
1823 #endif
1824 #if defined(_FM77AV_VARIANTS)
1825                 case SIG_DISPLAY_MODE320:
1826                         retval = (mode320) ? 0x40: 0x00;
1827                         break;
1828 #endif
1829                 case SIG_DISPLAY_Y_HEIGHT:
1830 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || defined(_FM77L4)
1831                         retval = ((display_mode == DISPLAY_MODE_8_400L) || (display_mode == DISPLAY_MODE_1_400L)) ? 400 : 200;
1832 #else
1833                         retval = 200;
1834 #endif
1835                         break;
1836                 case SIG_DISPLAY_EXTRA_MODE: // FD04 bit 4, 3
1837                         retval = 0;
1838 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
1839                         retval |= (kanjisub) ? 0x00 : 0x20;
1840                         retval |= (mode256k) ? 0x10 : 0x00;
1841                         retval |= (mode400line) ? 0x00 : 0x08;
1842                         retval |= (ram_protect) ? 0x00 : 0x04;
1843 #elif defined(_FM77_VARIANTS)
1844                         retval = 0x04;
1845                         retval |= (kanjisub) ? 0x00 : 0x20;
1846 #  if defined(_FM77L4)
1847                         retval |= (stat_400linecard) ? 0x00 : 0x08;
1848 #  else
1849                         retval |= 0x18;
1850 #  endif
1851 #else
1852                         retval = 0x2c;
1853 #endif
1854                         break;
1855                 case SIG_DISPLAY_X_WIDTH:
1856 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
1857                         retval = (mode320 || mode256k) ? 320 : 640;
1858 #elif defined(_FM77AV_VARIANTS)
1859                         retval = (mode320) ? 320 : 640;
1860 #else
1861                         retval = 640;
1862 #endif
1863                         break;
1864                 default:
1865                         break;
1866         }
1867         return retval;
1868 }
1869
1870 void DISPLAY::write_signal(int id, uint32_t data, uint32_t mask)
1871 {
1872         bool flag = ((data & mask) != 0);
1873         bool oldflag;
1874         int y;
1875         switch(id) {
1876                 case SIG_FM7_SUB_HALT:
1877                         if(flag) {
1878                                 sub_busy = true;
1879                         }
1880                         halt_flag = flag;
1881                         //call_write_signal(mainio, SIG_FM7_SUB_HALT, data, mask);
1882                         break;
1883                 case SIG_DISPLAY_HALT:
1884                         if(flag) {
1885                                 halt_subsystem();
1886                         } else {
1887                                 restart_subsystem();
1888                         }
1889                         break;
1890                 case SIG_FM7_SUB_CANCEL:
1891                         if(flag) {
1892                                 cancel_request = true;
1893                                 do_irq(true);
1894                         }
1895                         break;
1896                 case SIG_DISPLAY_CLOCK:
1897                         clock_fast = flag;
1898                         enter_display();
1899                         break;
1900 #if defined(_FM77AV_VARIANTS)
1901                 case SIG_FM7_SUB_BANK: // Main: FD13
1902                         set_monitor_bank(data & 0xff);
1903                         break;
1904 #endif
1905                 case SIG_DISPLAY_EXTRA_MODE: // FD04 bit 4, 3
1906 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
1907                         //printf("Wrote $FD04: %02x\n", data);
1908                         {
1909                                 int oldmode = display_mode;
1910                                 int mode;
1911                                 kanjisub = ((data & 0x20) == 0) ? true : false;
1912                                 mode256k = (((data & 0x10) != 0) && ((data & 0x08) != 0) ) ? true : false;
1913                                 mode400line = ((data & 0x08) == 0) ? true : false;
1914                                 ram_protect = ((data & 0x04) == 0) ? true : false;
1915                                 if((mode400line) && !(mode320)) {
1916                                         display_mode = DISPLAY_MODE_8_400L;
1917                                 } else if(mode256k) {
1918                                         display_mode = DISPLAY_MODE_256k;
1919                                 } else {
1920                                         display_mode = (mode320) ? DISPLAY_MODE_4096 : DISPLAY_MODE_8_200L;
1921                                 }
1922                                 if(oldmode != display_mode) {
1923                                         scrntype_t *pp;
1924                                         if(mode320 || mode256k) {
1925                                                 if(oldmode == DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(FRAMES_PER_SEC);
1926 #if !defined(FIXED_FRAMEBUFFER_SIZE)
1927                                                 emu->set_vm_screen_size(320, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
1928                                                 for(y = 0; y < 200; y++) {
1929                                                         pp = emu->get_screen_buffer(y);
1930                                                         if(pp != NULL) memset(pp, 0x00, 320 * sizeof(scrntype_t));
1931                                                 }
1932 #else
1933                                                 for(y = 0; y < 400; y++) {
1934                                                         pp = emu->get_screen_buffer(y);
1935                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
1936                                                 }
1937 #endif
1938                                                 //emu->set_vm_screen_lines(200);
1939                                         } else if(display_mode == DISPLAY_MODE_8_400L) {
1940                                                 emu->set_vm_screen_size(640, 400, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
1941                                                 if(oldmode != DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(55.40);
1942                                                 for(y = 0; y < 400; y++) {
1943                                                         pp = emu->get_screen_buffer(y);
1944                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
1945                                                 }
1946                                         } else {
1947                                                 if(oldmode == DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(FRAMES_PER_SEC);
1948 #if !defined(FIXED_FRAMEBUFFER_SIZE)
1949                                                 emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
1950                                                 for(y = 0; y < 200; y++) {
1951                                                         pp = emu->get_screen_buffer(y);
1952                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
1953                                                 }
1954 #else
1955                                                 for(y = 0; y < 400; y++) {
1956                                                         pp = emu->get_screen_buffer(y);
1957                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
1958                                                 }
1959 #endif
1960                                                 //emu->set_vm_screen_lines(200);
1961                                         }
1962                                         vram_wrote = true;
1963                                         call_write_signal(alu, SIG_ALU_X_WIDTH, (mode320 || mode256k) ? 40 :  80, 0xffff);
1964                                         call_write_signal(alu, SIG_ALU_Y_HEIGHT, (display_mode == DISPLAY_MODE_8_400L) ? 400 : 200, 0xffff);
1965                                         call_write_signal(alu, SIG_ALU_400LINE, (display_mode == DISPLAY_MODE_8_400L) ? 0xff : 0x00, 0xff);
1966                                         frame_skip_count_draw = 3;
1967                                         frame_skip_count_transfer = 3;
1968                                         setup_display_mode();
1969                                 }
1970                         }
1971 #elif defined(_FM77_VARIANTS)
1972                         {
1973                                 int oldmode = display_mode;
1974                                 kanjisub = ((data & 0x20) == 0) ? true : false;
1975 # if defined(_FM77L4)
1976                                 stat_400linecard = ((data & 0x08) != 0) ? false : true;
1977                                 if(mode400line && stat_400linecard) {
1978                                         double usec;
1979                                         uint8_t *regs = l4crtc->get_regs();
1980                                         display_mode = DISPLAY_MODE_1_400L;
1981                                         if(event_id_l4_cursor_blink >= 0) {
1982                                                 cancel_event(this, event_id_l4_cursor_blink);
1983                                         }
1984                                         if(event_id_l4_text_blink >= 0) {
1985                                                 cancel_event(this, event_id_l4_text_blink);
1986                                         }
1987                                         event_id_l4_cursor_blink = -1;
1988                                         event_id_l4_text_blink = -1;
1989                                         if(regs != NULL) {
1990                                                 usec = ((regs[10] & 0x20) == 0) ? 160.0 : 320.0;
1991                                                 usec = usec * 1000.0;
1992                                                 register_event(this, EVENT_FM7SUB_CURSOR_BLINK, true, usec, &event_id_l4_cursor_blink);
1993                                                 usec = 160.0 * 1000.0;
1994                                                 register_event(this, EVENT_FM7SUB_TEXT_BLINK, true, usec, &event_id_l4_cursor_blink);
1995                                         }
1996                                 } else {
1997                                         display_mode = DISPLAY_MODE_8_200L;
1998                                 }
1999                                 if(oldmode != display_mode) {
2000                                         scrntype_t *pp;
2001                                         if(display_mode == DISPLAY_MODE_1_400L) {
2002                                                 emu->set_vm_screen_size(640, 400, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2003                                                 for(int y = 0; y < 400; y++) {
2004                                                         pp = emu->get_screen_buffer(y);
2005                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2006                                                 }
2007                                         } else { // 200Line
2008
2009                                                 vm->set_vm_frame_rate(FRAMES_PER_SEC);
2010 #if !defined(FIXED_FRAMEBUFFER_SIZE)
2011                                                 emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2012                                                 for(int y = 0; y < 200; y++) {
2013                                                         pp = emu->get_screen_buffer(y);
2014                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2015                                                 }
2016 #else
2017                                                 for(int y = 0; y < 400; y++) {
2018                                                         pp = emu->get_screen_buffer(y);
2019                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2020                                                 }
2021 #endif
2022                                         }
2023                                         vram_wrote = true;
2024                                         setup_display_mode();
2025
2026                                 }
2027 # endif
2028                         }
2029 #endif
2030                         break;
2031 #if defined(_FM77AV_VARIANTS)
2032                 case SIG_DISPLAY_MODE320: // FD12 bit 6
2033 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2034                         {
2035                                 //printf("Wrote $FD12: %02x\n", data);
2036                                 int oldmode = display_mode;
2037                                 mode320 = flag;
2038                                 if(mode400line) {
2039                                         display_mode = DISPLAY_MODE_8_400L;
2040                                 } else if(mode256k) {
2041                                         display_mode = DISPLAY_MODE_256k;
2042                                 } else  if(!(mode320) && !(mode256k)) {
2043                                         //display_mode = (mode400line) ? DISPLAY_MODE_8_400L : DISPLAY_MODE_8_200L;
2044                                         display_mode = DISPLAY_MODE_8_200L;
2045                                 } else {
2046                                         display_mode = (mode256k) ? DISPLAY_MODE_256k : DISPLAY_MODE_4096;
2047                                 }
2048                                 if(oldmode != display_mode) {
2049                                         scrntype_t *pp;
2050                                         if(mode320 || mode256k) {
2051                                                 if(oldmode == DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(FRAMES_PER_SEC);
2052 #if !defined(FIXED_FRAMEBUFFER_SIZE)
2053                                                 emu->set_vm_screen_size(320, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2054                                                 for(y = 0; y < 200; y++) {
2055                                                         pp = emu->get_screen_buffer(y);
2056                                                         if(pp != NULL) memset(pp, 0x00, 320 * sizeof(scrntype_t));
2057                                                 }
2058 #else
2059                                                 for(y = 0; y < 400; y++) {
2060                                                         pp = emu->get_screen_buffer(y);
2061                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2062                                                 }
2063 #endif
2064                                                 //emu->set_vm_screen_lines(200);
2065                                         } else { // 200 lines, 8 colors.
2066                                                 if(display_mode == DISPLAY_MODE_8_400L) {
2067                                                         if(oldmode != DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(55.40);
2068                                                 } else {
2069                                                         if(oldmode == DISPLAY_MODE_8_400L) vm->set_vm_frame_rate(FRAMES_PER_SEC);
2070                                                 }
2071 #if !defined(FIXED_FRAMEBUFFER_SIZE)
2072                                                 int ymax =      (display_mode == DISPLAY_MODE_8_400L) ? 400 : 200;
2073
2074                                                 emu->set_vm_screen_size(640, ymax, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2075                                                 for(y = 0; y < ymax; y++) {
2076                                                         pp = emu->get_screen_buffer(y);
2077                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2078                                                 }
2079 #else
2080                                                 for(y = 0; y < 400; y++) {
2081                                                         pp = emu->get_screen_buffer(y);
2082                                                         if(pp != NULL) memset(pp, 0x00, 640 * sizeof(scrntype_t));
2083                                                 }
2084 #endif
2085                                                 //emu->set_vm_screen_lines(200);
2086                                         }
2087                                         vram_wrote = true;
2088                                         call_write_signal(alu, SIG_ALU_X_WIDTH, (mode320) ? 40 :  80, 0xffff);
2089                                         call_write_signal(alu, SIG_ALU_Y_HEIGHT, 200, 0xffff);
2090                                         call_write_signal(alu, SIG_ALU_400LINE, 0x00, 0xff);
2091                                         setup_display_mode();
2092                                         //frame_skip_count = 3;
2093                                 }
2094                         }
2095 # else /* FM77AV/20/20EX */
2096                         oldflag = mode320;
2097                         mode320 = flag;
2098                         if(oldflag != mode320) {
2099
2100                                 if(mode320) {
2101 #if !defined(FIXED_FRAMEBUFFER_SIZE)
2102                                                 emu->set_vm_screen_size(320, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2103                                                 for(y = 0; y < 200; y++) memset(emu->get_screen_buffer(y), 0x00, 320 * sizeof(scrntype_t));
2104 #else
2105                                                 for(y = 0; y < 400; y++) memset(emu->get_screen_buffer(y), 0x00, 640 * sizeof(scrntype_t));
2106 #endif
2107                                                 //emu->set_vm_screen_lines(200);
2108                                 } else {
2109 #if !defined(FIXED_FRAMEBUFFER_SIZE)
2110                                                 emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
2111                                                 for(y = 0; y < 200; y++) memset(emu->get_screen_buffer(y), 0x00, 640 * sizeof(scrntype_t));
2112 #else
2113                                                 for(y = 0; y < 400; y++) memset(emu->get_screen_buffer(y), 0x00, 640 * sizeof(scrntype_t));
2114 #endif
2115                                                 //emu->set_vm_screen_lines(200);
2116
2117                                 }
2118                                 display_mode = (mode320 == true) ? DISPLAY_MODE_4096 : DISPLAY_MODE_8_200L;
2119                                 call_write_signal(alu, SIG_ALU_X_WIDTH, (mode320) ? 40 :  80, 0xffff);
2120                                 call_write_signal(alu, SIG_ALU_Y_HEIGHT, 200, 0xffff);
2121                                 call_write_signal(alu, SIG_ALU_400LINE, 0, 0xffffffff);
2122                                 vram_wrote = true;
2123                                 setup_display_mode();
2124                         }
2125 # endif
2126 #endif
2127                         break;
2128                 case SIG_DISPLAY_MULTIPAGE:
2129                         set_multimode(data);
2130                         break;
2131                 case SIG_FM7_SUB_KEY_MASK:
2132                         if(firq_mask == flag) {
2133                                 do_firq(!flag && key_firq_req);
2134                         }
2135                         firq_mask = !flag;
2136                         break;
2137                 case SIG_FM7_SUB_KEY_FIRQ:
2138                         do_firq(flag & !(firq_mask));
2139                         key_firq_req = flag;
2140                         break;
2141                 case SIG_FM7_SUB_USE_CLR:
2142                         if(flag) {
2143                                 clr_count = data & 0x03;
2144                         } else {
2145                                 clr_count = 0;
2146                         }
2147                         break;
2148                 default:
2149                         break;
2150         }
2151 }
2152
2153 /*
2154  * Vram accessing functions moved to vram.cpp .
2155  */
2156
2157 uint32_t DISPLAY::read_mmio(uint32_t addr)
2158 {
2159         uint32_t retval = 0xff;
2160         uint32_t raddr;
2161         if(addr < 0xd400) return 0xff;
2162
2163 #if !defined(_FM77AV_VARIANTS)
2164         raddr = (addr - 0xd400) & 0x000f;
2165 #elif !defined(_FM77AV40SX) && !defined(_FM77AV40EX)
2166         raddr = (addr - 0xd400) & 0x003f;
2167 #else // FM77AV40EX || FM77AV40SX
2168         raddr = (addr - 0xd400) & 0x00ff;
2169 #endif
2170         switch(raddr) {
2171                 case 0x00: // Read keyboard
2172                         retval = (call_read_data8(keyboard, 0x00) != 0) ? 0xff : 0x7f;
2173                         break;
2174                 case 0x01: // Read keyboard
2175                         retval = call_read_data8(keyboard, 0x01) & 0xff;
2176                         break;
2177                 case 0x02: // Acknowledge
2178                         acknowledge_irq();
2179                         break;
2180                 case 0x03:
2181                         beep();
2182                         break;
2183                 case 0x04:
2184                         attention_irq();
2185                         break;
2186 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
2187      defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX) || defined(_FM77_VARIANTS) // _FM77L4
2188                 case 0x06:
2189                         if(!kanjisub) return 0xff;
2190 # if !defined(_FM77_VARIANTS)
2191                         if(kanji_level2) {
2192                                 return (uint8_t)call_read_data8(kanjiclass2, KANJIROM_DIRECTADDR + ((kanjiaddr.d << 1) & 0x1ffff));
2193                         }
2194 # endif
2195                         if(kanjiclass1 != NULL) retval = call_read_data8(kanjiclass1, KANJIROM_DIRECTADDR + ((kanjiaddr.d << 1) & 0x1ffff));
2196                         break;
2197                 case 0x07:
2198                         if(!kanjisub) return 0xff;
2199 # if !defined(_FM77_VARIANTS)
2200                         if(kanji_level2) {
2201                                 return (uint8_t)call_read_data8(kanjiclass2, KANJIROM_DIRECTADDR + ((kanjiaddr.d << 1) & 0x1ffff) + 1);
2202                         }
2203 # endif
2204                         if(kanjiclass1 != NULL) retval = call_read_data8(kanjiclass1, KANJIROM_DIRECTADDR + ((kanjiaddr.d << 1) & 0x1ffff) + 1);
2205                         break;
2206 #endif
2207                 case 0x08:
2208                         set_crtflag();
2209                         break;
2210                 case 0x09:
2211                         retval = set_vramaccess();
2212                         break;
2213                 case 0x0a:
2214                         reset_subbusy();
2215                         break;
2216 #if defined(_FM77L4)
2217                 case 0x0b:
2218                         if(stat_400linecard) {
2219                                 retval = l4crtc->read_io8(0);
2220                         }
2221                         break;
2222                 case 0x0c:
2223                         if(stat_400linecard) {
2224                                 retval = l4crtc->read_io8(1);
2225                                 // Update parameters.
2226                         }
2227                         break;
2228 #endif
2229                 case 0x0d:
2230                         call_write_signal(keyboard, SIG_FM7KEY_SET_INSLED, 0x01, 0x01);
2231                         break;
2232 #if defined(_FM77AV_VARIANTS)
2233                 // ALU
2234                 case 0x10:
2235                         retval = call_read_data8(alu, ALU_CMDREG);
2236                         break;
2237                 case 0x11:
2238                         retval = call_read_data8(alu, ALU_LOGICAL_COLOR);
2239                         break;
2240                 case 0x12:
2241                         retval = call_read_data8(alu, ALU_WRITE_MASKREG);
2242                         break;
2243                 case 0x13:
2244                         retval = call_read_data8(alu, ALU_CMP_STATUS_REG);
2245                         break;
2246                 case 0x1b:
2247                         retval = call_read_data8(alu, ALU_BANK_DISABLE);
2248                         break;
2249 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2250                 case 0x2f: // VRAM BANK
2251                         retval = 0xfc | (vram_bank & 0x03);
2252                         break;
2253 # endif
2254                 // MISC
2255                 case 0x30:
2256                         retval = get_miscreg();
2257                         break;
2258                 // KEY ENCODER.
2259                 case 0x31:
2260                         retval = call_read_data8(keyboard, 0x31);
2261                         break;
2262                 case 0x32:
2263                         retval = call_read_data8(keyboard, 0x32);
2264                         break;
2265 #endif
2266                 default:
2267                         break;
2268         }
2269         return (uint8_t)retval;
2270 }
2271
2272 uint32_t DISPLAY::read_vram_data8(uint32_t addr)
2273 {
2274         uint32_t offset;
2275         uint32_t vramaddr;
2276         uint32_t color = (addr >> 14) & 0x03;
2277 #if defined(_FM77L4)
2278         if(mode400line) {
2279                 if(addr < 0x8000) {
2280                         offset = offset_point;
2281                         if(workram_l4) {
2282                                 if(multimode_accessflags[2]) return 0xff;
2283                                 vramaddr = ((addr + offset) & 0x3fff) + 0x8000;
2284                                 return gvram[vramaddr];
2285                         }
2286                 } else {
2287                         if(addr < 0x9800) {
2288                                 return text_vram[addr & 0x0fff];
2289                         } else if(addr < 0xc000) {
2290                                 return subsys_l4[addr - 0x9800];
2291                         }
2292                         return 0xff;
2293                 }
2294         }
2295 #endif
2296 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2297         if(display_mode == DISPLAY_MODE_8_400L) {
2298                 color = vram_bank & 0x03;
2299                 if(color > 2) color = 0;
2300         } else {
2301                 color = (addr >> 14) & 0x03;
2302         }
2303 # endif
2304 # if !defined(_FM8)
2305         //if((multimode_accessmask & (1 << color)) != 0) return 0xff;
2306         if(multimode_accessflags[color]) return 0xff;
2307 # endif
2308 #if defined(_FM77AV_VARIANTS)
2309         if (active_page != 0) {
2310                 offset = offset_point_bank1;
2311         } else {
2312                 offset = offset_point;
2313         }
2314 #else
2315         offset = offset_point;
2316 #endif
2317 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2318         if(vram_active_block != 0) {
2319                 if(display_mode != DISPLAY_MODE_256k) offset = 0; // Don't scroll at BLOCK 1.
2320         }
2321 # endif
2322 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2323                 if(display_mode == DISPLAY_MODE_8_400L) {
2324                         uint32_t pagemod;
2325                         uint32_t page_offset_alt = 0;
2326                         if(addr >= 0x8000) return 0xff;
2327                         color = vram_bank & 0x03;
2328                         if(color > 2) color = 0;
2329                         offset <<= 1;
2330                         pagemod = 0x8000 * color;
2331 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2332                         if(vram_active_block != 0) page_offset = 0x18000;
2333 # endif
2334                         vramaddr = (((addr + offset) & 0x7fff) | pagemod) + page_offset_alt;
2335                         return gvram[vramaddr];
2336                 } else {
2337                         if(mode256k) {
2338                                 uint32_t page_offset_alt;
2339 #if defined(_FM77AV40)
2340                                 if(vram_bank < 3) {
2341                                         page_offset_alt = 0xc000 * (vram_bank & 0x03);
2342                                 } else {
2343                                         page_offset_alt = 0; // right?
2344                                 }
2345 #else
2346                                 page_offset_alt = 0xc000 * (vram_bank & 0x03);
2347 #endif
2348                                 vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset_alt;
2349                                 //page_mask = 0x1fff;
2350                                 //pagemod = addr & 0xe000;
2351                         } else {
2352                                 vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2353                         }
2354                         return gvram[vramaddr];
2355                 }
2356 #elif defined(_FM77AV_VARIANTS)
2357                 {
2358                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2359                         return gvram[vramaddr];
2360                 }
2361 #elif defined(_FM77L4) //_FM77L4
2362                 {
2363                         if(mode400line) {
2364                                 vramaddr = (addr + offset) & 0x7fff;
2365                                 return gvram[vramaddr];
2366                         } else {
2367                                 vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2368                                 return gvram[vramaddr];
2369                         }
2370                         return 0xff;
2371                 }
2372 #else // Others (77/7/8)
2373                 vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2374                 return gvram[vramaddr];
2375 #endif
2376 }
2377
2378 void DISPLAY::write_dma_data8(uint32_t addr, uint32_t data)
2379 {
2380         uint32_t raddr = (addr & 0xffff) >> 7;
2381         if(write_dma_func_table[raddr] != NULL) {
2382                 (this->*write_dma_func_table[raddr])(addr, (uint8_t) data);
2383         }
2384 }
2385
2386 void DISPLAY::write_vram_data8(uint32_t addr, uint8_t data)
2387 {
2388         uint32_t offset;
2389         uint32_t color = (addr >> 14) & 0x03;
2390         uint32_t vramaddr;
2391         uint8_t tdata;
2392
2393 #if defined(_FM77AV_VARIANTS)
2394         if (active_page != 0) {
2395                 offset = offset_point_bank1;
2396         } else {
2397                 offset = offset_point;
2398         }
2399 #else
2400         offset = offset_point;
2401 #endif
2402 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2403         if(vram_active_block != 0) offset = 0; // Don't scroll at BLOCK 1.
2404 # endif
2405
2406 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2407                 if(display_mode == DISPLAY_MODE_8_400L) {
2408                         uint32_t pagemod;
2409                         uint32_t page_offset_alt = 0;
2410                         uint32_t naddr;
2411                         if(addr >= 0x8000) {
2412                                 return;
2413                         }
2414                         color = vram_bank & 0x03;
2415                         if(color > 2) color = 0;
2416                         offset <<= 1;
2417                         pagemod = 0x8000 * color;
2418 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2419                         if(vram_active_block != 0) page_offset_alt = 0x18000;
2420 # endif
2421                         vramaddr = (((addr + offset) & 0x7fff) | pagemod) + page_offset_alt;
2422                         // Reduce data transfer.
2423                         tdata = gvram[vramaddr];
2424                         if(tdata != data) {
2425                                 naddr = (addr & 0x7fff) >> 4;
2426                                 gvram[vramaddr] = data;
2427                                 vram_wrote_table[naddr] = true;
2428                         }
2429                 } else  if(display_mode == DISPLAY_MODE_256k) {
2430                         uint32_t page_offset_alt;
2431                         uint32_t naddr;
2432 #if defined(_FM77AV40)
2433                         if(vram_bank < 3) {
2434                                 page_offset_alt = 0xc000 * (vram_bank & 0x03);
2435                         } else {
2436                                 page_offset_alt = 0; // right?
2437                         }
2438 #else
2439                         page_offset_alt = 0xc000 * (vram_bank & 0x03);
2440 #endif
2441                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset_alt;
2442                         tdata = gvram[vramaddr];
2443                         if(tdata != data) {
2444                                 naddr = (addr & page_mask) >> 3;
2445                                 gvram[vramaddr] = data;
2446                                 vram_wrote_table[naddr] = true;
2447                         }
2448                         return;
2449                 } else if(display_mode == DISPLAY_MODE_4096) {
2450                         uint32_t naddr;
2451                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2452                         tdata = gvram[vramaddr];
2453                         if(tdata != data) {
2454                                 naddr = (addr & page_mask) >> 3;
2455                                 gvram[vramaddr] = data;
2456                                 vram_wrote_table[naddr] = true;
2457                         }
2458                 } else { // 200line
2459                         uint32_t naddr;
2460                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2461                         tdata = gvram[vramaddr];
2462                         if(tdata != data) {
2463                                 naddr = (addr & page_mask) >> 4;
2464                                 gvram[vramaddr] = data;
2465                                 vram_wrote_table[naddr] = true;
2466                         }
2467                 }
2468 #elif defined(_FM77AV_VARIANTS)
2469                 if(display_mode == DISPLAY_MODE_4096) {
2470                         uint32_t naddr;
2471                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2472                         tdata = gvram[vramaddr];
2473                         if(tdata != data) {
2474                                 naddr = (addr & page_mask) >> 3;
2475                                 gvram[vramaddr] = data;
2476                                 vram_wrote_table[naddr] = true;
2477                         }
2478                 } else { // 200line
2479                         uint32_t naddr;
2480                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2481                         tdata = gvram[vramaddr];
2482                         if(tdata != data) {
2483                                 naddr = (addr & page_mask) >> 4;
2484                                 gvram[vramaddr] = data;
2485                                 vram_wrote_table[naddr] = true;
2486                         }
2487                 }
2488 #elif defined(_FM77L4) //_FM77L4
2489                 if(display_mode == DISPLAY_MODE_1_400L) {
2490                         if(addr < 0x8000) {
2491                                 if(workram_l4) {
2492                                         //if(multimode_accessflags[2]) return;
2493                                         vramaddr = ((addr + offset) & 0x3fff) + 0x8000;
2494                                         gvram[vramaddr] = data;
2495                                 } else {
2496                                         uint32_t naddr;
2497                                         vramaddr = (addr + offset) & 0x7fff;
2498                                         tdata = gvram[vramaddr];
2499                                         if(tdata != data) {
2500                                                 naddr = (addr & 0x7fff) >> 4;
2501                                                 gvram[vramaddr] = data;
2502                                                 vram_wrote_table[naddr] = true;
2503                                         }
2504                                 }
2505                                 return;
2506                         }
2507                 } else {
2508                         uint32_t naddr;
2509                         vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2510                         tdata = gvram[vramaddr];
2511                         if(tdata != data) {
2512                                 naddr = (addr & 0x3fff) >> 4;
2513                                 gvram[vramaddr] = data;
2514                                 vram_wrote_table[naddr] = true;
2515                         }
2516                 }
2517 #else // Others (77/7/8)
2518         {
2519                 uint32_t naddr;
2520                 vramaddr = (((addr + offset) & page_mask) | (pagemod_mask & addr)) + page_offset;
2521                 tdata = gvram[vramaddr];
2522                 if(tdata != data) {
2523                         naddr = (addr & 0x3fff) >> 4;
2524                         gvram[vramaddr] = data;
2525                         vram_wrote_table[naddr] = true;
2526                 }
2527         }
2528 #endif
2529 }
2530
2531 uint32_t DISPLAY::read_cpu_vram_data8(uint32_t addr)
2532 {
2533         uint8_t color;
2534 #if defined(_FM77AV_VARIANTS)
2535         if(use_alu) {
2536                 call_read_data8(alu, addr);
2537         }
2538 #endif
2539         return read_vram_data8(addr);
2540 }
2541
2542 uint32_t DISPLAY::read_dma_vram_data8(uint32_t addr)
2543 {
2544         return read_vram_data8(addr);
2545 }
2546
2547 void DISPLAY::init_read_table(void)
2548 {
2549         uint32_t _at;
2550         for(_at = 0 ; _at < 0xc000; _at += 0x80) {
2551                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_cpu_vram_data8;
2552                 read_dma_func_table[_at >> 7] = &DISPLAY::read_dma_vram_data8;
2553         }
2554         for(_at = 0xc000; _at < 0xd000; _at += 0x80) {
2555                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_console_ram;
2556                 read_dma_func_table[_at >> 7] = &DISPLAY::read_console_ram;
2557         }
2558         for(_at = 0xd000; _at < 0xd380; _at += 0x80) {
2559                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_work_ram;
2560                 read_dma_func_table[_at >> 7] = &DISPLAY::read_work_ram;
2561         }
2562         for(_at = 0xd380; _at < 0xd400; _at += 0x80) {
2563                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_shared_ram;
2564                 read_dma_func_table[_at >> 7] = &DISPLAY::read_shared_ram;
2565         }
2566 #if defined(_FM77AV_VARIANTS)
2567         for(_at = 0xd400; _at < 0xd500; _at += 0x80) {
2568                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_mmio;
2569                 read_dma_func_table[_at >> 7] = &DISPLAY::read_mmio;
2570         }
2571         for(_at = 0xd500; _at < 0xd800; _at += 0x80) {
2572                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_hidden_ram;
2573                 read_dma_func_table[_at >> 7] = &DISPLAY::read_hidden_ram;
2574         }
2575 #else
2576         for(_at = 0xd400; _at < 0xd800; _at += 0x80) {
2577                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_mmio;
2578                 read_dma_func_table[_at >> 7] = &DISPLAY::read_mmio;
2579         }
2580 #endif
2581         for(_at = 0xd800; _at < 0xe000; _at += 0x80) {
2582                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_cgrom;
2583                 read_dma_func_table[_at >> 7] = &DISPLAY::read_cgrom;
2584         }
2585         for(_at = 0xe000; _at < 0x10000; _at += 0x80) {
2586                 read_cpu_func_table[_at >> 7] = &DISPLAY::read_subsys_monitor;
2587                 read_dma_func_table[_at >> 7] = &DISPLAY::read_subsys_monitor;
2588         }
2589 }
2590
2591 uint32_t DISPLAY::read_console_ram(uint32_t addr)
2592 {
2593         uint32_t raddr = addr & 0xfff;
2594 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2595         if(monitor_ram) {
2596                 if(console_ram_bank >= 1) {
2597                         return submem_console_av40[((console_ram_bank - 1) << 12) + raddr];
2598                 }
2599         }
2600 #endif
2601         return console_ram[raddr];
2602 }
2603
2604 uint32_t DISPLAY::read_work_ram(uint32_t addr)
2605 {
2606         addr = addr & 0x3ff;
2607         return work_ram[addr];
2608 }
2609
2610
2611 uint32_t DISPLAY::read_shared_ram(uint32_t addr)
2612 {
2613         addr = addr - 0xd380;
2614         return shared_ram[addr];
2615 }
2616
2617 #if defined(_FM77AV_VARIANTS)
2618 uint32_t DISPLAY::read_hidden_ram(uint32_t addr)
2619 {
2620         if(addr >= 0xd500) {
2621                 return submem_hidden[addr - 0xd500];
2622         }
2623         return 0xff;
2624 }
2625 #endif
2626
2627 uint32_t DISPLAY::read_cgrom(uint32_t addr)
2628 {
2629 #if defined(_FM77AV_VARIANTS)
2630 # if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
2631         if(monitor_ram) {
2632                 return submem_cgram[cgram_bank * 0x0800 + (addr - 0xd800)]; //FIXME
2633         }
2634 # endif
2635         return subsys_cg[(addr - 0xd800) + cgrom_bank * 0x800];
2636 #else
2637         return subsys_c[addr - 0xd800];
2638 #endif
2639 }
2640
2641 uint32_t DISPLAY::read_subsys_monitor(uint32_t addr)
2642 {
2643 #if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
2644         if(monitor_ram) {
2645                 return subsys_ram[addr - 0xe000];
2646         }
2647 #endif
2648 #if defined(_FM77AV_VARIANTS)
2649         switch(subrom_bank_using & 3) {
2650         case 0: // SUBSYS_C
2651                 return subsys_c[addr - 0xd800];
2652                 break;
2653         case 1:
2654                 return subsys_a[addr - 0xe000];
2655                 break;
2656         case 2:
2657                 return subsys_b[addr - 0xe000];
2658                 break;
2659         default:
2660                 return subsys_cg[addr - 0xe000];
2661                 break;
2662         }
2663 #elif defined(_FM77L4)
2664         if(mode400line) {
2665                 return subsys_l4[addr - 0xb800];
2666         }
2667         return subsys_c[addr - 0xd800];
2668 #else
2669         return subsys_c[addr - 0xd800];
2670 #endif
2671 }
2672
2673 uint32_t DISPLAY::read_dma_data8(uint32_t addr)
2674 {
2675         uint32_t raddr = (addr & 0xffff) >> 7;
2676         if(read_dma_func_table[raddr] != NULL) {
2677                 return (this->*read_dma_func_table[raddr])(addr);
2678         }
2679         return 0xff;
2680 }
2681
2682 uint32_t DISPLAY::read_data8(uint32_t addr)
2683 {
2684         uint32_t raddr = addr;
2685         uint32_t offset;
2686         if(addr < 0x10000) {
2687                 raddr = (addr & 0xffff) >> 7;
2688                 if(read_cpu_func_table[raddr] != NULL) {
2689                         return (this->*read_cpu_func_table[raddr])(addr);
2690                 }
2691                 return 0xff;
2692         }
2693 #if !defined(_FM8)
2694         else if((addr >= FM7_SUBMEM_OFFSET_DPALETTE) && (addr < (FM7_SUBMEM_OFFSET_DPALETTE + 8))) {
2695                 return dpalette_data[addr - FM7_SUBMEM_OFFSET_DPALETTE];
2696         }
2697 #endif
2698 #if defined(_FM77AV_VARIANTS)
2699         // ACCESS VIA ALU.
2700         else if((addr >= DISPLAY_VRAM_DIRECT_ACCESS) && (addr < (DISPLAY_VRAM_DIRECT_ACCESS + 0x18000))) {
2701                 addr = addr - DISPLAY_VRAM_DIRECT_ACCESS;
2702 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2703                 if(vram_active_block != 0) {
2704                         offset = 0;
2705                 }
2706 # endif
2707 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2708                 if(display_mode == DISPLAY_MODE_8_400L) {
2709                         uint32_t page_offset_alt = 0;
2710                         uint32_t color;
2711                         uint32_t pagemod;
2712                         color = (addr & 0x18000) >> 15;
2713                         if(color > 2) color = 0;
2714                         pagemod = 0x8000 * color;
2715                         if (active_page != 0) {
2716                                 offset = offset_point_bank1 << 1;
2717                         } else {
2718                                 offset = offset_point << 1;
2719                         }
2720 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2721                         if(vram_active_block != 0) {
2722                                 page_offset_alt = 0x18000;
2723                                 offset = 0;
2724                         }
2725 # endif
2726                         return gvram[(((addr + offset) & 0x7fff) | pagemod) + page_offset_alt];
2727                 }
2728 # endif
2729                 return read_vram_data8(addr);
2730         }
2731 #endif
2732         return 0xff;
2733 }
2734
2735 /*
2736  * Vram accessing functions moved to vram.cpp .
2737  */
2738
2739 void DISPLAY::write_mmio(uint32_t addr, uint8_t data)
2740 {
2741         uint8_t rval = 0;
2742         uint8_t active_block_old;
2743         pair_t tmpvar;
2744         if(addr < 0xd400) return;
2745
2746 #if !defined(_FM77AV_VARIANTS)
2747         addr = (addr - 0xd400) & 0x000f;
2748 #elif !defined(_FM77AV40SX) && !defined(_FM77AV40EX)
2749         addr = (addr - 0xd400) & 0x003f;
2750 #else // FM77AV40EX || FM77AV40SX
2751         addr = (addr - 0xd400) & 0x00ff;
2752 #endif
2753         io_w_latch[addr] = (uint8_t)data;
2754         switch(addr) {
2755 #if defined(_FM77) || defined(_FM77L2) || defined(_FM77L4)
2756                 // FM77 SPECIFIED
2757                 case 0x05:
2758                         set_cyclesteal((uint8_t)data);
2759 #  if defined(_FM77L4)
2760                         setup_400linemode((uint8_t)data);
2761 #  endif
2762                         break;
2763 #endif
2764 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
2765      defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX) || defined(_FM77_VARIANTS) // _FM77L4
2766                 // KANJI
2767                 case 0x06:
2768                         if(!kanjisub) return;
2769                         kanjiaddr.w.h = 0x0000;
2770                         kanjiaddr.b.h = (uint8_t) data;
2771                         break;
2772                 case 0x07:
2773                         if(!kanjisub) return;
2774                         kanjiaddr.w.h = 0x0000;
2775                         kanjiaddr.b.l = (uint8_t)data;
2776                         break;
2777 #endif
2778                 // CRT OFF
2779                 case 0x08:
2780                         reset_crtflag();
2781                         break;
2782                 // VRAM ACCESS
2783                 case 0x09:
2784                         reset_vramaccess();
2785                         break;
2786                 // BUSY
2787                 case 0x0a:
2788                         if(clr_count <= 0) {
2789                                 set_subbusy();
2790                         } else { // Read once when using clr_foo() to set busy flag.
2791                                 double usec;
2792                                 if(clock_fast) {
2793                                         usec = (1000.0 * 1000.0) / 2000000.0;
2794                                 } else {
2795                                         usec = (1000.0 * 1000.0) / 999000.0;
2796                                 }
2797                                 if(!(is_cyclesteal) && (vram_accessflag))  usec = usec * 3.0;
2798                                 usec = (double)clr_count * usec;
2799                                 register_event(this, EVENT_FM7SUB_CLR_BUSY, usec, false, NULL); // NEXT CYCLE_
2800                                 reset_subbusy();
2801                                 clr_count = 0;
2802                         }
2803                         break;
2804                 // LED
2805 #if defined(_FM77L4)
2806                 case 0x0b:
2807                         if(stat_400linecard) {
2808                                 l4crtc->write_io8(0, data & 0x1f);
2809                         }
2810                         break;
2811                 case 0x0c:
2812                         if(stat_400linecard) {
2813                                 l4crtc->write_io8(1, data);
2814                                 // Update parameters.
2815                                 uint8_t crtc_addr = l4crtc->read_io8(0);
2816                                 const uint8_t *regs = l4crtc->get_regs();
2817                                 switch(crtc_addr & 0x1f) {
2818                                 case 10:
2819                                 case 11:
2820                                         cursor_addr.w.l &= 0x0ffc;
2821                                         cursor_addr.w.l |= (((uint16_t)regs[14]) << 10);
2822                                         cursor_addr.w.l |= (((uint16_t)regs[15]) << 2);
2823                                         if(cursor_lsb) {
2824                                                 cursor_addr.w.l += 2;
2825                                         }
2826                                         cursor_addr.w.l &= 0xfff;
2827                                         // Redraw request
2828                                         if((crtc_addr & 0x1f) == 10) {
2829                                                 double usec;
2830                                                 if(event_id_l4_cursor_blink >= 0) {
2831                                                         cancel_event(this, event_id_l4_cursor_blink);
2832                                                 }
2833                                                 usec = ((data & 0x20) == 0) ? 160.0 : 320.0;
2834                                                 usec = usec * 1000.0;
2835                                                 register_event(this, EVENT_FM7SUB_CURSOR_BLINK, true, usec, &event_id_l4_cursor_blink);
2836                                         }
2837                                         break;
2838                                 case 12:
2839                                         text_start_addr.w.l &= 0x03fc;
2840                                         text_start_addr.w.l |= (((uint16_t)data & 3) << 10);
2841                                         text_scroll_count++;
2842                                         if((text_scroll_count & 1) == 0) {
2843                                                 // Redraw request
2844                                         }
2845                                         break;
2846                                 case 13:
2847                                         text_start_addr.w.l &= 0xfc00;
2848                                         text_start_addr.w.l |= ((uint16_t)data << 2);
2849                                         text_scroll_count++;
2850                                         if((text_scroll_count & 1) == 0) {
2851                                                 // Redraw request
2852                                         }
2853                                 case 14:
2854                                 case 15:
2855                                         text_scroll_count++;
2856                                         if((text_scroll_count & 1) == 0) {
2857                                                 // Redraw request
2858                                                 cursor_addr.w.l &= 0x0ffc;
2859                                                 cursor_addr.w.l |= (((uint16_t)regs[14]) << 10);
2860                                                 cursor_addr.w.l |= (((uint16_t)regs[15]) << 2);
2861                                                 if(cursor_lsb) {
2862                                                         cursor_addr.w.l += 2;
2863                                                 }
2864                                                 cursor_addr.w.l &= 0xfff;
2865                                         }
2866                                         break;
2867                                 default:
2868                                         break;
2869                                 }
2870
2871                         }
2872                         break;
2873 #endif
2874                 case 0x0d:
2875                         call_write_signal(keyboard, SIG_FM7KEY_SET_INSLED, 0x00, 0x01);
2876                         break;
2877                 // OFFSET
2878                 case 0x0e:
2879                 case 0x0f:
2880                         rval = (uint8_t)data;
2881                         if(offset_changed[active_page]) {
2882 #if defined(_FM77AV_VARIANTS)
2883                                 if(active_page != 0) {
2884                                         tmp_offset_point[active_page].d = offset_point_bank1;
2885                                 } else {
2886                                         tmp_offset_point[active_page].d = offset_point;
2887                                 }
2888 #else
2889                                 tmp_offset_point[active_page].d = offset_point;
2890 #endif
2891                         }
2892                         tmp_offset_point[active_page].w.h = 0x0000;
2893                         if(addr == 0x0e) {
2894                                 tmp_offset_point[active_page].b.h = rval;
2895                         } else {
2896                                 tmp_offset_point[active_page].b.l = rval;
2897                         }
2898                         offset_changed[active_page] = !offset_changed[active_page];
2899                         if(offset_changed[active_page]) {
2900                                 vram_wrote = true;
2901 #if defined(_FM77AV_VARIANTS)
2902                                 if(active_page != 0) {
2903                                         if(offset_77av) {
2904                                                 offset_point_bank1 = tmp_offset_point[active_page].d & 0x007fff;
2905                                         } else {
2906                                                 offset_point_bank1 = tmp_offset_point[active_page].d & 0x007fe0;
2907                                         }
2908                                 } else {
2909                                         if(offset_77av) {
2910                                                 offset_point = tmp_offset_point[active_page].d & 0x007fff;
2911                                         } else {
2912                                                 offset_point = tmp_offset_point[active_page].d & 0x007fe0;
2913                                         }
2914                                 }
2915 #else
2916                                 offset_point = tmp_offset_point[active_page].d & 0x7fe0;
2917 #endif
2918                         }
2919                         break;
2920 #if defined(_FM77AV_VARIANTS)
2921                 // ALU
2922                 case 0x10:
2923                         alu_write_cmdreg(data);
2924                         break;
2925                 case 0x11:
2926                         alu_write_logical_color(data);
2927                         break;
2928                 case 0x12:
2929                         alu_write_mask_reg(data);
2930                         break;
2931                 case 0x1b:
2932                         alu_write_disable_reg(data);
2933                         break;
2934                 case 0x20:
2935                         alu_write_offsetreg_hi(data);
2936                         break;
2937                 case 0x21:
2938                         alu_write_offsetreg_lo(data);
2939                         break;
2940                 case 0x22:
2941                         alu_write_linepattern_hi(data);
2942                         break;
2943                 case 0x23:
2944                         alu_write_linepattern_lo(data);
2945                         break;
2946 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
2947                 case 0x2e: //
2948                         console_ram_bank = (data & 0x18) >> 3;
2949                         if(console_ram_bank > 2) console_ram_bank = 0;
2950                         cgram_bank = data & 0x07;
2951                         kanji_level2 = ((data & 0x80) == 0) ? false : true;
2952                         break;
2953                 case 0x2f: // VRAM BANK
2954                         vram_bank = data &  0x03;
2955                         if(vram_bank > 2) vram_bank = 0;
2956                         vram_wrote = true;
2957                         break;
2958 # endif
2959                 // MISC
2960                 case 0x30:
2961                         set_miscreg(data);
2962                         break;
2963                 // KEYBOARD ENCODER
2964                 case 0x31:
2965                         call_write_data8(keyboard, 0x31, data);
2966                         break;
2967 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
2968                 case 0x33: //
2969                         active_block_old = vram_active_block;
2970                         vram_active_block = data & 0x01;
2971                         if(vram_display_block != (((data & 0x10) != 0) ? 1 : 0)) vram_wrote = true;
2972                         vram_display_block = ((data & 0x10) != 0) ? 1 : 0;
2973                         if(vram_active_block != active_block_old) setup_display_mode();
2974                         break;
2975                         // Window
2976                 case 0x38: //
2977                 case 0x39: //
2978                         tmpvar.d = window_xbegin * 8;
2979                         tmpvar.w.h = 0;
2980                         if(addr == 0x38) {
2981                                 tmpvar.b.h = data & 0x03;
2982                         } else {
2983                                 tmpvar.b.l = data & 0xf8;
2984                         }
2985                         if(mode320 || mode256k) {
2986                            if(tmpvar.d > 320) tmpvar.d = 320;
2987                         } else {
2988                            if(tmpvar.d > 640) tmpvar.d = 640;
2989                         }
2990                         window_xbegin = tmpvar.d / 8;
2991                         vram_wrote = true;
2992                         break;
2993                 case 0x3a: //
2994                 case 0x3b: //
2995                         tmpvar.d = window_xend * 8;
2996                         tmpvar.w.h = 0;
2997                         if(addr == 0x3a) {
2998                                 tmpvar.b.h = data & 0x03;
2999                         } else {
3000                                 tmpvar.b.l = data & 0xf8;
3001                         }
3002                         if(mode320 || mode256k) {
3003                            if(tmpvar.d > 320) tmpvar.d = 320;
3004                         } else {
3005                            if(tmpvar.d > 640) tmpvar.d = 640;
3006                         }
3007                         window_xend = tmpvar.d / 8;
3008                         vram_wrote = true;
3009                         break;
3010                 case 0x3c: //
3011                 case 0x3d: //
3012                         tmpvar.d = window_low;
3013                         tmpvar.w.h = 0;
3014                         if(addr == 0x3c) {
3015                                 tmpvar.b.h = data & 0x03;
3016                         } else {
3017                                 tmpvar.b.l = data & 0xff;
3018                         }
3019                         if(display_mode == DISPLAY_MODE_8_400L) {
3020                                 if(tmpvar.d > 400) tmpvar.d = 400;
3021                         } else {
3022                                 tmpvar.d <<= 1;
3023                                 if(tmpvar.d > 400) tmpvar.d = 400;
3024                         }
3025                         window_low = tmpvar.d;
3026                         vram_wrote = true;
3027                         break;
3028                 case 0x3e: //
3029                 case 0x3f: //
3030                         tmpvar.d = window_high;
3031                         tmpvar.w.h = 0;
3032                         if(addr == 0x3e) {
3033                                 tmpvar.b.h = data & 0x03;
3034                         } else {
3035                                 tmpvar.b.l = data & 0xff;
3036                         }
3037                         if(display_mode == DISPLAY_MODE_8_400L) {
3038                                 if(tmpvar.d > 400) tmpvar.d = 400;
3039                         } else {
3040                                 tmpvar.d <<= 1;
3041                                 if(tmpvar.d > 400) tmpvar.d = 400;
3042                         }
3043                         window_high = tmpvar.d;
3044                         vram_wrote = true;
3045                         break;
3046 # endif
3047 #endif
3048                 default:
3049 #if defined(_FM77AV_VARIANTS)
3050                         //ALU
3051                         if((addr >= 0x13) && (addr <= 0x1a)) {
3052                                 alu_write_cmpdata_reg(addr - 0x13, data);
3053                         } else if((addr >= 0x1c) && (addr <= 0x1e)) {
3054                                 alu_write_tilepaint_data(addr, data);
3055                         } else if((addr >= 0x24) && (addr <= 0x2b)) {
3056                                 alu_write_line_position(addr - 0x24, data);
3057                         }
3058 #endif
3059                         break;
3060         }
3061 }
3062
3063 void DISPLAY::init_write_table(void)
3064 {
3065         uint32_t _at;
3066         for(_at = 0 ; _at < 0xc000; _at += 0x80) {
3067                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_cpu_vram_data8;
3068                 write_dma_func_table[_at >> 7] = &DISPLAY::write_dma_vram_data8;
3069         }
3070         for(_at = 0xc000; _at < 0xd000; _at += 0x80) {
3071                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_console_ram;
3072                 write_dma_func_table[_at >> 7] = &DISPLAY::write_console_ram;
3073         }
3074         for(_at = 0xd000; _at < 0xd380; _at += 0x80) {
3075                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_work_ram;
3076                 write_dma_func_table[_at >> 7] = &DISPLAY::write_work_ram;
3077         }
3078         for(_at = 0xd380; _at < 0xd400; _at += 0x80) {
3079                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_shared_ram;
3080                 write_dma_func_table[_at >> 7] = &DISPLAY::write_shared_ram;
3081         }
3082 #if defined(_FM77AV_VARIANTS)
3083         for(_at = 0xd400; _at < 0xd500; _at += 0x80) {
3084                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_mmio;
3085                 write_dma_func_table[_at >> 7] = &DISPLAY::write_mmio;
3086         }
3087         for(_at = 0xd500; _at < 0xd800; _at += 0x80) {
3088                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_hidden_ram;
3089                 write_dma_func_table[_at >> 7] = &DISPLAY::write_hidden_ram;
3090         }
3091 #else
3092         for(_at = 0xd400; _at < 0xd800; _at += 0x80) {
3093                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_mmio;
3094                 write_dma_func_table[_at >> 7] = &DISPLAY::write_mmio;
3095         }
3096 #endif
3097 #if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
3098         for(_at = 0xd800; _at < 0xe000; _at += 0x80) {
3099                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_subsys_cgram;
3100                 write_dma_func_table[_at >> 7] = &DISPLAY::write_subsys_cgram;
3101         }
3102         for(_at = 0xe000; _at < 0x10000; _at += 0x80) {
3103                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_subsys_ram;
3104                 write_dma_func_table[_at >> 7] = &DISPLAY::write_subsys_ram;
3105         }
3106 #else
3107         for(_at = 0xd800; _at < 0x10000; _at += 0x80) {
3108                 write_cpu_func_table[_at >> 7] = &DISPLAY::write_dummy;
3109                 write_dma_func_table[_at >> 7] = &DISPLAY::write_dummy;
3110         }
3111 #endif
3112 }
3113
3114 void DISPLAY::write_console_ram(uint32_t addr, uint8_t data)
3115 {
3116         uint32_t raddr = addr & 0xfff;
3117 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3118         if(monitor_ram) {
3119                 if(console_ram_bank >= 1) {
3120                         submem_console_av40[((console_ram_bank - 1) << 12) + raddr] = data;
3121                         return;
3122                 }
3123         }
3124 #endif
3125         console_ram[raddr] = data;
3126         return;
3127 }
3128
3129 void DISPLAY::write_work_ram(uint32_t addr, uint8_t data)
3130 {
3131         uint32_t raddr = addr & 0xfff;
3132         work_ram[raddr] = data;
3133         return;
3134 }
3135
3136 void DISPLAY::write_shared_ram(uint32_t addr, uint8_t data)
3137 {
3138         uint32_t raddr = addr & 0x7f;
3139         shared_ram[raddr] = data;
3140         return;
3141 }
3142
3143 #if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
3144 void DISPLAY::write_subsys_cgram(uint32_t addr, uint8_t data)
3145 {
3146         uint32_t raddr = addr - 0xd800;
3147         if(ram_protect) return;
3148         if(!monitor_ram) return;
3149         submem_cgram[cgram_bank * 0x0800 + raddr] = data; //FIXME
3150 }
3151
3152 void DISPLAY::write_subsys_ram(uint32_t addr, uint8_t data)
3153 {
3154         if(ram_protect) return;
3155         if(!monitor_ram) return;
3156         subsys_ram[addr - 0xe000] = data; //FIXME
3157 }
3158 #endif
3159
3160 #if defined(_FM77AV_VARIANTS)
3161 void DISPLAY::write_hidden_ram(uint32_t addr, uint8_t data)
3162 {
3163         submem_hidden[addr - 0xd500] = data;
3164         return;
3165 }
3166 #endif
3167
3168 void DISPLAY::write_cpu_vram_data8(uint32_t addr, uint8_t data)
3169 {
3170         uint32_t color = (addr & 0xc000) >> 14;
3171 #if defined(_FM77AV_VARIANTS)
3172         if(use_alu) {
3173                 call_read_data8(alu, addr);
3174                 return;
3175         }
3176 #endif
3177 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3178         if(display_mode == DISPLAY_MODE_8_400L) {
3179                 color = vram_bank & 0x03;
3180                 if(color > 2) color = 0;
3181         }
3182 #endif
3183 #if defined(_FM77L4)
3184         if(mode400line) {
3185                 if(addr < 0x8000) {
3186                         if(workram_l4) {
3187                                 if(!(multimode_accessflags[2])) write_vram_data8(addr & 0x7fff, data);
3188                                 return;
3189                         }
3190                 } else if(addr < 0x9800) {
3191                         uint32_t naddr;
3192                         uint32_t x, y;
3193                         addr = addr & 0x0fff;
3194                         if(text_vram[addr] != data) {
3195                                 text_vram[addr] = data;
3196                                 if(text_width40) {
3197                                         x = ((addr / 2) % 40) / 8;
3198                                         y = (addr / 2) / 40;
3199                                 } else { // Width 80
3200                                         x = ((addr / 2) % 80) / 8;
3201                                         y = (addr / 2) / 80;
3202                                 }
3203                                 for(int yy = 0; yy < 8; yy++) {
3204                                         naddr = (y + yy) * 5 + x;
3205                                         vram_wrote_table[naddr] = true;
3206                                 }
3207                         }
3208                         return;
3209                 } else {
3210                         return;
3211                 }
3212         }
3213 #endif
3214 #if !defined(_FM8)
3215         //if((multimode_accessmask & (1 << color)) != 0) return;
3216         if(multimode_accessflags[color]) return;
3217 #endif
3218         write_vram_data8(addr & 0xffff, data);
3219 }
3220
3221 void DISPLAY::write_dma_vram_data8(uint32_t addr, uint8_t data)
3222 {
3223         uint32_t color = (addr & 0xc000) >> 14;
3224 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3225         if(display_mode == DISPLAY_MODE_8_400L) {
3226                 color = vram_bank & 0x03;
3227                 if(color > 2) color = 0;
3228         }
3229 #endif
3230 #if !defined(_FM8)
3231         //if((multimode_accessmask & (1 << color)) != 0) return;
3232         if(multimode_accessflags[color]) return;
3233 #endif
3234         write_vram_data8(addr & 0xffff, data);
3235 }
3236
3237 void DISPLAY::write_dummy(uint32_t addr, uint8_t data)
3238 {
3239 }
3240
3241 void DISPLAY::write_data8(uint32_t addr, uint32_t data)
3242 {
3243         uint32_t offset;
3244         uint32_t raddr;
3245         //uint32_t page_offset = 0x0000;
3246         uint8_t val8 = data & 0xff;
3247         uint32_t color = (addr & 0xc000) >> 14;
3248         uint8_t tdata;
3249
3250         if(addr < 0x10000) {
3251                 void (*_write_func)(uint32_t, uint32_t);
3252                 raddr = (addr & 0xffff) >> 7;
3253                 if(write_cpu_func_table[raddr] != NULL) {
3254                         (this->*write_cpu_func_table[raddr])(addr, (uint8_t)data);
3255                         return;
3256                 }
3257                 return;
3258         }
3259 #if !defined(_FM8)
3260         else if((addr >= FM7_SUBMEM_OFFSET_DPALETTE) && (addr < (FM7_SUBMEM_OFFSET_DPALETTE + 8))) {
3261                 set_dpalette(addr - FM7_SUBMEM_OFFSET_DPALETTE, val8);
3262                 return;
3263         }
3264 #endif
3265 #if defined(_FM77AV_VARIANTS)
3266         // ANALOG PALETTE
3267         else if(addr == FM7_SUBMEM_OFFSET_APALETTE_R) {
3268                 set_apalette_r(val8);
3269                 return;
3270         } else if(addr == FM7_SUBMEM_OFFSET_APALETTE_G) {
3271                 set_apalette_g(val8);
3272                 return;
3273         } else if(addr == FM7_SUBMEM_OFFSET_APALETTE_B) {
3274                 set_apalette_b(val8);
3275                 return;
3276         } else if(addr == FM7_SUBMEM_OFFSET_APALETTE_HI) {
3277                 set_apalette_index_hi(val8);
3278                 return;
3279         } else if(addr == FM7_SUBMEM_OFFSET_APALETTE_LO) {
3280                 set_apalette_index_lo(val8);
3281                 return;
3282         }
3283         // ACCESS VIA ALU.
3284         else if((addr >= DISPLAY_VRAM_DIRECT_ACCESS) && (addr < (DISPLAY_VRAM_DIRECT_ACCESS + 0x18000))) {
3285                 addr = addr - DISPLAY_VRAM_DIRECT_ACCESS;
3286 #if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3287                 if(display_mode == DISPLAY_MODE_8_400L) {
3288                         uint32_t vramaddr;
3289                         uint32_t naddr;
3290                         uint32_t page_offset_alt = 0;
3291                         uint32_t pagemod;
3292                         color = (addr & 0x18000) >> 15;
3293                         if(color > 2) color = 0;
3294                         if (active_page != 0) {
3295                                 offset = offset_point_bank1 << 1;
3296                         } else {
3297                                 offset = offset_point << 1;
3298                         }
3299 # if defined(_FM77AV40EX) || defined(_FM77AV40SX)
3300                         if(vram_active_block != 0) {
3301                                 page_offset_alt = 0x18000;
3302                                 offset = 0;
3303                         }
3304 # endif
3305                         naddr = (addr & 0x7fff) >> 4;
3306                         pagemod = 0x8000 * color;
3307                         vramaddr = (((addr + offset) & 0x7fff) | pagemod) + page_offset_alt;
3308                         tdata = gvram[vramaddr];
3309                         if(tdata != (uint8_t)data) {
3310                                 gvram[vramaddr] = data;
3311                                 vram_wrote_table[naddr] = true;
3312                         }
3313                         return;
3314                 }
3315                 write_vram_data8(addr, data);
3316 #else
3317                 write_vram_data8(addr, data);
3318 #endif
3319                 //if((config.dipswitch & FM7_DIPSW_SYNC_TO_HSYNC) == 0) vram_wrote = true;
3320         }
3321 #endif
3322         return;
3323 }
3324
3325
3326 uint32_t DISPLAY::read_bios(const _TCHAR *name, uint8_t *ptr, uint32_t size)
3327 {
3328         FILEIO fio;
3329         uint32_t blocks;
3330         const _TCHAR *s;
3331
3332         if((name == NULL) || (ptr == NULL))  return 0;
3333         s = create_local_path(name);
3334         if(s == NULL) return 0;
3335
3336         if(!fio.Fopen(s, FILEIO_READ_BINARY)) return 0;
3337         blocks = fio.Fread(ptr, size, 1);
3338         fio.Fclose();
3339
3340         return blocks * size;
3341 }
3342
3343
3344 void DISPLAY::initialize()
3345 {
3346         int i;
3347
3348         memset(io_w_latch, 0xff, sizeof(io_w_latch));
3349         screen_update_flag = true;
3350         memset(gvram, 0x00, sizeof(gvram));
3351         vram_wrote_shadow = false;
3352         memset(gvram_shadow, 0x00, sizeof(gvram_shadow));
3353         for(i = 0; i < 411 * 5; i++) vram_wrote_table[i] = false;
3354         for(i = 0; i < 411; i++) vram_draw_table[i] = false;
3355         force_update = false;
3356
3357         memset(console_ram, 0x00, sizeof(console_ram));
3358         memset(work_ram, 0x00, sizeof(work_ram));
3359         memset(shared_ram, 0x00, sizeof(shared_ram));
3360         memset(subsys_c, 0xff, sizeof(subsys_c));
3361         need_transfer_line = true;
3362         frame_skip_count_draw = 3;
3363         frame_skip_count_transfer = 3;
3364
3365         diag_load_subrom_c = false;
3366 #if defined(_FM8)
3367         if(read_bios(_T(ROM_FM8_SUBSYSTEM), subsys_c, 0x2800) >= 0x2800) diag_load_subrom_c = true;
3368         this->out_debug_log(_T("SUBSYSTEM ROM READING : %s"), diag_load_subrom_c ? "OK" : "NG");
3369 #else
3370         if(read_bios(_T(ROM_FM7_SUBSYSTEM_TYPE_C), subsys_c, 0x2800) >= 0x2800) diag_load_subrom_c = true;
3371         this->out_debug_log(_T("SUBSYSTEM ROM Type C READING : %s"), diag_load_subrom_c ? "OK" : "NG");
3372 #endif
3373 #if defined(_FM77AV_VARIANTS)
3374         memset(subsys_a, 0xff, sizeof(subsys_a));
3375         memset(subsys_b, 0xff, sizeof(subsys_b));
3376         memset(subsys_cg, 0xff, sizeof(subsys_cg));
3377         memset(submem_hidden, 0x00, sizeof(submem_hidden));
3378
3379         diag_load_subrom_a = false;
3380         if(read_bios(_T(ROM_FM7_SUBSYSTEM_TYPE_A), subsys_a, 0x2000) >= 0x2000) diag_load_subrom_a = true;
3381         this->out_debug_log(_T("SUBSYSTEM ROM Type A READING : %s"), diag_load_subrom_a ? "OK" : "NG");
3382
3383         diag_load_subrom_b = false;
3384         if(read_bios(_T(ROM_FM7_SUBSYSTEM_TYPE_B), subsys_b, 0x2000) >= 0x2000) diag_load_subrom_b = true;
3385         this->out_debug_log(_T("SUBSYSTEM ROM Type B READING : %s"), diag_load_subrom_b ? "OK" : "NG");
3386
3387         diag_load_subrom_cg = false;
3388         if(read_bios(_T(ROM_FM7_SUBSYSTEM_CG), subsys_cg, 0x2000) >= 0x2000) diag_load_subrom_cg = true;
3389         this->out_debug_log(_T("SUBSYSTEM CG ROM READING : %s"), diag_load_subrom_cg ? "OK" : "NG");
3390 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX) || \
3391     defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
3392         memset(subsys_ram, 0x00, sizeof(subsys_ram));
3393         memset(submem_cgram, 0x00, sizeof(submem_cgram));
3394         memset(submem_console_av40, 0x00, sizeof(submem_console_av40));
3395         ram_protect = true;
3396 # endif
3397 #endif
3398 #if defined(_FM77L4)
3399         memset(subsys_cg_l4, 0xff, sizeof(subsys_cg_l4));
3400         memset(subsys_l4, 0xff, sizeof(subsys_l4));
3401
3402         read_bios(_T(ROM_FM77_400LINE_ANKCG), subsys_cg_l4, sizeof(subsys_cg_l4));
3403         read_bios(_T(ROM_FM77_400LINE_SUBSYS), subsys_l4, sizeof(subsys_l4));
3404         memset(text_vram, 0x00, sizeof(text_vram));
3405         //memset(crtc_regs, 0x00, sizeof(crtc_regs));
3406
3407         workram_l4 = false;
3408         cursor_lsb = false;
3409     text_width40 = false;
3410
3411         text_blink = true;
3412         cursor_blink = true;
3413
3414         text_start_addr.d = 0x0000;
3415         text_lines = 64;
3416         text_xmax = 80;
3417
3418         cursor_addr.d = 0;
3419         cursor_start = 0;
3420         cursor_end = 15;
3421         cursor_type = 0;
3422         text_scroll_count = 0;
3423
3424         event_id_l4_cursor_blink = -1;
3425         event_id_l4_text_blink = -1;
3426 #endif
3427
3428         init_read_table();
3429         init_write_table();
3430
3431 #if defined(_FM77AV_VARIANTS)
3432         mode320 = false;
3433         apalette_index.d = 0;
3434         for(i = 0; i < 4096; i++) {
3435                 analog_palette_r[i] = i & 0x0f0;
3436                 analog_palette_g[i] = (i & 0xf00) >> 4;
3437                 analog_palette_b[i] = (i & 0x00f) << 4;
3438                 calc_apalette(i);
3439                 memcpy(analog_palette_pixel, analog_palette_pixel_tmp, sizeof(analog_palette_pixel));
3440         }
3441 #endif
3442         for(i = 0; i < 8; i++) set_dpalette(i, i);
3443 #if defined(USE_GREEN_DISPLAY)
3444         memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
3445         use_green_monitor = false;
3446 #endif
3447
3448         memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
3449 //#if defined(_FM77AV_VARIANTS)
3450         hblank_event_id = -1;
3451         hdisp_event_id = -1;
3452         vsync_event_id = -1;
3453         vstart_event_id = -1;
3454 //#endif
3455 #if defined(_FM8)
3456         clock_fast = false;
3457 #else
3458         clock_fast = true;
3459 #endif
3460 #if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
3461         is_cyclesteal = true;
3462 #else
3463         is_cyclesteal = false;
3464 #endif
3465         multimode_accessmask = multimode_dispmask = 0;
3466         for(i = 0; i < 4; i++) {
3467                 multimode_accessflags[i] = ((multimode_accessmask & (1 << i)) != 0) ? true : false;
3468                 multimode_dispflags[i] = ((multimode_dispmask & (1 << i)) != 0) ? true : false;
3469         }
3470
3471         prev_clock = SUBCLOCK_NORMAL;
3472         //enter_display();
3473         nmi_event_id = -1;
3474         firq_mask = false;
3475         key_firq_req = false;   //firq_mask = true;
3476         frame_skip_count_transfer = 3;
3477         frame_skip_count_draw = 3;
3478 #if !defined(FIXED_FRAMEBUFFER_SIZE)
3479         emu->set_vm_screen_size(640, 200, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
3480 #else
3481         emu->set_vm_screen_size(640, 400, WINDOW_WIDTH, WINDOW_HEIGHT, WINDOW_WIDTH_ASPECT, WINDOW_HEIGHT_ASPECT);
3482 #endif
3483         emu->set_vm_screen_lines(200);
3484 #if defined(_FM77AV40SX) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3485         mode400line = false;
3486         mode256k = false;
3487 #elif defined(_FM77L4)
3488         mode400line = false;
3489 #endif
3490
3491         palette_changed = true;
3492 //#if !defined(_FM77AV_VARIANTS) && !defined(_FM77L4)
3493         //register_vline_event(this);
3494         register_frame_event(this);
3495 //#endif
3496         setup_display_mode();
3497 }
3498
3499 void DISPLAY::release()
3500 {
3501 }
3502
3503 #define STATE_VERSION 11
3504 void DISPLAY::decl_state(void)
3505 {
3506         enter_decl_state(STATE_VERSION);
3507         DECL_STATE_ENTRY_INT(this_device_id);
3508         {
3509                 int i;
3510                 DECL_STATE_ENTRY_INT32(clr_count);
3511                 DECL_STATE_ENTRY_BOOL(halt_flag);
3512                 DECL_STATE_ENTRY_INT32(active_page);
3513                 DECL_STATE_ENTRY_BOOL(sub_busy);
3514                 DECL_STATE_ENTRY_BOOL(crt_flag);
3515                 DECL_STATE_ENTRY_BOOL(vram_wrote);
3516                 DECL_STATE_ENTRY_BOOL(is_cyclesteal);
3517
3518                 DECL_STATE_ENTRY_BOOL(clock_fast);
3519
3520 #if defined(_FM77AV_VARIANTS)
3521                 DECL_STATE_ENTRY_BOOL(subcpu_resetreq);
3522                 DECL_STATE_ENTRY_BOOL(power_on_reset);
3523 #endif
3524                 DECL_STATE_ENTRY_BOOL(cancel_request);
3525                 DECL_STATE_ENTRY_BOOL(key_firq_req);
3526
3527                 DECL_STATE_ENTRY_INT32(display_mode);
3528                 DECL_STATE_ENTRY_UINT32(prev_clock);
3529
3530 #if !defined(_FM8)
3531                 DECL_STATE_ENTRY_MULTI(void, dpalette_data, sizeof(dpalette_data));
3532                 DECL_STATE_ENTRY_UINT8(multimode_accessmask);
3533                 DECL_STATE_ENTRY_UINT8(multimode_dispmask);
3534 #endif
3535                 DECL_STATE_ENTRY_UINT32(offset_point);
3536 #if defined(_FM77AV_VARIANTS)
3537                 DECL_STATE_ENTRY_UINT32(offset_point_bank1);
3538 #endif
3539                 //for(i = 0; i < 2; i++) {
3540                 DECL_STATE_ENTRY_PAIR_ARRAY(tmp_offset_point, 2);
3541                 DECL_STATE_ENTRY_BOOL_ARRAY(offset_changed, 2);
3542                         //}
3543                 DECL_STATE_ENTRY_BOOL(offset_77av);
3544                 DECL_STATE_ENTRY_BOOL(diag_load_subrom_c);
3545
3546
3547                 DECL_STATE_ENTRY_MULTI(void, io_w_latch, sizeof(io_w_latch));
3548                 DECL_STATE_ENTRY_MULTI(void, console_ram, sizeof(console_ram));
3549                 DECL_STATE_ENTRY_MULTI(void, work_ram, sizeof(work_ram));
3550                 DECL_STATE_ENTRY_MULTI(void, shared_ram, sizeof(shared_ram));
3551                 DECL_STATE_ENTRY_MULTI(void, subsys_c, sizeof(subsys_c));
3552                 DECL_STATE_ENTRY_MULTI(void, gvram, sizeof(gvram));
3553                 DECL_STATE_ENTRY_MULTI(void, gvram_shadow, sizeof(gvram_shadow));
3554
3555 #if defined(_FM77_VARIANTS)
3556                 DECL_STATE_ENTRY_BOOL(kanjisub);
3557                 DECL_STATE_ENTRY_PAIR(kanjiaddr);
3558 # if defined(_FM77L4)
3559                 DECL_STATE_ENTRY_BOOL(mode400line);
3560                 DECL_STATE_ENTRY_BOOL(stat_400linecard);
3561 # endif
3562 #elif defined(_FM77AV_VARIANTS)
3563                 DECL_STATE_ENTRY_BOOL(kanjisub);
3564                 DECL_STATE_ENTRY_PAIR(kanjiaddr);
3565
3566                 DECL_STATE_ENTRY_BOOL(mode320);
3567                 DECL_STATE_ENTRY_INT32(cgrom_bank);
3568 #if defined(_FM77AV40) || defined(_FM77AV40SX)|| defined(_FM77AV40SX) || \
3569     defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
3570                 DECL_STATE_ENTRY_INT32(vram_bank);
3571 #endif
3572
3573                 DECL_STATE_ENTRY_UINT32(displine);
3574                 DECL_STATE_ENTRY_UINT8(subrom_bank);
3575                 DECL_STATE_ENTRY_UINT8(subrom_bank_using);
3576
3577                 DECL_STATE_ENTRY_BOOL(nmi_enable);
3578                 DECL_STATE_ENTRY_BOOL(use_alu);
3579
3580                 DECL_STATE_ENTRY_PAIR(apalette_index);
3581                 DECL_STATE_ENTRY_MULTI(void, analog_palette_r, sizeof(analog_palette_r));
3582                 DECL_STATE_ENTRY_MULTI(void, analog_palette_g, sizeof(analog_palette_g));
3583                 DECL_STATE_ENTRY_MULTI(void, analog_palette_b, sizeof(analog_palette_b));
3584
3585
3586                 DECL_STATE_ENTRY_BOOL(diag_load_subrom_a);
3587                 DECL_STATE_ENTRY_BOOL(diag_load_subrom_b);
3588                 DECL_STATE_ENTRY_BOOL(diag_load_subrom_cg);
3589
3590                 DECL_STATE_ENTRY_MULTI(void, subsys_a, sizeof(subsys_a));
3591                 DECL_STATE_ENTRY_MULTI(void, subsys_b, sizeof(subsys_b));
3592                 DECL_STATE_ENTRY_MULTI(void, subsys_cg, sizeof(subsys_cg));
3593                 DECL_STATE_ENTRY_MULTI(void, submem_hidden, sizeof(submem_hidden));
3594 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
3595                 DECL_STATE_ENTRY_BOOL(mode400line);
3596                 DECL_STATE_ENTRY_BOOL(mode256k);
3597
3598                 DECL_STATE_ENTRY_BOOL(monitor_ram);
3599 #  if defined(_FM77AV40EX) || defined(_FM77AV40SX)
3600                 DECL_STATE_ENTRY_UINT16(window_low);
3601                 DECL_STATE_ENTRY_UINT16(window_high);
3602                 DECL_STATE_ENTRY_UINT16(window_xbegin);
3603                 DECL_STATE_ENTRY_UINT16(window_xend);
3604                 DECL_STATE_ENTRY_BOOL(window_opened);
3605 #  endif
3606                 DECL_STATE_ENTRY_BOOL(kanji_level2);
3607
3608                 DECL_STATE_ENTRY_UINT8(vram_active_block);
3609                 DECL_STATE_ENTRY_UINT8(vram_display_block);
3610                 DECL_STATE_ENTRY_UINT8(console_ram_bank);
3611                 DECL_STATE_ENTRY_BOOL(ram_protect);
3612
3613                 DECL_STATE_ENTRY_UINT8(cgram_bank);
3614                 DECL_STATE_ENTRY_MULTI(void, subsys_ram, sizeof(subsys_ram));
3615                 DECL_STATE_ENTRY_MULTI(void, submem_cgram, sizeof(submem_cgram));
3616                 DECL_STATE_ENTRY_MULTI(void, submem_console_av40, sizeof(submem_console_av40));
3617 # endif
3618 #endif
3619         }
3620         // V2
3621         {
3622                 DECL_STATE_ENTRY_INT32(nmi_event_id);
3623 //#if defined(_FM77AV_VARIANTS)
3624                 DECL_STATE_ENTRY_INT32(hblank_event_id);
3625                 DECL_STATE_ENTRY_INT32(hdisp_event_id);
3626                 DECL_STATE_ENTRY_INT32(vsync_event_id);
3627                 DECL_STATE_ENTRY_INT32(vstart_event_id);
3628 //#endif
3629                 DECL_STATE_ENTRY_BOOL(firq_mask);
3630                 DECL_STATE_ENTRY_BOOL(vram_accessflag);
3631
3632                 DECL_STATE_ENTRY_INT8(display_page);
3633                 DECL_STATE_ENTRY_INT8(display_page_bak);
3634
3635                 DECL_STATE_ENTRY_BOOL(vblank);
3636                 DECL_STATE_ENTRY_BOOL(vsync);
3637                 DECL_STATE_ENTRY_BOOL(hblank);
3638                 DECL_STATE_ENTRY_INT32(vblank_count);
3639         }
3640 #if defined(_FM77L4)
3641         DECL_STATE_ENTRY_MULTI(void, subsys_cg_l4, sizeof(subsys_cg_l4));
3642         DECL_STATE_ENTRY_MULTI(void, subsys_l4, sizeof(subsys_l4));
3643         DECL_STATE_ENTRY_MULTI(void, text_vram, sizeof(text_vram));
3644         //state_fio->Fwrite(crtc_regs, sizeof(crtc_regs), 1);
3645
3646         DECL_STATE_ENTRY_BOOL(workram_l4);
3647         DECL_STATE_ENTRY_BOOL(cursor_lsb);
3648     DECL_STATE_ENTRY_BOOL(text_width40);
3649
3650         DECL_STATE_ENTRY_BOOL(text_blink);
3651         DECL_STATE_ENTRY_BOOL(cursor_blink);
3652
3653         DECL_STATE_ENTRY_PAIR(text_start_addr);
3654         DECL_STATE_ENTRY_UINT32(text_lines);
3655         DECL_STATE_ENTRY_UINT32(text_xmax);
3656
3657         DECL_STATE_ENTRY_PAIR(cursor_addr);
3658         DECL_STATE_ENTRY_INT32(cursor_start);
3659         DECL_STATE_ENTRY_INT32(cursor_end);
3660         DECL_STATE_ENTRY_UINT8(cursor_type);
3661         DECL_STATE_ENTRY_UINT8(text_scroll_count);
3662
3663         DECL_STATE_ENTRY_INT32(event_id_l4_cursor_blink);
3664         DECL_STATE_ENTRY_INT32(event_id_l4_text_blink);
3665 #endif
3666         leave_decl_state();
3667 }
3668
3669 void DISPLAY::save_state(FILEIO *state_fio)
3670 {
3671         if(state_entry != NULL) state_entry->save_state(state_fio);
3672 }
3673
3674 bool DISPLAY::load_state(FILEIO *state_fio)
3675 {
3676         bool mb = false;
3677         if(state_entry != NULL) {
3678                 mb = state_entry->load_state(state_fio);
3679         }
3680         this->out_debug_log(_T("Load State: DISPLAY : id=%d stat=%s"), this_device_id, (mb) ? _T("OK") : _T("NG"));
3681         if(!mb) return false;
3682
3683         {
3684                 int addr;
3685                 int i;
3686                 crt_flag_bak = true;
3687                 for(i = 0; i < 411 * 5; i++) vram_wrote_table[i] = true;
3688                 for(i = 0; i < 411; i++) vram_draw_table[i] = true;
3689 #if defined(_FM8)
3690                 for(addr = 0; addr < 8; addr++) set_dpalette(addr, addr);
3691                 memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
3692   #if defined(USE_GREEN_DISPLAY)
3693                 memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
3694   #endif
3695 #else
3696
3697                 for(addr = 0; addr < 8; addr++) set_dpalette(addr, dpalette_data[addr]);
3698                 memcpy(dpalette_pixel, dpalette_pixel_tmp, sizeof(dpalette_pixel));
3699 #if defined(USE_GREEN_DISPLAY)
3700                 memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
3701 #endif
3702                 for(i = 0; i < 4; i++) {
3703                         multimode_accessflags[i] = ((multimode_accessmask & (1 << i)) != 0) ? true : false;
3704                         multimode_dispflags[i] = ((multimode_dispmask & (1 << i)) != 0) ? true : false;
3705                 }
3706 #endif
3707 #if defined(_FM77_VARIANTS)
3708 # if defined(_FM77L4)
3709 # endif
3710 #elif defined(_FM77AV_VARIANTS)
3711 #if defined(_FM77AV40) || defined(_FM77AV40SX)|| defined(_FM77AV40SX) || \
3712     defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
3713 #endif
3714                 screen_update_flag = true;
3715                 for(i = 0; i < 4096; i++) calc_apalette(i);
3716                 memcpy(analog_palette_pixel, analog_palette_pixel_tmp, sizeof(analog_palette_pixel));
3717
3718 #endif
3719                 palette_changed = true;
3720                 vram_wrote_shadow = true; // Force Draw
3721                 this->draw_screen();
3722         }
3723                 frame_skip_count_draw = 3;
3724                 frame_skip_count_transfer = 3;
3725                 need_transfer_line = true;
3726 #if defined(USE_GREEN_DISPLAY) && defined(USE_MONITOR_TYPE)
3727         memcpy(dpalette_pixel_green, dpalette_green_tmp, sizeof(dpalette_pixel_green));
3728         switch(config.monitor_type) {
3729         case FM7_MONITOR_GREEN:
3730                 use_green_monitor = true;
3731                 break;
3732         case FM7_MONITOR_STANDARD:
3733         default:
3734                 use_green_monitor = false;
3735                 break;
3736         }
3737 #else
3738         //use_green_monitor = false;
3739 #endif
3740         force_update = true;
3741         setup_display_mode();
3742         return mb;
3743 }
3744
3745