2 * FM77AV/FM16β ALU [mb61vh010.cpp]
3 * of Fujitsu MB61VH010/011
5 * Author: K.Ohta <whatisthis.sowhat _at_ gmail.com>
8 * Mar 28, 2015 : Initial
12 #include "mb61vh010.h"
15 MB61VH010::MB61VH010(VM *parent_vm, EMU *parent_emu) : DEVICE(parent_vm, parent_emu)
21 MB61VH010::~MB61VH010()
25 uint8 MB61VH010::do_read(uint32 addr, uint32 bank)
29 if(((1 << bank) & multi_page) != 0) return 0xff;
31 if((addr & 0xffff) < 0x8000) {
32 raddr = (addr & 0x7fff) | (0x8000 * bank);
33 return target->read_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS);
36 raddr = (addr & 0x3fff) | (0x4000 * bank);
37 return target->read_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS);
42 uint8 MB61VH010::do_write(uint32 addr, uint32 bank, uint8 data)
47 if(((1 << bank) & multi_page) != 0) return 0xff;
48 if((command_reg & 0x40) != 0) { // Calculate before writing
49 readdata = do_read(addr, bank);
51 if((command_reg & 0x20) != 0) { // NAND
52 readdata = readdata & cmp_status_reg;
53 data = data & (~cmp_status_reg);
55 readdata = readdata & (~cmp_status_reg);
56 data = data & cmp_status_reg;
58 readdata = readdata | data;
63 if((addr & 0xffff) < 0x8000) {
64 //raddr = ((addr + (line_addr_offset.w.l << 1)) & 0x7fff) | (0x8000 * bank);
65 raddr = (addr & 0x7fff) | (0x8000 * bank);
66 target->write_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS, readdata);
69 //raddr = ((addr + (line_addr_offset.w.l << 1)) & 0x3fff) | (0x4000 * bank);
70 raddr = (addr & 0x3fff) | (0x4000 * bank);
71 target->write_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS, readdata);
77 uint8 MB61VH010::do_pset(uint32 addr)
80 uint32 raddr = addr; // Use banked ram.
83 int planes_b = planes;
84 if(planes_b >= 4) planes_b = 4;
85 for(i = 0; i < planes_b; i++) {
86 if((bank_disable_reg & (1 << i)) != 0) {
89 if((color_reg & (1 << i)) == 0) {
95 srcdata = do_read(addr, i);
96 bitmask = bitmask & (~mask_reg);
97 srcdata = srcdata & mask_reg;
98 srcdata = srcdata | bitmask;
99 do_write(addr, i, srcdata);
104 uint8 MB61VH010::do_blank(uint32 addr)
109 if(planes >= 4) planes = 4;
110 for(i = 0; i < planes; i++) {
111 if((bank_disable_reg & (1 << i)) != 0) {
114 srcdata = do_read(addr, i);
115 srcdata = srcdata & mask_reg;
116 do_write(addr, i, srcdata);
121 uint8 MB61VH010::do_or(uint32 addr)
127 if(planes >= 4) planes = 4;
128 for(i = 0; i < planes; i++) {
129 if((bank_disable_reg & (1 << i)) != 0) {
132 srcdata = do_read(addr, i);
133 if((color_reg & (1 << i)) == 0) {
134 bitmask = srcdata; // srcdata | 0x00
136 bitmask = 0xff; // srcdata | 0xff
138 bitmask = bitmask & ~mask_reg;
139 srcdata = (srcdata & mask_reg) | bitmask;
140 do_write(addr, i, srcdata);
145 uint8 MB61VH010::do_and(uint32 addr)
151 if(planes >= 4) planes = 4;
152 for(i = 0; i < planes; i++) {
153 if((bank_disable_reg & (1 << i)) != 0) {
156 srcdata = do_read(addr, i);
157 if((color_reg & (1 << i)) == 0) {
158 bitmask = 0x00; // srcdata & 0x00
160 bitmask = srcdata; // srcdata & 0xff;
162 bitmask = bitmask & ~mask_reg;
163 srcdata = (srcdata & mask_reg) | bitmask;
164 do_write(addr, i, srcdata);
169 uint8 MB61VH010::do_xor(uint32 addr)
175 if(planes >= 4) planes = 4;
176 for(i = 0; i < planes; i++) {
177 if((bank_disable_reg & (1 << i)) != 0) {
180 srcdata = do_read(addr, i);
181 if((color_reg & (1 << i)) == 0) {
182 bitmask = srcdata ^ 0x00;
184 bitmask = srcdata ^ 0xff;
186 bitmask = bitmask & ~mask_reg;
187 srcdata = (srcdata & mask_reg) | bitmask;
188 do_write(addr, i, srcdata);
193 uint8 MB61VH010::do_not(uint32 addr)
199 if(planes >= 4) planes = 4;
200 for(i = 0; i < planes; i++) {
201 if((bank_disable_reg & (1 << i)) != 0) {
204 srcdata = do_read(addr, i);
207 bitmask = bitmask & ~mask_reg;
208 srcdata = (srcdata & mask_reg) | bitmask;
209 do_write(addr, i, srcdata);
215 uint8 MB61VH010::do_tilepaint(uint32 addr)
220 //printf("Tilepaint CMD=%02x, ADDR=%04x Planes=%d, disable=%d, tile_reg=(%02x %02x %02x %02x)\n",
221 // command_reg, addr, planes, bank_disable_reg, tile_reg[0], tile_reg[1], tile_reg[2], tile_reg[3]);
222 if(planes > 4) planes = 4;
223 for(i = 0; i < planes; i++) {
224 if((bank_disable_reg & (1 << i)) != 0) {
227 srcdata = do_read(addr, i);
228 bitmask = tile_reg[i] & (~mask_reg);
229 srcdata = (srcdata & mask_reg) | bitmask;
230 do_write(addr, i, srcdata);
235 uint8 MB61VH010::do_compare(uint32 addr)
237 uint32 offset = 0x4000;
239 uint8 disables = ~bank_disable_reg;
240 //uint8 disables = bank_disable_reg;
243 uint8 cmp_reg_bak[8];
248 disables = disables & 0x07;
250 for(j = 0; j < 8; j++) {
251 if((cmp_color_data[j] & 0x80) == 0) {
252 cmp_reg_bak[k] = cmp_color_data[j] & disables;
256 cmp_status_reg = 0x00;
257 if(k <= 0) return 0xff;
259 b = do_read(addr, 0);
260 r = do_read(addr, 1);
261 g = do_read(addr, 2);
262 for(i = 0; i < 8; i++) {
264 tmpcol = (b & 0x80) >> 7;
265 tmpcol = tmpcol | ((r & 0x80) >> 6);
266 tmpcol = tmpcol | ((g & 0x80) >> 5);
267 //tmpcol |= ((t & 0x80) != 0) ? 8 : 0;
268 tmpcol = tmpcol & disables;
269 for(j = 0; j < k; j++) {
270 if(cmp_reg_bak[j] == tmpcol) {
271 tmp_stat = tmp_stat | 0x01;
280 cmp_status_reg = tmp_stat;
284 void MB61VH010::do_alucmds_dmyread(uint32 addr)
287 addr = addr & 0x3fff;
293 addr = addr & 0x7fff;
295 if((command_reg & 0x80) == 0) {
299 cmp_status_reg = 0x00;
300 if((command_reg & 0x40) != 0) do_compare(addr);
301 switch(command_reg & 0x07) {
327 //printf("ALU DMYREAD ADDR=%04x, CMD=%02x CMP STATUS=%02x\n", addr, command_reg, cmp_status_reg);
328 if(eventid_busy >= 0) cancel_event(this, eventid_busy) ;
329 register_event(this, EVENT_MB61VH010_BUSY_OFF, 1.0 / 16.0, false, &eventid_busy) ;
332 uint8 MB61VH010::do_alucmds(uint32 addr)
335 addr = addr & 0x3fff;
341 addr = addr & 0x7fff;
343 cmp_status_reg = 0x00;
344 if((command_reg & 0x40) != 0) do_compare(addr);
345 switch(command_reg & 0x07) {
347 return do_pset(addr);
350 return do_blank(addr);
365 return do_tilepaint(addr);
368 if((command_reg & 0x40) != 0) return do_compare(addr);
374 void MB61VH010::do_line(void)
376 int x_begin = line_xbegin.w.l;
377 int x_end = line_xend.w.l;
378 int y_begin = line_ybegin.w.l;
379 int y_end = line_yend.w.l;
382 int ax = x_end - x_begin;
383 int ay = y_end - y_begin;
388 uint8 mask_bak = mask_reg;
390 uint8 vmask[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01};
391 //printf("Line: (%d,%d) - (%d,%d) CMD=%02x\n", x_begin, y_begin, x_end, y_end, command_reg);
393 bool lastflag = false;
395 //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
396 planes = target->read_signal(SIG_DISPLAY_PLANES) & 0x07;
397 screen_width = target->read_signal(SIG_DISPLAY_X_WIDTH) * 8;
398 screen_height = target->read_signal(SIG_DISPLAY_Y_HEIGHT);
400 //if((command_reg & 0x80) == 0) return;
401 oldaddr = 0xffffffff;
402 //alu_addr = 0xffffffff;
405 line_style = line_pattern;
410 if((line_style.b.h & 0x80) != 0) {
411 mask_reg &= ~vmask[cpx_t & 7];
413 tmp8a = ((line_style.b.h & 0x80) >> 7) & 0x01;
414 line_style.w.l = (line_style.w.l << 1) | tmp8a;
418 //lastflag = put_dot(x_begin, y_begin);
421 for(; cpx_t <= x_end; cpx_t++) {
422 lastflag = put_dot(cpx_t, cpy_t);
425 for(; cpx_t >= x_end; cpx_t--) {
426 lastflag = put_dot(cpx_t, cpy_t);
429 } else if(xcount == 0) {
431 for(; cpy_t <= y_end; cpy_t++) {
432 lastflag = put_dot(cpx_t, cpy_t);
435 for(; cpy_t >= y_end; cpy_t--) {
436 lastflag = put_dot(cpx_t, cpy_t);
439 } else if(xcount >= ycount) {
440 diff = (ycount * 32768) / xcount;
441 for(; xcount >= 0; xcount-- ) {
442 lastflag = put_dot(cpx_t, cpy_t);
446 if(cpy_t > y_end) cpy_t--;
448 if(cpy_t < y_end) cpy_t++;
458 } else if(xcount == ycount) {
460 for(; xcount >= 0; xcount-- ) {
461 lastflag = put_dot(cpx_t, cpy_t);
474 } else { // (abs(ax) <= abs(ay)
475 diff = (xcount * 32768) / ycount;
476 for(; ycount >= 0; ycount--) {
477 lastflag = put_dot(cpx_t, cpy_t);
481 if(cpx_t > x_end) cpx_t--;
483 if(cpx_t < x_end) cpx_t++;
495 //lastflag = put_dot(x_end, y_end);
496 if(!lastflag) total_bytes++;
497 do_alucmds(alu_addr);
498 //printf("** %04x %02x %02x %02x\n", alu_addr, command_reg, mask_bak, mask_reg);
500 if(total_bytes > 0) { // Over 0.5us
501 usec = (double)total_bytes / 16.0;
502 if(eventid_busy >= 0) cancel_event(this, eventid_busy) ;
503 register_event(this, EVENT_MB61VH010_BUSY_OFF, usec, false, &eventid_busy) ;
510 bool MB61VH010::put_dot(int x, int y)
512 uint8 vmask[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01};
516 if((x < 0) || (y < 0)) return flag;
517 if((x >= screen_width) || (y >= screen_height)) return flag;
518 if((command_reg & 0x80) == 0) return flag;
520 alu_addr = ((y * screen_width) >> 3) + (x >> 3);
521 alu_addr = alu_addr + (line_addr_offset.w.l << 1);
522 alu_addr = alu_addr & 0x7fff;
523 if(!is_400line) alu_addr = alu_addr & 0x3fff;
524 //if(oldaddr == 0xffffffff) oldaddr = alu_addr;
526 if(oldaddr != alu_addr) {
527 if(oldaddr == 0xffffffff) oldaddr = alu_addr;
535 if((line_style.b.h & 0x80) != 0) {
536 mask_reg &= ~vmask[x & 7];
538 //tmp8a = (line_style.w.l & 0x8000) >> 15;
539 tmp8a = ((line_style.b.h & 0x80) >> 7) & 0x01;
540 line_style.w.l = (line_style.w.l << 1) | tmp8a;
544 void MB61VH010::write_data8(uint32 id, uint32 data)
546 //printf("ALU: ADDR=%02x DATA=%02x\n", id, data);
547 if(id == ALU_CMDREG) {
552 case ALU_LOGICAL_COLOR:
555 case ALU_WRITE_MASKREG:
558 case ALU_BANK_DISABLE:
559 bank_disable_reg = data;
561 case ALU_TILEPAINT_B:
564 case ALU_TILEPAINT_R:
567 case ALU_TILEPAINT_G:
570 case ALU_TILEPAINT_L:
573 case ALU_OFFSET_REG_HIGH:
574 line_addr_offset.b.h = data;
576 case ALU_OFFSET_REG_LO:
577 line_addr_offset.b.l = data;
579 case ALU_LINEPATTERN_REG_HIGH:
580 line_pattern.b.h = data;
582 case ALU_LINEPATTERN_REG_LO:
583 line_pattern.b.l = data;
585 case ALU_LINEPOS_START_X_HIGH:
586 line_xbegin.b.h = data;
588 case ALU_LINEPOS_START_X_LOW:
589 line_xbegin.b.l = data;
591 case ALU_LINEPOS_START_Y_HIGH:
592 line_ybegin.b.h = data;
594 case ALU_LINEPOS_START_Y_LOW:
595 line_ybegin.b.l = data;
597 case ALU_LINEPOS_END_X_HIGH:
598 line_xend.b.h = data;
600 case ALU_LINEPOS_END_X_LOW:
601 line_xend.b.l = data;
603 case ALU_LINEPOS_END_Y_HIGH:
604 line_yend.b.h = data;
606 case ALU_LINEPOS_END_Y_LOW:
607 line_yend.b.l = data;
611 if((id >= (ALU_CMPDATA_REG + 0)) && (id < (ALU_CMPDATA_REG + 8))) {
612 cmp_color_data[id - ALU_CMPDATA_REG] = data;
613 } else if((id >= ALU_WRITE_PROXY) && (id < (ALU_WRITE_PROXY + 0x18000))) {
614 uint32 raddr = id - ALU_WRITE_PROXY;
616 raddr = raddr & 0x7fff;
618 raddr = raddr & 0x3fff;
620 do_alucmds_dmyread(raddr);
626 uint32 MB61VH010::read_data8(uint32 id)
631 return (uint32)command_reg;
633 case ALU_LOGICAL_COLOR:
634 return (uint32)color_reg;
636 case ALU_WRITE_MASKREG:
637 return (uint32)mask_reg;
639 case ALU_CMP_STATUS_REG:
640 return (uint32)cmp_status_reg;
642 case ALU_BANK_DISABLE:
643 return (uint32)bank_disable_reg;
646 if((id >= ALU_WRITE_PROXY) && (id < (ALU_WRITE_PROXY + 0x18000))) {
648 raddr = id - ALU_WRITE_PROXY;
649 //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
651 raddr = raddr & 0x7fff;
653 raddr = raddr & 0x3fff;
655 //dmydata = target->read_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS);
656 do_alucmds_dmyread(raddr);
657 dmydata = target->read_data8(raddr + DISPLAY_VRAM_DIRECT_ACCESS);
665 uint32 MB61VH010::read_signal(int id)
667 uint32 val = 0x00000000;
669 case SIG_ALU_BUSYSTAT:
670 if(busy_flag) val = 0xffffffff;
676 void MB61VH010::write_signal(int id, uint32 data, uint32 mask)
678 bool flag = ((data & mask) != 0);
680 case SIG_ALU_400LINE:
683 case SIG_ALU_MULTIPAGE:
684 multi_page = (data & mask) & 0x07;
689 void MB61VH010::event_callback(int event_id, int err)
692 case EVENT_MB61VH010_BUSY_ON:
694 if(eventid_busy >= 0) cancel_event(this, eventid_busy);
697 case EVENT_MB61VH010_BUSY_OFF:
704 void MB61VH010::initialize(void)
712 void MB61VH010::reset(void)
716 if(eventid_busy >= 0) cancel_event(this, eventid_busy);
719 command_reg = 0; // D410 (RW)
720 color_reg = 0; // D411 (RW)
721 mask_reg = 0; // D412 (RW)
722 cmp_status_reg = 0; // D413 (RO)
723 for(i = 0; i < 8; i++) cmp_color_data[i] = 0x80; // D413-D41A (WO)
724 bank_disable_reg = 0; // D41B (RW)
725 for(i = 0; i < 4; i++) tile_reg[i] = 0; // D41C-D41F (WO)
727 line_addr_offset.d = 0; // D420-D421 (WO)
728 line_pattern.d = 0; // D422-D423 (WO)
729 line_xbegin.d = 0; // D424-D425 (WO)
730 line_ybegin.d = 0; // D426-D427 (WO)
731 line_xend.d = 0; // D428-D429 (WO)
732 line_yend.d = 0; // D42A-D42B (WO)
734 oldaddr = 0xffffffff;
736 planes = target->read_signal(SIG_DISPLAY_PLANES) & 0x07;
737 if(planes >= 4) planes = 4;
738 //is_400line = (target->read_signal(SIG_DISPLAY_MODE_IS_400LINE) != 0) ? true : false;
740 screen_width = target->read_signal(SIG_DISPLAY_X_WIDTH) * 8;
741 screen_height = target->read_signal(SIG_DISPLAY_Y_HEIGHT);