source/src/vm/fmr50/scsi.cpp

   1 /*
   2         FUJITSU FMR-50 Emulator 'eFMR-50'
   3         FUJITSU FMR-60 Emulator 'eFMR-60'
   4
   5         Author : Takeda.Toshiya
   6         Date   : 2008.05.02 -
   7
   8         [ scsi ]
   9 */
  10
  11 #include "scsi.h"
  12
  13 // phase
  14 #define PHASE_BUSFREE           0
  15 #define PHASE_ARBITRATION       1
  16 #define PHASE_SELECTION         2
  17 #define PHASE_RESELECTION       3
  18 #define PHASE_COMMAND           4
  19 #define PHASE_EXECUTE           5
  20 #define PHASE_MSG_IN            6
  21 #define PHASE_MSG_OUT           7
  22 #define PHASE_DATA_IN           8
  23 #define PHASE_DATA_OUT          9
  24 #define PHASE_STATUS            10
  25
  26 // control register
  27 #define CTRL_WEN        0x80
  28 #define CTRL_IMSK       0x40
  29 #define CTRL_ATN        0x10
  30 #define CTRL_SEL        0x04
  31 #define CTRL_DMAE       0x02
  32 #define CTRL_RST        0x01
  33
  34 // status register
  35 #define STAT_REQ        0x80
  36 #define STAT_IO         0x40
  37 #define STAT_MSG        0x20
  38 #define STAT_CD         0x10
  39 #define STAT_BUSY       0x08
  40 #define STAT_INT        0x02
  41 #define STAT_PERR       0x01
  42
  43 // DMA: SIG_UPD71071_CH1
  44 // IRQ: SIG_I8259_CHIP1 | SIG_I8259_IR0
  45
  46 void SCSI::initialize()
  47 {
  48         phase = PHASE_BUSFREE;
  49         ctrlreg = datareg = statreg = 0;
  50 }
  51
  52 void SCSI::write_io8(uint32 addr, uint32 data)
  53 {
  54         switch(addr & 0xffff) {
  55         case 0xc30:
  56                 // data register
  57                 datareg = data;
  58                 break;
  59         case 0xc32:
  60                 // control register
  61                 if((ctrlreg & CTRL_RST) && ~(data & CTRL_RST)) {
  62                         // reset
  63                         statreg = 0;
  64                 }
  65                 if(~(ctrlreg & CTRL_SEL) && (data & CTRL_SEL)) {
  66                         // sel
  67 //                      statreg |= 8;
  68 //                      datareg = 0x80;
  69                 }
  70                 ctrlreg = data;
  71                 break;
  72         }
  73 }
  74
  75 uint32 SCSI::read_io8(uint32 addr)
  76 {
  77 //      uint32 val;
  78
  79         switch(addr & 0xffff) {
  80         case 0xc30:
  81                 // data register
  82                 return 0;
  83         case 0xc32:
  84                 // status register
  85                 return 0;
  86 //              val = statreg;
  87 //              statreg &= ~8;
  88 //              return val;
  89         }
  90         return 0xff;
  91 }
  92
  93 void SCSI::write_dma_io8(uint32 addr, uint32 data)
  94 {
  95         write_io8(0xc30, data);
  96 }
  97
  98 uint32 SCSI::read_dma_io8(uint32 addr)
  99 {
 100         return read_io8(0xc30);
 101 }
 102